ice.h 9.4 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /* Copyright (c) 2018, Intel Corporation. */
  3. #ifndef _ICE_H_
  4. #define _ICE_H_
  5. #include <linux/types.h>
  6. #include <linux/errno.h>
  7. #include <linux/kernel.h>
  8. #include <linux/module.h>
  9. #include <linux/netdevice.h>
  10. #include <linux/compiler.h>
  11. #include <linux/etherdevice.h>
  12. #include <linux/skbuff.h>
  13. #include <linux/cpumask.h>
  14. #include <linux/rtnetlink.h>
  15. #include <linux/if_vlan.h>
  16. #include <linux/dma-mapping.h>
  17. #include <linux/pci.h>
  18. #include <linux/workqueue.h>
  19. #include <linux/aer.h>
  20. #include <linux/interrupt.h>
  21. #include <linux/ethtool.h>
  22. #include <linux/timer.h>
  23. #include <linux/delay.h>
  24. #include <linux/bitmap.h>
  25. #include <linux/log2.h>
  26. #include <linux/ip.h>
  27. #include <linux/ipv6.h>
  28. #include <linux/if_bridge.h>
  29. #include <net/ipv6.h>
  30. #include "ice_devids.h"
  31. #include "ice_type.h"
  32. #include "ice_txrx.h"
  33. #include "ice_switch.h"
  34. #include "ice_common.h"
  35. #include "ice_sched.h"
  36. extern const char ice_drv_ver[];
  37. #define ICE_BAR0 0
  38. #define ICE_DFLT_NUM_DESC 128
  39. #define ICE_MIN_NUM_DESC 8
  40. #define ICE_MAX_NUM_DESC 8160
  41. #define ICE_REQ_DESC_MULTIPLE 32
  42. #define ICE_DFLT_TRAFFIC_CLASS BIT(0)
  43. #define ICE_INT_NAME_STR_LEN (IFNAMSIZ + 16)
  44. #define ICE_ETHTOOL_FWVER_LEN 32
  45. #define ICE_AQ_LEN 64
  46. #define ICE_MIN_MSIX 2
  47. #define ICE_NO_VSI 0xffff
  48. #define ICE_MAX_VSI_ALLOC 130
  49. #define ICE_MAX_TXQS 2048
  50. #define ICE_MAX_RXQS 2048
  51. #define ICE_VSI_MAP_CONTIG 0
  52. #define ICE_VSI_MAP_SCATTER 1
  53. #define ICE_MAX_SCATTER_TXQS 16
  54. #define ICE_MAX_SCATTER_RXQS 16
  55. #define ICE_Q_WAIT_RETRY_LIMIT 10
  56. #define ICE_Q_WAIT_MAX_RETRY (5 * ICE_Q_WAIT_RETRY_LIMIT)
  57. #define ICE_MAX_LG_RSS_QS 256
  58. #define ICE_MAX_SMALL_RSS_QS 8
  59. #define ICE_RES_VALID_BIT 0x8000
  60. #define ICE_RES_MISC_VEC_ID (ICE_RES_VALID_BIT - 1)
  61. #define ICE_INVAL_Q_INDEX 0xffff
  62. #define ICE_VSIQF_HKEY_ARRAY_SIZE ((VSIQF_HKEY_MAX_INDEX + 1) * 4)
  63. #define ICE_DFLT_NETIF_M (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK)
  64. #define ICE_MAX_MTU (ICE_AQ_SET_MAC_FRAME_SIZE_MAX - \
  65. ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN)
  66. #define ICE_UP_TABLE_TRANSLATE(val, i) \
  67. (((val) << ICE_AQ_VSI_UP_TABLE_UP##i##_S) & \
  68. ICE_AQ_VSI_UP_TABLE_UP##i##_M)
  69. #define ICE_TX_DESC(R, i) (&(((struct ice_tx_desc *)((R)->desc))[i]))
  70. #define ICE_RX_DESC(R, i) (&(((union ice_32b_rx_flex_desc *)((R)->desc))[i]))
  71. #define ICE_TX_CTX_DESC(R, i) (&(((struct ice_tx_ctx_desc *)((R)->desc))[i]))
  72. /* Macro for each VSI in a PF */
  73. #define ice_for_each_vsi(pf, i) \
  74. for ((i) = 0; (i) < (pf)->num_alloc_vsi; (i)++)
  75. /* Macros for each tx/rx ring in a VSI */
  76. #define ice_for_each_txq(vsi, i) \
  77. for ((i) = 0; (i) < (vsi)->num_txq; (i)++)
  78. #define ice_for_each_rxq(vsi, i) \
  79. for ((i) = 0; (i) < (vsi)->num_rxq; (i)++)
  80. struct ice_tc_info {
  81. u16 qoffset;
  82. u16 qcount;
  83. };
  84. struct ice_tc_cfg {
  85. u8 numtc; /* Total number of enabled TCs */
  86. u8 ena_tc; /* TX map */
  87. struct ice_tc_info tc_info[ICE_MAX_TRAFFIC_CLASS];
  88. };
  89. struct ice_res_tracker {
  90. u16 num_entries;
  91. u16 search_hint;
  92. u16 list[1];
  93. };
  94. struct ice_sw {
  95. struct ice_pf *pf;
  96. u16 sw_id; /* switch ID for this switch */
  97. u16 bridge_mode; /* VEB/VEPA/Port Virtualizer */
  98. };
  99. enum ice_state {
  100. __ICE_DOWN,
  101. __ICE_NEEDS_RESTART,
  102. __ICE_RESET_RECOVERY_PENDING, /* set by driver when reset starts */
  103. __ICE_PFR_REQ, /* set by driver and peers */
  104. __ICE_CORER_REQ, /* set by driver and peers */
  105. __ICE_GLOBR_REQ, /* set by driver and peers */
  106. __ICE_CORER_RECV, /* set by OICR handler */
  107. __ICE_GLOBR_RECV, /* set by OICR handler */
  108. __ICE_EMPR_RECV, /* set by OICR handler */
  109. __ICE_SUSPENDED, /* set on module remove path */
  110. __ICE_RESET_FAILED, /* set by reset/rebuild */
  111. __ICE_ADMINQ_EVENT_PENDING,
  112. __ICE_FLTR_OVERFLOW_PROMISC,
  113. __ICE_CFG_BUSY,
  114. __ICE_SERVICE_SCHED,
  115. __ICE_STATE_NBITS /* must be last */
  116. };
  117. enum ice_vsi_flags {
  118. ICE_VSI_FLAG_UMAC_FLTR_CHANGED,
  119. ICE_VSI_FLAG_MMAC_FLTR_CHANGED,
  120. ICE_VSI_FLAG_VLAN_FLTR_CHANGED,
  121. ICE_VSI_FLAG_PROMISC_CHANGED,
  122. ICE_VSI_FLAG_NBITS /* must be last */
  123. };
  124. /* struct that defines a VSI, associated with a dev */
  125. struct ice_vsi {
  126. struct net_device *netdev;
  127. struct ice_sw *vsw; /* switch this VSI is on */
  128. struct ice_pf *back; /* back pointer to PF */
  129. struct ice_port_info *port_info; /* back pointer to port_info */
  130. struct ice_ring **rx_rings; /* rx ring array */
  131. struct ice_ring **tx_rings; /* tx ring array */
  132. struct ice_q_vector **q_vectors; /* q_vector array */
  133. irqreturn_t (*irq_handler)(int irq, void *data);
  134. u64 tx_linearize;
  135. DECLARE_BITMAP(state, __ICE_STATE_NBITS);
  136. DECLARE_BITMAP(flags, ICE_VSI_FLAG_NBITS);
  137. unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
  138. unsigned int current_netdev_flags;
  139. u32 tx_restart;
  140. u32 tx_busy;
  141. u32 rx_buf_failed;
  142. u32 rx_page_failed;
  143. int num_q_vectors;
  144. int base_vector;
  145. enum ice_vsi_type type;
  146. u16 vsi_num; /* HW (absolute) index of this VSI */
  147. u16 idx; /* software index in pf->vsi[] */
  148. /* Interrupt thresholds */
  149. u16 work_lmt;
  150. /* RSS config */
  151. u16 rss_table_size; /* HW RSS table size */
  152. u16 rss_size; /* Allocated RSS queues */
  153. u8 *rss_hkey_user; /* User configured hash keys */
  154. u8 *rss_lut_user; /* User configured lookup table entries */
  155. u8 rss_lut_type; /* used to configure Get/Set RSS LUT AQ call */
  156. u16 max_frame;
  157. u16 rx_buf_len;
  158. struct ice_aqc_vsi_props info; /* VSI properties */
  159. /* VSI stats */
  160. struct rtnl_link_stats64 net_stats;
  161. struct ice_eth_stats eth_stats;
  162. struct ice_eth_stats eth_stats_prev;
  163. struct list_head tmp_sync_list; /* MAC filters to be synced */
  164. struct list_head tmp_unsync_list; /* MAC filters to be unsynced */
  165. bool irqs_ready;
  166. bool current_isup; /* Sync 'link up' logging */
  167. bool stat_offsets_loaded;
  168. /* queue information */
  169. u8 tx_mapping_mode; /* ICE_MAP_MODE_[CONTIG|SCATTER] */
  170. u8 rx_mapping_mode; /* ICE_MAP_MODE_[CONTIG|SCATTER] */
  171. u16 txq_map[ICE_MAX_TXQS]; /* index in pf->avail_txqs */
  172. u16 rxq_map[ICE_MAX_RXQS]; /* index in pf->avail_rxqs */
  173. u16 alloc_txq; /* Allocated Tx queues */
  174. u16 num_txq; /* Used Tx queues */
  175. u16 alloc_rxq; /* Allocated Rx queues */
  176. u16 num_rxq; /* Used Rx queues */
  177. u16 num_desc;
  178. struct ice_tc_cfg tc_cfg;
  179. } ____cacheline_internodealigned_in_smp;
  180. /* struct that defines an interrupt vector */
  181. struct ice_q_vector {
  182. struct ice_vsi *vsi;
  183. cpumask_t affinity_mask;
  184. struct napi_struct napi;
  185. struct ice_ring_container rx;
  186. struct ice_ring_container tx;
  187. struct irq_affinity_notify affinity_notify;
  188. u16 v_idx; /* index in the vsi->q_vector array. */
  189. u8 num_ring_tx; /* total number of tx rings in vector */
  190. u8 num_ring_rx; /* total number of rx rings in vector */
  191. char name[ICE_INT_NAME_STR_LEN];
  192. } ____cacheline_internodealigned_in_smp;
  193. enum ice_pf_flags {
  194. ICE_FLAG_MSIX_ENA,
  195. ICE_FLAG_FLTR_SYNC,
  196. ICE_FLAG_RSS_ENA,
  197. ICE_PF_FLAGS_NBITS /* must be last */
  198. };
  199. struct ice_pf {
  200. struct pci_dev *pdev;
  201. struct msix_entry *msix_entries;
  202. struct ice_res_tracker *irq_tracker;
  203. struct ice_vsi **vsi; /* VSIs created by the driver */
  204. struct ice_sw *first_sw; /* first switch created by firmware */
  205. DECLARE_BITMAP(state, __ICE_STATE_NBITS);
  206. DECLARE_BITMAP(avail_txqs, ICE_MAX_TXQS);
  207. DECLARE_BITMAP(avail_rxqs, ICE_MAX_RXQS);
  208. DECLARE_BITMAP(flags, ICE_PF_FLAGS_NBITS);
  209. unsigned long serv_tmr_period;
  210. unsigned long serv_tmr_prev;
  211. struct timer_list serv_tmr;
  212. struct work_struct serv_task;
  213. struct mutex avail_q_mutex; /* protects access to avail_[rx|tx]qs */
  214. struct mutex sw_mutex; /* lock for protecting VSI alloc flow */
  215. u32 msg_enable;
  216. u32 hw_csum_rx_error;
  217. u32 oicr_idx; /* Other interrupt cause vector index */
  218. u32 num_lan_msix; /* Total MSIX vectors for base driver */
  219. u32 num_avail_msix; /* remaining MSIX vectors left unclaimed */
  220. u16 num_lan_tx; /* num lan tx queues setup */
  221. u16 num_lan_rx; /* num lan rx queues setup */
  222. u16 q_left_tx; /* remaining num tx queues left unclaimed */
  223. u16 q_left_rx; /* remaining num rx queues left unclaimed */
  224. u16 next_vsi; /* Next free slot in pf->vsi[] - 0-based! */
  225. u16 num_alloc_vsi;
  226. u16 corer_count; /* Core reset count */
  227. u16 globr_count; /* Global reset count */
  228. u16 empr_count; /* EMP reset count */
  229. u16 pfr_count; /* PF reset count */
  230. struct ice_hw_port_stats stats;
  231. struct ice_hw_port_stats stats_prev;
  232. struct ice_hw hw;
  233. bool stat_prev_loaded; /* has previous stats been loaded */
  234. char int_name[ICE_INT_NAME_STR_LEN];
  235. };
  236. struct ice_netdev_priv {
  237. struct ice_vsi *vsi;
  238. };
  239. /**
  240. * ice_irq_dynamic_ena - Enable default interrupt generation settings
  241. * @hw: pointer to hw struct
  242. * @vsi: pointer to vsi struct, can be NULL
  243. * @q_vector: pointer to q_vector, can be NULL
  244. */
  245. static inline void ice_irq_dynamic_ena(struct ice_hw *hw, struct ice_vsi *vsi,
  246. struct ice_q_vector *q_vector)
  247. {
  248. u32 vector = (vsi && q_vector) ? vsi->base_vector + q_vector->v_idx :
  249. ((struct ice_pf *)hw->back)->oicr_idx;
  250. int itr = ICE_ITR_NONE;
  251. u32 val;
  252. /* clear the PBA here, as this function is meant to clean out all
  253. * previous interrupts and enable the interrupt
  254. */
  255. val = GLINT_DYN_CTL_INTENA_M | GLINT_DYN_CTL_CLEARPBA_M |
  256. (itr << GLINT_DYN_CTL_ITR_INDX_S);
  257. if (vsi)
  258. if (test_bit(__ICE_DOWN, vsi->state))
  259. return;
  260. wr32(hw, GLINT_DYN_CTL(vector), val);
  261. }
  262. static inline void ice_vsi_set_tc_cfg(struct ice_vsi *vsi)
  263. {
  264. vsi->tc_cfg.ena_tc = ICE_DFLT_TRAFFIC_CLASS;
  265. vsi->tc_cfg.numtc = 1;
  266. }
  267. void ice_set_ethtool_ops(struct net_device *netdev);
  268. int ice_up(struct ice_vsi *vsi);
  269. int ice_down(struct ice_vsi *vsi);
  270. int ice_set_rss(struct ice_vsi *vsi, u8 *seed, u8 *lut, u16 lut_size);
  271. int ice_get_rss(struct ice_vsi *vsi, u8 *seed, u8 *lut, u16 lut_size);
  272. void ice_fill_rss_lut(u8 *lut, u16 rss_table_size, u16 rss_size);
  273. void ice_print_link_msg(struct ice_vsi *vsi, bool isup);
  274. #endif /* _ICE_H_ */