e1000_osdep.h 2.6 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /* Copyright(c) 1999 - 2006 Intel Corporation. */
  3. /* glue for the OS independent part of e1000
  4. * includes register access macros
  5. */
  6. #ifndef _E1000_OSDEP_H_
  7. #define _E1000_OSDEP_H_
  8. #include <asm/io.h>
  9. #define CONFIG_RAM_BASE 0x60000
  10. #define GBE_CONFIG_OFFSET 0x0
  11. #define GBE_CONFIG_RAM_BASE \
  12. ((unsigned int)(CONFIG_RAM_BASE + GBE_CONFIG_OFFSET))
  13. #define GBE_CONFIG_BASE_VIRT \
  14. ((void __iomem *)phys_to_virt(GBE_CONFIG_RAM_BASE))
  15. #define GBE_CONFIG_FLASH_WRITE(base, offset, count, data) \
  16. (iowrite16_rep(base + offset, data, count))
  17. #define GBE_CONFIG_FLASH_READ(base, offset, count, data) \
  18. (ioread16_rep(base + (offset << 1), data, count))
  19. #define er32(reg) \
  20. (readl(hw->hw_addr + ((hw->mac_type >= e1000_82543) \
  21. ? E1000_##reg : E1000_82542_##reg)))
  22. #define ew32(reg, value) \
  23. (writel((value), (hw->hw_addr + ((hw->mac_type >= e1000_82543) \
  24. ? E1000_##reg : E1000_82542_##reg))))
  25. #define E1000_WRITE_REG_ARRAY(a, reg, offset, value) ( \
  26. writel((value), ((a)->hw_addr + \
  27. (((a)->mac_type >= e1000_82543) ? E1000_##reg : E1000_82542_##reg) + \
  28. ((offset) << 2))))
  29. #define E1000_READ_REG_ARRAY(a, reg, offset) ( \
  30. readl((a)->hw_addr + \
  31. (((a)->mac_type >= e1000_82543) ? E1000_##reg : E1000_82542_##reg) + \
  32. ((offset) << 2)))
  33. #define E1000_READ_REG_ARRAY_DWORD E1000_READ_REG_ARRAY
  34. #define E1000_WRITE_REG_ARRAY_DWORD E1000_WRITE_REG_ARRAY
  35. #define E1000_WRITE_REG_ARRAY_WORD(a, reg, offset, value) ( \
  36. writew((value), ((a)->hw_addr + \
  37. (((a)->mac_type >= e1000_82543) ? E1000_##reg : E1000_82542_##reg) + \
  38. ((offset) << 1))))
  39. #define E1000_READ_REG_ARRAY_WORD(a, reg, offset) ( \
  40. readw((a)->hw_addr + \
  41. (((a)->mac_type >= e1000_82543) ? E1000_##reg : E1000_82542_##reg) + \
  42. ((offset) << 1)))
  43. #define E1000_WRITE_REG_ARRAY_BYTE(a, reg, offset, value) ( \
  44. writeb((value), ((a)->hw_addr + \
  45. (((a)->mac_type >= e1000_82543) ? E1000_##reg : E1000_82542_##reg) + \
  46. (offset))))
  47. #define E1000_READ_REG_ARRAY_BYTE(a, reg, offset) ( \
  48. readb((a)->hw_addr + \
  49. (((a)->mac_type >= e1000_82543) ? E1000_##reg : E1000_82542_##reg) + \
  50. (offset)))
  51. #define E1000_WRITE_FLUSH() er32(STATUS)
  52. #define E1000_WRITE_ICH_FLASH_REG(a, reg, value) ( \
  53. writel((value), ((a)->flash_address + reg)))
  54. #define E1000_READ_ICH_FLASH_REG(a, reg) ( \
  55. readl((a)->flash_address + reg))
  56. #define E1000_WRITE_ICH_FLASH_REG16(a, reg, value) ( \
  57. writew((value), ((a)->flash_address + reg)))
  58. #define E1000_READ_ICH_FLASH_REG16(a, reg) ( \
  59. readw((a)->flash_address + reg))
  60. #endif /* _E1000_OSDEP_H_ */