hinic_tx.c 13 KB

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  1. /*
  2. * Huawei HiNIC PCI Express Linux driver
  3. * Copyright(c) 2017 Huawei Technologies Co., Ltd
  4. *
  5. * This program is free software; you can redistribute it and/or modify it
  6. * under the terms and conditions of the GNU General Public License,
  7. * version 2, as published by the Free Software Foundation.
  8. *
  9. * This program is distributed in the hope it will be useful, but WITHOUT
  10. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
  12. * for more details.
  13. *
  14. */
  15. #include <linux/kernel.h>
  16. #include <linux/netdevice.h>
  17. #include <linux/u64_stats_sync.h>
  18. #include <linux/errno.h>
  19. #include <linux/types.h>
  20. #include <linux/pci.h>
  21. #include <linux/device.h>
  22. #include <linux/dma-mapping.h>
  23. #include <linux/slab.h>
  24. #include <linux/interrupt.h>
  25. #include <linux/skbuff.h>
  26. #include <linux/smp.h>
  27. #include <asm/byteorder.h>
  28. #include "hinic_common.h"
  29. #include "hinic_hw_if.h"
  30. #include "hinic_hw_wqe.h"
  31. #include "hinic_hw_wq.h"
  32. #include "hinic_hw_qp.h"
  33. #include "hinic_hw_dev.h"
  34. #include "hinic_dev.h"
  35. #include "hinic_tx.h"
  36. #define TX_IRQ_NO_PENDING 0
  37. #define TX_IRQ_NO_COALESC 0
  38. #define TX_IRQ_NO_LLI_TIMER 0
  39. #define TX_IRQ_NO_CREDIT 0
  40. #define TX_IRQ_NO_RESEND_TIMER 0
  41. #define CI_UPDATE_NO_PENDING 0
  42. #define CI_UPDATE_NO_COALESC 0
  43. #define HW_CONS_IDX(sq) be16_to_cpu(*(u16 *)((sq)->hw_ci_addr))
  44. #define MIN_SKB_LEN 64
  45. /**
  46. * hinic_txq_clean_stats - Clean the statistics of specific queue
  47. * @txq: Logical Tx Queue
  48. **/
  49. void hinic_txq_clean_stats(struct hinic_txq *txq)
  50. {
  51. struct hinic_txq_stats *txq_stats = &txq->txq_stats;
  52. u64_stats_update_begin(&txq_stats->syncp);
  53. txq_stats->pkts = 0;
  54. txq_stats->bytes = 0;
  55. txq_stats->tx_busy = 0;
  56. txq_stats->tx_wake = 0;
  57. txq_stats->tx_dropped = 0;
  58. u64_stats_update_end(&txq_stats->syncp);
  59. }
  60. /**
  61. * hinic_txq_get_stats - get statistics of Tx Queue
  62. * @txq: Logical Tx Queue
  63. * @stats: return updated stats here
  64. **/
  65. void hinic_txq_get_stats(struct hinic_txq *txq, struct hinic_txq_stats *stats)
  66. {
  67. struct hinic_txq_stats *txq_stats = &txq->txq_stats;
  68. unsigned int start;
  69. u64_stats_update_begin(&stats->syncp);
  70. do {
  71. start = u64_stats_fetch_begin(&txq_stats->syncp);
  72. stats->pkts = txq_stats->pkts;
  73. stats->bytes = txq_stats->bytes;
  74. stats->tx_busy = txq_stats->tx_busy;
  75. stats->tx_wake = txq_stats->tx_wake;
  76. stats->tx_dropped = txq_stats->tx_dropped;
  77. } while (u64_stats_fetch_retry(&txq_stats->syncp, start));
  78. u64_stats_update_end(&stats->syncp);
  79. }
  80. /**
  81. * txq_stats_init - Initialize the statistics of specific queue
  82. * @txq: Logical Tx Queue
  83. **/
  84. static void txq_stats_init(struct hinic_txq *txq)
  85. {
  86. struct hinic_txq_stats *txq_stats = &txq->txq_stats;
  87. u64_stats_init(&txq_stats->syncp);
  88. hinic_txq_clean_stats(txq);
  89. }
  90. /**
  91. * tx_map_skb - dma mapping for skb and return sges
  92. * @nic_dev: nic device
  93. * @skb: the skb
  94. * @sges: returned sges
  95. *
  96. * Return 0 - Success, negative - Failure
  97. **/
  98. static int tx_map_skb(struct hinic_dev *nic_dev, struct sk_buff *skb,
  99. struct hinic_sge *sges)
  100. {
  101. struct hinic_hwdev *hwdev = nic_dev->hwdev;
  102. struct hinic_hwif *hwif = hwdev->hwif;
  103. struct pci_dev *pdev = hwif->pdev;
  104. struct skb_frag_struct *frag;
  105. dma_addr_t dma_addr;
  106. int i, j;
  107. dma_addr = dma_map_single(&pdev->dev, skb->data, skb_headlen(skb),
  108. DMA_TO_DEVICE);
  109. if (dma_mapping_error(&pdev->dev, dma_addr)) {
  110. dev_err(&pdev->dev, "Failed to map Tx skb data\n");
  111. return -EFAULT;
  112. }
  113. hinic_set_sge(&sges[0], dma_addr, skb_headlen(skb));
  114. for (i = 0 ; i < skb_shinfo(skb)->nr_frags; i++) {
  115. frag = &skb_shinfo(skb)->frags[i];
  116. dma_addr = skb_frag_dma_map(&pdev->dev, frag, 0,
  117. skb_frag_size(frag),
  118. DMA_TO_DEVICE);
  119. if (dma_mapping_error(&pdev->dev, dma_addr)) {
  120. dev_err(&pdev->dev, "Failed to map Tx skb frag\n");
  121. goto err_tx_map;
  122. }
  123. hinic_set_sge(&sges[i + 1], dma_addr, skb_frag_size(frag));
  124. }
  125. return 0;
  126. err_tx_map:
  127. for (j = 0; j < i; j++)
  128. dma_unmap_page(&pdev->dev, hinic_sge_to_dma(&sges[j + 1]),
  129. sges[j + 1].len, DMA_TO_DEVICE);
  130. dma_unmap_single(&pdev->dev, hinic_sge_to_dma(&sges[0]), sges[0].len,
  131. DMA_TO_DEVICE);
  132. return -EFAULT;
  133. }
  134. /**
  135. * tx_unmap_skb - unmap the dma address of the skb
  136. * @nic_dev: nic device
  137. * @skb: the skb
  138. * @sges: the sges that are connected to the skb
  139. **/
  140. static void tx_unmap_skb(struct hinic_dev *nic_dev, struct sk_buff *skb,
  141. struct hinic_sge *sges)
  142. {
  143. struct hinic_hwdev *hwdev = nic_dev->hwdev;
  144. struct hinic_hwif *hwif = hwdev->hwif;
  145. struct pci_dev *pdev = hwif->pdev;
  146. int i;
  147. for (i = 0; i < skb_shinfo(skb)->nr_frags ; i++)
  148. dma_unmap_page(&pdev->dev, hinic_sge_to_dma(&sges[i + 1]),
  149. sges[i + 1].len, DMA_TO_DEVICE);
  150. dma_unmap_single(&pdev->dev, hinic_sge_to_dma(&sges[0]), sges[0].len,
  151. DMA_TO_DEVICE);
  152. }
  153. netdev_tx_t hinic_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
  154. {
  155. struct hinic_dev *nic_dev = netdev_priv(netdev);
  156. struct netdev_queue *netdev_txq;
  157. int nr_sges, err = NETDEV_TX_OK;
  158. struct hinic_sq_wqe *sq_wqe;
  159. unsigned int wqe_size;
  160. struct hinic_txq *txq;
  161. struct hinic_qp *qp;
  162. u16 prod_idx;
  163. txq = &nic_dev->txqs[skb->queue_mapping];
  164. qp = container_of(txq->sq, struct hinic_qp, sq);
  165. if (skb->len < MIN_SKB_LEN) {
  166. if (skb_pad(skb, MIN_SKB_LEN - skb->len)) {
  167. netdev_err(netdev, "Failed to pad skb\n");
  168. goto update_error_stats;
  169. }
  170. skb->len = MIN_SKB_LEN;
  171. }
  172. nr_sges = skb_shinfo(skb)->nr_frags + 1;
  173. if (nr_sges > txq->max_sges) {
  174. netdev_err(netdev, "Too many Tx sges\n");
  175. goto skb_error;
  176. }
  177. err = tx_map_skb(nic_dev, skb, txq->sges);
  178. if (err)
  179. goto skb_error;
  180. wqe_size = HINIC_SQ_WQE_SIZE(nr_sges);
  181. sq_wqe = hinic_sq_get_wqe(txq->sq, wqe_size, &prod_idx);
  182. if (!sq_wqe) {
  183. netif_stop_subqueue(netdev, qp->q_id);
  184. /* Check for the case free_tx_poll is called in another cpu
  185. * and we stopped the subqueue after free_tx_poll check.
  186. */
  187. sq_wqe = hinic_sq_get_wqe(txq->sq, wqe_size, &prod_idx);
  188. if (sq_wqe) {
  189. netif_wake_subqueue(nic_dev->netdev, qp->q_id);
  190. goto process_sq_wqe;
  191. }
  192. tx_unmap_skb(nic_dev, skb, txq->sges);
  193. u64_stats_update_begin(&txq->txq_stats.syncp);
  194. txq->txq_stats.tx_busy++;
  195. u64_stats_update_end(&txq->txq_stats.syncp);
  196. err = NETDEV_TX_BUSY;
  197. goto flush_skbs;
  198. }
  199. process_sq_wqe:
  200. hinic_sq_prepare_wqe(txq->sq, prod_idx, sq_wqe, txq->sges, nr_sges);
  201. hinic_sq_write_wqe(txq->sq, prod_idx, sq_wqe, skb, wqe_size);
  202. flush_skbs:
  203. netdev_txq = netdev_get_tx_queue(netdev, skb->queue_mapping);
  204. if ((!skb->xmit_more) || (netif_xmit_stopped(netdev_txq)))
  205. hinic_sq_write_db(txq->sq, prod_idx, wqe_size, 0);
  206. return err;
  207. skb_error:
  208. dev_kfree_skb_any(skb);
  209. update_error_stats:
  210. u64_stats_update_begin(&txq->txq_stats.syncp);
  211. txq->txq_stats.tx_dropped++;
  212. u64_stats_update_end(&txq->txq_stats.syncp);
  213. return err;
  214. }
  215. /**
  216. * tx_free_skb - unmap and free skb
  217. * @nic_dev: nic device
  218. * @skb: the skb
  219. * @sges: the sges that are connected to the skb
  220. **/
  221. static void tx_free_skb(struct hinic_dev *nic_dev, struct sk_buff *skb,
  222. struct hinic_sge *sges)
  223. {
  224. tx_unmap_skb(nic_dev, skb, sges);
  225. dev_kfree_skb_any(skb);
  226. }
  227. /**
  228. * free_all_rx_skbs - free all skbs in tx queue
  229. * @txq: tx queue
  230. **/
  231. static void free_all_tx_skbs(struct hinic_txq *txq)
  232. {
  233. struct hinic_dev *nic_dev = netdev_priv(txq->netdev);
  234. struct hinic_sq *sq = txq->sq;
  235. struct hinic_sq_wqe *sq_wqe;
  236. unsigned int wqe_size;
  237. struct sk_buff *skb;
  238. int nr_sges;
  239. u16 ci;
  240. while ((sq_wqe = hinic_sq_read_wqe(sq, &skb, &wqe_size, &ci))) {
  241. nr_sges = skb_shinfo(skb)->nr_frags + 1;
  242. hinic_sq_get_sges(sq_wqe, txq->free_sges, nr_sges);
  243. hinic_sq_put_wqe(sq, wqe_size);
  244. tx_free_skb(nic_dev, skb, txq->free_sges);
  245. }
  246. }
  247. /**
  248. * free_tx_poll - free finished tx skbs in tx queue that connected to napi
  249. * @napi: napi
  250. * @budget: number of tx
  251. *
  252. * Return 0 - Success, negative - Failure
  253. **/
  254. static int free_tx_poll(struct napi_struct *napi, int budget)
  255. {
  256. struct hinic_txq *txq = container_of(napi, struct hinic_txq, napi);
  257. struct hinic_qp *qp = container_of(txq->sq, struct hinic_qp, sq);
  258. struct hinic_dev *nic_dev = netdev_priv(txq->netdev);
  259. struct netdev_queue *netdev_txq;
  260. struct hinic_sq *sq = txq->sq;
  261. struct hinic_wq *wq = sq->wq;
  262. struct hinic_sq_wqe *sq_wqe;
  263. unsigned int wqe_size;
  264. int nr_sges, pkts = 0;
  265. struct sk_buff *skb;
  266. u64 tx_bytes = 0;
  267. u16 hw_ci, sw_ci;
  268. do {
  269. hw_ci = HW_CONS_IDX(sq) & wq->mask;
  270. sq_wqe = hinic_sq_read_wqe(sq, &skb, &wqe_size, &sw_ci);
  271. if ((!sq_wqe) ||
  272. (((hw_ci - sw_ci) & wq->mask) * wq->wqebb_size < wqe_size))
  273. break;
  274. tx_bytes += skb->len;
  275. pkts++;
  276. nr_sges = skb_shinfo(skb)->nr_frags + 1;
  277. hinic_sq_get_sges(sq_wqe, txq->free_sges, nr_sges);
  278. hinic_sq_put_wqe(sq, wqe_size);
  279. tx_free_skb(nic_dev, skb, txq->free_sges);
  280. } while (pkts < budget);
  281. if (__netif_subqueue_stopped(nic_dev->netdev, qp->q_id) &&
  282. hinic_get_sq_free_wqebbs(sq) >= HINIC_MIN_TX_NUM_WQEBBS(sq)) {
  283. netdev_txq = netdev_get_tx_queue(txq->netdev, qp->q_id);
  284. __netif_tx_lock(netdev_txq, smp_processor_id());
  285. netif_wake_subqueue(nic_dev->netdev, qp->q_id);
  286. __netif_tx_unlock(netdev_txq);
  287. u64_stats_update_begin(&txq->txq_stats.syncp);
  288. txq->txq_stats.tx_wake++;
  289. u64_stats_update_end(&txq->txq_stats.syncp);
  290. }
  291. u64_stats_update_begin(&txq->txq_stats.syncp);
  292. txq->txq_stats.bytes += tx_bytes;
  293. txq->txq_stats.pkts += pkts;
  294. u64_stats_update_end(&txq->txq_stats.syncp);
  295. if (pkts < budget) {
  296. napi_complete(napi);
  297. enable_irq(sq->irq);
  298. return pkts;
  299. }
  300. return budget;
  301. }
  302. static void tx_napi_add(struct hinic_txq *txq, int weight)
  303. {
  304. netif_napi_add(txq->netdev, &txq->napi, free_tx_poll, weight);
  305. napi_enable(&txq->napi);
  306. }
  307. static void tx_napi_del(struct hinic_txq *txq)
  308. {
  309. napi_disable(&txq->napi);
  310. netif_napi_del(&txq->napi);
  311. }
  312. static irqreturn_t tx_irq(int irq, void *data)
  313. {
  314. struct hinic_txq *txq = data;
  315. struct hinic_dev *nic_dev;
  316. nic_dev = netdev_priv(txq->netdev);
  317. /* Disable the interrupt until napi will be completed */
  318. disable_irq_nosync(txq->sq->irq);
  319. hinic_hwdev_msix_cnt_set(nic_dev->hwdev, txq->sq->msix_entry);
  320. napi_schedule(&txq->napi);
  321. return IRQ_HANDLED;
  322. }
  323. static int tx_request_irq(struct hinic_txq *txq)
  324. {
  325. struct hinic_dev *nic_dev = netdev_priv(txq->netdev);
  326. struct hinic_hwdev *hwdev = nic_dev->hwdev;
  327. struct hinic_hwif *hwif = hwdev->hwif;
  328. struct pci_dev *pdev = hwif->pdev;
  329. struct hinic_sq *sq = txq->sq;
  330. int err;
  331. tx_napi_add(txq, nic_dev->tx_weight);
  332. hinic_hwdev_msix_set(nic_dev->hwdev, sq->msix_entry,
  333. TX_IRQ_NO_PENDING, TX_IRQ_NO_COALESC,
  334. TX_IRQ_NO_LLI_TIMER, TX_IRQ_NO_CREDIT,
  335. TX_IRQ_NO_RESEND_TIMER);
  336. err = request_irq(sq->irq, tx_irq, 0, txq->irq_name, txq);
  337. if (err) {
  338. dev_err(&pdev->dev, "Failed to request Tx irq\n");
  339. tx_napi_del(txq);
  340. return err;
  341. }
  342. return 0;
  343. }
  344. static void tx_free_irq(struct hinic_txq *txq)
  345. {
  346. struct hinic_sq *sq = txq->sq;
  347. free_irq(sq->irq, txq);
  348. tx_napi_del(txq);
  349. }
  350. /**
  351. * hinic_init_txq - Initialize the Tx Queue
  352. * @txq: Logical Tx Queue
  353. * @sq: Hardware Tx Queue to connect the Logical queue with
  354. * @netdev: network device to connect the Logical queue with
  355. *
  356. * Return 0 - Success, negative - Failure
  357. **/
  358. int hinic_init_txq(struct hinic_txq *txq, struct hinic_sq *sq,
  359. struct net_device *netdev)
  360. {
  361. struct hinic_qp *qp = container_of(sq, struct hinic_qp, sq);
  362. struct hinic_dev *nic_dev = netdev_priv(netdev);
  363. struct hinic_hwdev *hwdev = nic_dev->hwdev;
  364. int err, irqname_len;
  365. size_t sges_size;
  366. txq->netdev = netdev;
  367. txq->sq = sq;
  368. txq_stats_init(txq);
  369. txq->max_sges = HINIC_MAX_SQ_BUFDESCS;
  370. sges_size = txq->max_sges * sizeof(*txq->sges);
  371. txq->sges = devm_kzalloc(&netdev->dev, sges_size, GFP_KERNEL);
  372. if (!txq->sges)
  373. return -ENOMEM;
  374. sges_size = txq->max_sges * sizeof(*txq->free_sges);
  375. txq->free_sges = devm_kzalloc(&netdev->dev, sges_size, GFP_KERNEL);
  376. if (!txq->free_sges) {
  377. err = -ENOMEM;
  378. goto err_alloc_free_sges;
  379. }
  380. irqname_len = snprintf(NULL, 0, "hinic_txq%d", qp->q_id) + 1;
  381. txq->irq_name = devm_kzalloc(&netdev->dev, irqname_len, GFP_KERNEL);
  382. if (!txq->irq_name) {
  383. err = -ENOMEM;
  384. goto err_alloc_irqname;
  385. }
  386. sprintf(txq->irq_name, "hinic_txq%d", qp->q_id);
  387. err = hinic_hwdev_hw_ci_addr_set(hwdev, sq, CI_UPDATE_NO_PENDING,
  388. CI_UPDATE_NO_COALESC);
  389. if (err)
  390. goto err_hw_ci;
  391. err = tx_request_irq(txq);
  392. if (err) {
  393. netdev_err(netdev, "Failed to request Tx irq\n");
  394. goto err_req_tx_irq;
  395. }
  396. return 0;
  397. err_req_tx_irq:
  398. err_hw_ci:
  399. devm_kfree(&netdev->dev, txq->irq_name);
  400. err_alloc_irqname:
  401. devm_kfree(&netdev->dev, txq->free_sges);
  402. err_alloc_free_sges:
  403. devm_kfree(&netdev->dev, txq->sges);
  404. return err;
  405. }
  406. /**
  407. * hinic_clean_txq - Clean the Tx Queue
  408. * @txq: Logical Tx Queue
  409. **/
  410. void hinic_clean_txq(struct hinic_txq *txq)
  411. {
  412. struct net_device *netdev = txq->netdev;
  413. tx_free_irq(txq);
  414. free_all_tx_skbs(txq);
  415. devm_kfree(&netdev->dev, txq->irq_name);
  416. devm_kfree(&netdev->dev, txq->free_sges);
  417. devm_kfree(&netdev->dev, txq->sges);
  418. }