enic.h 8.2 KB

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  1. /*
  2. * Copyright 2008-2010 Cisco Systems, Inc. All rights reserved.
  3. * Copyright 2007 Nuova Systems, Inc. All rights reserved.
  4. *
  5. * This program is free software; you may redistribute it and/or modify
  6. * it under the terms of the GNU General Public License as published by
  7. * the Free Software Foundation; version 2 of the License.
  8. *
  9. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  10. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  11. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  12. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  13. * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  14. * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  15. * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  16. * SOFTWARE.
  17. *
  18. */
  19. #ifndef _ENIC_H_
  20. #define _ENIC_H_
  21. #include "vnic_enet.h"
  22. #include "vnic_dev.h"
  23. #include "vnic_wq.h"
  24. #include "vnic_rq.h"
  25. #include "vnic_cq.h"
  26. #include "vnic_intr.h"
  27. #include "vnic_stats.h"
  28. #include "vnic_nic.h"
  29. #include "vnic_rss.h"
  30. #include <linux/irq.h>
  31. #define DRV_NAME "enic"
  32. #define DRV_DESCRIPTION "Cisco VIC Ethernet NIC Driver"
  33. #define DRV_VERSION "2.3.0.53"
  34. #define DRV_COPYRIGHT "Copyright 2008-2013 Cisco Systems, Inc"
  35. #define ENIC_BARS_MAX 6
  36. #define ENIC_WQ_MAX 8
  37. #define ENIC_RQ_MAX 8
  38. #define ENIC_CQ_MAX (ENIC_WQ_MAX + ENIC_RQ_MAX)
  39. #define ENIC_INTR_MAX (ENIC_CQ_MAX + 2)
  40. #define ENIC_WQ_NAPI_BUDGET 256
  41. #define ENIC_AIC_LARGE_PKT_DIFF 3
  42. struct enic_msix_entry {
  43. int requested;
  44. char devname[IFNAMSIZ + 8];
  45. irqreturn_t (*isr)(int, void *);
  46. void *devid;
  47. cpumask_var_t affinity_mask;
  48. };
  49. /* Store only the lower range. Higher range is given by fw. */
  50. struct enic_intr_mod_range {
  51. u32 small_pkt_range_start;
  52. u32 large_pkt_range_start;
  53. };
  54. struct enic_intr_mod_table {
  55. u32 rx_rate;
  56. u32 range_percent;
  57. };
  58. #define ENIC_MAX_LINK_SPEEDS 3
  59. #define ENIC_LINK_SPEED_10G 10000
  60. #define ENIC_LINK_SPEED_4G 4000
  61. #define ENIC_LINK_40G_INDEX 2
  62. #define ENIC_LINK_10G_INDEX 1
  63. #define ENIC_LINK_4G_INDEX 0
  64. #define ENIC_RX_COALESCE_RANGE_END 125
  65. #define ENIC_AIC_TS_BREAK 100
  66. struct enic_rx_coal {
  67. u32 small_pkt_range_start;
  68. u32 large_pkt_range_start;
  69. u32 range_end;
  70. u32 use_adaptive_rx_coalesce;
  71. };
  72. /* priv_flags */
  73. #define ENIC_SRIOV_ENABLED (1 << 0)
  74. /* enic port profile set flags */
  75. #define ENIC_PORT_REQUEST_APPLIED (1 << 0)
  76. #define ENIC_SET_REQUEST (1 << 1)
  77. #define ENIC_SET_NAME (1 << 2)
  78. #define ENIC_SET_INSTANCE (1 << 3)
  79. #define ENIC_SET_HOST (1 << 4)
  80. struct enic_port_profile {
  81. u32 set;
  82. u8 request;
  83. char name[PORT_PROFILE_MAX];
  84. u8 instance_uuid[PORT_UUID_MAX];
  85. u8 host_uuid[PORT_UUID_MAX];
  86. u8 vf_mac[ETH_ALEN];
  87. u8 mac_addr[ETH_ALEN];
  88. };
  89. /* enic_rfs_fltr_node - rfs filter node in hash table
  90. * @@keys: IPv4 5 tuple
  91. * @flow_id: flow_id of clsf filter provided by kernel
  92. * @fltr_id: filter id of clsf filter returned by adaptor
  93. * @rq_id: desired rq index
  94. * @node: hlist_node
  95. */
  96. struct enic_rfs_fltr_node {
  97. struct flow_keys keys;
  98. u32 flow_id;
  99. u16 fltr_id;
  100. u16 rq_id;
  101. struct hlist_node node;
  102. };
  103. /* enic_rfs_flw_tbl - rfs flow table
  104. * @max: Maximum number of filters vNIC supports
  105. * @free: Number of free filters available
  106. * @toclean: hash table index to clean next
  107. * @ht_head: hash table list head
  108. * @lock: spin lock
  109. * @rfs_may_expire: timer function for enic_rps_may_expire_flow
  110. */
  111. struct enic_rfs_flw_tbl {
  112. u16 max;
  113. int free;
  114. #define ENIC_RFS_FLW_BITSHIFT (10)
  115. #define ENIC_RFS_FLW_MASK ((1 << ENIC_RFS_FLW_BITSHIFT) - 1)
  116. u16 toclean:ENIC_RFS_FLW_BITSHIFT;
  117. struct hlist_head ht_head[1 << ENIC_RFS_FLW_BITSHIFT];
  118. spinlock_t lock;
  119. struct timer_list rfs_may_expire;
  120. };
  121. struct vxlan_offload {
  122. u16 vxlan_udp_port_number;
  123. u8 patch_level;
  124. u8 flags;
  125. };
  126. /* Per-instance private data structure */
  127. struct enic {
  128. struct net_device *netdev;
  129. struct pci_dev *pdev;
  130. struct vnic_enet_config config;
  131. struct vnic_dev_bar bar[ENIC_BARS_MAX];
  132. struct vnic_dev *vdev;
  133. struct timer_list notify_timer;
  134. struct work_struct reset;
  135. struct work_struct tx_hang_reset;
  136. struct work_struct change_mtu_work;
  137. struct msix_entry msix_entry[ENIC_INTR_MAX];
  138. struct enic_msix_entry msix[ENIC_INTR_MAX];
  139. u32 msg_enable;
  140. spinlock_t devcmd_lock;
  141. u8 mac_addr[ETH_ALEN];
  142. unsigned int flags;
  143. unsigned int priv_flags;
  144. unsigned int mc_count;
  145. unsigned int uc_count;
  146. u32 port_mtu;
  147. struct enic_rx_coal rx_coalesce_setting;
  148. u32 rx_coalesce_usecs;
  149. u32 tx_coalesce_usecs;
  150. #ifdef CONFIG_PCI_IOV
  151. u16 num_vfs;
  152. #endif
  153. spinlock_t enic_api_lock;
  154. struct enic_port_profile *pp;
  155. /* work queue cache line section */
  156. ____cacheline_aligned struct vnic_wq wq[ENIC_WQ_MAX];
  157. spinlock_t wq_lock[ENIC_WQ_MAX];
  158. unsigned int wq_count;
  159. u16 loop_enable;
  160. u16 loop_tag;
  161. /* receive queue cache line section */
  162. ____cacheline_aligned struct vnic_rq rq[ENIC_RQ_MAX];
  163. unsigned int rq_count;
  164. struct vxlan_offload vxlan;
  165. u64 rq_truncated_pkts;
  166. u64 rq_bad_fcs;
  167. struct napi_struct napi[ENIC_RQ_MAX + ENIC_WQ_MAX];
  168. /* interrupt resource cache line section */
  169. ____cacheline_aligned struct vnic_intr intr[ENIC_INTR_MAX];
  170. unsigned int intr_count;
  171. u32 __iomem *legacy_pba; /* memory-mapped */
  172. /* completion queue cache line section */
  173. ____cacheline_aligned struct vnic_cq cq[ENIC_CQ_MAX];
  174. unsigned int cq_count;
  175. struct enic_rfs_flw_tbl rfs_h;
  176. u32 rx_copybreak;
  177. u8 rss_key[ENIC_RSS_LEN];
  178. struct vnic_gen_stats gen_stats;
  179. };
  180. static inline struct net_device *vnic_get_netdev(struct vnic_dev *vdev)
  181. {
  182. struct enic *enic = vdev->priv;
  183. return enic->netdev;
  184. }
  185. /* wrappers function for kernel log
  186. */
  187. #define vdev_err(vdev, fmt, ...) \
  188. dev_err(&(vdev)->pdev->dev, fmt, ##__VA_ARGS__)
  189. #define vdev_warn(vdev, fmt, ...) \
  190. dev_warn(&(vdev)->pdev->dev, fmt, ##__VA_ARGS__)
  191. #define vdev_info(vdev, fmt, ...) \
  192. dev_info(&(vdev)->pdev->dev, fmt, ##__VA_ARGS__)
  193. #define vdev_neterr(vdev, fmt, ...) \
  194. netdev_err(vnic_get_netdev(vdev), fmt, ##__VA_ARGS__)
  195. #define vdev_netwarn(vdev, fmt, ...) \
  196. netdev_warn(vnic_get_netdev(vdev), fmt, ##__VA_ARGS__)
  197. #define vdev_netinfo(vdev, fmt, ...) \
  198. netdev_info(vnic_get_netdev(vdev), fmt, ##__VA_ARGS__)
  199. static inline struct device *enic_get_dev(struct enic *enic)
  200. {
  201. return &(enic->pdev->dev);
  202. }
  203. static inline unsigned int enic_cq_rq(struct enic *enic, unsigned int rq)
  204. {
  205. return rq;
  206. }
  207. static inline unsigned int enic_cq_wq(struct enic *enic, unsigned int wq)
  208. {
  209. return enic->rq_count + wq;
  210. }
  211. static inline unsigned int enic_legacy_io_intr(void)
  212. {
  213. return 0;
  214. }
  215. static inline unsigned int enic_legacy_err_intr(void)
  216. {
  217. return 1;
  218. }
  219. static inline unsigned int enic_legacy_notify_intr(void)
  220. {
  221. return 2;
  222. }
  223. static inline unsigned int enic_msix_rq_intr(struct enic *enic,
  224. unsigned int rq)
  225. {
  226. return enic->cq[enic_cq_rq(enic, rq)].interrupt_offset;
  227. }
  228. static inline unsigned int enic_msix_wq_intr(struct enic *enic,
  229. unsigned int wq)
  230. {
  231. return enic->cq[enic_cq_wq(enic, wq)].interrupt_offset;
  232. }
  233. static inline unsigned int enic_msix_err_intr(struct enic *enic)
  234. {
  235. return enic->rq_count + enic->wq_count;
  236. }
  237. static inline unsigned int enic_msix_notify_intr(struct enic *enic)
  238. {
  239. return enic->rq_count + enic->wq_count + 1;
  240. }
  241. static inline bool enic_is_err_intr(struct enic *enic, int intr)
  242. {
  243. switch (vnic_dev_get_intr_mode(enic->vdev)) {
  244. case VNIC_DEV_INTR_MODE_INTX:
  245. return intr == enic_legacy_err_intr();
  246. case VNIC_DEV_INTR_MODE_MSIX:
  247. return intr == enic_msix_err_intr(enic);
  248. case VNIC_DEV_INTR_MODE_MSI:
  249. default:
  250. return false;
  251. }
  252. }
  253. static inline bool enic_is_notify_intr(struct enic *enic, int intr)
  254. {
  255. switch (vnic_dev_get_intr_mode(enic->vdev)) {
  256. case VNIC_DEV_INTR_MODE_INTX:
  257. return intr == enic_legacy_notify_intr();
  258. case VNIC_DEV_INTR_MODE_MSIX:
  259. return intr == enic_msix_notify_intr(enic);
  260. case VNIC_DEV_INTR_MODE_MSI:
  261. default:
  262. return false;
  263. }
  264. }
  265. static inline int enic_dma_map_check(struct enic *enic, dma_addr_t dma_addr)
  266. {
  267. if (unlikely(pci_dma_mapping_error(enic->pdev, dma_addr))) {
  268. net_warn_ratelimited("%s: PCI dma mapping failed!\n",
  269. enic->netdev->name);
  270. enic->gen_stats.dma_map_error++;
  271. return -ENOMEM;
  272. }
  273. return 0;
  274. }
  275. void enic_reset_addr_lists(struct enic *enic);
  276. int enic_sriov_enabled(struct enic *enic);
  277. int enic_is_valid_vf(struct enic *enic, int vf);
  278. int enic_is_dynamic(struct enic *enic);
  279. void enic_set_ethtool_ops(struct net_device *netdev);
  280. int __enic_set_rsskey(struct enic *enic);
  281. #endif /* _ENIC_H_ */