xsurf100.c 11 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382
  1. // SPDX-License-Identifier: GPL-2.0
  2. #include <linux/module.h>
  3. #include <linux/netdevice.h>
  4. #include <linux/platform_device.h>
  5. #include <linux/zorro.h>
  6. #include <net/ax88796.h>
  7. #include <asm/amigaints.h>
  8. #define ZORRO_PROD_INDIVIDUAL_COMPUTERS_X_SURF100 \
  9. ZORRO_ID(INDIVIDUAL_COMPUTERS, 0x64, 0)
  10. #define XS100_IRQSTATUS_BASE 0x40
  11. #define XS100_8390_BASE 0x800
  12. /* Longword-access area. Translated to 2 16-bit access cycles by the
  13. * X-Surf 100 FPGA
  14. */
  15. #define XS100_8390_DATA32_BASE 0x8000
  16. #define XS100_8390_DATA32_SIZE 0x2000
  17. /* Sub-Areas for fast data register access; addresses relative to area begin */
  18. #define XS100_8390_DATA_READ32_BASE 0x0880
  19. #define XS100_8390_DATA_WRITE32_BASE 0x0C80
  20. #define XS100_8390_DATA_AREA_SIZE 0x80
  21. #define __NS8390_init ax_NS8390_init
  22. /* force unsigned long back to 'void __iomem *' */
  23. #define ax_convert_addr(_a) ((void __force __iomem *)(_a))
  24. #define ei_inb(_a) z_readb(ax_convert_addr(_a))
  25. #define ei_outb(_v, _a) z_writeb(_v, ax_convert_addr(_a))
  26. #define ei_inw(_a) z_readw(ax_convert_addr(_a))
  27. #define ei_outw(_v, _a) z_writew(_v, ax_convert_addr(_a))
  28. #define ei_inb_p(_a) ei_inb(_a)
  29. #define ei_outb_p(_v, _a) ei_outb(_v, _a)
  30. /* define EI_SHIFT() to take into account our register offsets */
  31. #define EI_SHIFT(x) (ei_local->reg_offset[(x)])
  32. /* Ensure we have our RCR base value */
  33. #define AX88796_PLATFORM
  34. static unsigned char version[] =
  35. "ax88796.c: Copyright 2005,2007 Simtec Electronics\n";
  36. #include "lib8390.c"
  37. /* from ne.c */
  38. #define NE_CMD EI_SHIFT(0x00)
  39. #define NE_RESET EI_SHIFT(0x1f)
  40. #define NE_DATAPORT EI_SHIFT(0x10)
  41. struct xsurf100_ax_plat_data {
  42. struct ax_plat_data ax;
  43. void __iomem *base_regs;
  44. void __iomem *data_area;
  45. };
  46. static int is_xsurf100_network_irq(struct platform_device *pdev)
  47. {
  48. struct xsurf100_ax_plat_data *xs100 = dev_get_platdata(&pdev->dev);
  49. return (readw(xs100->base_regs + XS100_IRQSTATUS_BASE) & 0xaaaa) != 0;
  50. }
  51. /* These functions guarantee that the iomem is accessed with 32 bit
  52. * cycles only. z_memcpy_fromio / z_memcpy_toio don't
  53. */
  54. static void z_memcpy_fromio32(void *dst, const void __iomem *src, size_t bytes)
  55. {
  56. while (bytes > 32) {
  57. asm __volatile__
  58. ("movem.l (%0)+,%%d0-%%d7\n"
  59. "movem.l %%d0-%%d7,(%1)\n"
  60. "adda.l #32,%1" : "=a"(src), "=a"(dst)
  61. : "0"(src), "1"(dst) : "d0", "d1", "d2", "d3", "d4",
  62. "d5", "d6", "d7", "memory");
  63. bytes -= 32;
  64. }
  65. while (bytes) {
  66. *(uint32_t *)dst = z_readl(src);
  67. src += 4;
  68. dst += 4;
  69. bytes -= 4;
  70. }
  71. }
  72. static void z_memcpy_toio32(void __iomem *dst, const void *src, size_t bytes)
  73. {
  74. while (bytes) {
  75. z_writel(*(const uint32_t *)src, dst);
  76. src += 4;
  77. dst += 4;
  78. bytes -= 4;
  79. }
  80. }
  81. static void xs100_write(struct net_device *dev, const void *src,
  82. unsigned int count)
  83. {
  84. struct ei_device *ei_local = netdev_priv(dev);
  85. struct platform_device *pdev = to_platform_device(dev->dev.parent);
  86. struct xsurf100_ax_plat_data *xs100 = dev_get_platdata(&pdev->dev);
  87. /* copy whole blocks */
  88. while (count > XS100_8390_DATA_AREA_SIZE) {
  89. z_memcpy_toio32(xs100->data_area +
  90. XS100_8390_DATA_WRITE32_BASE, src,
  91. XS100_8390_DATA_AREA_SIZE);
  92. src += XS100_8390_DATA_AREA_SIZE;
  93. count -= XS100_8390_DATA_AREA_SIZE;
  94. }
  95. /* copy whole dwords */
  96. z_memcpy_toio32(xs100->data_area + XS100_8390_DATA_WRITE32_BASE,
  97. src, count & ~3);
  98. src += count & ~3;
  99. if (count & 2) {
  100. ei_outw(*(uint16_t *)src, ei_local->mem + NE_DATAPORT);
  101. src += 2;
  102. }
  103. if (count & 1)
  104. ei_outb(*(uint8_t *)src, ei_local->mem + NE_DATAPORT);
  105. }
  106. static void xs100_read(struct net_device *dev, void *dst, unsigned int count)
  107. {
  108. struct ei_device *ei_local = netdev_priv(dev);
  109. struct platform_device *pdev = to_platform_device(dev->dev.parent);
  110. struct xsurf100_ax_plat_data *xs100 = dev_get_platdata(&pdev->dev);
  111. /* copy whole blocks */
  112. while (count > XS100_8390_DATA_AREA_SIZE) {
  113. z_memcpy_fromio32(dst, xs100->data_area +
  114. XS100_8390_DATA_READ32_BASE,
  115. XS100_8390_DATA_AREA_SIZE);
  116. dst += XS100_8390_DATA_AREA_SIZE;
  117. count -= XS100_8390_DATA_AREA_SIZE;
  118. }
  119. /* copy whole dwords */
  120. z_memcpy_fromio32(dst, xs100->data_area + XS100_8390_DATA_READ32_BASE,
  121. count & ~3);
  122. dst += count & ~3;
  123. if (count & 2) {
  124. *(uint16_t *)dst = ei_inw(ei_local->mem + NE_DATAPORT);
  125. dst += 2;
  126. }
  127. if (count & 1)
  128. *(uint8_t *)dst = ei_inb(ei_local->mem + NE_DATAPORT);
  129. }
  130. /* Block input and output, similar to the Crynwr packet driver. If
  131. * you are porting to a new ethercard, look at the packet driver
  132. * source for hints. The NEx000 doesn't share the on-board packet
  133. * memory -- you have to put the packet out through the "remote DMA"
  134. * dataport using ei_outb.
  135. */
  136. static void xs100_block_input(struct net_device *dev, int count,
  137. struct sk_buff *skb, int ring_offset)
  138. {
  139. struct ei_device *ei_local = netdev_priv(dev);
  140. void __iomem *nic_base = ei_local->mem;
  141. char *buf = skb->data;
  142. if (ei_local->dmaing) {
  143. netdev_err(dev,
  144. "DMAing conflict in %s [DMAstat:%d][irqlock:%d]\n",
  145. __func__,
  146. ei_local->dmaing, ei_local->irqlock);
  147. return;
  148. }
  149. ei_local->dmaing |= 0x01;
  150. ei_outb(E8390_NODMA + E8390_PAGE0 + E8390_START, nic_base + NE_CMD);
  151. ei_outb(count & 0xff, nic_base + EN0_RCNTLO);
  152. ei_outb(count >> 8, nic_base + EN0_RCNTHI);
  153. ei_outb(ring_offset & 0xff, nic_base + EN0_RSARLO);
  154. ei_outb(ring_offset >> 8, nic_base + EN0_RSARHI);
  155. ei_outb(E8390_RREAD + E8390_START, nic_base + NE_CMD);
  156. xs100_read(dev, buf, count);
  157. ei_local->dmaing &= ~1;
  158. }
  159. static void xs100_block_output(struct net_device *dev, int count,
  160. const unsigned char *buf, const int start_page)
  161. {
  162. struct ei_device *ei_local = netdev_priv(dev);
  163. void __iomem *nic_base = ei_local->mem;
  164. unsigned long dma_start;
  165. /* Round the count up for word writes. Do we need to do this?
  166. * What effect will an odd byte count have on the 8390? I
  167. * should check someday.
  168. */
  169. if (ei_local->word16 && (count & 0x01))
  170. count++;
  171. /* This *shouldn't* happen. If it does, it's the last thing
  172. * you'll see
  173. */
  174. if (ei_local->dmaing) {
  175. netdev_err(dev,
  176. "DMAing conflict in %s [DMAstat:%d][irqlock:%d]\n",
  177. __func__,
  178. ei_local->dmaing, ei_local->irqlock);
  179. return;
  180. }
  181. ei_local->dmaing |= 0x01;
  182. /* We should already be in page 0, but to be safe... */
  183. ei_outb(E8390_PAGE0 + E8390_START + E8390_NODMA, nic_base + NE_CMD);
  184. ei_outb(ENISR_RDC, nic_base + EN0_ISR);
  185. /* Now the normal output. */
  186. ei_outb(count & 0xff, nic_base + EN0_RCNTLO);
  187. ei_outb(count >> 8, nic_base + EN0_RCNTHI);
  188. ei_outb(0x00, nic_base + EN0_RSARLO);
  189. ei_outb(start_page, nic_base + EN0_RSARHI);
  190. ei_outb(E8390_RWRITE + E8390_START, nic_base + NE_CMD);
  191. xs100_write(dev, buf, count);
  192. dma_start = jiffies;
  193. while ((ei_inb(nic_base + EN0_ISR) & ENISR_RDC) == 0) {
  194. if (jiffies - dma_start > 2 * HZ / 100) { /* 20ms */
  195. netdev_warn(dev, "timeout waiting for Tx RDC.\n");
  196. ei_local->reset_8390(dev);
  197. ax_NS8390_init(dev, 1);
  198. break;
  199. }
  200. }
  201. ei_outb(ENISR_RDC, nic_base + EN0_ISR); /* Ack intr. */
  202. ei_local->dmaing &= ~0x01;
  203. }
  204. static int xsurf100_probe(struct zorro_dev *zdev,
  205. const struct zorro_device_id *ent)
  206. {
  207. struct platform_device *pdev;
  208. struct xsurf100_ax_plat_data ax88796_data;
  209. struct resource res[2] = {
  210. DEFINE_RES_NAMED(IRQ_AMIGA_PORTS, 1, NULL,
  211. IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE),
  212. DEFINE_RES_MEM(zdev->resource.start + XS100_8390_BASE,
  213. 4 * 0x20)
  214. };
  215. int reg;
  216. /* This table is referenced in the device structure, so it must
  217. * outlive the scope of xsurf100_probe.
  218. */
  219. static u32 reg_offsets[32];
  220. int ret = 0;
  221. /* X-Surf 100 control and 32 bit ring buffer data access areas.
  222. * These resources are not used by the ax88796 driver, so must
  223. * be requested here and passed via platform data.
  224. */
  225. if (!request_mem_region(zdev->resource.start, 0x100, zdev->name)) {
  226. dev_err(&zdev->dev, "cannot reserve X-Surf 100 control registers\n");
  227. return -ENXIO;
  228. }
  229. if (!request_mem_region(zdev->resource.start +
  230. XS100_8390_DATA32_BASE,
  231. XS100_8390_DATA32_SIZE,
  232. "X-Surf 100 32-bit data access")) {
  233. dev_err(&zdev->dev, "cannot reserve 32-bit area\n");
  234. ret = -ENXIO;
  235. goto exit_req;
  236. }
  237. for (reg = 0; reg < 0x20; reg++)
  238. reg_offsets[reg] = 4 * reg;
  239. memset(&ax88796_data, 0, sizeof(ax88796_data));
  240. ax88796_data.ax.flags = AXFLG_HAS_EEPROM;
  241. ax88796_data.ax.wordlength = 2;
  242. ax88796_data.ax.dcr_val = 0x48;
  243. ax88796_data.ax.rcr_val = 0x40;
  244. ax88796_data.ax.reg_offsets = reg_offsets;
  245. ax88796_data.ax.check_irq = is_xsurf100_network_irq;
  246. ax88796_data.base_regs = ioremap(zdev->resource.start, 0x100);
  247. /* error handling for ioremap regs */
  248. if (!ax88796_data.base_regs) {
  249. dev_err(&zdev->dev, "Cannot ioremap area %pR (registers)\n",
  250. &zdev->resource);
  251. ret = -ENXIO;
  252. goto exit_req2;
  253. }
  254. ax88796_data.data_area = ioremap(zdev->resource.start +
  255. XS100_8390_DATA32_BASE, XS100_8390_DATA32_SIZE);
  256. /* error handling for ioremap data */
  257. if (!ax88796_data.data_area) {
  258. dev_err(&zdev->dev,
  259. "Cannot ioremap area %pR offset %x (32-bit access)\n",
  260. &zdev->resource, XS100_8390_DATA32_BASE);
  261. ret = -ENXIO;
  262. goto exit_mem;
  263. }
  264. ax88796_data.ax.block_output = xs100_block_output;
  265. ax88796_data.ax.block_input = xs100_block_input;
  266. pdev = platform_device_register_resndata(&zdev->dev, "ax88796",
  267. zdev->slotaddr, res, 2,
  268. &ax88796_data,
  269. sizeof(ax88796_data));
  270. if (IS_ERR(pdev)) {
  271. dev_err(&zdev->dev, "cannot register platform device\n");
  272. ret = -ENXIO;
  273. goto exit_mem2;
  274. }
  275. zorro_set_drvdata(zdev, pdev);
  276. if (!ret)
  277. return 0;
  278. exit_mem2:
  279. iounmap(ax88796_data.data_area);
  280. exit_mem:
  281. iounmap(ax88796_data.base_regs);
  282. exit_req2:
  283. release_mem_region(zdev->resource.start + XS100_8390_DATA32_BASE,
  284. XS100_8390_DATA32_SIZE);
  285. exit_req:
  286. release_mem_region(zdev->resource.start, 0x100);
  287. return ret;
  288. }
  289. static void xsurf100_remove(struct zorro_dev *zdev)
  290. {
  291. struct platform_device *pdev = zorro_get_drvdata(zdev);
  292. struct xsurf100_ax_plat_data *xs100 = dev_get_platdata(&pdev->dev);
  293. platform_device_unregister(pdev);
  294. iounmap(xs100->base_regs);
  295. release_mem_region(zdev->resource.start, 0x100);
  296. iounmap(xs100->data_area);
  297. release_mem_region(zdev->resource.start + XS100_8390_DATA32_BASE,
  298. XS100_8390_DATA32_SIZE);
  299. }
  300. static const struct zorro_device_id xsurf100_zorro_tbl[] = {
  301. { ZORRO_PROD_INDIVIDUAL_COMPUTERS_X_SURF100, },
  302. { 0 }
  303. };
  304. MODULE_DEVICE_TABLE(zorro, xsurf100_zorro_tbl);
  305. static struct zorro_driver xsurf100_driver = {
  306. .name = "xsurf100",
  307. .id_table = xsurf100_zorro_tbl,
  308. .probe = xsurf100_probe,
  309. .remove = xsurf100_remove,
  310. };
  311. module_driver(xsurf100_driver, zorro_register_driver, zorro_unregister_driver);
  312. MODULE_DESCRIPTION("X-Surf 100 driver");
  313. MODULE_AUTHOR("Michael Karcher <kernel@mkarcher.dialup.fu-berlin.de>");
  314. MODULE_LICENSE("GPL v2");