fsl_ifc_nand.c 31 KB

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  1. /*
  2. * Freescale Integrated Flash Controller NAND driver
  3. *
  4. * Copyright 2011-2012 Freescale Semiconductor, Inc
  5. *
  6. * Author: Dipen Dudhat <Dipen.Dudhat@freescale.com>
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License as published by
  10. * the Free Software Foundation; either version 2 of the License, or
  11. * (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  21. */
  22. #include <linux/module.h>
  23. #include <linux/types.h>
  24. #include <linux/kernel.h>
  25. #include <linux/of_address.h>
  26. #include <linux/slab.h>
  27. #include <linux/mtd/mtd.h>
  28. #include <linux/mtd/rawnand.h>
  29. #include <linux/mtd/partitions.h>
  30. #include <linux/mtd/nand_ecc.h>
  31. #include <linux/fsl_ifc.h>
  32. #define ERR_BYTE 0xFF /* Value returned for read
  33. bytes when read failed */
  34. #define IFC_TIMEOUT_MSECS 500 /* Maximum number of mSecs to wait
  35. for IFC NAND Machine */
  36. struct fsl_ifc_ctrl;
  37. /* mtd information per set */
  38. struct fsl_ifc_mtd {
  39. struct nand_chip chip;
  40. struct fsl_ifc_ctrl *ctrl;
  41. struct device *dev;
  42. int bank; /* Chip select bank number */
  43. unsigned int bufnum_mask; /* bufnum = page & bufnum_mask */
  44. u8 __iomem *vbase; /* Chip select base virtual address */
  45. };
  46. /* overview of the fsl ifc controller */
  47. struct fsl_ifc_nand_ctrl {
  48. struct nand_hw_control controller;
  49. struct fsl_ifc_mtd *chips[FSL_IFC_BANK_COUNT];
  50. void __iomem *addr; /* Address of assigned IFC buffer */
  51. unsigned int page; /* Last page written to / read from */
  52. unsigned int read_bytes;/* Number of bytes read during command */
  53. unsigned int column; /* Saved column from SEQIN */
  54. unsigned int index; /* Pointer to next byte to 'read' */
  55. unsigned int oob; /* Non zero if operating on OOB data */
  56. unsigned int eccread; /* Non zero for a full-page ECC read */
  57. unsigned int counter; /* counter for the initializations */
  58. unsigned int max_bitflips; /* Saved during READ0 cmd */
  59. };
  60. static struct fsl_ifc_nand_ctrl *ifc_nand_ctrl;
  61. /*
  62. * Generic flash bbt descriptors
  63. */
  64. static u8 bbt_pattern[] = {'B', 'b', 't', '0' };
  65. static u8 mirror_pattern[] = {'1', 't', 'b', 'B' };
  66. static struct nand_bbt_descr bbt_main_descr = {
  67. .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
  68. NAND_BBT_2BIT | NAND_BBT_VERSION,
  69. .offs = 2, /* 0 on 8-bit small page */
  70. .len = 4,
  71. .veroffs = 6,
  72. .maxblocks = 4,
  73. .pattern = bbt_pattern,
  74. };
  75. static struct nand_bbt_descr bbt_mirror_descr = {
  76. .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
  77. NAND_BBT_2BIT | NAND_BBT_VERSION,
  78. .offs = 2, /* 0 on 8-bit small page */
  79. .len = 4,
  80. .veroffs = 6,
  81. .maxblocks = 4,
  82. .pattern = mirror_pattern,
  83. };
  84. static int fsl_ifc_ooblayout_ecc(struct mtd_info *mtd, int section,
  85. struct mtd_oob_region *oobregion)
  86. {
  87. struct nand_chip *chip = mtd_to_nand(mtd);
  88. if (section)
  89. return -ERANGE;
  90. oobregion->offset = 8;
  91. oobregion->length = chip->ecc.total;
  92. return 0;
  93. }
  94. static int fsl_ifc_ooblayout_free(struct mtd_info *mtd, int section,
  95. struct mtd_oob_region *oobregion)
  96. {
  97. struct nand_chip *chip = mtd_to_nand(mtd);
  98. if (section > 1)
  99. return -ERANGE;
  100. if (mtd->writesize == 512 &&
  101. !(chip->options & NAND_BUSWIDTH_16)) {
  102. if (!section) {
  103. oobregion->offset = 0;
  104. oobregion->length = 5;
  105. } else {
  106. oobregion->offset = 6;
  107. oobregion->length = 2;
  108. }
  109. return 0;
  110. }
  111. if (!section) {
  112. oobregion->offset = 2;
  113. oobregion->length = 6;
  114. } else {
  115. oobregion->offset = chip->ecc.total + 8;
  116. oobregion->length = mtd->oobsize - oobregion->offset;
  117. }
  118. return 0;
  119. }
  120. static const struct mtd_ooblayout_ops fsl_ifc_ooblayout_ops = {
  121. .ecc = fsl_ifc_ooblayout_ecc,
  122. .free = fsl_ifc_ooblayout_free,
  123. };
  124. /*
  125. * Set up the IFC hardware block and page address fields, and the ifc nand
  126. * structure addr field to point to the correct IFC buffer in memory
  127. */
  128. static void set_addr(struct mtd_info *mtd, int column, int page_addr, int oob)
  129. {
  130. struct nand_chip *chip = mtd_to_nand(mtd);
  131. struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
  132. struct fsl_ifc_ctrl *ctrl = priv->ctrl;
  133. struct fsl_ifc_runtime __iomem *ifc = ctrl->rregs;
  134. int buf_num;
  135. ifc_nand_ctrl->page = page_addr;
  136. /* Program ROW0/COL0 */
  137. ifc_out32(page_addr, &ifc->ifc_nand.row0);
  138. ifc_out32((oob ? IFC_NAND_COL_MS : 0) | column, &ifc->ifc_nand.col0);
  139. buf_num = page_addr & priv->bufnum_mask;
  140. ifc_nand_ctrl->addr = priv->vbase + buf_num * (mtd->writesize * 2);
  141. ifc_nand_ctrl->index = column;
  142. /* for OOB data point to the second half of the buffer */
  143. if (oob)
  144. ifc_nand_ctrl->index += mtd->writesize;
  145. }
  146. /* returns nonzero if entire page is blank */
  147. static int check_read_ecc(struct mtd_info *mtd, struct fsl_ifc_ctrl *ctrl,
  148. u32 eccstat, unsigned int bufnum)
  149. {
  150. return (eccstat >> ((3 - bufnum % 4) * 8)) & 15;
  151. }
  152. /*
  153. * execute IFC NAND command and wait for it to complete
  154. */
  155. static void fsl_ifc_run_command(struct mtd_info *mtd)
  156. {
  157. struct nand_chip *chip = mtd_to_nand(mtd);
  158. struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
  159. struct fsl_ifc_ctrl *ctrl = priv->ctrl;
  160. struct fsl_ifc_nand_ctrl *nctrl = ifc_nand_ctrl;
  161. struct fsl_ifc_runtime __iomem *ifc = ctrl->rregs;
  162. u32 eccstat;
  163. int i;
  164. /* set the chip select for NAND Transaction */
  165. ifc_out32(priv->bank << IFC_NAND_CSEL_SHIFT,
  166. &ifc->ifc_nand.nand_csel);
  167. dev_vdbg(priv->dev,
  168. "%s: fir0=%08x fcr0=%08x\n",
  169. __func__,
  170. ifc_in32(&ifc->ifc_nand.nand_fir0),
  171. ifc_in32(&ifc->ifc_nand.nand_fcr0));
  172. ctrl->nand_stat = 0;
  173. /* start read/write seq */
  174. ifc_out32(IFC_NAND_SEQ_STRT_FIR_STRT, &ifc->ifc_nand.nandseq_strt);
  175. /* wait for command complete flag or timeout */
  176. wait_event_timeout(ctrl->nand_wait, ctrl->nand_stat,
  177. msecs_to_jiffies(IFC_TIMEOUT_MSECS));
  178. /* ctrl->nand_stat will be updated from IRQ context */
  179. if (!ctrl->nand_stat)
  180. dev_err(priv->dev, "Controller is not responding\n");
  181. if (ctrl->nand_stat & IFC_NAND_EVTER_STAT_FTOER)
  182. dev_err(priv->dev, "NAND Flash Timeout Error\n");
  183. if (ctrl->nand_stat & IFC_NAND_EVTER_STAT_WPER)
  184. dev_err(priv->dev, "NAND Flash Write Protect Error\n");
  185. nctrl->max_bitflips = 0;
  186. if (nctrl->eccread) {
  187. int errors;
  188. int bufnum = nctrl->page & priv->bufnum_mask;
  189. int sector_start = bufnum * chip->ecc.steps;
  190. int sector_end = sector_start + chip->ecc.steps - 1;
  191. __be32 *eccstat_regs;
  192. eccstat_regs = ifc->ifc_nand.nand_eccstat;
  193. eccstat = ifc_in32(&eccstat_regs[sector_start / 4]);
  194. for (i = sector_start; i <= sector_end; i++) {
  195. if (i != sector_start && !(i % 4))
  196. eccstat = ifc_in32(&eccstat_regs[i / 4]);
  197. errors = check_read_ecc(mtd, ctrl, eccstat, i);
  198. if (errors == 15) {
  199. /*
  200. * Uncorrectable error.
  201. * We'll check for blank pages later.
  202. *
  203. * We disable ECCER reporting due to...
  204. * erratum IFC-A002770 -- so report it now if we
  205. * see an uncorrectable error in ECCSTAT.
  206. */
  207. ctrl->nand_stat |= IFC_NAND_EVTER_STAT_ECCER;
  208. continue;
  209. }
  210. mtd->ecc_stats.corrected += errors;
  211. nctrl->max_bitflips = max_t(unsigned int,
  212. nctrl->max_bitflips,
  213. errors);
  214. }
  215. nctrl->eccread = 0;
  216. }
  217. }
  218. static void fsl_ifc_do_read(struct nand_chip *chip,
  219. int oob,
  220. struct mtd_info *mtd)
  221. {
  222. struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
  223. struct fsl_ifc_ctrl *ctrl = priv->ctrl;
  224. struct fsl_ifc_runtime __iomem *ifc = ctrl->rregs;
  225. /* Program FIR/IFC_NAND_FCR0 for Small/Large page */
  226. if (mtd->writesize > 512) {
  227. ifc_out32((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
  228. (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
  229. (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) |
  230. (IFC_FIR_OP_CMD1 << IFC_NAND_FIR0_OP3_SHIFT) |
  231. (IFC_FIR_OP_RBCD << IFC_NAND_FIR0_OP4_SHIFT),
  232. &ifc->ifc_nand.nand_fir0);
  233. ifc_out32(0x0, &ifc->ifc_nand.nand_fir1);
  234. ifc_out32((NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT) |
  235. (NAND_CMD_READSTART << IFC_NAND_FCR0_CMD1_SHIFT),
  236. &ifc->ifc_nand.nand_fcr0);
  237. } else {
  238. ifc_out32((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
  239. (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
  240. (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) |
  241. (IFC_FIR_OP_RBCD << IFC_NAND_FIR0_OP3_SHIFT),
  242. &ifc->ifc_nand.nand_fir0);
  243. ifc_out32(0x0, &ifc->ifc_nand.nand_fir1);
  244. if (oob)
  245. ifc_out32(NAND_CMD_READOOB <<
  246. IFC_NAND_FCR0_CMD0_SHIFT,
  247. &ifc->ifc_nand.nand_fcr0);
  248. else
  249. ifc_out32(NAND_CMD_READ0 <<
  250. IFC_NAND_FCR0_CMD0_SHIFT,
  251. &ifc->ifc_nand.nand_fcr0);
  252. }
  253. }
  254. /* cmdfunc send commands to the IFC NAND Machine */
  255. static void fsl_ifc_cmdfunc(struct mtd_info *mtd, unsigned int command,
  256. int column, int page_addr) {
  257. struct nand_chip *chip = mtd_to_nand(mtd);
  258. struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
  259. struct fsl_ifc_ctrl *ctrl = priv->ctrl;
  260. struct fsl_ifc_runtime __iomem *ifc = ctrl->rregs;
  261. /* clear the read buffer */
  262. ifc_nand_ctrl->read_bytes = 0;
  263. if (command != NAND_CMD_PAGEPROG)
  264. ifc_nand_ctrl->index = 0;
  265. switch (command) {
  266. /* READ0 read the entire buffer to use hardware ECC. */
  267. case NAND_CMD_READ0:
  268. ifc_out32(0, &ifc->ifc_nand.nand_fbcr);
  269. set_addr(mtd, 0, page_addr, 0);
  270. ifc_nand_ctrl->read_bytes = mtd->writesize + mtd->oobsize;
  271. ifc_nand_ctrl->index += column;
  272. if (chip->ecc.mode == NAND_ECC_HW)
  273. ifc_nand_ctrl->eccread = 1;
  274. fsl_ifc_do_read(chip, 0, mtd);
  275. fsl_ifc_run_command(mtd);
  276. return;
  277. /* READOOB reads only the OOB because no ECC is performed. */
  278. case NAND_CMD_READOOB:
  279. ifc_out32(mtd->oobsize - column, &ifc->ifc_nand.nand_fbcr);
  280. set_addr(mtd, column, page_addr, 1);
  281. ifc_nand_ctrl->read_bytes = mtd->writesize + mtd->oobsize;
  282. fsl_ifc_do_read(chip, 1, mtd);
  283. fsl_ifc_run_command(mtd);
  284. return;
  285. case NAND_CMD_READID:
  286. case NAND_CMD_PARAM: {
  287. /*
  288. * For READID, read 8 bytes that are currently used.
  289. * For PARAM, read all 3 copies of 256-bytes pages.
  290. */
  291. int len = 8;
  292. int timing = IFC_FIR_OP_RB;
  293. if (command == NAND_CMD_PARAM) {
  294. timing = IFC_FIR_OP_RBCD;
  295. len = 256 * 3;
  296. }
  297. ifc_out32((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
  298. (IFC_FIR_OP_UA << IFC_NAND_FIR0_OP1_SHIFT) |
  299. (timing << IFC_NAND_FIR0_OP2_SHIFT),
  300. &ifc->ifc_nand.nand_fir0);
  301. ifc_out32(command << IFC_NAND_FCR0_CMD0_SHIFT,
  302. &ifc->ifc_nand.nand_fcr0);
  303. ifc_out32(column, &ifc->ifc_nand.row3);
  304. ifc_out32(len, &ifc->ifc_nand.nand_fbcr);
  305. ifc_nand_ctrl->read_bytes = len;
  306. set_addr(mtd, 0, 0, 0);
  307. fsl_ifc_run_command(mtd);
  308. return;
  309. }
  310. /* ERASE1 stores the block and page address */
  311. case NAND_CMD_ERASE1:
  312. set_addr(mtd, 0, page_addr, 0);
  313. return;
  314. /* ERASE2 uses the block and page address from ERASE1 */
  315. case NAND_CMD_ERASE2:
  316. ifc_out32((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
  317. (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP1_SHIFT) |
  318. (IFC_FIR_OP_CMD1 << IFC_NAND_FIR0_OP2_SHIFT),
  319. &ifc->ifc_nand.nand_fir0);
  320. ifc_out32((NAND_CMD_ERASE1 << IFC_NAND_FCR0_CMD0_SHIFT) |
  321. (NAND_CMD_ERASE2 << IFC_NAND_FCR0_CMD1_SHIFT),
  322. &ifc->ifc_nand.nand_fcr0);
  323. ifc_out32(0, &ifc->ifc_nand.nand_fbcr);
  324. ifc_nand_ctrl->read_bytes = 0;
  325. fsl_ifc_run_command(mtd);
  326. return;
  327. /* SEQIN sets up the addr buffer and all registers except the length */
  328. case NAND_CMD_SEQIN: {
  329. u32 nand_fcr0;
  330. ifc_nand_ctrl->column = column;
  331. ifc_nand_ctrl->oob = 0;
  332. if (mtd->writesize > 512) {
  333. nand_fcr0 =
  334. (NAND_CMD_SEQIN << IFC_NAND_FCR0_CMD0_SHIFT) |
  335. (NAND_CMD_STATUS << IFC_NAND_FCR0_CMD1_SHIFT) |
  336. (NAND_CMD_PAGEPROG << IFC_NAND_FCR0_CMD2_SHIFT);
  337. ifc_out32(
  338. (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
  339. (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
  340. (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) |
  341. (IFC_FIR_OP_WBCD << IFC_NAND_FIR0_OP3_SHIFT) |
  342. (IFC_FIR_OP_CMD2 << IFC_NAND_FIR0_OP4_SHIFT),
  343. &ifc->ifc_nand.nand_fir0);
  344. ifc_out32(
  345. (IFC_FIR_OP_CW1 << IFC_NAND_FIR1_OP5_SHIFT) |
  346. (IFC_FIR_OP_RDSTAT << IFC_NAND_FIR1_OP6_SHIFT) |
  347. (IFC_FIR_OP_NOP << IFC_NAND_FIR1_OP7_SHIFT),
  348. &ifc->ifc_nand.nand_fir1);
  349. } else {
  350. nand_fcr0 = ((NAND_CMD_PAGEPROG <<
  351. IFC_NAND_FCR0_CMD1_SHIFT) |
  352. (NAND_CMD_SEQIN <<
  353. IFC_NAND_FCR0_CMD2_SHIFT) |
  354. (NAND_CMD_STATUS <<
  355. IFC_NAND_FCR0_CMD3_SHIFT));
  356. ifc_out32(
  357. (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
  358. (IFC_FIR_OP_CMD2 << IFC_NAND_FIR0_OP1_SHIFT) |
  359. (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP2_SHIFT) |
  360. (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP3_SHIFT) |
  361. (IFC_FIR_OP_WBCD << IFC_NAND_FIR0_OP4_SHIFT),
  362. &ifc->ifc_nand.nand_fir0);
  363. ifc_out32(
  364. (IFC_FIR_OP_CMD1 << IFC_NAND_FIR1_OP5_SHIFT) |
  365. (IFC_FIR_OP_CW3 << IFC_NAND_FIR1_OP6_SHIFT) |
  366. (IFC_FIR_OP_RDSTAT << IFC_NAND_FIR1_OP7_SHIFT) |
  367. (IFC_FIR_OP_NOP << IFC_NAND_FIR1_OP8_SHIFT),
  368. &ifc->ifc_nand.nand_fir1);
  369. if (column >= mtd->writesize)
  370. nand_fcr0 |=
  371. NAND_CMD_READOOB << IFC_NAND_FCR0_CMD0_SHIFT;
  372. else
  373. nand_fcr0 |=
  374. NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT;
  375. }
  376. if (column >= mtd->writesize) {
  377. /* OOB area --> READOOB */
  378. column -= mtd->writesize;
  379. ifc_nand_ctrl->oob = 1;
  380. }
  381. ifc_out32(nand_fcr0, &ifc->ifc_nand.nand_fcr0);
  382. set_addr(mtd, column, page_addr, ifc_nand_ctrl->oob);
  383. return;
  384. }
  385. /* PAGEPROG reuses all of the setup from SEQIN and adds the length */
  386. case NAND_CMD_PAGEPROG: {
  387. if (ifc_nand_ctrl->oob) {
  388. ifc_out32(ifc_nand_ctrl->index -
  389. ifc_nand_ctrl->column,
  390. &ifc->ifc_nand.nand_fbcr);
  391. } else {
  392. ifc_out32(0, &ifc->ifc_nand.nand_fbcr);
  393. }
  394. fsl_ifc_run_command(mtd);
  395. return;
  396. }
  397. case NAND_CMD_STATUS: {
  398. void __iomem *addr;
  399. ifc_out32((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
  400. (IFC_FIR_OP_RB << IFC_NAND_FIR0_OP1_SHIFT),
  401. &ifc->ifc_nand.nand_fir0);
  402. ifc_out32(NAND_CMD_STATUS << IFC_NAND_FCR0_CMD0_SHIFT,
  403. &ifc->ifc_nand.nand_fcr0);
  404. ifc_out32(1, &ifc->ifc_nand.nand_fbcr);
  405. set_addr(mtd, 0, 0, 0);
  406. ifc_nand_ctrl->read_bytes = 1;
  407. fsl_ifc_run_command(mtd);
  408. /*
  409. * The chip always seems to report that it is
  410. * write-protected, even when it is not.
  411. */
  412. addr = ifc_nand_ctrl->addr;
  413. if (chip->options & NAND_BUSWIDTH_16)
  414. ifc_out16(ifc_in16(addr) | (NAND_STATUS_WP), addr);
  415. else
  416. ifc_out8(ifc_in8(addr) | (NAND_STATUS_WP), addr);
  417. return;
  418. }
  419. case NAND_CMD_RESET:
  420. ifc_out32(IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT,
  421. &ifc->ifc_nand.nand_fir0);
  422. ifc_out32(NAND_CMD_RESET << IFC_NAND_FCR0_CMD0_SHIFT,
  423. &ifc->ifc_nand.nand_fcr0);
  424. fsl_ifc_run_command(mtd);
  425. return;
  426. default:
  427. dev_err(priv->dev, "%s: error, unsupported command 0x%x.\n",
  428. __func__, command);
  429. }
  430. }
  431. static void fsl_ifc_select_chip(struct mtd_info *mtd, int chip)
  432. {
  433. /* The hardware does not seem to support multiple
  434. * chips per bank.
  435. */
  436. }
  437. /*
  438. * Write buf to the IFC NAND Controller Data Buffer
  439. */
  440. static void fsl_ifc_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
  441. {
  442. struct nand_chip *chip = mtd_to_nand(mtd);
  443. struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
  444. unsigned int bufsize = mtd->writesize + mtd->oobsize;
  445. if (len <= 0) {
  446. dev_err(priv->dev, "%s: len %d bytes", __func__, len);
  447. return;
  448. }
  449. if ((unsigned int)len > bufsize - ifc_nand_ctrl->index) {
  450. dev_err(priv->dev,
  451. "%s: beyond end of buffer (%d requested, %u available)\n",
  452. __func__, len, bufsize - ifc_nand_ctrl->index);
  453. len = bufsize - ifc_nand_ctrl->index;
  454. }
  455. memcpy_toio(ifc_nand_ctrl->addr + ifc_nand_ctrl->index, buf, len);
  456. ifc_nand_ctrl->index += len;
  457. }
  458. /*
  459. * Read a byte from either the IFC hardware buffer
  460. * read function for 8-bit buswidth
  461. */
  462. static uint8_t fsl_ifc_read_byte(struct mtd_info *mtd)
  463. {
  464. struct nand_chip *chip = mtd_to_nand(mtd);
  465. struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
  466. unsigned int offset;
  467. /*
  468. * If there are still bytes in the IFC buffer, then use the
  469. * next byte.
  470. */
  471. if (ifc_nand_ctrl->index < ifc_nand_ctrl->read_bytes) {
  472. offset = ifc_nand_ctrl->index++;
  473. return ifc_in8(ifc_nand_ctrl->addr + offset);
  474. }
  475. dev_err(priv->dev, "%s: beyond end of buffer\n", __func__);
  476. return ERR_BYTE;
  477. }
  478. /*
  479. * Read two bytes from the IFC hardware buffer
  480. * read function for 16-bit buswith
  481. */
  482. static uint8_t fsl_ifc_read_byte16(struct mtd_info *mtd)
  483. {
  484. struct nand_chip *chip = mtd_to_nand(mtd);
  485. struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
  486. uint16_t data;
  487. /*
  488. * If there are still bytes in the IFC buffer, then use the
  489. * next byte.
  490. */
  491. if (ifc_nand_ctrl->index < ifc_nand_ctrl->read_bytes) {
  492. data = ifc_in16(ifc_nand_ctrl->addr + ifc_nand_ctrl->index);
  493. ifc_nand_ctrl->index += 2;
  494. return (uint8_t) data;
  495. }
  496. dev_err(priv->dev, "%s: beyond end of buffer\n", __func__);
  497. return ERR_BYTE;
  498. }
  499. /*
  500. * Read from the IFC Controller Data Buffer
  501. */
  502. static void fsl_ifc_read_buf(struct mtd_info *mtd, u8 *buf, int len)
  503. {
  504. struct nand_chip *chip = mtd_to_nand(mtd);
  505. struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
  506. int avail;
  507. if (len < 0) {
  508. dev_err(priv->dev, "%s: len %d bytes", __func__, len);
  509. return;
  510. }
  511. avail = min((unsigned int)len,
  512. ifc_nand_ctrl->read_bytes - ifc_nand_ctrl->index);
  513. memcpy_fromio(buf, ifc_nand_ctrl->addr + ifc_nand_ctrl->index, avail);
  514. ifc_nand_ctrl->index += avail;
  515. if (len > avail)
  516. dev_err(priv->dev,
  517. "%s: beyond end of buffer (%d requested, %d available)\n",
  518. __func__, len, avail);
  519. }
  520. /*
  521. * This function is called after Program and Erase Operations to
  522. * check for success or failure.
  523. */
  524. static int fsl_ifc_wait(struct mtd_info *mtd, struct nand_chip *chip)
  525. {
  526. struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
  527. struct fsl_ifc_ctrl *ctrl = priv->ctrl;
  528. struct fsl_ifc_runtime __iomem *ifc = ctrl->rregs;
  529. u32 nand_fsr;
  530. int status;
  531. /* Use READ_STATUS command, but wait for the device to be ready */
  532. ifc_out32((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
  533. (IFC_FIR_OP_RDSTAT << IFC_NAND_FIR0_OP1_SHIFT),
  534. &ifc->ifc_nand.nand_fir0);
  535. ifc_out32(NAND_CMD_STATUS << IFC_NAND_FCR0_CMD0_SHIFT,
  536. &ifc->ifc_nand.nand_fcr0);
  537. ifc_out32(1, &ifc->ifc_nand.nand_fbcr);
  538. set_addr(mtd, 0, 0, 0);
  539. ifc_nand_ctrl->read_bytes = 1;
  540. fsl_ifc_run_command(mtd);
  541. nand_fsr = ifc_in32(&ifc->ifc_nand.nand_fsr);
  542. status = nand_fsr >> 24;
  543. /*
  544. * The chip always seems to report that it is
  545. * write-protected, even when it is not.
  546. */
  547. return status | NAND_STATUS_WP;
  548. }
  549. /*
  550. * The controller does not check for bitflips in erased pages,
  551. * therefore software must check instead.
  552. */
  553. static int check_erased_page(struct nand_chip *chip, u8 *buf)
  554. {
  555. struct mtd_info *mtd = nand_to_mtd(chip);
  556. u8 *ecc = chip->oob_poi;
  557. const int ecc_size = chip->ecc.bytes;
  558. const int pkt_size = chip->ecc.size;
  559. int i, res, bitflips = 0;
  560. struct mtd_oob_region oobregion = { };
  561. mtd_ooblayout_ecc(mtd, 0, &oobregion);
  562. ecc += oobregion.offset;
  563. for (i = 0; i < chip->ecc.steps; ++i) {
  564. res = nand_check_erased_ecc_chunk(buf, pkt_size, ecc, ecc_size,
  565. NULL, 0,
  566. chip->ecc.strength);
  567. if (res < 0)
  568. mtd->ecc_stats.failed++;
  569. else
  570. mtd->ecc_stats.corrected += res;
  571. bitflips = max(res, bitflips);
  572. buf += pkt_size;
  573. ecc += ecc_size;
  574. }
  575. return bitflips;
  576. }
  577. static int fsl_ifc_read_page(struct mtd_info *mtd, struct nand_chip *chip,
  578. uint8_t *buf, int oob_required, int page)
  579. {
  580. struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
  581. struct fsl_ifc_ctrl *ctrl = priv->ctrl;
  582. struct fsl_ifc_nand_ctrl *nctrl = ifc_nand_ctrl;
  583. nand_read_page_op(chip, page, 0, buf, mtd->writesize);
  584. if (oob_required)
  585. fsl_ifc_read_buf(mtd, chip->oob_poi, mtd->oobsize);
  586. if (ctrl->nand_stat & IFC_NAND_EVTER_STAT_ECCER) {
  587. if (!oob_required)
  588. fsl_ifc_read_buf(mtd, chip->oob_poi, mtd->oobsize);
  589. return check_erased_page(chip, buf);
  590. }
  591. if (ctrl->nand_stat != IFC_NAND_EVTER_STAT_OPC)
  592. mtd->ecc_stats.failed++;
  593. return nctrl->max_bitflips;
  594. }
  595. /* ECC will be calculated automatically, and errors will be detected in
  596. * waitfunc.
  597. */
  598. static int fsl_ifc_write_page(struct mtd_info *mtd, struct nand_chip *chip,
  599. const uint8_t *buf, int oob_required, int page)
  600. {
  601. nand_prog_page_begin_op(chip, page, 0, buf, mtd->writesize);
  602. fsl_ifc_write_buf(mtd, chip->oob_poi, mtd->oobsize);
  603. return nand_prog_page_end_op(chip);
  604. }
  605. static int fsl_ifc_chip_init_tail(struct mtd_info *mtd)
  606. {
  607. struct nand_chip *chip = mtd_to_nand(mtd);
  608. struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
  609. dev_dbg(priv->dev, "%s: nand->numchips = %d\n", __func__,
  610. chip->numchips);
  611. dev_dbg(priv->dev, "%s: nand->chipsize = %lld\n", __func__,
  612. chip->chipsize);
  613. dev_dbg(priv->dev, "%s: nand->pagemask = %8x\n", __func__,
  614. chip->pagemask);
  615. dev_dbg(priv->dev, "%s: nand->chip_delay = %d\n", __func__,
  616. chip->chip_delay);
  617. dev_dbg(priv->dev, "%s: nand->badblockpos = %d\n", __func__,
  618. chip->badblockpos);
  619. dev_dbg(priv->dev, "%s: nand->chip_shift = %d\n", __func__,
  620. chip->chip_shift);
  621. dev_dbg(priv->dev, "%s: nand->page_shift = %d\n", __func__,
  622. chip->page_shift);
  623. dev_dbg(priv->dev, "%s: nand->phys_erase_shift = %d\n", __func__,
  624. chip->phys_erase_shift);
  625. dev_dbg(priv->dev, "%s: nand->ecc.mode = %d\n", __func__,
  626. chip->ecc.mode);
  627. dev_dbg(priv->dev, "%s: nand->ecc.steps = %d\n", __func__,
  628. chip->ecc.steps);
  629. dev_dbg(priv->dev, "%s: nand->ecc.bytes = %d\n", __func__,
  630. chip->ecc.bytes);
  631. dev_dbg(priv->dev, "%s: nand->ecc.total = %d\n", __func__,
  632. chip->ecc.total);
  633. dev_dbg(priv->dev, "%s: mtd->ooblayout = %p\n", __func__,
  634. mtd->ooblayout);
  635. dev_dbg(priv->dev, "%s: mtd->flags = %08x\n", __func__, mtd->flags);
  636. dev_dbg(priv->dev, "%s: mtd->size = %lld\n", __func__, mtd->size);
  637. dev_dbg(priv->dev, "%s: mtd->erasesize = %d\n", __func__,
  638. mtd->erasesize);
  639. dev_dbg(priv->dev, "%s: mtd->writesize = %d\n", __func__,
  640. mtd->writesize);
  641. dev_dbg(priv->dev, "%s: mtd->oobsize = %d\n", __func__,
  642. mtd->oobsize);
  643. return 0;
  644. }
  645. static void fsl_ifc_sram_init(struct fsl_ifc_mtd *priv)
  646. {
  647. struct fsl_ifc_ctrl *ctrl = priv->ctrl;
  648. struct fsl_ifc_runtime __iomem *ifc_runtime = ctrl->rregs;
  649. struct fsl_ifc_global __iomem *ifc_global = ctrl->gregs;
  650. uint32_t csor = 0, csor_8k = 0, csor_ext = 0;
  651. uint32_t cs = priv->bank;
  652. /* Save CSOR and CSOR_ext */
  653. csor = ifc_in32(&ifc_global->csor_cs[cs].csor);
  654. csor_ext = ifc_in32(&ifc_global->csor_cs[cs].csor_ext);
  655. /* chage PageSize 8K and SpareSize 1K*/
  656. csor_8k = (csor & ~(CSOR_NAND_PGS_MASK)) | 0x0018C000;
  657. ifc_out32(csor_8k, &ifc_global->csor_cs[cs].csor);
  658. ifc_out32(0x0000400, &ifc_global->csor_cs[cs].csor_ext);
  659. /* READID */
  660. ifc_out32((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
  661. (IFC_FIR_OP_UA << IFC_NAND_FIR0_OP1_SHIFT) |
  662. (IFC_FIR_OP_RB << IFC_NAND_FIR0_OP2_SHIFT),
  663. &ifc_runtime->ifc_nand.nand_fir0);
  664. ifc_out32(NAND_CMD_READID << IFC_NAND_FCR0_CMD0_SHIFT,
  665. &ifc_runtime->ifc_nand.nand_fcr0);
  666. ifc_out32(0x0, &ifc_runtime->ifc_nand.row3);
  667. ifc_out32(0x0, &ifc_runtime->ifc_nand.nand_fbcr);
  668. /* Program ROW0/COL0 */
  669. ifc_out32(0x0, &ifc_runtime->ifc_nand.row0);
  670. ifc_out32(0x0, &ifc_runtime->ifc_nand.col0);
  671. /* set the chip select for NAND Transaction */
  672. ifc_out32(cs << IFC_NAND_CSEL_SHIFT,
  673. &ifc_runtime->ifc_nand.nand_csel);
  674. /* start read seq */
  675. ifc_out32(IFC_NAND_SEQ_STRT_FIR_STRT,
  676. &ifc_runtime->ifc_nand.nandseq_strt);
  677. /* wait for command complete flag or timeout */
  678. wait_event_timeout(ctrl->nand_wait, ctrl->nand_stat,
  679. msecs_to_jiffies(IFC_TIMEOUT_MSECS));
  680. if (ctrl->nand_stat != IFC_NAND_EVTER_STAT_OPC)
  681. pr_err("fsl-ifc: Failed to Initialise SRAM\n");
  682. /* Restore CSOR and CSOR_ext */
  683. ifc_out32(csor, &ifc_global->csor_cs[cs].csor);
  684. ifc_out32(csor_ext, &ifc_global->csor_cs[cs].csor_ext);
  685. }
  686. static int fsl_ifc_chip_init(struct fsl_ifc_mtd *priv)
  687. {
  688. struct fsl_ifc_ctrl *ctrl = priv->ctrl;
  689. struct fsl_ifc_global __iomem *ifc_global = ctrl->gregs;
  690. struct fsl_ifc_runtime __iomem *ifc_runtime = ctrl->rregs;
  691. struct nand_chip *chip = &priv->chip;
  692. struct mtd_info *mtd = nand_to_mtd(&priv->chip);
  693. u32 csor;
  694. /* Fill in fsl_ifc_mtd structure */
  695. mtd->dev.parent = priv->dev;
  696. nand_set_flash_node(chip, priv->dev->of_node);
  697. /* fill in nand_chip structure */
  698. /* set up function call table */
  699. if ((ifc_in32(&ifc_global->cspr_cs[priv->bank].cspr))
  700. & CSPR_PORT_SIZE_16)
  701. chip->read_byte = fsl_ifc_read_byte16;
  702. else
  703. chip->read_byte = fsl_ifc_read_byte;
  704. chip->write_buf = fsl_ifc_write_buf;
  705. chip->read_buf = fsl_ifc_read_buf;
  706. chip->select_chip = fsl_ifc_select_chip;
  707. chip->cmdfunc = fsl_ifc_cmdfunc;
  708. chip->waitfunc = fsl_ifc_wait;
  709. chip->set_features = nand_get_set_features_notsupp;
  710. chip->get_features = nand_get_set_features_notsupp;
  711. chip->bbt_td = &bbt_main_descr;
  712. chip->bbt_md = &bbt_mirror_descr;
  713. ifc_out32(0x0, &ifc_runtime->ifc_nand.ncfgr);
  714. /* set up nand options */
  715. chip->bbt_options = NAND_BBT_USE_FLASH;
  716. chip->options = NAND_NO_SUBPAGE_WRITE;
  717. if (ifc_in32(&ifc_global->cspr_cs[priv->bank].cspr)
  718. & CSPR_PORT_SIZE_16) {
  719. chip->read_byte = fsl_ifc_read_byte16;
  720. chip->options |= NAND_BUSWIDTH_16;
  721. } else {
  722. chip->read_byte = fsl_ifc_read_byte;
  723. }
  724. chip->controller = &ifc_nand_ctrl->controller;
  725. nand_set_controller_data(chip, priv);
  726. chip->ecc.read_page = fsl_ifc_read_page;
  727. chip->ecc.write_page = fsl_ifc_write_page;
  728. csor = ifc_in32(&ifc_global->csor_cs[priv->bank].csor);
  729. switch (csor & CSOR_NAND_PGS_MASK) {
  730. case CSOR_NAND_PGS_512:
  731. if (!(chip->options & NAND_BUSWIDTH_16)) {
  732. /* Avoid conflict with bad block marker */
  733. bbt_main_descr.offs = 0;
  734. bbt_mirror_descr.offs = 0;
  735. }
  736. priv->bufnum_mask = 15;
  737. break;
  738. case CSOR_NAND_PGS_2K:
  739. priv->bufnum_mask = 3;
  740. break;
  741. case CSOR_NAND_PGS_4K:
  742. priv->bufnum_mask = 1;
  743. break;
  744. case CSOR_NAND_PGS_8K:
  745. priv->bufnum_mask = 0;
  746. break;
  747. default:
  748. dev_err(priv->dev, "bad csor %#x: bad page size\n", csor);
  749. return -ENODEV;
  750. }
  751. /* Must also set CSOR_NAND_ECC_ENC_EN if DEC_EN set */
  752. if (csor & CSOR_NAND_ECC_DEC_EN) {
  753. chip->ecc.mode = NAND_ECC_HW;
  754. mtd_set_ooblayout(mtd, &fsl_ifc_ooblayout_ops);
  755. /* Hardware generates ECC per 512 Bytes */
  756. chip->ecc.size = 512;
  757. if ((csor & CSOR_NAND_ECC_MODE_MASK) == CSOR_NAND_ECC_MODE_4) {
  758. chip->ecc.bytes = 8;
  759. chip->ecc.strength = 4;
  760. } else {
  761. chip->ecc.bytes = 16;
  762. chip->ecc.strength = 8;
  763. }
  764. } else {
  765. chip->ecc.mode = NAND_ECC_SOFT;
  766. chip->ecc.algo = NAND_ECC_HAMMING;
  767. }
  768. if (ctrl->version >= FSL_IFC_VERSION_1_1_0)
  769. fsl_ifc_sram_init(priv);
  770. /*
  771. * As IFC version 2.0.0 has 16KB of internal SRAM as compared to older
  772. * versions which had 8KB. Hence bufnum mask needs to be updated.
  773. */
  774. if (ctrl->version >= FSL_IFC_VERSION_2_0_0)
  775. priv->bufnum_mask = (priv->bufnum_mask * 2) + 1;
  776. return 0;
  777. }
  778. static int fsl_ifc_chip_remove(struct fsl_ifc_mtd *priv)
  779. {
  780. struct mtd_info *mtd = nand_to_mtd(&priv->chip);
  781. kfree(mtd->name);
  782. if (priv->vbase)
  783. iounmap(priv->vbase);
  784. ifc_nand_ctrl->chips[priv->bank] = NULL;
  785. return 0;
  786. }
  787. static int match_bank(struct fsl_ifc_global __iomem *ifc_global, int bank,
  788. phys_addr_t addr)
  789. {
  790. u32 cspr = ifc_in32(&ifc_global->cspr_cs[bank].cspr);
  791. if (!(cspr & CSPR_V))
  792. return 0;
  793. if ((cspr & CSPR_MSEL) != CSPR_MSEL_NAND)
  794. return 0;
  795. return (cspr & CSPR_BA) == convert_ifc_address(addr);
  796. }
  797. static DEFINE_MUTEX(fsl_ifc_nand_mutex);
  798. static int fsl_ifc_nand_probe(struct platform_device *dev)
  799. {
  800. struct fsl_ifc_runtime __iomem *ifc;
  801. struct fsl_ifc_mtd *priv;
  802. struct resource res;
  803. static const char *part_probe_types[]
  804. = { "cmdlinepart", "RedBoot", "ofpart", NULL };
  805. int ret;
  806. int bank;
  807. struct device_node *node = dev->dev.of_node;
  808. struct mtd_info *mtd;
  809. if (!fsl_ifc_ctrl_dev || !fsl_ifc_ctrl_dev->rregs)
  810. return -ENODEV;
  811. ifc = fsl_ifc_ctrl_dev->rregs;
  812. /* get, allocate and map the memory resource */
  813. ret = of_address_to_resource(node, 0, &res);
  814. if (ret) {
  815. dev_err(&dev->dev, "%s: failed to get resource\n", __func__);
  816. return ret;
  817. }
  818. /* find which chip select it is connected to */
  819. for (bank = 0; bank < fsl_ifc_ctrl_dev->banks; bank++) {
  820. if (match_bank(fsl_ifc_ctrl_dev->gregs, bank, res.start))
  821. break;
  822. }
  823. if (bank >= fsl_ifc_ctrl_dev->banks) {
  824. dev_err(&dev->dev, "%s: address did not match any chip selects\n",
  825. __func__);
  826. return -ENODEV;
  827. }
  828. priv = devm_kzalloc(&dev->dev, sizeof(*priv), GFP_KERNEL);
  829. if (!priv)
  830. return -ENOMEM;
  831. mutex_lock(&fsl_ifc_nand_mutex);
  832. if (!fsl_ifc_ctrl_dev->nand) {
  833. ifc_nand_ctrl = kzalloc(sizeof(*ifc_nand_ctrl), GFP_KERNEL);
  834. if (!ifc_nand_ctrl) {
  835. mutex_unlock(&fsl_ifc_nand_mutex);
  836. return -ENOMEM;
  837. }
  838. ifc_nand_ctrl->read_bytes = 0;
  839. ifc_nand_ctrl->index = 0;
  840. ifc_nand_ctrl->addr = NULL;
  841. fsl_ifc_ctrl_dev->nand = ifc_nand_ctrl;
  842. nand_hw_control_init(&ifc_nand_ctrl->controller);
  843. } else {
  844. ifc_nand_ctrl = fsl_ifc_ctrl_dev->nand;
  845. }
  846. mutex_unlock(&fsl_ifc_nand_mutex);
  847. ifc_nand_ctrl->chips[bank] = priv;
  848. priv->bank = bank;
  849. priv->ctrl = fsl_ifc_ctrl_dev;
  850. priv->dev = &dev->dev;
  851. priv->vbase = ioremap(res.start, resource_size(&res));
  852. if (!priv->vbase) {
  853. dev_err(priv->dev, "%s: failed to map chip region\n", __func__);
  854. ret = -ENOMEM;
  855. goto err;
  856. }
  857. dev_set_drvdata(priv->dev, priv);
  858. ifc_out32(IFC_NAND_EVTER_EN_OPC_EN |
  859. IFC_NAND_EVTER_EN_FTOER_EN |
  860. IFC_NAND_EVTER_EN_WPER_EN,
  861. &ifc->ifc_nand.nand_evter_en);
  862. /* enable NAND Machine Interrupts */
  863. ifc_out32(IFC_NAND_EVTER_INTR_OPCIR_EN |
  864. IFC_NAND_EVTER_INTR_FTOERIR_EN |
  865. IFC_NAND_EVTER_INTR_WPERIR_EN,
  866. &ifc->ifc_nand.nand_evter_intr_en);
  867. mtd = nand_to_mtd(&priv->chip);
  868. mtd->name = kasprintf(GFP_KERNEL, "%llx.flash", (u64)res.start);
  869. if (!mtd->name) {
  870. ret = -ENOMEM;
  871. goto err;
  872. }
  873. ret = fsl_ifc_chip_init(priv);
  874. if (ret)
  875. goto err;
  876. ret = nand_scan_ident(mtd, 1, NULL);
  877. if (ret)
  878. goto err;
  879. ret = fsl_ifc_chip_init_tail(mtd);
  880. if (ret)
  881. goto err;
  882. ret = nand_scan_tail(mtd);
  883. if (ret)
  884. goto err;
  885. /* First look for RedBoot table or partitions on the command
  886. * line, these take precedence over device tree information */
  887. ret = mtd_device_parse_register(mtd, part_probe_types, NULL, NULL, 0);
  888. if (ret)
  889. goto cleanup_nand;
  890. dev_info(priv->dev, "IFC NAND device at 0x%llx, bank %d\n",
  891. (unsigned long long)res.start, priv->bank);
  892. return 0;
  893. cleanup_nand:
  894. nand_cleanup(&priv->chip);
  895. err:
  896. fsl_ifc_chip_remove(priv);
  897. return ret;
  898. }
  899. static int fsl_ifc_nand_remove(struct platform_device *dev)
  900. {
  901. struct fsl_ifc_mtd *priv = dev_get_drvdata(&dev->dev);
  902. struct mtd_info *mtd = nand_to_mtd(&priv->chip);
  903. nand_release(mtd);
  904. fsl_ifc_chip_remove(priv);
  905. mutex_lock(&fsl_ifc_nand_mutex);
  906. ifc_nand_ctrl->counter--;
  907. if (!ifc_nand_ctrl->counter) {
  908. fsl_ifc_ctrl_dev->nand = NULL;
  909. kfree(ifc_nand_ctrl);
  910. }
  911. mutex_unlock(&fsl_ifc_nand_mutex);
  912. return 0;
  913. }
  914. static const struct of_device_id fsl_ifc_nand_match[] = {
  915. {
  916. .compatible = "fsl,ifc-nand",
  917. },
  918. {}
  919. };
  920. MODULE_DEVICE_TABLE(of, fsl_ifc_nand_match);
  921. static struct platform_driver fsl_ifc_nand_driver = {
  922. .driver = {
  923. .name = "fsl,ifc-nand",
  924. .of_match_table = fsl_ifc_nand_match,
  925. },
  926. .probe = fsl_ifc_nand_probe,
  927. .remove = fsl_ifc_nand_remove,
  928. };
  929. module_platform_driver(fsl_ifc_nand_driver);
  930. MODULE_LICENSE("GPL");
  931. MODULE_AUTHOR("Freescale");
  932. MODULE_DESCRIPTION("Freescale Integrated Flash Controller MTD NAND driver");