au1550nd.c 12 KB

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  1. /*
  2. * Copyright (C) 2004 Embedded Edge, LLC
  3. *
  4. * This program is free software; you can redistribute it and/or modify
  5. * it under the terms of the GNU General Public License version 2 as
  6. * published by the Free Software Foundation.
  7. *
  8. */
  9. #include <linux/slab.h>
  10. #include <linux/gpio.h>
  11. #include <linux/module.h>
  12. #include <linux/interrupt.h>
  13. #include <linux/mtd/mtd.h>
  14. #include <linux/mtd/rawnand.h>
  15. #include <linux/mtd/partitions.h>
  16. #include <linux/platform_device.h>
  17. #include <asm/io.h>
  18. #include <asm/mach-au1x00/au1000.h>
  19. #include <asm/mach-au1x00/au1550nd.h>
  20. struct au1550nd_ctx {
  21. struct nand_chip chip;
  22. int cs;
  23. void __iomem *base;
  24. void (*write_byte)(struct mtd_info *, u_char);
  25. };
  26. /**
  27. * au_read_byte - read one byte from the chip
  28. * @mtd: MTD device structure
  29. *
  30. * read function for 8bit buswidth
  31. */
  32. static u_char au_read_byte(struct mtd_info *mtd)
  33. {
  34. struct nand_chip *this = mtd_to_nand(mtd);
  35. u_char ret = readb(this->IO_ADDR_R);
  36. wmb(); /* drain writebuffer */
  37. return ret;
  38. }
  39. /**
  40. * au_write_byte - write one byte to the chip
  41. * @mtd: MTD device structure
  42. * @byte: pointer to data byte to write
  43. *
  44. * write function for 8it buswidth
  45. */
  46. static void au_write_byte(struct mtd_info *mtd, u_char byte)
  47. {
  48. struct nand_chip *this = mtd_to_nand(mtd);
  49. writeb(byte, this->IO_ADDR_W);
  50. wmb(); /* drain writebuffer */
  51. }
  52. /**
  53. * au_read_byte16 - read one byte endianness aware from the chip
  54. * @mtd: MTD device structure
  55. *
  56. * read function for 16bit buswidth with endianness conversion
  57. */
  58. static u_char au_read_byte16(struct mtd_info *mtd)
  59. {
  60. struct nand_chip *this = mtd_to_nand(mtd);
  61. u_char ret = (u_char) cpu_to_le16(readw(this->IO_ADDR_R));
  62. wmb(); /* drain writebuffer */
  63. return ret;
  64. }
  65. /**
  66. * au_write_byte16 - write one byte endianness aware to the chip
  67. * @mtd: MTD device structure
  68. * @byte: pointer to data byte to write
  69. *
  70. * write function for 16bit buswidth with endianness conversion
  71. */
  72. static void au_write_byte16(struct mtd_info *mtd, u_char byte)
  73. {
  74. struct nand_chip *this = mtd_to_nand(mtd);
  75. writew(le16_to_cpu((u16) byte), this->IO_ADDR_W);
  76. wmb(); /* drain writebuffer */
  77. }
  78. /**
  79. * au_read_word - read one word from the chip
  80. * @mtd: MTD device structure
  81. *
  82. * read function for 16bit buswidth without endianness conversion
  83. */
  84. static u16 au_read_word(struct mtd_info *mtd)
  85. {
  86. struct nand_chip *this = mtd_to_nand(mtd);
  87. u16 ret = readw(this->IO_ADDR_R);
  88. wmb(); /* drain writebuffer */
  89. return ret;
  90. }
  91. /**
  92. * au_write_buf - write buffer to chip
  93. * @mtd: MTD device structure
  94. * @buf: data buffer
  95. * @len: number of bytes to write
  96. *
  97. * write function for 8bit buswidth
  98. */
  99. static void au_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
  100. {
  101. int i;
  102. struct nand_chip *this = mtd_to_nand(mtd);
  103. for (i = 0; i < len; i++) {
  104. writeb(buf[i], this->IO_ADDR_W);
  105. wmb(); /* drain writebuffer */
  106. }
  107. }
  108. /**
  109. * au_read_buf - read chip data into buffer
  110. * @mtd: MTD device structure
  111. * @buf: buffer to store date
  112. * @len: number of bytes to read
  113. *
  114. * read function for 8bit buswidth
  115. */
  116. static void au_read_buf(struct mtd_info *mtd, u_char *buf, int len)
  117. {
  118. int i;
  119. struct nand_chip *this = mtd_to_nand(mtd);
  120. for (i = 0; i < len; i++) {
  121. buf[i] = readb(this->IO_ADDR_R);
  122. wmb(); /* drain writebuffer */
  123. }
  124. }
  125. /**
  126. * au_write_buf16 - write buffer to chip
  127. * @mtd: MTD device structure
  128. * @buf: data buffer
  129. * @len: number of bytes to write
  130. *
  131. * write function for 16bit buswidth
  132. */
  133. static void au_write_buf16(struct mtd_info *mtd, const u_char *buf, int len)
  134. {
  135. int i;
  136. struct nand_chip *this = mtd_to_nand(mtd);
  137. u16 *p = (u16 *) buf;
  138. len >>= 1;
  139. for (i = 0; i < len; i++) {
  140. writew(p[i], this->IO_ADDR_W);
  141. wmb(); /* drain writebuffer */
  142. }
  143. }
  144. /**
  145. * au_read_buf16 - read chip data into buffer
  146. * @mtd: MTD device structure
  147. * @buf: buffer to store date
  148. * @len: number of bytes to read
  149. *
  150. * read function for 16bit buswidth
  151. */
  152. static void au_read_buf16(struct mtd_info *mtd, u_char *buf, int len)
  153. {
  154. int i;
  155. struct nand_chip *this = mtd_to_nand(mtd);
  156. u16 *p = (u16 *) buf;
  157. len >>= 1;
  158. for (i = 0; i < len; i++) {
  159. p[i] = readw(this->IO_ADDR_R);
  160. wmb(); /* drain writebuffer */
  161. }
  162. }
  163. /* Select the chip by setting nCE to low */
  164. #define NAND_CTL_SETNCE 1
  165. /* Deselect the chip by setting nCE to high */
  166. #define NAND_CTL_CLRNCE 2
  167. /* Select the command latch by setting CLE to high */
  168. #define NAND_CTL_SETCLE 3
  169. /* Deselect the command latch by setting CLE to low */
  170. #define NAND_CTL_CLRCLE 4
  171. /* Select the address latch by setting ALE to high */
  172. #define NAND_CTL_SETALE 5
  173. /* Deselect the address latch by setting ALE to low */
  174. #define NAND_CTL_CLRALE 6
  175. static void au1550_hwcontrol(struct mtd_info *mtd, int cmd)
  176. {
  177. struct nand_chip *this = mtd_to_nand(mtd);
  178. struct au1550nd_ctx *ctx = container_of(this, struct au1550nd_ctx,
  179. chip);
  180. switch (cmd) {
  181. case NAND_CTL_SETCLE:
  182. this->IO_ADDR_W = ctx->base + MEM_STNAND_CMD;
  183. break;
  184. case NAND_CTL_CLRCLE:
  185. this->IO_ADDR_W = ctx->base + MEM_STNAND_DATA;
  186. break;
  187. case NAND_CTL_SETALE:
  188. this->IO_ADDR_W = ctx->base + MEM_STNAND_ADDR;
  189. break;
  190. case NAND_CTL_CLRALE:
  191. this->IO_ADDR_W = ctx->base + MEM_STNAND_DATA;
  192. /* FIXME: Nobody knows why this is necessary,
  193. * but it works only that way */
  194. udelay(1);
  195. break;
  196. case NAND_CTL_SETNCE:
  197. /* assert (force assert) chip enable */
  198. alchemy_wrsmem((1 << (4 + ctx->cs)), AU1000_MEM_STNDCTL);
  199. break;
  200. case NAND_CTL_CLRNCE:
  201. /* deassert chip enable */
  202. alchemy_wrsmem(0, AU1000_MEM_STNDCTL);
  203. break;
  204. }
  205. this->IO_ADDR_R = this->IO_ADDR_W;
  206. wmb(); /* Drain the writebuffer */
  207. }
  208. int au1550_device_ready(struct mtd_info *mtd)
  209. {
  210. return (alchemy_rdsmem(AU1000_MEM_STSTAT) & 0x1) ? 1 : 0;
  211. }
  212. /**
  213. * au1550_select_chip - control -CE line
  214. * Forbid driving -CE manually permitting the NAND controller to do this.
  215. * Keeping -CE asserted during the whole sector reads interferes with the
  216. * NOR flash and PCMCIA drivers as it causes contention on the static bus.
  217. * We only have to hold -CE low for the NAND read commands since the flash
  218. * chip needs it to be asserted during chip not ready time but the NAND
  219. * controller keeps it released.
  220. *
  221. * @mtd: MTD device structure
  222. * @chip: chipnumber to select, -1 for deselect
  223. */
  224. static void au1550_select_chip(struct mtd_info *mtd, int chip)
  225. {
  226. }
  227. /**
  228. * au1550_command - Send command to NAND device
  229. * @mtd: MTD device structure
  230. * @command: the command to be sent
  231. * @column: the column address for this command, -1 if none
  232. * @page_addr: the page address for this command, -1 if none
  233. */
  234. static void au1550_command(struct mtd_info *mtd, unsigned command, int column, int page_addr)
  235. {
  236. struct nand_chip *this = mtd_to_nand(mtd);
  237. struct au1550nd_ctx *ctx = container_of(this, struct au1550nd_ctx,
  238. chip);
  239. int ce_override = 0, i;
  240. unsigned long flags = 0;
  241. /* Begin command latch cycle */
  242. au1550_hwcontrol(mtd, NAND_CTL_SETCLE);
  243. /*
  244. * Write out the command to the device.
  245. */
  246. if (command == NAND_CMD_SEQIN) {
  247. int readcmd;
  248. if (column >= mtd->writesize) {
  249. /* OOB area */
  250. column -= mtd->writesize;
  251. readcmd = NAND_CMD_READOOB;
  252. } else if (column < 256) {
  253. /* First 256 bytes --> READ0 */
  254. readcmd = NAND_CMD_READ0;
  255. } else {
  256. column -= 256;
  257. readcmd = NAND_CMD_READ1;
  258. }
  259. ctx->write_byte(mtd, readcmd);
  260. }
  261. ctx->write_byte(mtd, command);
  262. /* Set ALE and clear CLE to start address cycle */
  263. au1550_hwcontrol(mtd, NAND_CTL_CLRCLE);
  264. if (column != -1 || page_addr != -1) {
  265. au1550_hwcontrol(mtd, NAND_CTL_SETALE);
  266. /* Serially input address */
  267. if (column != -1) {
  268. /* Adjust columns for 16 bit buswidth */
  269. if (this->options & NAND_BUSWIDTH_16 &&
  270. !nand_opcode_8bits(command))
  271. column >>= 1;
  272. ctx->write_byte(mtd, column);
  273. }
  274. if (page_addr != -1) {
  275. ctx->write_byte(mtd, (u8)(page_addr & 0xff));
  276. if (command == NAND_CMD_READ0 ||
  277. command == NAND_CMD_READ1 ||
  278. command == NAND_CMD_READOOB) {
  279. /*
  280. * NAND controller will release -CE after
  281. * the last address byte is written, so we'll
  282. * have to forcibly assert it. No interrupts
  283. * are allowed while we do this as we don't
  284. * want the NOR flash or PCMCIA drivers to
  285. * steal our precious bytes of data...
  286. */
  287. ce_override = 1;
  288. local_irq_save(flags);
  289. au1550_hwcontrol(mtd, NAND_CTL_SETNCE);
  290. }
  291. ctx->write_byte(mtd, (u8)(page_addr >> 8));
  292. if (this->options & NAND_ROW_ADDR_3)
  293. ctx->write_byte(mtd,
  294. ((page_addr >> 16) & 0x0f));
  295. }
  296. /* Latch in address */
  297. au1550_hwcontrol(mtd, NAND_CTL_CLRALE);
  298. }
  299. /*
  300. * Program and erase have their own busy handlers.
  301. * Status and sequential in need no delay.
  302. */
  303. switch (command) {
  304. case NAND_CMD_PAGEPROG:
  305. case NAND_CMD_ERASE1:
  306. case NAND_CMD_ERASE2:
  307. case NAND_CMD_SEQIN:
  308. case NAND_CMD_STATUS:
  309. return;
  310. case NAND_CMD_RESET:
  311. break;
  312. case NAND_CMD_READ0:
  313. case NAND_CMD_READ1:
  314. case NAND_CMD_READOOB:
  315. /* Check if we're really driving -CE low (just in case) */
  316. if (unlikely(!ce_override))
  317. break;
  318. /* Apply a short delay always to ensure that we do wait tWB. */
  319. ndelay(100);
  320. /* Wait for a chip to become ready... */
  321. for (i = this->chip_delay; !this->dev_ready(mtd) && i > 0; --i)
  322. udelay(1);
  323. /* Release -CE and re-enable interrupts. */
  324. au1550_hwcontrol(mtd, NAND_CTL_CLRNCE);
  325. local_irq_restore(flags);
  326. return;
  327. }
  328. /* Apply this short delay always to ensure that we do wait tWB. */
  329. ndelay(100);
  330. while(!this->dev_ready(mtd));
  331. }
  332. static int find_nand_cs(unsigned long nand_base)
  333. {
  334. void __iomem *base =
  335. (void __iomem *)KSEG1ADDR(AU1000_STATIC_MEM_PHYS_ADDR);
  336. unsigned long addr, staddr, start, mask, end;
  337. int i;
  338. for (i = 0; i < 4; i++) {
  339. addr = 0x1000 + (i * 0x10); /* CSx */
  340. staddr = __raw_readl(base + addr + 0x08); /* STADDRx */
  341. /* figure out the decoded range of this CS */
  342. start = (staddr << 4) & 0xfffc0000;
  343. mask = (staddr << 18) & 0xfffc0000;
  344. end = (start | (start - 1)) & ~(start ^ mask);
  345. if ((nand_base >= start) && (nand_base < end))
  346. return i;
  347. }
  348. return -ENODEV;
  349. }
  350. static int au1550nd_probe(struct platform_device *pdev)
  351. {
  352. struct au1550nd_platdata *pd;
  353. struct au1550nd_ctx *ctx;
  354. struct nand_chip *this;
  355. struct mtd_info *mtd;
  356. struct resource *r;
  357. int ret, cs;
  358. pd = dev_get_platdata(&pdev->dev);
  359. if (!pd) {
  360. dev_err(&pdev->dev, "missing platform data\n");
  361. return -ENODEV;
  362. }
  363. ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
  364. if (!ctx)
  365. return -ENOMEM;
  366. r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  367. if (!r) {
  368. dev_err(&pdev->dev, "no NAND memory resource\n");
  369. ret = -ENODEV;
  370. goto out1;
  371. }
  372. if (request_mem_region(r->start, resource_size(r), "au1550-nand")) {
  373. dev_err(&pdev->dev, "cannot claim NAND memory area\n");
  374. ret = -ENOMEM;
  375. goto out1;
  376. }
  377. ctx->base = ioremap_nocache(r->start, 0x1000);
  378. if (!ctx->base) {
  379. dev_err(&pdev->dev, "cannot remap NAND memory area\n");
  380. ret = -ENODEV;
  381. goto out2;
  382. }
  383. this = &ctx->chip;
  384. mtd = nand_to_mtd(this);
  385. mtd->dev.parent = &pdev->dev;
  386. /* figure out which CS# r->start belongs to */
  387. cs = find_nand_cs(r->start);
  388. if (cs < 0) {
  389. dev_err(&pdev->dev, "cannot detect NAND chipselect\n");
  390. ret = -ENODEV;
  391. goto out3;
  392. }
  393. ctx->cs = cs;
  394. this->dev_ready = au1550_device_ready;
  395. this->select_chip = au1550_select_chip;
  396. this->cmdfunc = au1550_command;
  397. /* 30 us command delay time */
  398. this->chip_delay = 30;
  399. this->ecc.mode = NAND_ECC_SOFT;
  400. this->ecc.algo = NAND_ECC_HAMMING;
  401. if (pd->devwidth)
  402. this->options |= NAND_BUSWIDTH_16;
  403. this->read_byte = (pd->devwidth) ? au_read_byte16 : au_read_byte;
  404. ctx->write_byte = (pd->devwidth) ? au_write_byte16 : au_write_byte;
  405. this->read_word = au_read_word;
  406. this->write_buf = (pd->devwidth) ? au_write_buf16 : au_write_buf;
  407. this->read_buf = (pd->devwidth) ? au_read_buf16 : au_read_buf;
  408. ret = nand_scan(mtd, 1);
  409. if (ret) {
  410. dev_err(&pdev->dev, "NAND scan failed with %d\n", ret);
  411. goto out3;
  412. }
  413. mtd_device_register(mtd, pd->parts, pd->num_parts);
  414. platform_set_drvdata(pdev, ctx);
  415. return 0;
  416. out3:
  417. iounmap(ctx->base);
  418. out2:
  419. release_mem_region(r->start, resource_size(r));
  420. out1:
  421. kfree(ctx);
  422. return ret;
  423. }
  424. static int au1550nd_remove(struct platform_device *pdev)
  425. {
  426. struct au1550nd_ctx *ctx = platform_get_drvdata(pdev);
  427. struct resource *r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  428. nand_release(nand_to_mtd(&ctx->chip));
  429. iounmap(ctx->base);
  430. release_mem_region(r->start, 0x1000);
  431. kfree(ctx);
  432. return 0;
  433. }
  434. static struct platform_driver au1550nd_driver = {
  435. .driver = {
  436. .name = "au1550-nand",
  437. },
  438. .probe = au1550nd_probe,
  439. .remove = au1550nd_remove,
  440. };
  441. module_platform_driver(au1550nd_driver);
  442. MODULE_LICENSE("GPL");
  443. MODULE_AUTHOR("Embedded Edge, LLC");
  444. MODULE_DESCRIPTION("Board-specific glue layer for NAND flash on Pb1550 board");