dsi_pll_14nm.c 29 KB

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  1. /*
  2. * Copyright (c) 2016, The Linux Foundation. All rights reserved.
  3. *
  4. * This program is free software; you can redistribute it and/or modify
  5. * it under the terms of the GNU General Public License version 2 and
  6. * only version 2 as published by the Free Software Foundation.
  7. *
  8. * This program is distributed in the hope that it will be useful,
  9. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  11. * GNU General Public License for more details.
  12. */
  13. #include <linux/clk.h>
  14. #include <linux/clk-provider.h>
  15. #include "dsi_pll.h"
  16. #include "dsi.xml.h"
  17. /*
  18. * DSI PLL 14nm - clock diagram (eg: DSI0):
  19. *
  20. * dsi0n1_postdiv_clk
  21. * |
  22. * |
  23. * +----+ | +----+
  24. * dsi0vco_clk ---| n1 |--o--| /8 |-- dsi0pllbyte
  25. * +----+ | +----+
  26. * | dsi0n1_postdivby2_clk
  27. * | +----+ |
  28. * o---| /2 |--o--|\
  29. * | +----+ | \ +----+
  30. * | | |--| n2 |-- dsi0pll
  31. * o--------------| / +----+
  32. * |/
  33. */
  34. #define POLL_MAX_READS 15
  35. #define POLL_TIMEOUT_US 1000
  36. #define NUM_PROVIDED_CLKS 2
  37. #define VCO_REF_CLK_RATE 19200000
  38. #define VCO_MIN_RATE 1300000000UL
  39. #define VCO_MAX_RATE 2600000000UL
  40. #define DSI_BYTE_PLL_CLK 0
  41. #define DSI_PIXEL_PLL_CLK 1
  42. #define DSI_PLL_DEFAULT_VCO_POSTDIV 1
  43. struct dsi_pll_input {
  44. u32 fref; /* reference clk */
  45. u32 fdata; /* bit clock rate */
  46. u32 dsiclk_sel; /* Mux configuration (see diagram) */
  47. u32 ssc_en; /* SSC enable/disable */
  48. u32 ldo_en;
  49. /* fixed params */
  50. u32 refclk_dbler_en;
  51. u32 vco_measure_time;
  52. u32 kvco_measure_time;
  53. u32 bandgap_timer;
  54. u32 pll_wakeup_timer;
  55. u32 plllock_cnt;
  56. u32 plllock_rng;
  57. u32 ssc_center;
  58. u32 ssc_adj_period;
  59. u32 ssc_spread;
  60. u32 ssc_freq;
  61. u32 pll_ie_trim;
  62. u32 pll_ip_trim;
  63. u32 pll_iptat_trim;
  64. u32 pll_cpcset_cur;
  65. u32 pll_cpmset_cur;
  66. u32 pll_icpmset;
  67. u32 pll_icpcset;
  68. u32 pll_icpmset_p;
  69. u32 pll_icpmset_m;
  70. u32 pll_icpcset_p;
  71. u32 pll_icpcset_m;
  72. u32 pll_lpf_res1;
  73. u32 pll_lpf_cap1;
  74. u32 pll_lpf_cap2;
  75. u32 pll_c3ctrl;
  76. u32 pll_r3ctrl;
  77. };
  78. struct dsi_pll_output {
  79. u32 pll_txclk_en;
  80. u32 dec_start;
  81. u32 div_frac_start;
  82. u32 ssc_period;
  83. u32 ssc_step_size;
  84. u32 plllock_cmp;
  85. u32 pll_vco_div_ref;
  86. u32 pll_vco_count;
  87. u32 pll_kvco_div_ref;
  88. u32 pll_kvco_count;
  89. u32 pll_misc1;
  90. u32 pll_lpf2_postdiv;
  91. u32 pll_resetsm_cntrl;
  92. u32 pll_resetsm_cntrl2;
  93. u32 pll_resetsm_cntrl5;
  94. u32 pll_kvco_code;
  95. u32 cmn_clk_cfg0;
  96. u32 cmn_clk_cfg1;
  97. u32 cmn_ldo_cntrl;
  98. u32 pll_postdiv;
  99. u32 fcvo;
  100. };
  101. struct pll_14nm_cached_state {
  102. unsigned long vco_rate;
  103. u8 n2postdiv;
  104. u8 n1postdiv;
  105. };
  106. struct dsi_pll_14nm {
  107. struct msm_dsi_pll base;
  108. int id;
  109. struct platform_device *pdev;
  110. void __iomem *phy_cmn_mmio;
  111. void __iomem *mmio;
  112. int vco_delay;
  113. struct dsi_pll_input in;
  114. struct dsi_pll_output out;
  115. /* protects REG_DSI_14nm_PHY_CMN_CLK_CFG0 register */
  116. spinlock_t postdiv_lock;
  117. u64 vco_current_rate;
  118. u64 vco_ref_clk_rate;
  119. /* private clocks: */
  120. struct clk_hw *hws[NUM_DSI_CLOCKS_MAX];
  121. u32 num_hws;
  122. /* clock-provider: */
  123. struct clk_hw_onecell_data *hw_data;
  124. struct pll_14nm_cached_state cached_state;
  125. enum msm_dsi_phy_usecase uc;
  126. struct dsi_pll_14nm *slave;
  127. };
  128. #define to_pll_14nm(x) container_of(x, struct dsi_pll_14nm, base)
  129. /*
  130. * Private struct for N1/N2 post-divider clocks. These clocks are similar to
  131. * the generic clk_divider class of clocks. The only difference is that it
  132. * also sets the slave DSI PLL's post-dividers if in Dual DSI mode
  133. */
  134. struct dsi_pll_14nm_postdiv {
  135. struct clk_hw hw;
  136. /* divider params */
  137. u8 shift;
  138. u8 width;
  139. u8 flags; /* same flags as used by clk_divider struct */
  140. struct dsi_pll_14nm *pll;
  141. };
  142. #define to_pll_14nm_postdiv(_hw) container_of(_hw, struct dsi_pll_14nm_postdiv, hw)
  143. /*
  144. * Global list of private DSI PLL struct pointers. We need this for Dual DSI
  145. * mode, where the master PLL's clk_ops needs access the slave's private data
  146. */
  147. static struct dsi_pll_14nm *pll_14nm_list[DSI_MAX];
  148. static bool pll_14nm_poll_for_ready(struct dsi_pll_14nm *pll_14nm,
  149. u32 nb_tries, u32 timeout_us)
  150. {
  151. bool pll_locked = false;
  152. void __iomem *base = pll_14nm->mmio;
  153. u32 tries, val;
  154. tries = nb_tries;
  155. while (tries--) {
  156. val = pll_read(base +
  157. REG_DSI_14nm_PHY_PLL_RESET_SM_READY_STATUS);
  158. pll_locked = !!(val & BIT(5));
  159. if (pll_locked)
  160. break;
  161. udelay(timeout_us);
  162. }
  163. if (!pll_locked) {
  164. tries = nb_tries;
  165. while (tries--) {
  166. val = pll_read(base +
  167. REG_DSI_14nm_PHY_PLL_RESET_SM_READY_STATUS);
  168. pll_locked = !!(val & BIT(0));
  169. if (pll_locked)
  170. break;
  171. udelay(timeout_us);
  172. }
  173. }
  174. DBG("DSI PLL is %slocked", pll_locked ? "" : "*not* ");
  175. return pll_locked;
  176. }
  177. static void dsi_pll_14nm_input_init(struct dsi_pll_14nm *pll)
  178. {
  179. pll->in.fref = pll->vco_ref_clk_rate;
  180. pll->in.fdata = 0;
  181. pll->in.dsiclk_sel = 1; /* Use the /2 path in Mux */
  182. pll->in.ldo_en = 0; /* disabled for now */
  183. /* fixed input */
  184. pll->in.refclk_dbler_en = 0;
  185. pll->in.vco_measure_time = 5;
  186. pll->in.kvco_measure_time = 5;
  187. pll->in.bandgap_timer = 4;
  188. pll->in.pll_wakeup_timer = 5;
  189. pll->in.plllock_cnt = 1;
  190. pll->in.plllock_rng = 0;
  191. /*
  192. * SSC is enabled by default. We might need DT props for configuring
  193. * some SSC params like PPM and center/down spread etc.
  194. */
  195. pll->in.ssc_en = 1;
  196. pll->in.ssc_center = 0; /* down spread by default */
  197. pll->in.ssc_spread = 5; /* PPM / 1000 */
  198. pll->in.ssc_freq = 31500; /* default recommended */
  199. pll->in.ssc_adj_period = 37;
  200. pll->in.pll_ie_trim = 4;
  201. pll->in.pll_ip_trim = 4;
  202. pll->in.pll_cpcset_cur = 1;
  203. pll->in.pll_cpmset_cur = 1;
  204. pll->in.pll_icpmset = 4;
  205. pll->in.pll_icpcset = 4;
  206. pll->in.pll_icpmset_p = 0;
  207. pll->in.pll_icpmset_m = 0;
  208. pll->in.pll_icpcset_p = 0;
  209. pll->in.pll_icpcset_m = 0;
  210. pll->in.pll_lpf_res1 = 3;
  211. pll->in.pll_lpf_cap1 = 11;
  212. pll->in.pll_lpf_cap2 = 1;
  213. pll->in.pll_iptat_trim = 7;
  214. pll->in.pll_c3ctrl = 2;
  215. pll->in.pll_r3ctrl = 1;
  216. }
  217. #define CEIL(x, y) (((x) + ((y) - 1)) / (y))
  218. static void pll_14nm_ssc_calc(struct dsi_pll_14nm *pll)
  219. {
  220. u32 period, ssc_period;
  221. u32 ref, rem;
  222. u64 step_size;
  223. DBG("vco=%lld ref=%lld", pll->vco_current_rate, pll->vco_ref_clk_rate);
  224. ssc_period = pll->in.ssc_freq / 500;
  225. period = (u32)pll->vco_ref_clk_rate / 1000;
  226. ssc_period = CEIL(period, ssc_period);
  227. ssc_period -= 1;
  228. pll->out.ssc_period = ssc_period;
  229. DBG("ssc freq=%d spread=%d period=%d", pll->in.ssc_freq,
  230. pll->in.ssc_spread, pll->out.ssc_period);
  231. step_size = (u32)pll->vco_current_rate;
  232. ref = pll->vco_ref_clk_rate;
  233. ref /= 1000;
  234. step_size = div_u64(step_size, ref);
  235. step_size <<= 20;
  236. step_size = div_u64(step_size, 1000);
  237. step_size *= pll->in.ssc_spread;
  238. step_size = div_u64(step_size, 1000);
  239. step_size *= (pll->in.ssc_adj_period + 1);
  240. rem = 0;
  241. step_size = div_u64_rem(step_size, ssc_period + 1, &rem);
  242. if (rem)
  243. step_size++;
  244. DBG("step_size=%lld", step_size);
  245. step_size &= 0x0ffff; /* take lower 16 bits */
  246. pll->out.ssc_step_size = step_size;
  247. }
  248. static void pll_14nm_dec_frac_calc(struct dsi_pll_14nm *pll)
  249. {
  250. struct dsi_pll_input *pin = &pll->in;
  251. struct dsi_pll_output *pout = &pll->out;
  252. u64 multiplier = BIT(20);
  253. u64 dec_start_multiple, dec_start, pll_comp_val;
  254. u32 duration, div_frac_start;
  255. u64 vco_clk_rate = pll->vco_current_rate;
  256. u64 fref = pll->vco_ref_clk_rate;
  257. DBG("vco_clk_rate=%lld ref_clk_rate=%lld", vco_clk_rate, fref);
  258. dec_start_multiple = div_u64(vco_clk_rate * multiplier, fref);
  259. div_u64_rem(dec_start_multiple, multiplier, &div_frac_start);
  260. dec_start = div_u64(dec_start_multiple, multiplier);
  261. pout->dec_start = (u32)dec_start;
  262. pout->div_frac_start = div_frac_start;
  263. if (pin->plllock_cnt == 0)
  264. duration = 1024;
  265. else if (pin->plllock_cnt == 1)
  266. duration = 256;
  267. else if (pin->plllock_cnt == 2)
  268. duration = 128;
  269. else
  270. duration = 32;
  271. pll_comp_val = duration * dec_start_multiple;
  272. pll_comp_val = div_u64(pll_comp_val, multiplier);
  273. do_div(pll_comp_val, 10);
  274. pout->plllock_cmp = (u32)pll_comp_val;
  275. pout->pll_txclk_en = 1;
  276. pout->cmn_ldo_cntrl = 0x3c;
  277. }
  278. static u32 pll_14nm_kvco_slop(u32 vrate)
  279. {
  280. u32 slop = 0;
  281. if (vrate > VCO_MIN_RATE && vrate <= 1800000000UL)
  282. slop = 600;
  283. else if (vrate > 1800000000UL && vrate < 2300000000UL)
  284. slop = 400;
  285. else if (vrate > 2300000000UL && vrate < VCO_MAX_RATE)
  286. slop = 280;
  287. return slop;
  288. }
  289. static void pll_14nm_calc_vco_count(struct dsi_pll_14nm *pll)
  290. {
  291. struct dsi_pll_input *pin = &pll->in;
  292. struct dsi_pll_output *pout = &pll->out;
  293. u64 vco_clk_rate = pll->vco_current_rate;
  294. u64 fref = pll->vco_ref_clk_rate;
  295. u64 data;
  296. u32 cnt;
  297. data = fref * pin->vco_measure_time;
  298. do_div(data, 1000000);
  299. data &= 0x03ff; /* 10 bits */
  300. data -= 2;
  301. pout->pll_vco_div_ref = data;
  302. data = div_u64(vco_clk_rate, 1000000); /* unit is Mhz */
  303. data *= pin->vco_measure_time;
  304. do_div(data, 10);
  305. pout->pll_vco_count = data;
  306. data = fref * pin->kvco_measure_time;
  307. do_div(data, 1000000);
  308. data &= 0x03ff; /* 10 bits */
  309. data -= 1;
  310. pout->pll_kvco_div_ref = data;
  311. cnt = pll_14nm_kvco_slop(vco_clk_rate);
  312. cnt *= 2;
  313. cnt /= 100;
  314. cnt *= pin->kvco_measure_time;
  315. pout->pll_kvco_count = cnt;
  316. pout->pll_misc1 = 16;
  317. pout->pll_resetsm_cntrl = 48;
  318. pout->pll_resetsm_cntrl2 = pin->bandgap_timer << 3;
  319. pout->pll_resetsm_cntrl5 = pin->pll_wakeup_timer;
  320. pout->pll_kvco_code = 0;
  321. }
  322. static void pll_db_commit_ssc(struct dsi_pll_14nm *pll)
  323. {
  324. void __iomem *base = pll->mmio;
  325. struct dsi_pll_input *pin = &pll->in;
  326. struct dsi_pll_output *pout = &pll->out;
  327. u8 data;
  328. data = pin->ssc_adj_period;
  329. data &= 0x0ff;
  330. pll_write(base + REG_DSI_14nm_PHY_PLL_SSC_ADJ_PER1, data);
  331. data = (pin->ssc_adj_period >> 8);
  332. data &= 0x03;
  333. pll_write(base + REG_DSI_14nm_PHY_PLL_SSC_ADJ_PER2, data);
  334. data = pout->ssc_period;
  335. data &= 0x0ff;
  336. pll_write(base + REG_DSI_14nm_PHY_PLL_SSC_PER1, data);
  337. data = (pout->ssc_period >> 8);
  338. data &= 0x0ff;
  339. pll_write(base + REG_DSI_14nm_PHY_PLL_SSC_PER2, data);
  340. data = pout->ssc_step_size;
  341. data &= 0x0ff;
  342. pll_write(base + REG_DSI_14nm_PHY_PLL_SSC_STEP_SIZE1, data);
  343. data = (pout->ssc_step_size >> 8);
  344. data &= 0x0ff;
  345. pll_write(base + REG_DSI_14nm_PHY_PLL_SSC_STEP_SIZE2, data);
  346. data = (pin->ssc_center & 0x01);
  347. data <<= 1;
  348. data |= 0x01; /* enable */
  349. pll_write(base + REG_DSI_14nm_PHY_PLL_SSC_EN_CENTER, data);
  350. wmb(); /* make sure register committed */
  351. }
  352. static void pll_db_commit_common(struct dsi_pll_14nm *pll,
  353. struct dsi_pll_input *pin,
  354. struct dsi_pll_output *pout)
  355. {
  356. void __iomem *base = pll->mmio;
  357. u8 data;
  358. /* confgiure the non frequency dependent pll registers */
  359. data = 0;
  360. pll_write(base + REG_DSI_14nm_PHY_PLL_SYSCLK_EN_RESET, data);
  361. data = pout->pll_txclk_en;
  362. pll_write(base + REG_DSI_14nm_PHY_PLL_TXCLK_EN, data);
  363. data = pout->pll_resetsm_cntrl;
  364. pll_write(base + REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL, data);
  365. data = pout->pll_resetsm_cntrl2;
  366. pll_write(base + REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL2, data);
  367. data = pout->pll_resetsm_cntrl5;
  368. pll_write(base + REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL5, data);
  369. data = pout->pll_vco_div_ref & 0xff;
  370. pll_write(base + REG_DSI_14nm_PHY_PLL_VCO_DIV_REF1, data);
  371. data = (pout->pll_vco_div_ref >> 8) & 0x3;
  372. pll_write(base + REG_DSI_14nm_PHY_PLL_VCO_DIV_REF2, data);
  373. data = pout->pll_kvco_div_ref & 0xff;
  374. pll_write(base + REG_DSI_14nm_PHY_PLL_KVCO_DIV_REF1, data);
  375. data = (pout->pll_kvco_div_ref >> 8) & 0x3;
  376. pll_write(base + REG_DSI_14nm_PHY_PLL_KVCO_DIV_REF2, data);
  377. data = pout->pll_misc1;
  378. pll_write(base + REG_DSI_14nm_PHY_PLL_PLL_MISC1, data);
  379. data = pin->pll_ie_trim;
  380. pll_write(base + REG_DSI_14nm_PHY_PLL_IE_TRIM, data);
  381. data = pin->pll_ip_trim;
  382. pll_write(base + REG_DSI_14nm_PHY_PLL_IP_TRIM, data);
  383. data = pin->pll_cpmset_cur << 3 | pin->pll_cpcset_cur;
  384. pll_write(base + REG_DSI_14nm_PHY_PLL_CP_SET_CUR, data);
  385. data = pin->pll_icpcset_p << 3 | pin->pll_icpcset_m;
  386. pll_write(base + REG_DSI_14nm_PHY_PLL_PLL_ICPCSET, data);
  387. data = pin->pll_icpmset_p << 3 | pin->pll_icpcset_m;
  388. pll_write(base + REG_DSI_14nm_PHY_PLL_PLL_ICPMSET, data);
  389. data = pin->pll_icpmset << 3 | pin->pll_icpcset;
  390. pll_write(base + REG_DSI_14nm_PHY_PLL_PLL_ICP_SET, data);
  391. data = pin->pll_lpf_cap2 << 4 | pin->pll_lpf_cap1;
  392. pll_write(base + REG_DSI_14nm_PHY_PLL_PLL_LPF1, data);
  393. data = pin->pll_iptat_trim;
  394. pll_write(base + REG_DSI_14nm_PHY_PLL_IPTAT_TRIM, data);
  395. data = pin->pll_c3ctrl | pin->pll_r3ctrl << 4;
  396. pll_write(base + REG_DSI_14nm_PHY_PLL_PLL_CRCTRL, data);
  397. }
  398. static void pll_14nm_software_reset(struct dsi_pll_14nm *pll_14nm)
  399. {
  400. void __iomem *cmn_base = pll_14nm->phy_cmn_mmio;
  401. /* de assert pll start and apply pll sw reset */
  402. /* stop pll */
  403. pll_write(cmn_base + REG_DSI_14nm_PHY_CMN_PLL_CNTRL, 0);
  404. /* pll sw reset */
  405. pll_write_udelay(cmn_base + REG_DSI_14nm_PHY_CMN_CTRL_1, 0x20, 10);
  406. wmb(); /* make sure register committed */
  407. pll_write(cmn_base + REG_DSI_14nm_PHY_CMN_CTRL_1, 0);
  408. wmb(); /* make sure register committed */
  409. }
  410. static void pll_db_commit_14nm(struct dsi_pll_14nm *pll,
  411. struct dsi_pll_input *pin,
  412. struct dsi_pll_output *pout)
  413. {
  414. void __iomem *base = pll->mmio;
  415. void __iomem *cmn_base = pll->phy_cmn_mmio;
  416. u8 data;
  417. DBG("DSI%d PLL", pll->id);
  418. data = pout->cmn_ldo_cntrl;
  419. pll_write(cmn_base + REG_DSI_14nm_PHY_CMN_LDO_CNTRL, data);
  420. pll_db_commit_common(pll, pin, pout);
  421. pll_14nm_software_reset(pll);
  422. data = pin->dsiclk_sel; /* set dsiclk_sel = 1 */
  423. pll_write(cmn_base + REG_DSI_14nm_PHY_CMN_CLK_CFG1, data);
  424. data = 0xff; /* data, clk, pll normal operation */
  425. pll_write(cmn_base + REG_DSI_14nm_PHY_CMN_CTRL_0, data);
  426. /* configure the frequency dependent pll registers */
  427. data = pout->dec_start;
  428. pll_write(base + REG_DSI_14nm_PHY_PLL_DEC_START, data);
  429. data = pout->div_frac_start & 0xff;
  430. pll_write(base + REG_DSI_14nm_PHY_PLL_DIV_FRAC_START1, data);
  431. data = (pout->div_frac_start >> 8) & 0xff;
  432. pll_write(base + REG_DSI_14nm_PHY_PLL_DIV_FRAC_START2, data);
  433. data = (pout->div_frac_start >> 16) & 0xf;
  434. pll_write(base + REG_DSI_14nm_PHY_PLL_DIV_FRAC_START3, data);
  435. data = pout->plllock_cmp & 0xff;
  436. pll_write(base + REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP1, data);
  437. data = (pout->plllock_cmp >> 8) & 0xff;
  438. pll_write(base + REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP2, data);
  439. data = (pout->plllock_cmp >> 16) & 0x3;
  440. pll_write(base + REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP3, data);
  441. data = pin->plllock_cnt << 1 | pin->plllock_rng << 3;
  442. pll_write(base + REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP_EN, data);
  443. data = pout->pll_vco_count & 0xff;
  444. pll_write(base + REG_DSI_14nm_PHY_PLL_VCO_COUNT1, data);
  445. data = (pout->pll_vco_count >> 8) & 0xff;
  446. pll_write(base + REG_DSI_14nm_PHY_PLL_VCO_COUNT2, data);
  447. data = pout->pll_kvco_count & 0xff;
  448. pll_write(base + REG_DSI_14nm_PHY_PLL_KVCO_COUNT1, data);
  449. data = (pout->pll_kvco_count >> 8) & 0x3;
  450. pll_write(base + REG_DSI_14nm_PHY_PLL_KVCO_COUNT2, data);
  451. data = (pout->pll_postdiv - 1) << 4 | pin->pll_lpf_res1;
  452. pll_write(base + REG_DSI_14nm_PHY_PLL_PLL_LPF2_POSTDIV, data);
  453. if (pin->ssc_en)
  454. pll_db_commit_ssc(pll);
  455. wmb(); /* make sure register committed */
  456. }
  457. /*
  458. * VCO clock Callbacks
  459. */
  460. static int dsi_pll_14nm_vco_set_rate(struct clk_hw *hw, unsigned long rate,
  461. unsigned long parent_rate)
  462. {
  463. struct msm_dsi_pll *pll = hw_clk_to_pll(hw);
  464. struct dsi_pll_14nm *pll_14nm = to_pll_14nm(pll);
  465. struct dsi_pll_input *pin = &pll_14nm->in;
  466. struct dsi_pll_output *pout = &pll_14nm->out;
  467. DBG("DSI PLL%d rate=%lu, parent's=%lu", pll_14nm->id, rate,
  468. parent_rate);
  469. pll_14nm->vco_current_rate = rate;
  470. pll_14nm->vco_ref_clk_rate = VCO_REF_CLK_RATE;
  471. dsi_pll_14nm_input_init(pll_14nm);
  472. /*
  473. * This configures the post divider internal to the VCO. It's
  474. * fixed to divide by 1 for now.
  475. *
  476. * tx_band = pll_postdiv.
  477. * 0: divided by 1
  478. * 1: divided by 2
  479. * 2: divided by 4
  480. * 3: divided by 8
  481. */
  482. pout->pll_postdiv = DSI_PLL_DEFAULT_VCO_POSTDIV;
  483. pll_14nm_dec_frac_calc(pll_14nm);
  484. if (pin->ssc_en)
  485. pll_14nm_ssc_calc(pll_14nm);
  486. pll_14nm_calc_vco_count(pll_14nm);
  487. /* commit the slave DSI PLL registers if we're master. Note that we
  488. * don't lock the slave PLL. We just ensure that the PLL/PHY registers
  489. * of the master and slave are identical
  490. */
  491. if (pll_14nm->uc == MSM_DSI_PHY_MASTER) {
  492. struct dsi_pll_14nm *pll_14nm_slave = pll_14nm->slave;
  493. pll_db_commit_14nm(pll_14nm_slave, pin, pout);
  494. }
  495. pll_db_commit_14nm(pll_14nm, pin, pout);
  496. return 0;
  497. }
  498. static unsigned long dsi_pll_14nm_vco_recalc_rate(struct clk_hw *hw,
  499. unsigned long parent_rate)
  500. {
  501. struct msm_dsi_pll *pll = hw_clk_to_pll(hw);
  502. struct dsi_pll_14nm *pll_14nm = to_pll_14nm(pll);
  503. void __iomem *base = pll_14nm->mmio;
  504. u64 vco_rate, multiplier = BIT(20);
  505. u32 div_frac_start;
  506. u32 dec_start;
  507. u64 ref_clk = parent_rate;
  508. dec_start = pll_read(base + REG_DSI_14nm_PHY_PLL_DEC_START);
  509. dec_start &= 0x0ff;
  510. DBG("dec_start = %x", dec_start);
  511. div_frac_start = (pll_read(base + REG_DSI_14nm_PHY_PLL_DIV_FRAC_START3)
  512. & 0xf) << 16;
  513. div_frac_start |= (pll_read(base + REG_DSI_14nm_PHY_PLL_DIV_FRAC_START2)
  514. & 0xff) << 8;
  515. div_frac_start |= pll_read(base + REG_DSI_14nm_PHY_PLL_DIV_FRAC_START1)
  516. & 0xff;
  517. DBG("div_frac_start = %x", div_frac_start);
  518. vco_rate = ref_clk * dec_start;
  519. vco_rate += ((ref_clk * div_frac_start) / multiplier);
  520. /*
  521. * Recalculating the rate from dec_start and frac_start doesn't end up
  522. * the rate we originally set. Convert the freq to KHz, round it up and
  523. * convert it back to MHz.
  524. */
  525. vco_rate = DIV_ROUND_UP_ULL(vco_rate, 1000) * 1000;
  526. DBG("returning vco rate = %lu", (unsigned long)vco_rate);
  527. return (unsigned long)vco_rate;
  528. }
  529. static const struct clk_ops clk_ops_dsi_pll_14nm_vco = {
  530. .round_rate = msm_dsi_pll_helper_clk_round_rate,
  531. .set_rate = dsi_pll_14nm_vco_set_rate,
  532. .recalc_rate = dsi_pll_14nm_vco_recalc_rate,
  533. .prepare = msm_dsi_pll_helper_clk_prepare,
  534. .unprepare = msm_dsi_pll_helper_clk_unprepare,
  535. };
  536. /*
  537. * N1 and N2 post-divider clock callbacks
  538. */
  539. #define div_mask(width) ((1 << (width)) - 1)
  540. static unsigned long dsi_pll_14nm_postdiv_recalc_rate(struct clk_hw *hw,
  541. unsigned long parent_rate)
  542. {
  543. struct dsi_pll_14nm_postdiv *postdiv = to_pll_14nm_postdiv(hw);
  544. struct dsi_pll_14nm *pll_14nm = postdiv->pll;
  545. void __iomem *base = pll_14nm->phy_cmn_mmio;
  546. u8 shift = postdiv->shift;
  547. u8 width = postdiv->width;
  548. u32 val;
  549. DBG("DSI%d PLL parent rate=%lu", pll_14nm->id, parent_rate);
  550. val = pll_read(base + REG_DSI_14nm_PHY_CMN_CLK_CFG0) >> shift;
  551. val &= div_mask(width);
  552. return divider_recalc_rate(hw, parent_rate, val, NULL,
  553. postdiv->flags, width);
  554. }
  555. static long dsi_pll_14nm_postdiv_round_rate(struct clk_hw *hw,
  556. unsigned long rate,
  557. unsigned long *prate)
  558. {
  559. struct dsi_pll_14nm_postdiv *postdiv = to_pll_14nm_postdiv(hw);
  560. struct dsi_pll_14nm *pll_14nm = postdiv->pll;
  561. DBG("DSI%d PLL parent rate=%lu", pll_14nm->id, rate);
  562. return divider_round_rate(hw, rate, prate, NULL,
  563. postdiv->width,
  564. postdiv->flags);
  565. }
  566. static int dsi_pll_14nm_postdiv_set_rate(struct clk_hw *hw, unsigned long rate,
  567. unsigned long parent_rate)
  568. {
  569. struct dsi_pll_14nm_postdiv *postdiv = to_pll_14nm_postdiv(hw);
  570. struct dsi_pll_14nm *pll_14nm = postdiv->pll;
  571. void __iomem *base = pll_14nm->phy_cmn_mmio;
  572. spinlock_t *lock = &pll_14nm->postdiv_lock;
  573. u8 shift = postdiv->shift;
  574. u8 width = postdiv->width;
  575. unsigned int value;
  576. unsigned long flags = 0;
  577. u32 val;
  578. DBG("DSI%d PLL parent rate=%lu parent rate %lu", pll_14nm->id, rate,
  579. parent_rate);
  580. value = divider_get_val(rate, parent_rate, NULL, postdiv->width,
  581. postdiv->flags);
  582. spin_lock_irqsave(lock, flags);
  583. val = pll_read(base + REG_DSI_14nm_PHY_CMN_CLK_CFG0);
  584. val &= ~(div_mask(width) << shift);
  585. val |= value << shift;
  586. pll_write(base + REG_DSI_14nm_PHY_CMN_CLK_CFG0, val);
  587. /* If we're master in dual DSI mode, then the slave PLL's post-dividers
  588. * follow the master's post dividers
  589. */
  590. if (pll_14nm->uc == MSM_DSI_PHY_MASTER) {
  591. struct dsi_pll_14nm *pll_14nm_slave = pll_14nm->slave;
  592. void __iomem *slave_base = pll_14nm_slave->phy_cmn_mmio;
  593. pll_write(slave_base + REG_DSI_14nm_PHY_CMN_CLK_CFG0, val);
  594. }
  595. spin_unlock_irqrestore(lock, flags);
  596. return 0;
  597. }
  598. static const struct clk_ops clk_ops_dsi_pll_14nm_postdiv = {
  599. .recalc_rate = dsi_pll_14nm_postdiv_recalc_rate,
  600. .round_rate = dsi_pll_14nm_postdiv_round_rate,
  601. .set_rate = dsi_pll_14nm_postdiv_set_rate,
  602. };
  603. /*
  604. * PLL Callbacks
  605. */
  606. static int dsi_pll_14nm_enable_seq(struct msm_dsi_pll *pll)
  607. {
  608. struct dsi_pll_14nm *pll_14nm = to_pll_14nm(pll);
  609. void __iomem *base = pll_14nm->mmio;
  610. void __iomem *cmn_base = pll_14nm->phy_cmn_mmio;
  611. bool locked;
  612. DBG("");
  613. pll_write(base + REG_DSI_14nm_PHY_PLL_VREF_CFG1, 0x10);
  614. pll_write(cmn_base + REG_DSI_14nm_PHY_CMN_PLL_CNTRL, 1);
  615. locked = pll_14nm_poll_for_ready(pll_14nm, POLL_MAX_READS,
  616. POLL_TIMEOUT_US);
  617. if (unlikely(!locked))
  618. dev_err(&pll_14nm->pdev->dev, "DSI PLL lock failed\n");
  619. else
  620. DBG("DSI PLL lock success");
  621. return locked ? 0 : -EINVAL;
  622. }
  623. static void dsi_pll_14nm_disable_seq(struct msm_dsi_pll *pll)
  624. {
  625. struct dsi_pll_14nm *pll_14nm = to_pll_14nm(pll);
  626. void __iomem *cmn_base = pll_14nm->phy_cmn_mmio;
  627. DBG("");
  628. pll_write(cmn_base + REG_DSI_14nm_PHY_CMN_PLL_CNTRL, 0);
  629. }
  630. static void dsi_pll_14nm_save_state(struct msm_dsi_pll *pll)
  631. {
  632. struct dsi_pll_14nm *pll_14nm = to_pll_14nm(pll);
  633. struct pll_14nm_cached_state *cached_state = &pll_14nm->cached_state;
  634. void __iomem *cmn_base = pll_14nm->phy_cmn_mmio;
  635. u32 data;
  636. data = pll_read(cmn_base + REG_DSI_14nm_PHY_CMN_CLK_CFG0);
  637. cached_state->n1postdiv = data & 0xf;
  638. cached_state->n2postdiv = (data >> 4) & 0xf;
  639. DBG("DSI%d PLL save state %x %x", pll_14nm->id,
  640. cached_state->n1postdiv, cached_state->n2postdiv);
  641. cached_state->vco_rate = clk_hw_get_rate(&pll->clk_hw);
  642. }
  643. static int dsi_pll_14nm_restore_state(struct msm_dsi_pll *pll)
  644. {
  645. struct dsi_pll_14nm *pll_14nm = to_pll_14nm(pll);
  646. struct pll_14nm_cached_state *cached_state = &pll_14nm->cached_state;
  647. void __iomem *cmn_base = pll_14nm->phy_cmn_mmio;
  648. u32 data;
  649. int ret;
  650. ret = dsi_pll_14nm_vco_set_rate(&pll->clk_hw,
  651. cached_state->vco_rate, 0);
  652. if (ret) {
  653. dev_err(&pll_14nm->pdev->dev,
  654. "restore vco rate failed. ret=%d\n", ret);
  655. return ret;
  656. }
  657. data = cached_state->n1postdiv | (cached_state->n2postdiv << 4);
  658. DBG("DSI%d PLL restore state %x %x", pll_14nm->id,
  659. cached_state->n1postdiv, cached_state->n2postdiv);
  660. pll_write(cmn_base + REG_DSI_14nm_PHY_CMN_CLK_CFG0, data);
  661. /* also restore post-dividers for slave DSI PLL */
  662. if (pll_14nm->uc == MSM_DSI_PHY_MASTER) {
  663. struct dsi_pll_14nm *pll_14nm_slave = pll_14nm->slave;
  664. void __iomem *slave_base = pll_14nm_slave->phy_cmn_mmio;
  665. pll_write(slave_base + REG_DSI_14nm_PHY_CMN_CLK_CFG0, data);
  666. }
  667. return 0;
  668. }
  669. static int dsi_pll_14nm_set_usecase(struct msm_dsi_pll *pll,
  670. enum msm_dsi_phy_usecase uc)
  671. {
  672. struct dsi_pll_14nm *pll_14nm = to_pll_14nm(pll);
  673. void __iomem *base = pll_14nm->mmio;
  674. u32 clkbuflr_en, bandgap = 0;
  675. switch (uc) {
  676. case MSM_DSI_PHY_STANDALONE:
  677. clkbuflr_en = 0x1;
  678. break;
  679. case MSM_DSI_PHY_MASTER:
  680. clkbuflr_en = 0x3;
  681. pll_14nm->slave = pll_14nm_list[(pll_14nm->id + 1) % DSI_MAX];
  682. break;
  683. case MSM_DSI_PHY_SLAVE:
  684. clkbuflr_en = 0x0;
  685. bandgap = 0x3;
  686. break;
  687. default:
  688. return -EINVAL;
  689. }
  690. pll_write(base + REG_DSI_14nm_PHY_PLL_CLKBUFLR_EN, clkbuflr_en);
  691. if (bandgap)
  692. pll_write(base + REG_DSI_14nm_PHY_PLL_PLL_BANDGAP, bandgap);
  693. pll_14nm->uc = uc;
  694. return 0;
  695. }
  696. static int dsi_pll_14nm_get_provider(struct msm_dsi_pll *pll,
  697. struct clk **byte_clk_provider,
  698. struct clk **pixel_clk_provider)
  699. {
  700. struct dsi_pll_14nm *pll_14nm = to_pll_14nm(pll);
  701. struct clk_hw_onecell_data *hw_data = pll_14nm->hw_data;
  702. if (byte_clk_provider)
  703. *byte_clk_provider = hw_data->hws[DSI_BYTE_PLL_CLK]->clk;
  704. if (pixel_clk_provider)
  705. *pixel_clk_provider = hw_data->hws[DSI_PIXEL_PLL_CLK]->clk;
  706. return 0;
  707. }
  708. static void dsi_pll_14nm_destroy(struct msm_dsi_pll *pll)
  709. {
  710. struct dsi_pll_14nm *pll_14nm = to_pll_14nm(pll);
  711. struct platform_device *pdev = pll_14nm->pdev;
  712. int num_hws = pll_14nm->num_hws;
  713. of_clk_del_provider(pdev->dev.of_node);
  714. while (num_hws--)
  715. clk_hw_unregister(pll_14nm->hws[num_hws]);
  716. }
  717. static struct clk_hw *pll_14nm_postdiv_register(struct dsi_pll_14nm *pll_14nm,
  718. const char *name,
  719. const char *parent_name,
  720. unsigned long flags,
  721. u8 shift)
  722. {
  723. struct dsi_pll_14nm_postdiv *pll_postdiv;
  724. struct device *dev = &pll_14nm->pdev->dev;
  725. struct clk_init_data postdiv_init = {
  726. .parent_names = (const char *[]) { parent_name },
  727. .num_parents = 1,
  728. .name = name,
  729. .flags = flags,
  730. .ops = &clk_ops_dsi_pll_14nm_postdiv,
  731. };
  732. int ret;
  733. pll_postdiv = devm_kzalloc(dev, sizeof(*pll_postdiv), GFP_KERNEL);
  734. if (!pll_postdiv)
  735. return ERR_PTR(-ENOMEM);
  736. pll_postdiv->pll = pll_14nm;
  737. pll_postdiv->shift = shift;
  738. /* both N1 and N2 postdividers are 4 bits wide */
  739. pll_postdiv->width = 4;
  740. /* range of each divider is from 1 to 15 */
  741. pll_postdiv->flags = CLK_DIVIDER_ONE_BASED;
  742. pll_postdiv->hw.init = &postdiv_init;
  743. ret = clk_hw_register(dev, &pll_postdiv->hw);
  744. if (ret)
  745. return ERR_PTR(ret);
  746. return &pll_postdiv->hw;
  747. }
  748. static int pll_14nm_register(struct dsi_pll_14nm *pll_14nm)
  749. {
  750. char clk_name[32], parent[32], vco_name[32];
  751. struct clk_init_data vco_init = {
  752. .parent_names = (const char *[]){ "xo" },
  753. .num_parents = 1,
  754. .name = vco_name,
  755. .flags = CLK_IGNORE_UNUSED,
  756. .ops = &clk_ops_dsi_pll_14nm_vco,
  757. };
  758. struct device *dev = &pll_14nm->pdev->dev;
  759. struct clk_hw **hws = pll_14nm->hws;
  760. struct clk_hw_onecell_data *hw_data;
  761. struct clk_hw *hw;
  762. int num = 0;
  763. int ret;
  764. DBG("DSI%d", pll_14nm->id);
  765. hw_data = devm_kzalloc(dev, sizeof(*hw_data) +
  766. NUM_PROVIDED_CLKS * sizeof(struct clk_hw *),
  767. GFP_KERNEL);
  768. if (!hw_data)
  769. return -ENOMEM;
  770. snprintf(vco_name, 32, "dsi%dvco_clk", pll_14nm->id);
  771. pll_14nm->base.clk_hw.init = &vco_init;
  772. ret = clk_hw_register(dev, &pll_14nm->base.clk_hw);
  773. if (ret)
  774. return ret;
  775. hws[num++] = &pll_14nm->base.clk_hw;
  776. snprintf(clk_name, 32, "dsi%dn1_postdiv_clk", pll_14nm->id);
  777. snprintf(parent, 32, "dsi%dvco_clk", pll_14nm->id);
  778. /* N1 postdiv, bits 0-3 in REG_DSI_14nm_PHY_CMN_CLK_CFG0 */
  779. hw = pll_14nm_postdiv_register(pll_14nm, clk_name, parent,
  780. CLK_SET_RATE_PARENT, 0);
  781. if (IS_ERR(hw))
  782. return PTR_ERR(hw);
  783. hws[num++] = hw;
  784. snprintf(clk_name, 32, "dsi%dpllbyte", pll_14nm->id);
  785. snprintf(parent, 32, "dsi%dn1_postdiv_clk", pll_14nm->id);
  786. /* DSI Byte clock = VCO_CLK / N1 / 8 */
  787. hw = clk_hw_register_fixed_factor(dev, clk_name, parent,
  788. CLK_SET_RATE_PARENT, 1, 8);
  789. if (IS_ERR(hw))
  790. return PTR_ERR(hw);
  791. hws[num++] = hw;
  792. hw_data->hws[DSI_BYTE_PLL_CLK] = hw;
  793. snprintf(clk_name, 32, "dsi%dn1_postdivby2_clk", pll_14nm->id);
  794. snprintf(parent, 32, "dsi%dn1_postdiv_clk", pll_14nm->id);
  795. /*
  796. * Skip the mux for now, force DSICLK_SEL to 1, Add a /2 divider
  797. * on the way. Don't let it set parent.
  798. */
  799. hw = clk_hw_register_fixed_factor(dev, clk_name, parent, 0, 1, 2);
  800. if (IS_ERR(hw))
  801. return PTR_ERR(hw);
  802. hws[num++] = hw;
  803. snprintf(clk_name, 32, "dsi%dpll", pll_14nm->id);
  804. snprintf(parent, 32, "dsi%dn1_postdivby2_clk", pll_14nm->id);
  805. /* DSI pixel clock = VCO_CLK / N1 / 2 / N2
  806. * This is the output of N2 post-divider, bits 4-7 in
  807. * REG_DSI_14nm_PHY_CMN_CLK_CFG0. Don't let it set parent.
  808. */
  809. hw = pll_14nm_postdiv_register(pll_14nm, clk_name, parent, 0, 4);
  810. if (IS_ERR(hw))
  811. return PTR_ERR(hw);
  812. hws[num++] = hw;
  813. hw_data->hws[DSI_PIXEL_PLL_CLK] = hw;
  814. pll_14nm->num_hws = num;
  815. hw_data->num = NUM_PROVIDED_CLKS;
  816. pll_14nm->hw_data = hw_data;
  817. ret = of_clk_add_hw_provider(dev->of_node, of_clk_hw_onecell_get,
  818. pll_14nm->hw_data);
  819. if (ret) {
  820. dev_err(dev, "failed to register clk provider: %d\n", ret);
  821. return ret;
  822. }
  823. return 0;
  824. }
  825. struct msm_dsi_pll *msm_dsi_pll_14nm_init(struct platform_device *pdev, int id)
  826. {
  827. struct dsi_pll_14nm *pll_14nm;
  828. struct msm_dsi_pll *pll;
  829. int ret;
  830. if (!pdev)
  831. return ERR_PTR(-ENODEV);
  832. pll_14nm = devm_kzalloc(&pdev->dev, sizeof(*pll_14nm), GFP_KERNEL);
  833. if (!pll_14nm)
  834. return ERR_PTR(-ENOMEM);
  835. DBG("PLL%d", id);
  836. pll_14nm->pdev = pdev;
  837. pll_14nm->id = id;
  838. pll_14nm_list[id] = pll_14nm;
  839. pll_14nm->phy_cmn_mmio = msm_ioremap(pdev, "dsi_phy", "DSI_PHY");
  840. if (IS_ERR_OR_NULL(pll_14nm->phy_cmn_mmio)) {
  841. dev_err(&pdev->dev, "failed to map CMN PHY base\n");
  842. return ERR_PTR(-ENOMEM);
  843. }
  844. pll_14nm->mmio = msm_ioremap(pdev, "dsi_pll", "DSI_PLL");
  845. if (IS_ERR_OR_NULL(pll_14nm->mmio)) {
  846. dev_err(&pdev->dev, "failed to map PLL base\n");
  847. return ERR_PTR(-ENOMEM);
  848. }
  849. spin_lock_init(&pll_14nm->postdiv_lock);
  850. pll = &pll_14nm->base;
  851. pll->min_rate = VCO_MIN_RATE;
  852. pll->max_rate = VCO_MAX_RATE;
  853. pll->get_provider = dsi_pll_14nm_get_provider;
  854. pll->destroy = dsi_pll_14nm_destroy;
  855. pll->disable_seq = dsi_pll_14nm_disable_seq;
  856. pll->save_state = dsi_pll_14nm_save_state;
  857. pll->restore_state = dsi_pll_14nm_restore_state;
  858. pll->set_usecase = dsi_pll_14nm_set_usecase;
  859. pll_14nm->vco_delay = 1;
  860. pll->en_seq_cnt = 1;
  861. pll->enable_seqs[0] = dsi_pll_14nm_enable_seq;
  862. ret = pll_14nm_register(pll_14nm);
  863. if (ret) {
  864. dev_err(&pdev->dev, "failed to register PLL: %d\n", ret);
  865. return ERR_PTR(ret);
  866. }
  867. return pll;
  868. }