adreno_device.c 8.0 KB

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  1. /*
  2. * Copyright (C) 2013-2014 Red Hat
  3. * Author: Rob Clark <robdclark@gmail.com>
  4. *
  5. * Copyright (c) 2014,2017 The Linux Foundation. All rights reserved.
  6. *
  7. * This program is free software; you can redistribute it and/or modify it
  8. * under the terms of the GNU General Public License version 2 as published by
  9. * the Free Software Foundation.
  10. *
  11. * This program is distributed in the hope that it will be useful, but WITHOUT
  12. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  14. * more details.
  15. *
  16. * You should have received a copy of the GNU General Public License along with
  17. * this program. If not, see <http://www.gnu.org/licenses/>.
  18. */
  19. #include "adreno_gpu.h"
  20. #define ANY_ID 0xff
  21. bool hang_debug = false;
  22. MODULE_PARM_DESC(hang_debug, "Dump registers when hang is detected (can be slow!)");
  23. module_param_named(hang_debug, hang_debug, bool, 0600);
  24. static const struct adreno_info gpulist[] = {
  25. {
  26. .rev = ADRENO_REV(3, 0, 5, ANY_ID),
  27. .revn = 305,
  28. .name = "A305",
  29. .fw = {
  30. [ADRENO_FW_PM4] = "a300_pm4.fw",
  31. [ADRENO_FW_PFP] = "a300_pfp.fw",
  32. },
  33. .gmem = SZ_256K,
  34. .init = a3xx_gpu_init,
  35. }, {
  36. .rev = ADRENO_REV(3, 0, 6, 0),
  37. .revn = 307, /* because a305c is revn==306 */
  38. .name = "A306",
  39. .fw = {
  40. [ADRENO_FW_PM4] = "a300_pm4.fw",
  41. [ADRENO_FW_PFP] = "a300_pfp.fw",
  42. },
  43. .gmem = SZ_128K,
  44. .init = a3xx_gpu_init,
  45. }, {
  46. .rev = ADRENO_REV(3, 2, ANY_ID, ANY_ID),
  47. .revn = 320,
  48. .name = "A320",
  49. .fw = {
  50. [ADRENO_FW_PM4] = "a300_pm4.fw",
  51. [ADRENO_FW_PFP] = "a300_pfp.fw",
  52. },
  53. .gmem = SZ_512K,
  54. .init = a3xx_gpu_init,
  55. }, {
  56. .rev = ADRENO_REV(3, 3, 0, ANY_ID),
  57. .revn = 330,
  58. .name = "A330",
  59. .fw = {
  60. [ADRENO_FW_PM4] = "a330_pm4.fw",
  61. [ADRENO_FW_PFP] = "a330_pfp.fw",
  62. },
  63. .gmem = SZ_1M,
  64. .init = a3xx_gpu_init,
  65. }, {
  66. .rev = ADRENO_REV(4, 2, 0, ANY_ID),
  67. .revn = 420,
  68. .name = "A420",
  69. .fw = {
  70. [ADRENO_FW_PM4] = "a420_pm4.fw",
  71. [ADRENO_FW_PFP] = "a420_pfp.fw",
  72. },
  73. .gmem = (SZ_1M + SZ_512K),
  74. .init = a4xx_gpu_init,
  75. }, {
  76. .rev = ADRENO_REV(4, 3, 0, ANY_ID),
  77. .revn = 430,
  78. .name = "A430",
  79. .fw = {
  80. [ADRENO_FW_PM4] = "a420_pm4.fw",
  81. [ADRENO_FW_PFP] = "a420_pfp.fw",
  82. },
  83. .gmem = (SZ_1M + SZ_512K),
  84. .init = a4xx_gpu_init,
  85. }, {
  86. .rev = ADRENO_REV(5, 3, 0, 2),
  87. .revn = 530,
  88. .name = "A530",
  89. .fw = {
  90. [ADRENO_FW_PM4] = "a530_pm4.fw",
  91. [ADRENO_FW_PFP] = "a530_pfp.fw",
  92. [ADRENO_FW_GPMU] = "a530v3_gpmu.fw2",
  93. },
  94. .gmem = SZ_1M,
  95. .quirks = ADRENO_QUIRK_TWO_PASS_USE_WFI |
  96. ADRENO_QUIRK_FAULT_DETECT_MASK,
  97. .init = a5xx_gpu_init,
  98. .zapfw = "a530_zap.mdt",
  99. },
  100. };
  101. MODULE_FIRMWARE("qcom/a300_pm4.fw");
  102. MODULE_FIRMWARE("qcom/a300_pfp.fw");
  103. MODULE_FIRMWARE("qcom/a330_pm4.fw");
  104. MODULE_FIRMWARE("qcom/a330_pfp.fw");
  105. MODULE_FIRMWARE("qcom/a420_pm4.fw");
  106. MODULE_FIRMWARE("qcom/a420_pfp.fw");
  107. MODULE_FIRMWARE("qcom/a530_pm4.fw");
  108. MODULE_FIRMWARE("qcom/a530_pfp.fw");
  109. MODULE_FIRMWARE("qcom/a530v3_gpmu.fw2");
  110. MODULE_FIRMWARE("qcom/a530_zap.mdt");
  111. MODULE_FIRMWARE("qcom/a530_zap.b00");
  112. MODULE_FIRMWARE("qcom/a530_zap.b01");
  113. MODULE_FIRMWARE("qcom/a530_zap.b02");
  114. static inline bool _rev_match(uint8_t entry, uint8_t id)
  115. {
  116. return (entry == ANY_ID) || (entry == id);
  117. }
  118. const struct adreno_info *adreno_info(struct adreno_rev rev)
  119. {
  120. int i;
  121. /* identify gpu: */
  122. for (i = 0; i < ARRAY_SIZE(gpulist); i++) {
  123. const struct adreno_info *info = &gpulist[i];
  124. if (_rev_match(info->rev.core, rev.core) &&
  125. _rev_match(info->rev.major, rev.major) &&
  126. _rev_match(info->rev.minor, rev.minor) &&
  127. _rev_match(info->rev.patchid, rev.patchid))
  128. return info;
  129. }
  130. return NULL;
  131. }
  132. struct msm_gpu *adreno_load_gpu(struct drm_device *dev)
  133. {
  134. struct msm_drm_private *priv = dev->dev_private;
  135. struct platform_device *pdev = priv->gpu_pdev;
  136. struct msm_gpu *gpu = NULL;
  137. int ret;
  138. if (pdev)
  139. gpu = platform_get_drvdata(pdev);
  140. if (!gpu) {
  141. dev_err_once(dev->dev, "no GPU device was found\n");
  142. return NULL;
  143. }
  144. pm_runtime_get_sync(&pdev->dev);
  145. mutex_lock(&dev->struct_mutex);
  146. ret = msm_gpu_hw_init(gpu);
  147. mutex_unlock(&dev->struct_mutex);
  148. pm_runtime_put_sync(&pdev->dev);
  149. if (ret) {
  150. dev_err(dev->dev, "gpu hw init failed: %d\n", ret);
  151. return NULL;
  152. }
  153. #ifdef CONFIG_DEBUG_FS
  154. if (gpu->funcs->debugfs_init) {
  155. gpu->funcs->debugfs_init(gpu, dev->primary);
  156. gpu->funcs->debugfs_init(gpu, dev->render);
  157. }
  158. #endif
  159. return gpu;
  160. }
  161. static void set_gpu_pdev(struct drm_device *dev,
  162. struct platform_device *pdev)
  163. {
  164. struct msm_drm_private *priv = dev->dev_private;
  165. priv->gpu_pdev = pdev;
  166. }
  167. static int find_chipid(struct device *dev, struct adreno_rev *rev)
  168. {
  169. struct device_node *node = dev->of_node;
  170. const char *compat;
  171. int ret;
  172. u32 chipid;
  173. /* first search the compat strings for qcom,adreno-XYZ.W: */
  174. ret = of_property_read_string_index(node, "compatible", 0, &compat);
  175. if (ret == 0) {
  176. unsigned int r, patch;
  177. if (sscanf(compat, "qcom,adreno-%u.%u", &r, &patch) == 2) {
  178. rev->core = r / 100;
  179. r %= 100;
  180. rev->major = r / 10;
  181. r %= 10;
  182. rev->minor = r;
  183. rev->patchid = patch;
  184. return 0;
  185. }
  186. }
  187. /* and if that fails, fall back to legacy "qcom,chipid" property: */
  188. ret = of_property_read_u32(node, "qcom,chipid", &chipid);
  189. if (ret) {
  190. dev_err(dev, "could not parse qcom,chipid: %d\n", ret);
  191. return ret;
  192. }
  193. rev->core = (chipid >> 24) & 0xff;
  194. rev->major = (chipid >> 16) & 0xff;
  195. rev->minor = (chipid >> 8) & 0xff;
  196. rev->patchid = (chipid & 0xff);
  197. dev_warn(dev, "Using legacy qcom,chipid binding!\n");
  198. dev_warn(dev, "Use compatible qcom,adreno-%u%u%u.%u instead.\n",
  199. rev->core, rev->major, rev->minor, rev->patchid);
  200. return 0;
  201. }
  202. static int adreno_bind(struct device *dev, struct device *master, void *data)
  203. {
  204. static struct adreno_platform_config config = {};
  205. const struct adreno_info *info;
  206. struct drm_device *drm = dev_get_drvdata(master);
  207. struct msm_gpu *gpu;
  208. int ret;
  209. ret = find_chipid(dev, &config.rev);
  210. if (ret)
  211. return ret;
  212. dev->platform_data = &config;
  213. set_gpu_pdev(drm, to_platform_device(dev));
  214. info = adreno_info(config.rev);
  215. if (!info) {
  216. dev_warn(drm->dev, "Unknown GPU revision: %u.%u.%u.%u\n",
  217. config.rev.core, config.rev.major,
  218. config.rev.minor, config.rev.patchid);
  219. return -ENXIO;
  220. }
  221. DBG("Found GPU: %u.%u.%u.%u", config.rev.core, config.rev.major,
  222. config.rev.minor, config.rev.patchid);
  223. gpu = info->init(drm);
  224. if (IS_ERR(gpu)) {
  225. dev_warn(drm->dev, "failed to load adreno gpu\n");
  226. return PTR_ERR(gpu);
  227. }
  228. dev_set_drvdata(dev, gpu);
  229. return 0;
  230. }
  231. static void adreno_unbind(struct device *dev, struct device *master,
  232. void *data)
  233. {
  234. struct msm_gpu *gpu = dev_get_drvdata(dev);
  235. gpu->funcs->pm_suspend(gpu);
  236. gpu->funcs->destroy(gpu);
  237. set_gpu_pdev(dev_get_drvdata(master), NULL);
  238. }
  239. static const struct component_ops a3xx_ops = {
  240. .bind = adreno_bind,
  241. .unbind = adreno_unbind,
  242. };
  243. static int adreno_probe(struct platform_device *pdev)
  244. {
  245. return component_add(&pdev->dev, &a3xx_ops);
  246. }
  247. static int adreno_remove(struct platform_device *pdev)
  248. {
  249. component_del(&pdev->dev, &a3xx_ops);
  250. return 0;
  251. }
  252. static const struct of_device_id dt_match[] = {
  253. { .compatible = "qcom,adreno" },
  254. { .compatible = "qcom,adreno-3xx" },
  255. /* for backwards compat w/ downstream kgsl DT files: */
  256. { .compatible = "qcom,kgsl-3d0" },
  257. {}
  258. };
  259. #ifdef CONFIG_PM
  260. static int adreno_resume(struct device *dev)
  261. {
  262. struct platform_device *pdev = to_platform_device(dev);
  263. struct msm_gpu *gpu = platform_get_drvdata(pdev);
  264. return gpu->funcs->pm_resume(gpu);
  265. }
  266. static int adreno_suspend(struct device *dev)
  267. {
  268. struct platform_device *pdev = to_platform_device(dev);
  269. struct msm_gpu *gpu = platform_get_drvdata(pdev);
  270. return gpu->funcs->pm_suspend(gpu);
  271. }
  272. #endif
  273. static const struct dev_pm_ops adreno_pm_ops = {
  274. SET_RUNTIME_PM_OPS(adreno_suspend, adreno_resume, NULL)
  275. };
  276. static struct platform_driver adreno_driver = {
  277. .probe = adreno_probe,
  278. .remove = adreno_remove,
  279. .driver = {
  280. .name = "adreno",
  281. .of_match_table = dt_match,
  282. .pm = &adreno_pm_ops,
  283. },
  284. };
  285. void __init adreno_register(void)
  286. {
  287. platform_driver_register(&adreno_driver);
  288. }
  289. void __exit adreno_unregister(void)
  290. {
  291. platform_driver_unregister(&adreno_driver);
  292. }