mtk_drm_drv.c 16 KB

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  1. /*
  2. * Copyright (c) 2015 MediaTek Inc.
  3. * Author: YT SHEN <yt.shen@mediatek.com>
  4. *
  5. * This program is free software; you can redistribute it and/or modify
  6. * it under the terms of the GNU General Public License version 2 as
  7. * published by the Free Software Foundation.
  8. *
  9. * This program is distributed in the hope that it will be useful,
  10. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  12. * GNU General Public License for more details.
  13. */
  14. #include <drm/drmP.h>
  15. #include <drm/drm_atomic.h>
  16. #include <drm/drm_atomic_helper.h>
  17. #include <drm/drm_crtc_helper.h>
  18. #include <drm/drm_gem.h>
  19. #include <drm/drm_gem_cma_helper.h>
  20. #include <drm/drm_of.h>
  21. #include <linux/component.h>
  22. #include <linux/iommu.h>
  23. #include <linux/of_address.h>
  24. #include <linux/of_platform.h>
  25. #include <linux/pm_runtime.h>
  26. #include "mtk_drm_crtc.h"
  27. #include "mtk_drm_ddp.h"
  28. #include "mtk_drm_ddp_comp.h"
  29. #include "mtk_drm_drv.h"
  30. #include "mtk_drm_fb.h"
  31. #include "mtk_drm_gem.h"
  32. #define DRIVER_NAME "mediatek"
  33. #define DRIVER_DESC "Mediatek SoC DRM"
  34. #define DRIVER_DATE "20150513"
  35. #define DRIVER_MAJOR 1
  36. #define DRIVER_MINOR 0
  37. static void mtk_atomic_schedule(struct mtk_drm_private *private,
  38. struct drm_atomic_state *state)
  39. {
  40. private->commit.state = state;
  41. schedule_work(&private->commit.work);
  42. }
  43. static void mtk_atomic_wait_for_fences(struct drm_atomic_state *state)
  44. {
  45. struct drm_plane *plane;
  46. struct drm_plane_state *new_plane_state;
  47. int i;
  48. for_each_new_plane_in_state(state, plane, new_plane_state, i)
  49. mtk_fb_wait(new_plane_state->fb);
  50. }
  51. static void mtk_atomic_complete(struct mtk_drm_private *private,
  52. struct drm_atomic_state *state)
  53. {
  54. struct drm_device *drm = private->drm;
  55. mtk_atomic_wait_for_fences(state);
  56. /*
  57. * Mediatek drm supports runtime PM, so plane registers cannot be
  58. * written when their crtc is disabled.
  59. *
  60. * The comment for drm_atomic_helper_commit states:
  61. * For drivers supporting runtime PM the recommended sequence is
  62. *
  63. * drm_atomic_helper_commit_modeset_disables(dev, state);
  64. * drm_atomic_helper_commit_modeset_enables(dev, state);
  65. * drm_atomic_helper_commit_planes(dev, state,
  66. * DRM_PLANE_COMMIT_ACTIVE_ONLY);
  67. *
  68. * See the kerneldoc entries for these three functions for more details.
  69. */
  70. drm_atomic_helper_commit_modeset_disables(drm, state);
  71. drm_atomic_helper_commit_modeset_enables(drm, state);
  72. drm_atomic_helper_commit_planes(drm, state,
  73. DRM_PLANE_COMMIT_ACTIVE_ONLY);
  74. drm_atomic_helper_wait_for_vblanks(drm, state);
  75. drm_atomic_helper_cleanup_planes(drm, state);
  76. drm_atomic_state_put(state);
  77. }
  78. static void mtk_atomic_work(struct work_struct *work)
  79. {
  80. struct mtk_drm_private *private = container_of(work,
  81. struct mtk_drm_private, commit.work);
  82. mtk_atomic_complete(private, private->commit.state);
  83. }
  84. static int mtk_atomic_commit(struct drm_device *drm,
  85. struct drm_atomic_state *state,
  86. bool async)
  87. {
  88. struct mtk_drm_private *private = drm->dev_private;
  89. int ret;
  90. ret = drm_atomic_helper_prepare_planes(drm, state);
  91. if (ret)
  92. return ret;
  93. mutex_lock(&private->commit.lock);
  94. flush_work(&private->commit.work);
  95. ret = drm_atomic_helper_swap_state(state, true);
  96. if (ret) {
  97. mutex_unlock(&private->commit.lock);
  98. drm_atomic_helper_cleanup_planes(drm, state);
  99. return ret;
  100. }
  101. drm_atomic_state_get(state);
  102. if (async)
  103. mtk_atomic_schedule(private, state);
  104. else
  105. mtk_atomic_complete(private, state);
  106. mutex_unlock(&private->commit.lock);
  107. return 0;
  108. }
  109. static const struct drm_mode_config_funcs mtk_drm_mode_config_funcs = {
  110. .fb_create = mtk_drm_mode_fb_create,
  111. .atomic_check = drm_atomic_helper_check,
  112. .atomic_commit = mtk_atomic_commit,
  113. };
  114. static const enum mtk_ddp_comp_id mt2701_mtk_ddp_main[] = {
  115. DDP_COMPONENT_OVL0,
  116. DDP_COMPONENT_RDMA0,
  117. DDP_COMPONENT_COLOR0,
  118. DDP_COMPONENT_BLS,
  119. DDP_COMPONENT_DSI0,
  120. };
  121. static const enum mtk_ddp_comp_id mt2701_mtk_ddp_ext[] = {
  122. DDP_COMPONENT_RDMA1,
  123. DDP_COMPONENT_DPI0,
  124. };
  125. static const enum mtk_ddp_comp_id mt8173_mtk_ddp_main[] = {
  126. DDP_COMPONENT_OVL0,
  127. DDP_COMPONENT_COLOR0,
  128. DDP_COMPONENT_AAL,
  129. DDP_COMPONENT_OD,
  130. DDP_COMPONENT_RDMA0,
  131. DDP_COMPONENT_UFOE,
  132. DDP_COMPONENT_DSI0,
  133. DDP_COMPONENT_PWM0,
  134. };
  135. static const enum mtk_ddp_comp_id mt8173_mtk_ddp_ext[] = {
  136. DDP_COMPONENT_OVL1,
  137. DDP_COMPONENT_COLOR1,
  138. DDP_COMPONENT_GAMMA,
  139. DDP_COMPONENT_RDMA1,
  140. DDP_COMPONENT_DPI0,
  141. };
  142. static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
  143. .main_path = mt2701_mtk_ddp_main,
  144. .main_len = ARRAY_SIZE(mt2701_mtk_ddp_main),
  145. .ext_path = mt2701_mtk_ddp_ext,
  146. .ext_len = ARRAY_SIZE(mt2701_mtk_ddp_ext),
  147. .shadow_register = true,
  148. };
  149. static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = {
  150. .main_path = mt8173_mtk_ddp_main,
  151. .main_len = ARRAY_SIZE(mt8173_mtk_ddp_main),
  152. .ext_path = mt8173_mtk_ddp_ext,
  153. .ext_len = ARRAY_SIZE(mt8173_mtk_ddp_ext),
  154. };
  155. static int mtk_drm_kms_init(struct drm_device *drm)
  156. {
  157. struct mtk_drm_private *private = drm->dev_private;
  158. struct platform_device *pdev;
  159. struct device_node *np;
  160. int ret;
  161. if (!iommu_present(&platform_bus_type))
  162. return -EPROBE_DEFER;
  163. pdev = of_find_device_by_node(private->mutex_node);
  164. if (!pdev) {
  165. dev_err(drm->dev, "Waiting for disp-mutex device %pOF\n",
  166. private->mutex_node);
  167. of_node_put(private->mutex_node);
  168. return -EPROBE_DEFER;
  169. }
  170. private->mutex_dev = &pdev->dev;
  171. drm_mode_config_init(drm);
  172. drm->mode_config.min_width = 64;
  173. drm->mode_config.min_height = 64;
  174. /*
  175. * set max width and height as default value(4096x4096).
  176. * this value would be used to check framebuffer size limitation
  177. * at drm_mode_addfb().
  178. */
  179. drm->mode_config.max_width = 4096;
  180. drm->mode_config.max_height = 4096;
  181. drm->mode_config.funcs = &mtk_drm_mode_config_funcs;
  182. ret = component_bind_all(drm->dev, drm);
  183. if (ret)
  184. goto err_config_cleanup;
  185. /*
  186. * We currently support two fixed data streams, each optional,
  187. * and each statically assigned to a crtc:
  188. * OVL0 -> COLOR0 -> AAL -> OD -> RDMA0 -> UFOE -> DSI0 ...
  189. */
  190. ret = mtk_drm_crtc_create(drm, private->data->main_path,
  191. private->data->main_len);
  192. if (ret < 0)
  193. goto err_component_unbind;
  194. /* ... and OVL1 -> COLOR1 -> GAMMA -> RDMA1 -> DPI0. */
  195. ret = mtk_drm_crtc_create(drm, private->data->ext_path,
  196. private->data->ext_len);
  197. if (ret < 0)
  198. goto err_component_unbind;
  199. /* Use OVL device for all DMA memory allocations */
  200. np = private->comp_node[private->data->main_path[0]] ?:
  201. private->comp_node[private->data->ext_path[0]];
  202. pdev = of_find_device_by_node(np);
  203. if (!pdev) {
  204. ret = -ENODEV;
  205. dev_err(drm->dev, "Need at least one OVL device\n");
  206. goto err_component_unbind;
  207. }
  208. private->dma_dev = &pdev->dev;
  209. /*
  210. * We don't use the drm_irq_install() helpers provided by the DRM
  211. * core, so we need to set this manually in order to allow the
  212. * DRM_IOCTL_WAIT_VBLANK to operate correctly.
  213. */
  214. drm->irq_enabled = true;
  215. ret = drm_vblank_init(drm, MAX_CRTC);
  216. if (ret < 0)
  217. goto err_component_unbind;
  218. drm_kms_helper_poll_init(drm);
  219. drm_mode_config_reset(drm);
  220. return 0;
  221. err_component_unbind:
  222. component_unbind_all(drm->dev, drm);
  223. err_config_cleanup:
  224. drm_mode_config_cleanup(drm);
  225. return ret;
  226. }
  227. static void mtk_drm_kms_deinit(struct drm_device *drm)
  228. {
  229. drm_kms_helper_poll_fini(drm);
  230. component_unbind_all(drm->dev, drm);
  231. drm_mode_config_cleanup(drm);
  232. }
  233. static const struct file_operations mtk_drm_fops = {
  234. .owner = THIS_MODULE,
  235. .open = drm_open,
  236. .release = drm_release,
  237. .unlocked_ioctl = drm_ioctl,
  238. .mmap = mtk_drm_gem_mmap,
  239. .poll = drm_poll,
  240. .read = drm_read,
  241. .compat_ioctl = drm_compat_ioctl,
  242. };
  243. static struct drm_driver mtk_drm_driver = {
  244. .driver_features = DRIVER_MODESET | DRIVER_GEM | DRIVER_PRIME |
  245. DRIVER_ATOMIC,
  246. .gem_free_object_unlocked = mtk_drm_gem_free_object,
  247. .gem_vm_ops = &drm_gem_cma_vm_ops,
  248. .dumb_create = mtk_drm_gem_dumb_create,
  249. .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
  250. .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
  251. .gem_prime_export = drm_gem_prime_export,
  252. .gem_prime_import = drm_gem_prime_import,
  253. .gem_prime_get_sg_table = mtk_gem_prime_get_sg_table,
  254. .gem_prime_import_sg_table = mtk_gem_prime_import_sg_table,
  255. .gem_prime_mmap = mtk_drm_gem_mmap_buf,
  256. .fops = &mtk_drm_fops,
  257. .name = DRIVER_NAME,
  258. .desc = DRIVER_DESC,
  259. .date = DRIVER_DATE,
  260. .major = DRIVER_MAJOR,
  261. .minor = DRIVER_MINOR,
  262. };
  263. static int compare_of(struct device *dev, void *data)
  264. {
  265. return dev->of_node == data;
  266. }
  267. static int mtk_drm_bind(struct device *dev)
  268. {
  269. struct mtk_drm_private *private = dev_get_drvdata(dev);
  270. struct drm_device *drm;
  271. int ret;
  272. drm = drm_dev_alloc(&mtk_drm_driver, dev);
  273. if (IS_ERR(drm))
  274. return PTR_ERR(drm);
  275. drm->dev_private = private;
  276. private->drm = drm;
  277. ret = mtk_drm_kms_init(drm);
  278. if (ret < 0)
  279. goto err_free;
  280. ret = drm_dev_register(drm, 0);
  281. if (ret < 0)
  282. goto err_deinit;
  283. return 0;
  284. err_deinit:
  285. mtk_drm_kms_deinit(drm);
  286. err_free:
  287. drm_dev_unref(drm);
  288. return ret;
  289. }
  290. static void mtk_drm_unbind(struct device *dev)
  291. {
  292. struct mtk_drm_private *private = dev_get_drvdata(dev);
  293. drm_dev_unregister(private->drm);
  294. drm_dev_unref(private->drm);
  295. private->drm = NULL;
  296. }
  297. static const struct component_master_ops mtk_drm_ops = {
  298. .bind = mtk_drm_bind,
  299. .unbind = mtk_drm_unbind,
  300. };
  301. static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
  302. { .compatible = "mediatek,mt2701-disp-ovl", .data = (void *)MTK_DISP_OVL },
  303. { .compatible = "mediatek,mt8173-disp-ovl", .data = (void *)MTK_DISP_OVL },
  304. { .compatible = "mediatek,mt2701-disp-rdma", .data = (void *)MTK_DISP_RDMA },
  305. { .compatible = "mediatek,mt8173-disp-rdma", .data = (void *)MTK_DISP_RDMA },
  306. { .compatible = "mediatek,mt8173-disp-wdma", .data = (void *)MTK_DISP_WDMA },
  307. { .compatible = "mediatek,mt2701-disp-color", .data = (void *)MTK_DISP_COLOR },
  308. { .compatible = "mediatek,mt8173-disp-color", .data = (void *)MTK_DISP_COLOR },
  309. { .compatible = "mediatek,mt8173-disp-aal", .data = (void *)MTK_DISP_AAL},
  310. { .compatible = "mediatek,mt8173-disp-gamma", .data = (void *)MTK_DISP_GAMMA, },
  311. { .compatible = "mediatek,mt8173-disp-ufoe", .data = (void *)MTK_DISP_UFOE },
  312. { .compatible = "mediatek,mt2701-dsi", .data = (void *)MTK_DSI },
  313. { .compatible = "mediatek,mt8173-dsi", .data = (void *)MTK_DSI },
  314. { .compatible = "mediatek,mt8173-dpi", .data = (void *)MTK_DPI },
  315. { .compatible = "mediatek,mt2701-disp-mutex", .data = (void *)MTK_DISP_MUTEX },
  316. { .compatible = "mediatek,mt8173-disp-mutex", .data = (void *)MTK_DISP_MUTEX },
  317. { .compatible = "mediatek,mt2701-disp-pwm", .data = (void *)MTK_DISP_BLS },
  318. { .compatible = "mediatek,mt8173-disp-pwm", .data = (void *)MTK_DISP_PWM },
  319. { .compatible = "mediatek,mt8173-disp-od", .data = (void *)MTK_DISP_OD },
  320. { }
  321. };
  322. static int mtk_drm_probe(struct platform_device *pdev)
  323. {
  324. struct device *dev = &pdev->dev;
  325. struct mtk_drm_private *private;
  326. struct resource *mem;
  327. struct device_node *node;
  328. struct component_match *match = NULL;
  329. int ret;
  330. int i;
  331. private = devm_kzalloc(dev, sizeof(*private), GFP_KERNEL);
  332. if (!private)
  333. return -ENOMEM;
  334. mutex_init(&private->commit.lock);
  335. INIT_WORK(&private->commit.work, mtk_atomic_work);
  336. private->data = of_device_get_match_data(dev);
  337. mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  338. private->config_regs = devm_ioremap_resource(dev, mem);
  339. if (IS_ERR(private->config_regs)) {
  340. ret = PTR_ERR(private->config_regs);
  341. dev_err(dev, "Failed to ioremap mmsys-config resource: %d\n",
  342. ret);
  343. return ret;
  344. }
  345. /* Iterate over sibling DISP function blocks */
  346. for_each_child_of_node(dev->of_node->parent, node) {
  347. const struct of_device_id *of_id;
  348. enum mtk_ddp_comp_type comp_type;
  349. int comp_id;
  350. of_id = of_match_node(mtk_ddp_comp_dt_ids, node);
  351. if (!of_id)
  352. continue;
  353. if (!of_device_is_available(node)) {
  354. dev_dbg(dev, "Skipping disabled component %pOF\n",
  355. node);
  356. continue;
  357. }
  358. comp_type = (enum mtk_ddp_comp_type)of_id->data;
  359. if (comp_type == MTK_DISP_MUTEX) {
  360. private->mutex_node = of_node_get(node);
  361. continue;
  362. }
  363. comp_id = mtk_ddp_comp_get_id(node, comp_type);
  364. if (comp_id < 0) {
  365. dev_warn(dev, "Skipping unknown component %pOF\n",
  366. node);
  367. continue;
  368. }
  369. private->comp_node[comp_id] = of_node_get(node);
  370. /*
  371. * Currently only the COLOR, OVL, RDMA, DSI, and DPI blocks have
  372. * separate component platform drivers and initialize their own
  373. * DDP component structure. The others are initialized here.
  374. */
  375. if (comp_type == MTK_DISP_COLOR ||
  376. comp_type == MTK_DISP_OVL ||
  377. comp_type == MTK_DISP_RDMA ||
  378. comp_type == MTK_DSI ||
  379. comp_type == MTK_DPI) {
  380. dev_info(dev, "Adding component match for %pOF\n",
  381. node);
  382. drm_of_component_match_add(dev, &match, compare_of,
  383. node);
  384. } else {
  385. struct mtk_ddp_comp *comp;
  386. comp = devm_kzalloc(dev, sizeof(*comp), GFP_KERNEL);
  387. if (!comp) {
  388. ret = -ENOMEM;
  389. goto err_node;
  390. }
  391. ret = mtk_ddp_comp_init(dev, node, comp, comp_id, NULL);
  392. if (ret)
  393. goto err_node;
  394. private->ddp_comp[comp_id] = comp;
  395. }
  396. }
  397. if (!private->mutex_node) {
  398. dev_err(dev, "Failed to find disp-mutex node\n");
  399. ret = -ENODEV;
  400. goto err_node;
  401. }
  402. pm_runtime_enable(dev);
  403. platform_set_drvdata(pdev, private);
  404. ret = component_master_add_with_match(dev, &mtk_drm_ops, match);
  405. if (ret)
  406. goto err_pm;
  407. return 0;
  408. err_pm:
  409. pm_runtime_disable(dev);
  410. err_node:
  411. of_node_put(private->mutex_node);
  412. for (i = 0; i < DDP_COMPONENT_ID_MAX; i++)
  413. of_node_put(private->comp_node[i]);
  414. return ret;
  415. }
  416. static int mtk_drm_remove(struct platform_device *pdev)
  417. {
  418. struct mtk_drm_private *private = platform_get_drvdata(pdev);
  419. struct drm_device *drm = private->drm;
  420. int i;
  421. drm_dev_unregister(drm);
  422. mtk_drm_kms_deinit(drm);
  423. drm_dev_unref(drm);
  424. component_master_del(&pdev->dev, &mtk_drm_ops);
  425. pm_runtime_disable(&pdev->dev);
  426. of_node_put(private->mutex_node);
  427. for (i = 0; i < DDP_COMPONENT_ID_MAX; i++)
  428. of_node_put(private->comp_node[i]);
  429. return 0;
  430. }
  431. #ifdef CONFIG_PM_SLEEP
  432. static int mtk_drm_sys_suspend(struct device *dev)
  433. {
  434. struct mtk_drm_private *private = dev_get_drvdata(dev);
  435. struct drm_device *drm = private->drm;
  436. drm_kms_helper_poll_disable(drm);
  437. private->suspend_state = drm_atomic_helper_suspend(drm);
  438. if (IS_ERR(private->suspend_state)) {
  439. drm_kms_helper_poll_enable(drm);
  440. return PTR_ERR(private->suspend_state);
  441. }
  442. DRM_DEBUG_DRIVER("mtk_drm_sys_suspend\n");
  443. return 0;
  444. }
  445. static int mtk_drm_sys_resume(struct device *dev)
  446. {
  447. struct mtk_drm_private *private = dev_get_drvdata(dev);
  448. struct drm_device *drm = private->drm;
  449. drm_atomic_helper_resume(drm, private->suspend_state);
  450. drm_kms_helper_poll_enable(drm);
  451. DRM_DEBUG_DRIVER("mtk_drm_sys_resume\n");
  452. return 0;
  453. }
  454. #endif
  455. static SIMPLE_DEV_PM_OPS(mtk_drm_pm_ops, mtk_drm_sys_suspend,
  456. mtk_drm_sys_resume);
  457. static const struct of_device_id mtk_drm_of_ids[] = {
  458. { .compatible = "mediatek,mt2701-mmsys",
  459. .data = &mt2701_mmsys_driver_data},
  460. { .compatible = "mediatek,mt8173-mmsys",
  461. .data = &mt8173_mmsys_driver_data},
  462. { }
  463. };
  464. static struct platform_driver mtk_drm_platform_driver = {
  465. .probe = mtk_drm_probe,
  466. .remove = mtk_drm_remove,
  467. .driver = {
  468. .name = "mediatek-drm",
  469. .of_match_table = mtk_drm_of_ids,
  470. .pm = &mtk_drm_pm_ops,
  471. },
  472. };
  473. static struct platform_driver * const mtk_drm_drivers[] = {
  474. &mtk_ddp_driver,
  475. &mtk_disp_color_driver,
  476. &mtk_disp_ovl_driver,
  477. &mtk_disp_rdma_driver,
  478. &mtk_dpi_driver,
  479. &mtk_drm_platform_driver,
  480. &mtk_dsi_driver,
  481. &mtk_mipi_tx_driver,
  482. };
  483. static int __init mtk_drm_init(void)
  484. {
  485. return platform_register_drivers(mtk_drm_drivers,
  486. ARRAY_SIZE(mtk_drm_drivers));
  487. }
  488. static void __exit mtk_drm_exit(void)
  489. {
  490. platform_unregister_drivers(mtk_drm_drivers,
  491. ARRAY_SIZE(mtk_drm_drivers));
  492. }
  493. module_init(mtk_drm_init);
  494. module_exit(mtk_drm_exit);
  495. MODULE_AUTHOR("YT SHEN <yt.shen@mediatek.com>");
  496. MODULE_DESCRIPTION("Mediatek SoC DRM driver");
  497. MODULE_LICENSE("GPL v2");