i915_gem_context.c 24 KB

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  1. /*
  2. * Copyright © 2011-2012 Intel Corporation
  3. *
  4. * Permission is hereby granted, free of charge, to any person obtaining a
  5. * copy of this software and associated documentation files (the "Software"),
  6. * to deal in the Software without restriction, including without limitation
  7. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8. * and/or sell copies of the Software, and to permit persons to whom the
  9. * Software is furnished to do so, subject to the following conditions:
  10. *
  11. * The above copyright notice and this permission notice (including the next
  12. * paragraph) shall be included in all copies or substantial portions of the
  13. * Software.
  14. *
  15. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  18. * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20. * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21. * IN THE SOFTWARE.
  22. *
  23. * Authors:
  24. * Ben Widawsky <ben@bwidawsk.net>
  25. *
  26. */
  27. /*
  28. * This file implements HW context support. On gen5+ a HW context consists of an
  29. * opaque GPU object which is referenced at times of context saves and restores.
  30. * With RC6 enabled, the context is also referenced as the GPU enters and exists
  31. * from RC6 (GPU has it's own internal power context, except on gen5). Though
  32. * something like a context does exist for the media ring, the code only
  33. * supports contexts for the render ring.
  34. *
  35. * In software, there is a distinction between contexts created by the user,
  36. * and the default HW context. The default HW context is used by GPU clients
  37. * that do not request setup of their own hardware context. The default
  38. * context's state is never restored to help prevent programming errors. This
  39. * would happen if a client ran and piggy-backed off another clients GPU state.
  40. * The default context only exists to give the GPU some offset to load as the
  41. * current to invoke a save of the context we actually care about. In fact, the
  42. * code could likely be constructed, albeit in a more complicated fashion, to
  43. * never use the default context, though that limits the driver's ability to
  44. * swap out, and/or destroy other contexts.
  45. *
  46. * All other contexts are created as a request by the GPU client. These contexts
  47. * store GPU state, and thus allow GPU clients to not re-emit state (and
  48. * potentially query certain state) at any time. The kernel driver makes
  49. * certain that the appropriate commands are inserted.
  50. *
  51. * The context life cycle is semi-complicated in that context BOs may live
  52. * longer than the context itself because of the way the hardware, and object
  53. * tracking works. Below is a very crude representation of the state machine
  54. * describing the context life.
  55. * refcount pincount active
  56. * S0: initial state 0 0 0
  57. * S1: context created 1 0 0
  58. * S2: context is currently running 2 1 X
  59. * S3: GPU referenced, but not current 2 0 1
  60. * S4: context is current, but destroyed 1 1 0
  61. * S5: like S3, but destroyed 1 0 1
  62. *
  63. * The most common (but not all) transitions:
  64. * S0->S1: client creates a context
  65. * S1->S2: client submits execbuf with context
  66. * S2->S3: other clients submits execbuf with context
  67. * S3->S1: context object was retired
  68. * S3->S2: clients submits another execbuf
  69. * S2->S4: context destroy called with current context
  70. * S3->S5->S0: destroy path
  71. * S4->S5->S0: destroy path on current context
  72. *
  73. * There are two confusing terms used above:
  74. * The "current context" means the context which is currently running on the
  75. * GPU. The GPU has loaded its state already and has stored away the gtt
  76. * offset of the BO. The GPU is not actively referencing the data at this
  77. * offset, but it will on the next context switch. The only way to avoid this
  78. * is to do a GPU reset.
  79. *
  80. * An "active context' is one which was previously the "current context" and is
  81. * on the active list waiting for the next context switch to occur. Until this
  82. * happens, the object must remain at the same gtt offset. It is therefore
  83. * possible to destroy a context, but it is still active.
  84. *
  85. */
  86. #include <linux/log2.h>
  87. #include <drm/drmP.h>
  88. #include <drm/i915_drm.h>
  89. #include "i915_drv.h"
  90. #include "i915_trace.h"
  91. #include "intel_workarounds.h"
  92. #define ALL_L3_SLICES(dev) (1 << NUM_L3_SLICES(dev)) - 1
  93. static void lut_close(struct i915_gem_context *ctx)
  94. {
  95. struct i915_lut_handle *lut, *ln;
  96. struct radix_tree_iter iter;
  97. void __rcu **slot;
  98. list_for_each_entry_safe(lut, ln, &ctx->handles_list, ctx_link) {
  99. list_del(&lut->obj_link);
  100. kmem_cache_free(ctx->i915->luts, lut);
  101. }
  102. rcu_read_lock();
  103. radix_tree_for_each_slot(slot, &ctx->handles_vma, &iter, 0) {
  104. struct i915_vma *vma = rcu_dereference_raw(*slot);
  105. radix_tree_iter_delete(&ctx->handles_vma, &iter, slot);
  106. __i915_gem_object_release_unless_active(vma->obj);
  107. }
  108. rcu_read_unlock();
  109. }
  110. static void i915_gem_context_free(struct i915_gem_context *ctx)
  111. {
  112. unsigned int n;
  113. lockdep_assert_held(&ctx->i915->drm.struct_mutex);
  114. GEM_BUG_ON(!i915_gem_context_is_closed(ctx));
  115. i915_ppgtt_put(ctx->ppgtt);
  116. for (n = 0; n < ARRAY_SIZE(ctx->__engine); n++) {
  117. struct intel_context *ce = &ctx->__engine[n];
  118. if (!ce->state)
  119. continue;
  120. WARN_ON(ce->pin_count);
  121. if (ce->ring)
  122. intel_ring_free(ce->ring);
  123. __i915_gem_object_release_unless_active(ce->state->obj);
  124. }
  125. kfree(ctx->name);
  126. put_pid(ctx->pid);
  127. list_del(&ctx->link);
  128. ida_simple_remove(&ctx->i915->contexts.hw_ida, ctx->hw_id);
  129. kfree_rcu(ctx, rcu);
  130. }
  131. static void contexts_free(struct drm_i915_private *i915)
  132. {
  133. struct llist_node *freed = llist_del_all(&i915->contexts.free_list);
  134. struct i915_gem_context *ctx, *cn;
  135. lockdep_assert_held(&i915->drm.struct_mutex);
  136. llist_for_each_entry_safe(ctx, cn, freed, free_link)
  137. i915_gem_context_free(ctx);
  138. }
  139. static void contexts_free_first(struct drm_i915_private *i915)
  140. {
  141. struct i915_gem_context *ctx;
  142. struct llist_node *freed;
  143. lockdep_assert_held(&i915->drm.struct_mutex);
  144. freed = llist_del_first(&i915->contexts.free_list);
  145. if (!freed)
  146. return;
  147. ctx = container_of(freed, typeof(*ctx), free_link);
  148. i915_gem_context_free(ctx);
  149. }
  150. static void contexts_free_worker(struct work_struct *work)
  151. {
  152. struct drm_i915_private *i915 =
  153. container_of(work, typeof(*i915), contexts.free_work);
  154. mutex_lock(&i915->drm.struct_mutex);
  155. contexts_free(i915);
  156. mutex_unlock(&i915->drm.struct_mutex);
  157. }
  158. void i915_gem_context_release(struct kref *ref)
  159. {
  160. struct i915_gem_context *ctx = container_of(ref, typeof(*ctx), ref);
  161. struct drm_i915_private *i915 = ctx->i915;
  162. trace_i915_context_free(ctx);
  163. if (llist_add(&ctx->free_link, &i915->contexts.free_list))
  164. queue_work(i915->wq, &i915->contexts.free_work);
  165. }
  166. static void context_close(struct i915_gem_context *ctx)
  167. {
  168. i915_gem_context_set_closed(ctx);
  169. /*
  170. * The LUT uses the VMA as a backpointer to unref the object,
  171. * so we need to clear the LUT before we close all the VMA (inside
  172. * the ppgtt).
  173. */
  174. lut_close(ctx);
  175. if (ctx->ppgtt)
  176. i915_ppgtt_close(&ctx->ppgtt->base);
  177. ctx->file_priv = ERR_PTR(-EBADF);
  178. i915_gem_context_put(ctx);
  179. }
  180. static int assign_hw_id(struct drm_i915_private *dev_priv, unsigned *out)
  181. {
  182. int ret;
  183. unsigned int max;
  184. if (INTEL_GEN(dev_priv) >= 11)
  185. max = GEN11_MAX_CONTEXT_HW_ID;
  186. else
  187. max = MAX_CONTEXT_HW_ID;
  188. ret = ida_simple_get(&dev_priv->contexts.hw_ida,
  189. 0, max, GFP_KERNEL);
  190. if (ret < 0) {
  191. /* Contexts are only released when no longer active.
  192. * Flush any pending retires to hopefully release some
  193. * stale contexts and try again.
  194. */
  195. i915_retire_requests(dev_priv);
  196. ret = ida_simple_get(&dev_priv->contexts.hw_ida,
  197. 0, max, GFP_KERNEL);
  198. if (ret < 0)
  199. return ret;
  200. }
  201. *out = ret;
  202. return 0;
  203. }
  204. static u32 default_desc_template(const struct drm_i915_private *i915,
  205. const struct i915_hw_ppgtt *ppgtt)
  206. {
  207. u32 address_mode;
  208. u32 desc;
  209. desc = GEN8_CTX_VALID | GEN8_CTX_PRIVILEGE;
  210. address_mode = INTEL_LEGACY_32B_CONTEXT;
  211. if (ppgtt && i915_vm_is_48bit(&ppgtt->base))
  212. address_mode = INTEL_LEGACY_64B_CONTEXT;
  213. desc |= address_mode << GEN8_CTX_ADDRESSING_MODE_SHIFT;
  214. if (IS_GEN8(i915))
  215. desc |= GEN8_CTX_L3LLC_COHERENT;
  216. /* TODO: WaDisableLiteRestore when we start using semaphore
  217. * signalling between Command Streamers
  218. * ring->ctx_desc_template |= GEN8_CTX_FORCE_RESTORE;
  219. */
  220. return desc;
  221. }
  222. static struct i915_gem_context *
  223. __create_hw_context(struct drm_i915_private *dev_priv,
  224. struct drm_i915_file_private *file_priv)
  225. {
  226. struct i915_gem_context *ctx;
  227. int ret;
  228. ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
  229. if (ctx == NULL)
  230. return ERR_PTR(-ENOMEM);
  231. ret = assign_hw_id(dev_priv, &ctx->hw_id);
  232. if (ret) {
  233. kfree(ctx);
  234. return ERR_PTR(ret);
  235. }
  236. kref_init(&ctx->ref);
  237. list_add_tail(&ctx->link, &dev_priv->contexts.list);
  238. ctx->i915 = dev_priv;
  239. ctx->sched.priority = I915_PRIORITY_NORMAL;
  240. INIT_RADIX_TREE(&ctx->handles_vma, GFP_KERNEL);
  241. INIT_LIST_HEAD(&ctx->handles_list);
  242. /* Default context will never have a file_priv */
  243. ret = DEFAULT_CONTEXT_HANDLE;
  244. if (file_priv) {
  245. ret = idr_alloc(&file_priv->context_idr, ctx,
  246. DEFAULT_CONTEXT_HANDLE, 0, GFP_KERNEL);
  247. if (ret < 0)
  248. goto err_lut;
  249. }
  250. ctx->user_handle = ret;
  251. ctx->file_priv = file_priv;
  252. if (file_priv) {
  253. ctx->pid = get_task_pid(current, PIDTYPE_PID);
  254. ctx->name = kasprintf(GFP_KERNEL, "%s[%d]/%x",
  255. current->comm,
  256. pid_nr(ctx->pid),
  257. ctx->user_handle);
  258. if (!ctx->name) {
  259. ret = -ENOMEM;
  260. goto err_pid;
  261. }
  262. }
  263. /* NB: Mark all slices as needing a remap so that when the context first
  264. * loads it will restore whatever remap state already exists. If there
  265. * is no remap info, it will be a NOP. */
  266. ctx->remap_slice = ALL_L3_SLICES(dev_priv);
  267. i915_gem_context_set_bannable(ctx);
  268. ctx->ring_size = 4 * PAGE_SIZE;
  269. ctx->desc_template =
  270. default_desc_template(dev_priv, dev_priv->mm.aliasing_ppgtt);
  271. /*
  272. * GuC requires the ring to be placed in Non-WOPCM memory. If GuC is not
  273. * present or not in use we still need a small bias as ring wraparound
  274. * at offset 0 sometimes hangs. No idea why.
  275. */
  276. if (USES_GUC(dev_priv))
  277. ctx->ggtt_offset_bias = dev_priv->guc.ggtt_pin_bias;
  278. else
  279. ctx->ggtt_offset_bias = I915_GTT_PAGE_SIZE;
  280. return ctx;
  281. err_pid:
  282. put_pid(ctx->pid);
  283. idr_remove(&file_priv->context_idr, ctx->user_handle);
  284. err_lut:
  285. context_close(ctx);
  286. return ERR_PTR(ret);
  287. }
  288. static void __destroy_hw_context(struct i915_gem_context *ctx,
  289. struct drm_i915_file_private *file_priv)
  290. {
  291. idr_remove(&file_priv->context_idr, ctx->user_handle);
  292. context_close(ctx);
  293. }
  294. static struct i915_gem_context *
  295. i915_gem_create_context(struct drm_i915_private *dev_priv,
  296. struct drm_i915_file_private *file_priv)
  297. {
  298. struct i915_gem_context *ctx;
  299. lockdep_assert_held(&dev_priv->drm.struct_mutex);
  300. /* Reap the most stale context */
  301. contexts_free_first(dev_priv);
  302. ctx = __create_hw_context(dev_priv, file_priv);
  303. if (IS_ERR(ctx))
  304. return ctx;
  305. if (USES_FULL_PPGTT(dev_priv)) {
  306. struct i915_hw_ppgtt *ppgtt;
  307. ppgtt = i915_ppgtt_create(dev_priv, file_priv, ctx->name);
  308. if (IS_ERR(ppgtt)) {
  309. DRM_DEBUG_DRIVER("PPGTT setup failed (%ld)\n",
  310. PTR_ERR(ppgtt));
  311. __destroy_hw_context(ctx, file_priv);
  312. return ERR_CAST(ppgtt);
  313. }
  314. ctx->ppgtt = ppgtt;
  315. ctx->desc_template = default_desc_template(dev_priv, ppgtt);
  316. }
  317. trace_i915_context_create(ctx);
  318. return ctx;
  319. }
  320. /**
  321. * i915_gem_context_create_gvt - create a GVT GEM context
  322. * @dev: drm device *
  323. *
  324. * This function is used to create a GVT specific GEM context.
  325. *
  326. * Returns:
  327. * pointer to i915_gem_context on success, error pointer if failed
  328. *
  329. */
  330. struct i915_gem_context *
  331. i915_gem_context_create_gvt(struct drm_device *dev)
  332. {
  333. struct i915_gem_context *ctx;
  334. int ret;
  335. if (!IS_ENABLED(CONFIG_DRM_I915_GVT))
  336. return ERR_PTR(-ENODEV);
  337. ret = i915_mutex_lock_interruptible(dev);
  338. if (ret)
  339. return ERR_PTR(ret);
  340. ctx = __create_hw_context(to_i915(dev), NULL);
  341. if (IS_ERR(ctx))
  342. goto out;
  343. ctx->file_priv = ERR_PTR(-EBADF);
  344. i915_gem_context_set_closed(ctx); /* not user accessible */
  345. i915_gem_context_clear_bannable(ctx);
  346. i915_gem_context_set_force_single_submission(ctx);
  347. if (!USES_GUC_SUBMISSION(to_i915(dev)))
  348. ctx->ring_size = 512 * PAGE_SIZE; /* Max ring buffer size */
  349. GEM_BUG_ON(i915_gem_context_is_kernel(ctx));
  350. out:
  351. mutex_unlock(&dev->struct_mutex);
  352. return ctx;
  353. }
  354. struct i915_gem_context *
  355. i915_gem_context_create_kernel(struct drm_i915_private *i915, int prio)
  356. {
  357. struct i915_gem_context *ctx;
  358. ctx = i915_gem_create_context(i915, NULL);
  359. if (IS_ERR(ctx))
  360. return ctx;
  361. i915_gem_context_clear_bannable(ctx);
  362. ctx->sched.priority = prio;
  363. ctx->ring_size = PAGE_SIZE;
  364. GEM_BUG_ON(!i915_gem_context_is_kernel(ctx));
  365. return ctx;
  366. }
  367. static void
  368. destroy_kernel_context(struct i915_gem_context **ctxp)
  369. {
  370. struct i915_gem_context *ctx;
  371. /* Keep the context ref so that we can free it immediately ourselves */
  372. ctx = i915_gem_context_get(fetch_and_zero(ctxp));
  373. GEM_BUG_ON(!i915_gem_context_is_kernel(ctx));
  374. context_close(ctx);
  375. i915_gem_context_free(ctx);
  376. }
  377. static bool needs_preempt_context(struct drm_i915_private *i915)
  378. {
  379. return HAS_LOGICAL_RING_PREEMPTION(i915);
  380. }
  381. int i915_gem_contexts_init(struct drm_i915_private *dev_priv)
  382. {
  383. struct i915_gem_context *ctx;
  384. int ret;
  385. /* Reassure ourselves we are only called once */
  386. GEM_BUG_ON(dev_priv->kernel_context);
  387. GEM_BUG_ON(dev_priv->preempt_context);
  388. ret = intel_ctx_workarounds_init(dev_priv);
  389. if (ret)
  390. return ret;
  391. INIT_LIST_HEAD(&dev_priv->contexts.list);
  392. INIT_WORK(&dev_priv->contexts.free_work, contexts_free_worker);
  393. init_llist_head(&dev_priv->contexts.free_list);
  394. /* Using the simple ida interface, the max is limited by sizeof(int) */
  395. BUILD_BUG_ON(MAX_CONTEXT_HW_ID > INT_MAX);
  396. BUILD_BUG_ON(GEN11_MAX_CONTEXT_HW_ID > INT_MAX);
  397. ida_init(&dev_priv->contexts.hw_ida);
  398. /* lowest priority; idle task */
  399. ctx = i915_gem_context_create_kernel(dev_priv, I915_PRIORITY_MIN);
  400. if (IS_ERR(ctx)) {
  401. DRM_ERROR("Failed to create default global context\n");
  402. return PTR_ERR(ctx);
  403. }
  404. /*
  405. * For easy recognisablity, we want the kernel context to be 0 and then
  406. * all user contexts will have non-zero hw_id.
  407. */
  408. GEM_BUG_ON(ctx->hw_id);
  409. dev_priv->kernel_context = ctx;
  410. /* highest priority; preempting task */
  411. if (needs_preempt_context(dev_priv)) {
  412. ctx = i915_gem_context_create_kernel(dev_priv, INT_MAX);
  413. if (!IS_ERR(ctx))
  414. dev_priv->preempt_context = ctx;
  415. else
  416. DRM_ERROR("Failed to create preempt context; disabling preemption\n");
  417. }
  418. DRM_DEBUG_DRIVER("%s context support initialized\n",
  419. dev_priv->engine[RCS]->context_size ? "logical" :
  420. "fake");
  421. return 0;
  422. }
  423. void i915_gem_contexts_lost(struct drm_i915_private *dev_priv)
  424. {
  425. struct intel_engine_cs *engine;
  426. enum intel_engine_id id;
  427. lockdep_assert_held(&dev_priv->drm.struct_mutex);
  428. for_each_engine(engine, dev_priv, id) {
  429. engine->legacy_active_context = NULL;
  430. engine->legacy_active_ppgtt = NULL;
  431. if (!engine->last_retired_context)
  432. continue;
  433. intel_context_unpin(engine->last_retired_context, engine);
  434. engine->last_retired_context = NULL;
  435. }
  436. }
  437. void i915_gem_contexts_fini(struct drm_i915_private *i915)
  438. {
  439. lockdep_assert_held(&i915->drm.struct_mutex);
  440. if (i915->preempt_context)
  441. destroy_kernel_context(&i915->preempt_context);
  442. destroy_kernel_context(&i915->kernel_context);
  443. /* Must free all deferred contexts (via flush_workqueue) first */
  444. ida_destroy(&i915->contexts.hw_ida);
  445. }
  446. static int context_idr_cleanup(int id, void *p, void *data)
  447. {
  448. struct i915_gem_context *ctx = p;
  449. context_close(ctx);
  450. return 0;
  451. }
  452. int i915_gem_context_open(struct drm_i915_private *i915,
  453. struct drm_file *file)
  454. {
  455. struct drm_i915_file_private *file_priv = file->driver_priv;
  456. struct i915_gem_context *ctx;
  457. idr_init(&file_priv->context_idr);
  458. mutex_lock(&i915->drm.struct_mutex);
  459. ctx = i915_gem_create_context(i915, file_priv);
  460. mutex_unlock(&i915->drm.struct_mutex);
  461. if (IS_ERR(ctx)) {
  462. idr_destroy(&file_priv->context_idr);
  463. return PTR_ERR(ctx);
  464. }
  465. GEM_BUG_ON(i915_gem_context_is_kernel(ctx));
  466. return 0;
  467. }
  468. void i915_gem_context_close(struct drm_file *file)
  469. {
  470. struct drm_i915_file_private *file_priv = file->driver_priv;
  471. lockdep_assert_held(&file_priv->dev_priv->drm.struct_mutex);
  472. idr_for_each(&file_priv->context_idr, context_idr_cleanup, NULL);
  473. idr_destroy(&file_priv->context_idr);
  474. }
  475. static struct i915_request *
  476. last_request_on_engine(struct i915_timeline *timeline,
  477. struct intel_engine_cs *engine)
  478. {
  479. struct i915_request *rq;
  480. if (timeline == &engine->timeline)
  481. return NULL;
  482. rq = i915_gem_active_raw(&timeline->last_request,
  483. &engine->i915->drm.struct_mutex);
  484. if (rq && rq->engine == engine)
  485. return rq;
  486. return NULL;
  487. }
  488. static bool engine_has_idle_kernel_context(struct intel_engine_cs *engine)
  489. {
  490. struct i915_timeline *timeline;
  491. list_for_each_entry(timeline, &engine->i915->gt.timelines, link) {
  492. if (last_request_on_engine(timeline, engine))
  493. return false;
  494. }
  495. return intel_engine_has_kernel_context(engine);
  496. }
  497. int i915_gem_switch_to_kernel_context(struct drm_i915_private *dev_priv)
  498. {
  499. struct intel_engine_cs *engine;
  500. struct i915_timeline *timeline;
  501. enum intel_engine_id id;
  502. lockdep_assert_held(&dev_priv->drm.struct_mutex);
  503. i915_retire_requests(dev_priv);
  504. for_each_engine(engine, dev_priv, id) {
  505. struct i915_request *rq;
  506. if (engine_has_idle_kernel_context(engine))
  507. continue;
  508. rq = i915_request_alloc(engine, dev_priv->kernel_context);
  509. if (IS_ERR(rq))
  510. return PTR_ERR(rq);
  511. /* Queue this switch after all other activity */
  512. list_for_each_entry(timeline, &dev_priv->gt.timelines, link) {
  513. struct i915_request *prev;
  514. prev = last_request_on_engine(timeline, engine);
  515. if (prev)
  516. i915_sw_fence_await_sw_fence_gfp(&rq->submit,
  517. &prev->submit,
  518. I915_FENCE_GFP);
  519. }
  520. /*
  521. * Force a flush after the switch to ensure that all rendering
  522. * and operations prior to switching to the kernel context hits
  523. * memory. This should be guaranteed by the previous request,
  524. * but an extra layer of paranoia before we declare the system
  525. * idle (on suspend etc) is advisable!
  526. */
  527. __i915_request_add(rq, true);
  528. }
  529. return 0;
  530. }
  531. static bool client_is_banned(struct drm_i915_file_private *file_priv)
  532. {
  533. return atomic_read(&file_priv->context_bans) > I915_MAX_CLIENT_CONTEXT_BANS;
  534. }
  535. int i915_gem_context_create_ioctl(struct drm_device *dev, void *data,
  536. struct drm_file *file)
  537. {
  538. struct drm_i915_private *dev_priv = to_i915(dev);
  539. struct drm_i915_gem_context_create *args = data;
  540. struct drm_i915_file_private *file_priv = file->driver_priv;
  541. struct i915_gem_context *ctx;
  542. int ret;
  543. if (!dev_priv->engine[RCS]->context_size)
  544. return -ENODEV;
  545. if (args->pad != 0)
  546. return -EINVAL;
  547. if (client_is_banned(file_priv)) {
  548. DRM_DEBUG("client %s[%d] banned from creating ctx\n",
  549. current->comm,
  550. pid_nr(get_task_pid(current, PIDTYPE_PID)));
  551. return -EIO;
  552. }
  553. ret = i915_mutex_lock_interruptible(dev);
  554. if (ret)
  555. return ret;
  556. ctx = i915_gem_create_context(dev_priv, file_priv);
  557. mutex_unlock(&dev->struct_mutex);
  558. if (IS_ERR(ctx))
  559. return PTR_ERR(ctx);
  560. GEM_BUG_ON(i915_gem_context_is_kernel(ctx));
  561. args->ctx_id = ctx->user_handle;
  562. DRM_DEBUG("HW context %d created\n", args->ctx_id);
  563. return 0;
  564. }
  565. int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data,
  566. struct drm_file *file)
  567. {
  568. struct drm_i915_gem_context_destroy *args = data;
  569. struct drm_i915_file_private *file_priv = file->driver_priv;
  570. struct i915_gem_context *ctx;
  571. int ret;
  572. if (args->pad != 0)
  573. return -EINVAL;
  574. if (args->ctx_id == DEFAULT_CONTEXT_HANDLE)
  575. return -ENOENT;
  576. ctx = i915_gem_context_lookup(file_priv, args->ctx_id);
  577. if (!ctx)
  578. return -ENOENT;
  579. ret = mutex_lock_interruptible(&dev->struct_mutex);
  580. if (ret)
  581. goto out;
  582. __destroy_hw_context(ctx, file_priv);
  583. mutex_unlock(&dev->struct_mutex);
  584. out:
  585. i915_gem_context_put(ctx);
  586. return 0;
  587. }
  588. int i915_gem_context_getparam_ioctl(struct drm_device *dev, void *data,
  589. struct drm_file *file)
  590. {
  591. struct drm_i915_file_private *file_priv = file->driver_priv;
  592. struct drm_i915_gem_context_param *args = data;
  593. struct i915_gem_context *ctx;
  594. int ret = 0;
  595. ctx = i915_gem_context_lookup(file_priv, args->ctx_id);
  596. if (!ctx)
  597. return -ENOENT;
  598. args->size = 0;
  599. switch (args->param) {
  600. case I915_CONTEXT_PARAM_BAN_PERIOD:
  601. ret = -EINVAL;
  602. break;
  603. case I915_CONTEXT_PARAM_NO_ZEROMAP:
  604. args->value = ctx->flags & CONTEXT_NO_ZEROMAP;
  605. break;
  606. case I915_CONTEXT_PARAM_GTT_SIZE:
  607. if (ctx->ppgtt)
  608. args->value = ctx->ppgtt->base.total;
  609. else if (to_i915(dev)->mm.aliasing_ppgtt)
  610. args->value = to_i915(dev)->mm.aliasing_ppgtt->base.total;
  611. else
  612. args->value = to_i915(dev)->ggtt.base.total;
  613. break;
  614. case I915_CONTEXT_PARAM_NO_ERROR_CAPTURE:
  615. args->value = i915_gem_context_no_error_capture(ctx);
  616. break;
  617. case I915_CONTEXT_PARAM_BANNABLE:
  618. args->value = i915_gem_context_is_bannable(ctx);
  619. break;
  620. case I915_CONTEXT_PARAM_PRIORITY:
  621. args->value = ctx->sched.priority;
  622. break;
  623. default:
  624. ret = -EINVAL;
  625. break;
  626. }
  627. i915_gem_context_put(ctx);
  628. return ret;
  629. }
  630. int i915_gem_context_setparam_ioctl(struct drm_device *dev, void *data,
  631. struct drm_file *file)
  632. {
  633. struct drm_i915_file_private *file_priv = file->driver_priv;
  634. struct drm_i915_gem_context_param *args = data;
  635. struct i915_gem_context *ctx;
  636. int ret;
  637. ctx = i915_gem_context_lookup(file_priv, args->ctx_id);
  638. if (!ctx)
  639. return -ENOENT;
  640. ret = i915_mutex_lock_interruptible(dev);
  641. if (ret)
  642. goto out;
  643. switch (args->param) {
  644. case I915_CONTEXT_PARAM_BAN_PERIOD:
  645. ret = -EINVAL;
  646. break;
  647. case I915_CONTEXT_PARAM_NO_ZEROMAP:
  648. if (args->size) {
  649. ret = -EINVAL;
  650. } else {
  651. ctx->flags &= ~CONTEXT_NO_ZEROMAP;
  652. ctx->flags |= args->value ? CONTEXT_NO_ZEROMAP : 0;
  653. }
  654. break;
  655. case I915_CONTEXT_PARAM_NO_ERROR_CAPTURE:
  656. if (args->size)
  657. ret = -EINVAL;
  658. else if (args->value)
  659. i915_gem_context_set_no_error_capture(ctx);
  660. else
  661. i915_gem_context_clear_no_error_capture(ctx);
  662. break;
  663. case I915_CONTEXT_PARAM_BANNABLE:
  664. if (args->size)
  665. ret = -EINVAL;
  666. else if (!capable(CAP_SYS_ADMIN) && !args->value)
  667. ret = -EPERM;
  668. else if (args->value)
  669. i915_gem_context_set_bannable(ctx);
  670. else
  671. i915_gem_context_clear_bannable(ctx);
  672. break;
  673. case I915_CONTEXT_PARAM_PRIORITY:
  674. {
  675. s64 priority = args->value;
  676. if (args->size)
  677. ret = -EINVAL;
  678. else if (!(to_i915(dev)->caps.scheduler & I915_SCHEDULER_CAP_PRIORITY))
  679. ret = -ENODEV;
  680. else if (priority > I915_CONTEXT_MAX_USER_PRIORITY ||
  681. priority < I915_CONTEXT_MIN_USER_PRIORITY)
  682. ret = -EINVAL;
  683. else if (priority > I915_CONTEXT_DEFAULT_PRIORITY &&
  684. !capable(CAP_SYS_NICE))
  685. ret = -EPERM;
  686. else
  687. ctx->sched.priority = priority;
  688. }
  689. break;
  690. default:
  691. ret = -EINVAL;
  692. break;
  693. }
  694. mutex_unlock(&dev->struct_mutex);
  695. out:
  696. i915_gem_context_put(ctx);
  697. return ret;
  698. }
  699. int i915_gem_context_reset_stats_ioctl(struct drm_device *dev,
  700. void *data, struct drm_file *file)
  701. {
  702. struct drm_i915_private *dev_priv = to_i915(dev);
  703. struct drm_i915_reset_stats *args = data;
  704. struct i915_gem_context *ctx;
  705. int ret;
  706. if (args->flags || args->pad)
  707. return -EINVAL;
  708. ret = -ENOENT;
  709. rcu_read_lock();
  710. ctx = __i915_gem_context_lookup_rcu(file->driver_priv, args->ctx_id);
  711. if (!ctx)
  712. goto out;
  713. /*
  714. * We opt for unserialised reads here. This may result in tearing
  715. * in the extremely unlikely event of a GPU hang on this context
  716. * as we are querying them. If we need that extra layer of protection,
  717. * we should wrap the hangstats with a seqlock.
  718. */
  719. if (capable(CAP_SYS_ADMIN))
  720. args->reset_count = i915_reset_count(&dev_priv->gpu_error);
  721. else
  722. args->reset_count = 0;
  723. args->batch_active = atomic_read(&ctx->guilty_count);
  724. args->batch_pending = atomic_read(&ctx->active_count);
  725. ret = 0;
  726. out:
  727. rcu_read_unlock();
  728. return ret;
  729. }
  730. #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
  731. #include "selftests/mock_context.c"
  732. #include "selftests/i915_gem_context.c"
  733. #endif