armada_overlay.c 14 KB

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  1. /*
  2. * Copyright (C) 2012 Russell King
  3. * Rewritten from the dovefb driver, and Armada510 manuals.
  4. *
  5. * This program is free software; you can redistribute it and/or modify
  6. * it under the terms of the GNU General Public License version 2 as
  7. * published by the Free Software Foundation.
  8. */
  9. #include <drm/drmP.h>
  10. #include <drm/drm_atomic_helper.h>
  11. #include "armada_crtc.h"
  12. #include "armada_drm.h"
  13. #include "armada_fb.h"
  14. #include "armada_gem.h"
  15. #include "armada_hw.h"
  16. #include <drm/armada_drm.h>
  17. #include "armada_ioctlP.h"
  18. #include "armada_trace.h"
  19. struct armada_ovl_plane_properties {
  20. uint32_t colorkey_yr;
  21. uint32_t colorkey_ug;
  22. uint32_t colorkey_vb;
  23. #define K2R(val) (((val) >> 0) & 0xff)
  24. #define K2G(val) (((val) >> 8) & 0xff)
  25. #define K2B(val) (((val) >> 16) & 0xff)
  26. int16_t brightness;
  27. uint16_t contrast;
  28. uint16_t saturation;
  29. uint32_t colorkey_mode;
  30. };
  31. struct armada_ovl_plane {
  32. struct armada_plane base;
  33. struct armada_ovl_plane_properties prop;
  34. };
  35. #define drm_to_armada_ovl_plane(p) \
  36. container_of(p, struct armada_ovl_plane, base.base)
  37. static void
  38. armada_ovl_update_attr(struct armada_ovl_plane_properties *prop,
  39. struct armada_crtc *dcrtc)
  40. {
  41. writel_relaxed(prop->colorkey_yr, dcrtc->base + LCD_SPU_COLORKEY_Y);
  42. writel_relaxed(prop->colorkey_ug, dcrtc->base + LCD_SPU_COLORKEY_U);
  43. writel_relaxed(prop->colorkey_vb, dcrtc->base + LCD_SPU_COLORKEY_V);
  44. writel_relaxed(prop->brightness << 16 | prop->contrast,
  45. dcrtc->base + LCD_SPU_CONTRAST);
  46. /* Docs say 15:0, but it seems to actually be 31:16 on Armada 510 */
  47. writel_relaxed(prop->saturation << 16,
  48. dcrtc->base + LCD_SPU_SATURATION);
  49. writel_relaxed(0x00002000, dcrtc->base + LCD_SPU_CBSH_HUE);
  50. spin_lock_irq(&dcrtc->irq_lock);
  51. armada_updatel(prop->colorkey_mode | CFG_ALPHAM_GRA,
  52. CFG_CKMODE_MASK | CFG_ALPHAM_MASK | CFG_ALPHA_MASK,
  53. dcrtc->base + LCD_SPU_DMA_CTRL1);
  54. armada_updatel(ADV_GRACOLORKEY, 0, dcrtc->base + LCD_SPU_ADV_REG);
  55. spin_unlock_irq(&dcrtc->irq_lock);
  56. }
  57. /* === Plane support === */
  58. static void armada_ovl_plane_work(struct armada_crtc *dcrtc,
  59. struct armada_plane_work *work)
  60. {
  61. unsigned long flags;
  62. trace_armada_ovl_plane_work(&dcrtc->crtc, work->plane);
  63. spin_lock_irqsave(&dcrtc->irq_lock, flags);
  64. armada_drm_crtc_update_regs(dcrtc, work->regs);
  65. spin_unlock_irqrestore(&dcrtc->irq_lock, flags);
  66. }
  67. static void armada_ovl_plane_update_state(struct drm_plane_state *state,
  68. struct armada_regs *regs)
  69. {
  70. struct armada_ovl_plane *dplane = drm_to_armada_ovl_plane(state->plane);
  71. struct armada_framebuffer *dfb = drm_fb_to_armada_fb(state->fb);
  72. const struct drm_format_info *format;
  73. unsigned int idx = 0;
  74. bool fb_changed;
  75. u32 val, ctrl0;
  76. u16 src_x, src_y;
  77. ctrl0 = CFG_DMA_FMT(dfb->fmt) | CFG_DMA_MOD(dfb->mod) | CFG_CBSH_ENA;
  78. if (state->visible)
  79. ctrl0 |= CFG_DMA_ENA;
  80. if (drm_rect_width(&state->src) >> 16 != drm_rect_width(&state->dst))
  81. ctrl0 |= CFG_DMA_HSMOOTH;
  82. /*
  83. * Shifting a YUV packed format image by one pixel causes the U/V
  84. * planes to swap. Compensate for it by also toggling the UV swap.
  85. */
  86. format = dfb->fb.format;
  87. if (format->num_planes == 1 && state->src.x1 >> 16 & (format->hsub - 1))
  88. ctrl0 ^= CFG_DMA_MOD(CFG_SWAPUV);
  89. if (~dplane->base.state.ctrl0 & ctrl0 & CFG_DMA_ENA) {
  90. /* Power up the Y/U/V FIFOs on ENA 0->1 transitions */
  91. armada_reg_queue_mod(regs, idx,
  92. 0, CFG_PDWN16x66 | CFG_PDWN32x66,
  93. LCD_SPU_SRAM_PARA1);
  94. }
  95. fb_changed = dplane->base.base.fb != &dfb->fb ||
  96. dplane->base.state.src_x != state->src.x1 >> 16 ||
  97. dplane->base.state.src_y != state->src.y1 >> 16;
  98. dplane->base.state.vsync_update = fb_changed;
  99. /* FIXME: overlay on an interlaced display */
  100. if (fb_changed) {
  101. u32 addrs[3];
  102. dplane->base.state.src_y = src_y = state->src.y1 >> 16;
  103. dplane->base.state.src_x = src_x = state->src.x1 >> 16;
  104. armada_drm_plane_calc_addrs(addrs, &dfb->fb, src_x, src_y);
  105. armada_reg_queue_set(regs, idx, addrs[0],
  106. LCD_SPU_DMA_START_ADDR_Y0);
  107. armada_reg_queue_set(regs, idx, addrs[1],
  108. LCD_SPU_DMA_START_ADDR_U0);
  109. armada_reg_queue_set(regs, idx, addrs[2],
  110. LCD_SPU_DMA_START_ADDR_V0);
  111. armada_reg_queue_set(regs, idx, addrs[0],
  112. LCD_SPU_DMA_START_ADDR_Y1);
  113. armada_reg_queue_set(regs, idx, addrs[1],
  114. LCD_SPU_DMA_START_ADDR_U1);
  115. armada_reg_queue_set(regs, idx, addrs[2],
  116. LCD_SPU_DMA_START_ADDR_V1);
  117. val = dfb->fb.pitches[0] << 16 | dfb->fb.pitches[0];
  118. armada_reg_queue_set(regs, idx, val,
  119. LCD_SPU_DMA_PITCH_YC);
  120. val = dfb->fb.pitches[1] << 16 | dfb->fb.pitches[2];
  121. armada_reg_queue_set(regs, idx, val,
  122. LCD_SPU_DMA_PITCH_UV);
  123. }
  124. val = (drm_rect_height(&state->src) & 0xffff0000) |
  125. drm_rect_width(&state->src) >> 16;
  126. if (dplane->base.state.src_hw != val) {
  127. dplane->base.state.src_hw = val;
  128. armada_reg_queue_set(regs, idx, val,
  129. LCD_SPU_DMA_HPXL_VLN);
  130. }
  131. val = drm_rect_height(&state->dst) << 16 | drm_rect_width(&state->dst);
  132. if (dplane->base.state.dst_hw != val) {
  133. dplane->base.state.dst_hw = val;
  134. armada_reg_queue_set(regs, idx, val,
  135. LCD_SPU_DZM_HPXL_VLN);
  136. }
  137. val = state->dst.y1 << 16 | state->dst.x1;
  138. if (dplane->base.state.dst_yx != val) {
  139. dplane->base.state.dst_yx = val;
  140. armada_reg_queue_set(regs, idx, val,
  141. LCD_SPU_DMA_OVSA_HPXL_VLN);
  142. }
  143. if (dplane->base.state.ctrl0 != ctrl0) {
  144. dplane->base.state.ctrl0 = ctrl0;
  145. armada_reg_queue_mod(regs, idx, ctrl0,
  146. CFG_CBSH_ENA | CFG_DMAFORMAT | CFG_DMA_FTOGGLE |
  147. CFG_DMA_HSMOOTH | CFG_DMA_TSTMODE |
  148. CFG_DMA_MOD(CFG_SWAPRB | CFG_SWAPUV | CFG_SWAPYU |
  149. CFG_YUV2RGB) | CFG_DMA_ENA,
  150. LCD_SPU_DMA_CTRL0);
  151. dplane->base.state.vsync_update = true;
  152. }
  153. dplane->base.state.changed = idx != 0;
  154. armada_reg_queue_end(regs, idx);
  155. }
  156. static int
  157. armada_ovl_plane_update(struct drm_plane *plane, struct drm_crtc *crtc,
  158. struct drm_framebuffer *fb,
  159. int crtc_x, int crtc_y, unsigned crtc_w, unsigned crtc_h,
  160. uint32_t src_x, uint32_t src_y, uint32_t src_w, uint32_t src_h,
  161. struct drm_modeset_acquire_ctx *ctx)
  162. {
  163. struct armada_ovl_plane *dplane = drm_to_armada_ovl_plane(plane);
  164. struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
  165. struct armada_plane_work *work;
  166. struct drm_plane_state state = {
  167. .plane = plane,
  168. .crtc = crtc,
  169. .fb = fb,
  170. .src_x = src_x,
  171. .src_y = src_y,
  172. .src_w = src_w,
  173. .src_h = src_h,
  174. .crtc_x = crtc_x,
  175. .crtc_y = crtc_y,
  176. .crtc_w = crtc_w,
  177. .crtc_h = crtc_h,
  178. .rotation = DRM_MODE_ROTATE_0,
  179. };
  180. struct drm_crtc_state crtc_state = {
  181. .crtc = crtc,
  182. .enable = crtc->enabled,
  183. .mode = crtc->mode,
  184. };
  185. int ret;
  186. trace_armada_ovl_plane_update(plane, crtc, fb,
  187. crtc_x, crtc_y, crtc_w, crtc_h,
  188. src_x, src_y, src_w, src_h);
  189. ret = drm_atomic_helper_check_plane_state(&state, &crtc_state, 0,
  190. INT_MAX, true, false);
  191. if (ret)
  192. return ret;
  193. work = &dplane->base.works[dplane->base.next_work];
  194. if (plane->fb != fb) {
  195. /*
  196. * Take a reference on the new framebuffer - we want to
  197. * hold on to it while the hardware is displaying it.
  198. */
  199. drm_framebuffer_reference(fb);
  200. work->old_fb = plane->fb;
  201. } else {
  202. work->old_fb = NULL;
  203. }
  204. armada_ovl_plane_update_state(&state, work->regs);
  205. if (!dplane->base.state.changed)
  206. return 0;
  207. /* Wait for pending work to complete */
  208. if (armada_drm_plane_work_wait(&dplane->base, HZ / 25) == 0)
  209. armada_drm_plane_work_cancel(dcrtc, &dplane->base);
  210. /* Just updating the position/size? */
  211. if (!dplane->base.state.vsync_update) {
  212. armada_ovl_plane_work(dcrtc, work);
  213. return 0;
  214. }
  215. if (!dcrtc->plane) {
  216. dcrtc->plane = plane;
  217. armada_ovl_update_attr(&dplane->prop, dcrtc);
  218. }
  219. /* Queue it for update on the next interrupt if we are enabled */
  220. ret = armada_drm_plane_work_queue(dcrtc, work);
  221. if (ret)
  222. DRM_ERROR("failed to queue plane work: %d\n", ret);
  223. dplane->base.next_work = !dplane->base.next_work;
  224. return 0;
  225. }
  226. static void armada_ovl_plane_destroy(struct drm_plane *plane)
  227. {
  228. struct armada_ovl_plane *dplane = drm_to_armada_ovl_plane(plane);
  229. drm_plane_cleanup(plane);
  230. kfree(dplane);
  231. }
  232. static int armada_ovl_plane_set_property(struct drm_plane *plane,
  233. struct drm_property *property, uint64_t val)
  234. {
  235. struct armada_private *priv = plane->dev->dev_private;
  236. struct armada_ovl_plane *dplane = drm_to_armada_ovl_plane(plane);
  237. bool update_attr = false;
  238. if (property == priv->colorkey_prop) {
  239. #define CCC(v) ((v) << 24 | (v) << 16 | (v) << 8)
  240. dplane->prop.colorkey_yr = CCC(K2R(val));
  241. dplane->prop.colorkey_ug = CCC(K2G(val));
  242. dplane->prop.colorkey_vb = CCC(K2B(val));
  243. #undef CCC
  244. update_attr = true;
  245. } else if (property == priv->colorkey_min_prop) {
  246. dplane->prop.colorkey_yr &= ~0x00ff0000;
  247. dplane->prop.colorkey_yr |= K2R(val) << 16;
  248. dplane->prop.colorkey_ug &= ~0x00ff0000;
  249. dplane->prop.colorkey_ug |= K2G(val) << 16;
  250. dplane->prop.colorkey_vb &= ~0x00ff0000;
  251. dplane->prop.colorkey_vb |= K2B(val) << 16;
  252. update_attr = true;
  253. } else if (property == priv->colorkey_max_prop) {
  254. dplane->prop.colorkey_yr &= ~0xff000000;
  255. dplane->prop.colorkey_yr |= K2R(val) << 24;
  256. dplane->prop.colorkey_ug &= ~0xff000000;
  257. dplane->prop.colorkey_ug |= K2G(val) << 24;
  258. dplane->prop.colorkey_vb &= ~0xff000000;
  259. dplane->prop.colorkey_vb |= K2B(val) << 24;
  260. update_attr = true;
  261. } else if (property == priv->colorkey_val_prop) {
  262. dplane->prop.colorkey_yr &= ~0x0000ff00;
  263. dplane->prop.colorkey_yr |= K2R(val) << 8;
  264. dplane->prop.colorkey_ug &= ~0x0000ff00;
  265. dplane->prop.colorkey_ug |= K2G(val) << 8;
  266. dplane->prop.colorkey_vb &= ~0x0000ff00;
  267. dplane->prop.colorkey_vb |= K2B(val) << 8;
  268. update_attr = true;
  269. } else if (property == priv->colorkey_alpha_prop) {
  270. dplane->prop.colorkey_yr &= ~0x000000ff;
  271. dplane->prop.colorkey_yr |= K2R(val);
  272. dplane->prop.colorkey_ug &= ~0x000000ff;
  273. dplane->prop.colorkey_ug |= K2G(val);
  274. dplane->prop.colorkey_vb &= ~0x000000ff;
  275. dplane->prop.colorkey_vb |= K2B(val);
  276. update_attr = true;
  277. } else if (property == priv->colorkey_mode_prop) {
  278. dplane->prop.colorkey_mode &= ~CFG_CKMODE_MASK;
  279. dplane->prop.colorkey_mode |= CFG_CKMODE(val);
  280. update_attr = true;
  281. } else if (property == priv->brightness_prop) {
  282. dplane->prop.brightness = val - 256;
  283. update_attr = true;
  284. } else if (property == priv->contrast_prop) {
  285. dplane->prop.contrast = val;
  286. update_attr = true;
  287. } else if (property == priv->saturation_prop) {
  288. dplane->prop.saturation = val;
  289. update_attr = true;
  290. }
  291. if (update_attr && dplane->base.base.crtc)
  292. armada_ovl_update_attr(&dplane->prop,
  293. drm_to_armada_crtc(dplane->base.base.crtc));
  294. return 0;
  295. }
  296. static const struct drm_plane_funcs armada_ovl_plane_funcs = {
  297. .update_plane = armada_ovl_plane_update,
  298. .disable_plane = armada_drm_plane_disable,
  299. .destroy = armada_ovl_plane_destroy,
  300. .set_property = armada_ovl_plane_set_property,
  301. };
  302. static const uint32_t armada_ovl_formats[] = {
  303. DRM_FORMAT_UYVY,
  304. DRM_FORMAT_YUYV,
  305. DRM_FORMAT_YUV420,
  306. DRM_FORMAT_YVU420,
  307. DRM_FORMAT_YUV422,
  308. DRM_FORMAT_YVU422,
  309. DRM_FORMAT_VYUY,
  310. DRM_FORMAT_YVYU,
  311. DRM_FORMAT_ARGB8888,
  312. DRM_FORMAT_ABGR8888,
  313. DRM_FORMAT_XRGB8888,
  314. DRM_FORMAT_XBGR8888,
  315. DRM_FORMAT_RGB888,
  316. DRM_FORMAT_BGR888,
  317. DRM_FORMAT_ARGB1555,
  318. DRM_FORMAT_ABGR1555,
  319. DRM_FORMAT_RGB565,
  320. DRM_FORMAT_BGR565,
  321. };
  322. static const struct drm_prop_enum_list armada_drm_colorkey_enum_list[] = {
  323. { CKMODE_DISABLE, "disabled" },
  324. { CKMODE_Y, "Y component" },
  325. { CKMODE_U, "U component" },
  326. { CKMODE_V, "V component" },
  327. { CKMODE_RGB, "RGB" },
  328. { CKMODE_R, "R component" },
  329. { CKMODE_G, "G component" },
  330. { CKMODE_B, "B component" },
  331. };
  332. static int armada_overlay_create_properties(struct drm_device *dev)
  333. {
  334. struct armada_private *priv = dev->dev_private;
  335. if (priv->colorkey_prop)
  336. return 0;
  337. priv->colorkey_prop = drm_property_create_range(dev, 0,
  338. "colorkey", 0, 0xffffff);
  339. priv->colorkey_min_prop = drm_property_create_range(dev, 0,
  340. "colorkey_min", 0, 0xffffff);
  341. priv->colorkey_max_prop = drm_property_create_range(dev, 0,
  342. "colorkey_max", 0, 0xffffff);
  343. priv->colorkey_val_prop = drm_property_create_range(dev, 0,
  344. "colorkey_val", 0, 0xffffff);
  345. priv->colorkey_alpha_prop = drm_property_create_range(dev, 0,
  346. "colorkey_alpha", 0, 0xffffff);
  347. priv->colorkey_mode_prop = drm_property_create_enum(dev, 0,
  348. "colorkey_mode",
  349. armada_drm_colorkey_enum_list,
  350. ARRAY_SIZE(armada_drm_colorkey_enum_list));
  351. priv->brightness_prop = drm_property_create_range(dev, 0,
  352. "brightness", 0, 256 + 255);
  353. priv->contrast_prop = drm_property_create_range(dev, 0,
  354. "contrast", 0, 0x7fff);
  355. priv->saturation_prop = drm_property_create_range(dev, 0,
  356. "saturation", 0, 0x7fff);
  357. if (!priv->colorkey_prop)
  358. return -ENOMEM;
  359. return 0;
  360. }
  361. int armada_overlay_plane_create(struct drm_device *dev, unsigned long crtcs)
  362. {
  363. struct armada_private *priv = dev->dev_private;
  364. struct drm_mode_object *mobj;
  365. struct armada_ovl_plane *dplane;
  366. int ret;
  367. ret = armada_overlay_create_properties(dev);
  368. if (ret)
  369. return ret;
  370. dplane = kzalloc(sizeof(*dplane), GFP_KERNEL);
  371. if (!dplane)
  372. return -ENOMEM;
  373. ret = armada_drm_plane_init(&dplane->base);
  374. if (ret) {
  375. kfree(dplane);
  376. return ret;
  377. }
  378. dplane->base.works[0].fn = armada_ovl_plane_work;
  379. dplane->base.works[1].fn = armada_ovl_plane_work;
  380. ret = drm_universal_plane_init(dev, &dplane->base.base, crtcs,
  381. &armada_ovl_plane_funcs,
  382. armada_ovl_formats,
  383. ARRAY_SIZE(armada_ovl_formats),
  384. NULL,
  385. DRM_PLANE_TYPE_OVERLAY, NULL);
  386. if (ret) {
  387. kfree(dplane);
  388. return ret;
  389. }
  390. dplane->prop.colorkey_yr = 0xfefefe00;
  391. dplane->prop.colorkey_ug = 0x01010100;
  392. dplane->prop.colorkey_vb = 0x01010100;
  393. dplane->prop.colorkey_mode = CFG_CKMODE(CKMODE_RGB);
  394. dplane->prop.brightness = 0;
  395. dplane->prop.contrast = 0x4000;
  396. dplane->prop.saturation = 0x4000;
  397. mobj = &dplane->base.base.base;
  398. drm_object_attach_property(mobj, priv->colorkey_prop,
  399. 0x0101fe);
  400. drm_object_attach_property(mobj, priv->colorkey_min_prop,
  401. 0x0101fe);
  402. drm_object_attach_property(mobj, priv->colorkey_max_prop,
  403. 0x0101fe);
  404. drm_object_attach_property(mobj, priv->colorkey_val_prop,
  405. 0x0101fe);
  406. drm_object_attach_property(mobj, priv->colorkey_alpha_prop,
  407. 0x000000);
  408. drm_object_attach_property(mobj, priv->colorkey_mode_prop,
  409. CKMODE_RGB);
  410. drm_object_attach_property(mobj, priv->brightness_prop, 256);
  411. drm_object_attach_property(mobj, priv->contrast_prop,
  412. dplane->prop.contrast);
  413. drm_object_attach_property(mobj, priv->saturation_prop,
  414. dplane->prop.saturation);
  415. return 0;
  416. }