armada_510.c 2.0 KB

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  1. /*
  2. * Copyright (C) 2012 Russell King
  3. *
  4. * This program is free software; you can redistribute it and/or modify
  5. * it under the terms of the GNU General Public License version 2 as
  6. * published by the Free Software Foundation.
  7. *
  8. * Armada 510 (aka Dove) variant support
  9. */
  10. #include <linux/clk.h>
  11. #include <linux/io.h>
  12. #include <drm/drm_crtc_helper.h>
  13. #include "armada_crtc.h"
  14. #include "armada_drm.h"
  15. #include "armada_hw.h"
  16. static int armada510_crtc_init(struct armada_crtc *dcrtc, struct device *dev)
  17. {
  18. struct clk *clk;
  19. clk = devm_clk_get(dev, "ext_ref_clk1");
  20. if (IS_ERR(clk))
  21. return PTR_ERR(clk) == -ENOENT ? -EPROBE_DEFER : PTR_ERR(clk);
  22. dcrtc->extclk[0] = clk;
  23. /* Lower the watermark so to eliminate jitter at higher bandwidths */
  24. armada_updatel(0x20, (1 << 11) | 0xff, dcrtc->base + LCD_CFG_RDREG4F);
  25. return 0;
  26. }
  27. /*
  28. * Armada510 specific SCLK register selection.
  29. * This gets called with sclk = NULL to test whether the mode is
  30. * supportable, and again with sclk != NULL to set the clocks up for
  31. * that. The former can return an error, but the latter is expected
  32. * not to.
  33. *
  34. * We currently are pretty rudimentary here, always selecting
  35. * EXT_REF_CLK_1 for LCD0 and erroring LCD1. This needs improvement!
  36. */
  37. static int armada510_crtc_compute_clock(struct armada_crtc *dcrtc,
  38. const struct drm_display_mode *mode, uint32_t *sclk)
  39. {
  40. struct clk *clk = dcrtc->extclk[0];
  41. int ret;
  42. if (dcrtc->num == 1)
  43. return -EINVAL;
  44. if (IS_ERR(clk))
  45. return PTR_ERR(clk);
  46. if (dcrtc->clk != clk) {
  47. ret = clk_prepare_enable(clk);
  48. if (ret)
  49. return ret;
  50. dcrtc->clk = clk;
  51. }
  52. if (sclk) {
  53. uint32_t rate, ref, div;
  54. rate = mode->clock * 1000;
  55. ref = clk_round_rate(clk, rate);
  56. div = DIV_ROUND_UP(ref, rate);
  57. if (div < 1)
  58. div = 1;
  59. clk_set_rate(clk, ref);
  60. *sclk = div | SCLK_510_EXTCLK1;
  61. }
  62. return 0;
  63. }
  64. const struct armada_variant armada510_ops = {
  65. .has_spu_adv_reg = true,
  66. .spu_adv_reg = ADV_HWC32ENABLE | ADV_HWC32ARGB | ADV_HWC32BLEND,
  67. .init = armada510_crtc_init,
  68. .compute_clock = armada510_crtc_compute_clock,
  69. };