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reg_helper.h

reg_helper.h 14 KB
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  1. /*
    2. 

  2.  * Copyright 2016 Advanced Micro Devices, Inc.
    3. 

  3.  *
    4. 

  4.  * Permission is hereby granted, free of charge, to any person obtaining a
    5. 

  5.  * copy of this software and associated documentation files (the "Software"),
    6. 

  6.  * to deal in the Software without restriction, including without limitation
    7. 

  7.  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
    8. 

  8.  * and/or sell copies of the Software, and to permit persons to whom the
    9. 

  9.  * Software is furnished to do so, subject to the following conditions:
    10. 

  10.  *
    11. 

  11.  * The above copyright notice and this permission notice shall be included in
    12. 

  12.  * all copies or substantial portions of the Software.
    13. 

  13.  *
    14. 

  14.  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
    15. 

  15.  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
    16. 

  16.  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
    17. 

  17.  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
    18. 

  18.  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
    19. 

  19.  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
    20. 

  20.  * OTHER DEALINGS IN THE SOFTWARE.
    21. 

  21.  *
    22. 

  22.  * Authors: AMD
    23. 

  23.  */
    24. 

  24. 

  25. #ifndef DRIVERS_GPU_DRM_AMD_DC_DEV_DC_INC_REG_HELPER_H_
    26. 

  26. #define DRIVERS_GPU_DRM_AMD_DC_DEV_DC_INC_REG_HELPER_H_
    27. 

  27. 

  28. #include "dm_services.h"
    29. 

  29. 

  30. /* macro for register read/write
    31. 

  31.  * user of macro need to define
    32. 

  32.  *
    33. 

  33.  * CTX ==> macro to ptr to dc_context
    34. 

  34.  *    eg. aud110->base.ctx
    35. 

  35.  *
    36. 

  36.  * REG ==> macro to location of register offset
    37. 

  37.  *    eg. aud110->regs->reg
    38. 

  38.  */
    39. 

  39. #define REG_READ(reg_name) \
    40. 

  40. 		dm_read_reg(CTX, REG(reg_name))
    41. 

  41. 

  42. #define REG_WRITE(reg_name, value) \
    43. 

  43. 		dm_write_reg(CTX, REG(reg_name), value)
    44. 

  44. 

  45. #ifdef REG_SET
    46. 

  46. #undef REG_SET
    47. 

  47. #endif
    48. 

  48. 

  49. #ifdef REG_GET
    50. 

  50. #undef REG_GET
    51. 

  51. #endif
    52. 

  52. 

  53. /* macro to set register fields. */
    54. 

  54. #define REG_SET_N(reg_name, n, initial_val, ...)	\
    55. 

  55. 		generic_reg_update_ex(CTX, \
    56. 

  56. 				REG(reg_name), \
    57. 

  57. 				initial_val, \
    58. 

  58. 				n, __VA_ARGS__)
    59. 

  59. 

  60. #define FN(reg_name, field) \
    61. 

  61. 	FD(reg_name##__##field)
    62. 

  62. 

  63. #define REG_SET(reg_name, initial_val, field, val)	\
    64. 

  64. 		REG_SET_N(reg_name, 1, initial_val, \
    65. 

  65. 				FN(reg_name, field), val)
    66. 

  66. 

  67. #define REG_SET_2(reg, init_value, f1, v1, f2, v2)	\
    68. 

  68. 		REG_SET_N(reg, 2, init_value, \
    69. 

  69. 				FN(reg, f1), v1,\
    70. 

  70. 				FN(reg, f2), v2)
    71. 

  71. 

  72. #define REG_SET_3(reg, init_value, f1, v1, f2, v2, f3, v3)	\
    73. 

  73. 		REG_SET_N(reg, 3, init_value, \
    74. 

  74. 				FN(reg, f1), v1,\
    75. 

  75. 				FN(reg, f2), v2,\
    76. 

  76. 				FN(reg, f3), v3)
    77. 

  77. 

  78. #define REG_SET_4(reg, init_value, f1, v1, f2, v2, f3, v3, f4, v4)	\
    79. 

  79. 		REG_SET_N(reg, 4, init_value, \
    80. 

  80. 				FN(reg, f1), v1,\
    81. 

  81. 				FN(reg, f2), v2,\
    82. 

  82. 				FN(reg, f3), v3,\
    83. 

  83. 				FN(reg, f4), v4)
    84. 

  84. 

  85. #define REG_SET_5(reg, init_value, f1, v1, f2, v2, f3, v3, f4, v4,	\
    86. 

  86. 		f5, v5)	\
    87. 

  87. 		REG_SET_N(reg, 5, init_value, \
    88. 

  88. 				FN(reg, f1), v1,\
    89. 

  89. 				FN(reg, f2), v2,\
    90. 

  90. 				FN(reg, f3), v3,\
    91. 

  91. 				FN(reg, f4), v4,\
    92. 

  92. 				FN(reg, f5), v5)
    93. 

  93. 

  94. #define REG_SET_6(reg, init_value, f1, v1, f2, v2, f3, v3, f4, v4,	\
    95. 

  95. 		f5, v5, f6, v6)	\
    96. 

  96. 		REG_SET_N(reg, 6, init_value, \
    97. 

  97. 				FN(reg, f1), v1,\
    98. 

  98. 				FN(reg, f2), v2,\
    99. 

  99. 				FN(reg, f3), v3,\
    100. 

  100. 				FN(reg, f4), v4,\
    101. 

  101. 				FN(reg, f5), v5,\
    102. 

  102. 				FN(reg, f6), v6)
    103. 

  103. 

  104. #define REG_SET_7(reg, init_value, f1, v1, f2, v2, f3, v3, f4, v4,	\
    105. 

  105. 		f5, v5, f6, v6, f7, v7)	\
    106. 

  106. 		REG_SET_N(reg, 7, init_value, \
    107. 

  107. 				FN(reg, f1), v1,\
    108. 

  108. 				FN(reg, f2), v2,\
    109. 

  109. 				FN(reg, f3), v3,\
    110. 

  110. 				FN(reg, f4), v4,\
    111. 

  111. 				FN(reg, f5), v5,\
    112. 

  112. 				FN(reg, f6), v6,\
    113. 

  113. 				FN(reg, f7), v7)
    114. 

  114. 

  115. #define REG_SET_8(reg, init_value, f1, v1, f2, v2, f3, v3, f4, v4,	\
    116. 

  116. 		f5, v5, f6, v6, f7, v7, f8, v8)	\
    117. 

  117. 		REG_SET_N(reg, 8, init_value, \
    118. 

  118. 				FN(reg, f1), v1,\
    119. 

  119. 				FN(reg, f2), v2,\
    120. 

  120. 				FN(reg, f3), v3,\
    121. 

  121. 				FN(reg, f4), v4,\
    122. 

  122. 				FN(reg, f5), v5,\
    123. 

  123. 				FN(reg, f6), v6,\
    124. 

  124. 				FN(reg, f7), v7,\
    125. 

  125. 				FN(reg, f8), v8)
    126. 

  126. 

  127. #define REG_SET_9(reg, init_value, f1, v1, f2, v2, f3, v3, f4, v4, f5, \
    128. 

  128. 		v5, f6, v6, f7, v7, f8, v8, f9, v9)	\
    129. 

  129. 		REG_SET_N(reg, 9, init_value, \
    130. 

  130. 				FN(reg, f1), v1,\
    131. 

  131. 				FN(reg, f2), v2, \
    132. 

  132. 				FN(reg, f3), v3, \
    133. 

  133. 				FN(reg, f4), v4, \
    134. 

  134. 				FN(reg, f5), v5, \
    135. 

  135. 				FN(reg, f6), v6, \
    136. 

  136. 				FN(reg, f7), v7, \
    137. 

  137. 				FN(reg, f8), v8, \
    138. 

  138. 				FN(reg, f9), v9)
    139. 

  139. 

  140. #define REG_SET_10(reg, init_value, f1, v1, f2, v2, f3, v3, f4, v4, f5, \
    141. 

  141. 		v5, f6, v6, f7, v7, f8, v8, f9, v9, f10, v10)	\
    142. 

  142. 		REG_SET_N(reg, 10, init_value, \
    143. 

  143. 				FN(reg, f1), v1,\
    144. 

  144. 				FN(reg, f2), v2, \
    145. 

  145. 				FN(reg, f3), v3, \
    146. 

  146. 				FN(reg, f4), v4, \
    147. 

  147. 				FN(reg, f5), v5, \
    148. 

  148. 				FN(reg, f6), v6, \
    149. 

  149. 				FN(reg, f7), v7, \
    150. 

  150. 				FN(reg, f8), v8, \
    151. 

  151. 				FN(reg, f9), v9, \
    152. 

  152. 				FN(reg, f10), v10)
    153. 

  153. 

  154. /* macro to get register fields
    155. 

  155.  * read given register and fill in field value in output parameter */
    156. 

  156. #define REG_GET(reg_name, field, val)	\
    157. 

  157. 		generic_reg_get(CTX, REG(reg_name), \
    158. 

  158. 				FN(reg_name, field), val)
    159. 

  159. 

  160. #define REG_GET_2(reg_name, f1, v1, f2, v2)	\
    161. 

  161. 		generic_reg_get2(CTX, REG(reg_name), \
    162. 

  162. 				FN(reg_name, f1), v1, \
    163. 

  163. 				FN(reg_name, f2), v2)
    164. 

  164. 

  165. #define REG_GET_3(reg_name, f1, v1, f2, v2, f3, v3)	\
    166. 

  166. 		generic_reg_get3(CTX, REG(reg_name), \
    167. 

  167. 				FN(reg_name, f1), v1, \
    168. 

  168. 				FN(reg_name, f2), v2, \
    169. 

  169. 				FN(reg_name, f3), v3)
    170. 

  170. 

  171. #define REG_GET_4(reg_name, f1, v1, f2, v2, f3, v3, f4, v4)	\
    172. 

  172. 		generic_reg_get4(CTX, REG(reg_name), \
    173. 

  173. 				FN(reg_name, f1), v1, \
    174. 

  174. 				FN(reg_name, f2), v2, \
    175. 

  175. 				FN(reg_name, f3), v3, \
    176. 

  176. 				FN(reg_name, f4), v4)
    177. 

  177. 

  178. #define REG_GET_5(reg_name, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5)	\
    179. 

  179. 		generic_reg_get5(CTX, REG(reg_name), \
    180. 

  180. 				FN(reg_name, f1), v1, \
    181. 

  181. 				FN(reg_name, f2), v2, \
    182. 

  182. 				FN(reg_name, f3), v3, \
    183. 

  183. 				FN(reg_name, f4), v4, \
    184. 

  184. 				FN(reg_name, f5), v5)
    185. 

  185. 

  186. #define REG_GET_6(reg_name, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6)	\
    187. 

  187. 		generic_reg_get6(CTX, REG(reg_name), \
    188. 

  188. 				FN(reg_name, f1), v1, \
    189. 

  189. 				FN(reg_name, f2), v2, \
    190. 

  190. 				FN(reg_name, f3), v3, \
    191. 

  191. 				FN(reg_name, f4), v4, \
    192. 

  192. 				FN(reg_name, f5), v5, \
    193. 

  193. 				FN(reg_name, f6), v6)
    194. 

  194. 

  195. #define REG_GET_7(reg_name, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7)	\
    196. 

  196. 		generic_reg_get7(CTX, REG(reg_name), \
    197. 

  197. 				FN(reg_name, f1), v1, \
    198. 

  198. 				FN(reg_name, f2), v2, \
    199. 

  199. 				FN(reg_name, f3), v3, \
    200. 

  200. 				FN(reg_name, f4), v4, \
    201. 

  201. 				FN(reg_name, f5), v5, \
    202. 

  202. 				FN(reg_name, f6), v6, \
    203. 

  203. 				FN(reg_name, f7), v7)
    204. 

  204. 

  205. #define REG_GET_8(reg_name, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8)	\
    206. 

  206. 		generic_reg_get8(CTX, REG(reg_name), \
    207. 

  207. 				FN(reg_name, f1), v1, \
    208. 

  208. 				FN(reg_name, f2), v2, \
    209. 

  209. 				FN(reg_name, f3), v3, \
    210. 

  210. 				FN(reg_name, f4), v4, \
    211. 

  211. 				FN(reg_name, f5), v5, \
    212. 

  212. 				FN(reg_name, f6), v6, \
    213. 

  213. 				FN(reg_name, f7), v7, \
    214. 

  214. 				FN(reg_name, f8), v8)
    215. 

  215. 

  216. /* macro to poll and wait for a register field to read back given value */
    217. 

  217. 

  218. #define REG_WAIT(reg_name, field, val, delay_between_poll_us, max_try)	\
    219. 

  219. 		generic_reg_wait(CTX, \
    220. 

  220. 				REG(reg_name), FN(reg_name, field), val,\
    221. 

  221. 				delay_between_poll_us, max_try, __func__, __LINE__)
    222. 

  222. 

  223. /* macro to update (read, modify, write) register fields
    224. 

  224.  */
    225. 

  225. #define REG_UPDATE_N(reg_name, n, ...)	\
    226. 

  226. 		generic_reg_update_ex(CTX, \
    227. 

  227. 				REG(reg_name), \
    228. 

  228. 				REG_READ(reg_name), \
    229. 

  229. 				n, __VA_ARGS__)
    230. 

  230. 

  231. #define REG_UPDATE(reg_name, field, val)	\
    232. 

  232. 		REG_UPDATE_N(reg_name, 1, \
    233. 

  233. 				FN(reg_name, field), val)
    234. 

  234. 

  235. #define REG_UPDATE_2(reg, f1, v1, f2, v2)	\
    236. 

  236. 		REG_UPDATE_N(reg, 2,\
    237. 

  237. 				FN(reg, f1), v1,\
    238. 

  238. 				FN(reg, f2), v2)
    239. 

  239. 

  240. #define REG_UPDATE_3(reg, f1, v1, f2, v2, f3, v3)	\
    241. 

  241. 		REG_UPDATE_N(reg, 3, \
    242. 

  242. 				FN(reg, f1), v1,\
    243. 

  243. 				FN(reg, f2), v2, \
    244. 

  244. 				FN(reg, f3), v3)
    245. 

  245. 

  246. #define REG_UPDATE_4(reg, f1, v1, f2, v2, f3, v3, f4, v4)	\
    247. 

  247. 		REG_UPDATE_N(reg, 4, \
    248. 

  248. 				FN(reg, f1), v1,\
    249. 

  249. 				FN(reg, f2), v2, \
    250. 

  250. 				FN(reg, f3), v3, \
    251. 

  251. 				FN(reg, f4), v4)
    252. 

  252. 

  253. #define REG_UPDATE_5(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5)	\
    254. 

  254. 		REG_UPDATE_N(reg, 5, \
    255. 

  255. 				FN(reg, f1), v1,\
    256. 

  256. 				FN(reg, f2), v2, \
    257. 

  257. 				FN(reg, f3), v3, \
    258. 

  258. 				FN(reg, f4), v4, \
    259. 

  259. 				FN(reg, f5), v5)
    260. 

  260. 

  261. #define REG_UPDATE_6(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6)	\
    262. 

  262. 		REG_UPDATE_N(reg, 6, \
    263. 

  263. 				FN(reg, f1), v1,\
    264. 

  264. 				FN(reg, f2), v2, \
    265. 

  265. 				FN(reg, f3), v3, \
    266. 

  266. 				FN(reg, f4), v4, \
    267. 

  267. 				FN(reg, f5), v5, \
    268. 

  268. 				FN(reg, f6), v6)
    269. 

  269. 

  270. #define REG_UPDATE_7(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7)	\
    271. 

  271. 		REG_UPDATE_N(reg, 7, \
    272. 

  272. 				FN(reg, f1), v1,\
    273. 

  273. 				FN(reg, f2), v2, \
    274. 

  274. 				FN(reg, f3), v3, \
    275. 

  275. 				FN(reg, f4), v4, \
    276. 

  276. 				FN(reg, f5), v5, \
    277. 

  277. 				FN(reg, f6), v6, \
    278. 

  278. 				FN(reg, f7), v7)
    279. 

  279. 

  280. #define REG_UPDATE_8(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8)	\
    281. 

  281. 		REG_UPDATE_N(reg, 8, \
    282. 

  282. 				FN(reg, f1), v1,\
    283. 

  283. 				FN(reg, f2), v2, \
    284. 

  284. 				FN(reg, f3), v3, \
    285. 

  285. 				FN(reg, f4), v4, \
    286. 

  286. 				FN(reg, f5), v5, \
    287. 

  287. 				FN(reg, f6), v6, \
    288. 

  288. 				FN(reg, f7), v7, \
    289. 

  289. 				FN(reg, f8), v8)
    290. 

  290. 

  291. #define REG_UPDATE_9(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8, f9, v9)	\
    292. 

  292. 		REG_UPDATE_N(reg, 9, \
    293. 

  293. 				FN(reg, f1), v1,\
    294. 

  294. 				FN(reg, f2), v2, \
    295. 

  295. 				FN(reg, f3), v3, \
    296. 

  296. 				FN(reg, f4), v4, \
    297. 

  297. 				FN(reg, f5), v5, \
    298. 

  298. 				FN(reg, f6), v6, \
    299. 

  299. 				FN(reg, f7), v7, \
    300. 

  300. 				FN(reg, f8), v8, \
    301. 

  301. 				FN(reg, f9), v9)
    302. 

  302. 

  303. #define REG_UPDATE_10(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8, f9, v9, f10, v10)\
    304. 

  304. 		REG_UPDATE_N(reg, 10, \
    305. 

  305. 				FN(reg, f1), v1,\
    306. 

  306. 				FN(reg, f2), v2, \
    307. 

  307. 				FN(reg, f3), v3, \
    308. 

  308. 				FN(reg, f4), v4, \
    309. 

  309. 				FN(reg, f5), v5, \
    310. 

  310. 				FN(reg, f6), v6, \
    311. 

  311. 				FN(reg, f7), v7, \
    312. 

  312. 				FN(reg, f8), v8, \
    313. 

  313. 				FN(reg, f9), v9, \
    314. 

  314. 				FN(reg, f10), v10)
    315. 

  315. 

  316. #define REG_UPDATE_14(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8, f9, v9, f10,\
    317. 

  317. 		v10, f11, v11, f12, v12, f13, v13, f14, v14)\
    318. 

  318. 		REG_UPDATE_N(reg, 14, \
    319. 

  319. 				FN(reg, f1), v1,\
    320. 

  320. 				FN(reg, f2), v2, \
    321. 

  321. 				FN(reg, f3), v3, \
    322. 

  322. 				FN(reg, f4), v4, \
    323. 

  323. 				FN(reg, f5), v5, \
    324. 

  324. 				FN(reg, f6), v6, \
    325. 

  325. 				FN(reg, f7), v7, \
    326. 

  326. 				FN(reg, f8), v8, \
    327. 

  327. 				FN(reg, f9), v9, \
    328. 

  328. 				FN(reg, f10), v10, \
    329. 

  329. 				FN(reg, f11), v11, \
    330. 

  330. 				FN(reg, f12), v12, \
    331. 

  331. 				FN(reg, f13), v13, \
    332. 

  332. 				FN(reg, f14), v14)
    333. 

  333. 

  334. #define REG_UPDATE_19(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8, f9, v9, f10,\
    335. 

  335. 		v10, f11, v11, f12, v12, f13, v13, f14, v14, f15, v15, f16, v16, f17, v17, f18, v18, f19, v19)\
    336. 

  336. 		REG_UPDATE_N(reg, 19, \
    337. 

  337. 				FN(reg, f1), v1,\
    338. 

  338. 				FN(reg, f2), v2, \
    339. 

  339. 				FN(reg, f3), v3, \
    340. 

  340. 				FN(reg, f4), v4, \
    341. 

  341. 				FN(reg, f5), v5, \
    342. 

  342. 				FN(reg, f6), v6, \
    343. 

  343. 				FN(reg, f7), v7, \
    344. 

  344. 				FN(reg, f8), v8, \
    345. 

  345. 				FN(reg, f9), v9, \
    346. 

  346. 				FN(reg, f10), v10, \
    347. 

  347. 				FN(reg, f11), v11, \
    348. 

  348. 				FN(reg, f12), v12, \
    349. 

  349. 				FN(reg, f13), v13, \
    350. 

  350. 				FN(reg, f14), v14, \
    351. 

  351. 				FN(reg, f15), v15, \
    352. 

  352. 				FN(reg, f16), v16, \
    353. 

  353. 				FN(reg, f17), v17, \
    354. 

  354. 				FN(reg, f18), v18, \
    355. 

  355. 				FN(reg, f19), v19)
    356. 

  356. 

  357. #define REG_UPDATE_20(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8, f9, v9, f10,\
    358. 

  358. 		v10, f11, v11, f12, v12, f13, v13, f14, v14, f15, v15, f16, v16, f17, v17, f18, v18, f19, v19, f20, v20)\
    359. 

  359. 		REG_UPDATE_N(reg, 20, \
    360. 

  360. 				FN(reg, f1), v1,\
    361. 

  361. 				FN(reg, f2), v2, \
    362. 

  362. 				FN(reg, f3), v3, \
    363. 

  363. 				FN(reg, f4), v4, \
    364. 

  364. 				FN(reg, f5), v5, \
    365. 

  365. 				FN(reg, f6), v6, \
    366. 

  366. 				FN(reg, f7), v7, \
    367. 

  367. 				FN(reg, f8), v8, \
    368. 

  368. 				FN(reg, f9), v9, \
    369. 

  369. 				FN(reg, f10), v10, \
    370. 

  370. 				FN(reg, f11), v11, \
    371. 

  371. 				FN(reg, f12), v12, \
    372. 

  372. 				FN(reg, f13), v13, \
    373. 

  373. 				FN(reg, f14), v14, \
    374. 

  374. 				FN(reg, f15), v15, \
    375. 

  375. 				FN(reg, f16), v16, \
    376. 

  376. 				FN(reg, f17), v17, \
    377. 

  377. 				FN(reg, f18), v18, \
    378. 

  378. 				FN(reg, f19), v19, \
    379. 

  379. 				FN(reg, f20), v20)
    380. 

  380. /* macro to update a register field to specified values in given sequences.
    381. 

  381.  * useful when toggling bits
    382. 

  382.  */
    383. 

  383. #define REG_UPDATE_SEQ(reg, field, value1, value2) \
    384. 

  384. {	uint32_t val = REG_UPDATE(reg, field, value1); \
    385. 

  385. 	REG_SET(reg, val, field, value2); }
    386. 

  386. 

  387. /* macro to update fields in register 1 field at a time in given order */
    388. 

  388. #define REG_UPDATE_1BY1_2(reg, f1, v1, f2, v2) \
    389. 

  389. {	uint32_t val = REG_UPDATE(reg, f1, v1); \
    390. 

  390. 	REG_SET(reg, val, f2, v2); }
    391. 

  391. 

  392. #define REG_UPDATE_1BY1_3(reg, f1, v1, f2, v2, f3, v3) \
    393. 

  393. {	uint32_t val = REG_UPDATE(reg, f1, v1); \
    394. 

  394. 	val = REG_SET(reg, val, f2, v2); \
    395. 

  395. 	REG_SET(reg, val, f3, v3); }
    396. 

  396. 

  397. uint32_t generic_reg_get(const struct dc_context *ctx, uint32_t addr,
    398. 

  398. 		uint8_t shift, uint32_t mask, uint32_t *field_value);
    399. 

  399. 

  400. uint32_t generic_reg_get2(const struct dc_context *ctx, uint32_t addr,
    401. 

  401. 		uint8_t shift1, uint32_t mask1, uint32_t *field_value1,
    402. 

  402. 		uint8_t shift2, uint32_t mask2, uint32_t *field_value2);
    403. 

  403. 

  404. uint32_t generic_reg_get3(const struct dc_context *ctx, uint32_t addr,
    405. 

  405. 		uint8_t shift1, uint32_t mask1, uint32_t *field_value1,
    406. 

  406. 		uint8_t shift2, uint32_t mask2, uint32_t *field_value2,
    407. 

  407. 		uint8_t shift3, uint32_t mask3, uint32_t *field_value3);
    408. 

  408. 

  409. uint32_t generic_reg_get4(const struct dc_context *ctx, uint32_t addr,
    410. 

  410. 		uint8_t shift1, uint32_t mask1, uint32_t *field_value1,
    411. 

  411. 		uint8_t shift2, uint32_t mask2, uint32_t *field_value2,
    412. 

  412. 		uint8_t shift3, uint32_t mask3, uint32_t *field_value3,
    413. 

  413. 		uint8_t shift4, uint32_t mask4, uint32_t *field_value4);
    414. 

  414. 

  415. uint32_t generic_reg_get5(const struct dc_context *ctx, uint32_t addr,
    416. 

  416. 		uint8_t shift1, uint32_t mask1, uint32_t *field_value1,
    417. 

  417. 		uint8_t shift2, uint32_t mask2, uint32_t *field_value2,
    418. 

  418. 		uint8_t shift3, uint32_t mask3, uint32_t *field_value3,
    419. 

  419. 		uint8_t shift4, uint32_t mask4, uint32_t *field_value4,
    420. 

  420. 		uint8_t shift5, uint32_t mask5, uint32_t *field_value5);
    421. 

  421. 

  422. uint32_t generic_reg_get6(const struct dc_context *ctx, uint32_t addr,
    423. 

  423. 		uint8_t shift1, uint32_t mask1, uint32_t *field_value1,
    424. 

  424. 		uint8_t shift2, uint32_t mask2, uint32_t *field_value2,
    425. 

  425. 		uint8_t shift3, uint32_t mask3, uint32_t *field_value3,
    426. 

  426. 		uint8_t shift4, uint32_t mask4, uint32_t *field_value4,
    427. 

  427. 		uint8_t shift5, uint32_t mask5, uint32_t *field_value5,
    428. 

  428. 		uint8_t shift6, uint32_t mask6, uint32_t *field_value6);
    429. 

  429. 

  430. uint32_t generic_reg_get7(const struct dc_context *ctx, uint32_t addr,
    431. 

  431. 		uint8_t shift1, uint32_t mask1, uint32_t *field_value1,
    432. 

  432. 		uint8_t shift2, uint32_t mask2, uint32_t *field_value2,
    433. 

  433. 		uint8_t shift3, uint32_t mask3, uint32_t *field_value3,
    434. 

  434. 		uint8_t shift4, uint32_t mask4, uint32_t *field_value4,
    435. 

  435. 		uint8_t shift5, uint32_t mask5, uint32_t *field_value5,
    436. 

  436. 		uint8_t shift6, uint32_t mask6, uint32_t *field_value6,
    437. 

  437. 		uint8_t shift7, uint32_t mask7, uint32_t *field_value7);
    438. 

  438. 

  439. uint32_t generic_reg_get8(const struct dc_context *ctx, uint32_t addr,
    440. 

  440. 		uint8_t shift1, uint32_t mask1, uint32_t *field_value1,
    441. 

  441. 		uint8_t shift2, uint32_t mask2, uint32_t *field_value2,
    442. 

  442. 		uint8_t shift3, uint32_t mask3, uint32_t *field_value3,
    443. 

  443. 		uint8_t shift4, uint32_t mask4, uint32_t *field_value4,
    444. 

  444. 		uint8_t shift5, uint32_t mask5, uint32_t *field_value5,
    445. 

  445. 		uint8_t shift6, uint32_t mask6, uint32_t *field_value6,
    446. 

  446. 		uint8_t shift7, uint32_t mask7, uint32_t *field_value7,
    447. 

  447. 		uint8_t shift8, uint32_t mask8, uint32_t *field_value8);
    448. 

  448. #endif /* DRIVERS_GPU_DRM_AMD_DC_DEV_DC_INC_REG_HELPER_H_ */
    449.