dce80_resource.c 33 KB

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  1. /*
  2. * Copyright 2012-15 Advanced Micro Devices, Inc.
  3. *
  4. * Permission is hereby granted, free of charge, to any person obtaining a
  5. * copy of this software and associated documentation files (the "Software"),
  6. * to deal in the Software without restriction, including without limitation
  7. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8. * and/or sell copies of the Software, and to permit persons to whom the
  9. * Software is furnished to do so, subject to the following conditions:
  10. *
  11. * The above copyright notice and this permission notice shall be included in
  12. * all copies or substantial portions of the Software.
  13. *
  14. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  17. * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18. * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19. * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20. * OTHER DEALINGS IN THE SOFTWARE.
  21. *
  22. * Authors: AMD
  23. *
  24. */
  25. #include "dce/dce_8_0_d.h"
  26. #include "dce/dce_8_0_sh_mask.h"
  27. #include "dm_services.h"
  28. #include "link_encoder.h"
  29. #include "stream_encoder.h"
  30. #include "resource.h"
  31. #include "include/irq_service_interface.h"
  32. #include "irq/dce80/irq_service_dce80.h"
  33. #include "dce110/dce110_timing_generator.h"
  34. #include "dce110/dce110_resource.h"
  35. #include "dce80/dce80_timing_generator.h"
  36. #include "dce/dce_mem_input.h"
  37. #include "dce/dce_link_encoder.h"
  38. #include "dce/dce_stream_encoder.h"
  39. #include "dce/dce_mem_input.h"
  40. #include "dce/dce_ipp.h"
  41. #include "dce/dce_transform.h"
  42. #include "dce/dce_opp.h"
  43. #include "dce/dce_clocks.h"
  44. #include "dce/dce_clock_source.h"
  45. #include "dce/dce_audio.h"
  46. #include "dce/dce_hwseq.h"
  47. #include "dce80/dce80_hw_sequencer.h"
  48. #include "dce100/dce100_resource.h"
  49. #include "reg_helper.h"
  50. #include "dce/dce_dmcu.h"
  51. #include "dce/dce_abm.h"
  52. /* TODO remove this include */
  53. #ifndef mmMC_HUB_RDREQ_DMIF_LIMIT
  54. #include "gmc/gmc_7_1_d.h"
  55. #include "gmc/gmc_7_1_sh_mask.h"
  56. #endif
  57. #ifndef mmDP_DPHY_INTERNAL_CTRL
  58. #define mmDP_DPHY_INTERNAL_CTRL 0x1CDE
  59. #define mmDP0_DP_DPHY_INTERNAL_CTRL 0x1CDE
  60. #define mmDP1_DP_DPHY_INTERNAL_CTRL 0x1FDE
  61. #define mmDP2_DP_DPHY_INTERNAL_CTRL 0x42DE
  62. #define mmDP3_DP_DPHY_INTERNAL_CTRL 0x45DE
  63. #define mmDP4_DP_DPHY_INTERNAL_CTRL 0x48DE
  64. #define mmDP5_DP_DPHY_INTERNAL_CTRL 0x4BDE
  65. #define mmDP6_DP_DPHY_INTERNAL_CTRL 0x4EDE
  66. #endif
  67. #ifndef mmBIOS_SCRATCH_2
  68. #define mmBIOS_SCRATCH_2 0x05CB
  69. #define mmBIOS_SCRATCH_6 0x05CF
  70. #endif
  71. #ifndef mmDP_DPHY_FAST_TRAINING
  72. #define mmDP_DPHY_FAST_TRAINING 0x1CCE
  73. #define mmDP0_DP_DPHY_FAST_TRAINING 0x1CCE
  74. #define mmDP1_DP_DPHY_FAST_TRAINING 0x1FCE
  75. #define mmDP2_DP_DPHY_FAST_TRAINING 0x42CE
  76. #define mmDP3_DP_DPHY_FAST_TRAINING 0x45CE
  77. #define mmDP4_DP_DPHY_FAST_TRAINING 0x48CE
  78. #define mmDP5_DP_DPHY_FAST_TRAINING 0x4BCE
  79. #define mmDP6_DP_DPHY_FAST_TRAINING 0x4ECE
  80. #endif
  81. #ifndef mmHPD_DC_HPD_CONTROL
  82. #define mmHPD_DC_HPD_CONTROL 0x189A
  83. #define mmHPD0_DC_HPD_CONTROL 0x189A
  84. #define mmHPD1_DC_HPD_CONTROL 0x18A2
  85. #define mmHPD2_DC_HPD_CONTROL 0x18AA
  86. #define mmHPD3_DC_HPD_CONTROL 0x18B2
  87. #define mmHPD4_DC_HPD_CONTROL 0x18BA
  88. #define mmHPD5_DC_HPD_CONTROL 0x18C2
  89. #endif
  90. #define DCE11_DIG_FE_CNTL 0x4a00
  91. #define DCE11_DIG_BE_CNTL 0x4a47
  92. #define DCE11_DP_SEC 0x4ac3
  93. static const struct dce110_timing_generator_offsets dce80_tg_offsets[] = {
  94. {
  95. .crtc = (mmCRTC0_CRTC_CONTROL - mmCRTC_CONTROL),
  96. .dcp = (mmGRPH_CONTROL - mmGRPH_CONTROL),
  97. .dmif = (mmDMIF_PG0_DPG_WATERMARK_MASK_CONTROL
  98. - mmDPG_WATERMARK_MASK_CONTROL),
  99. },
  100. {
  101. .crtc = (mmCRTC1_CRTC_CONTROL - mmCRTC_CONTROL),
  102. .dcp = (mmDCP1_GRPH_CONTROL - mmGRPH_CONTROL),
  103. .dmif = (mmDMIF_PG1_DPG_WATERMARK_MASK_CONTROL
  104. - mmDPG_WATERMARK_MASK_CONTROL),
  105. },
  106. {
  107. .crtc = (mmCRTC2_CRTC_CONTROL - mmCRTC_CONTROL),
  108. .dcp = (mmDCP2_GRPH_CONTROL - mmGRPH_CONTROL),
  109. .dmif = (mmDMIF_PG2_DPG_WATERMARK_MASK_CONTROL
  110. - mmDPG_WATERMARK_MASK_CONTROL),
  111. },
  112. {
  113. .crtc = (mmCRTC3_CRTC_CONTROL - mmCRTC_CONTROL),
  114. .dcp = (mmDCP3_GRPH_CONTROL - mmGRPH_CONTROL),
  115. .dmif = (mmDMIF_PG3_DPG_WATERMARK_MASK_CONTROL
  116. - mmDPG_WATERMARK_MASK_CONTROL),
  117. },
  118. {
  119. .crtc = (mmCRTC4_CRTC_CONTROL - mmCRTC_CONTROL),
  120. .dcp = (mmDCP4_GRPH_CONTROL - mmGRPH_CONTROL),
  121. .dmif = (mmDMIF_PG4_DPG_WATERMARK_MASK_CONTROL
  122. - mmDPG_WATERMARK_MASK_CONTROL),
  123. },
  124. {
  125. .crtc = (mmCRTC5_CRTC_CONTROL - mmCRTC_CONTROL),
  126. .dcp = (mmDCP5_GRPH_CONTROL - mmGRPH_CONTROL),
  127. .dmif = (mmDMIF_PG5_DPG_WATERMARK_MASK_CONTROL
  128. - mmDPG_WATERMARK_MASK_CONTROL),
  129. }
  130. };
  131. /* set register offset */
  132. #define SR(reg_name)\
  133. .reg_name = mm ## reg_name
  134. /* set register offset with instance */
  135. #define SRI(reg_name, block, id)\
  136. .reg_name = mm ## block ## id ## _ ## reg_name
  137. static const struct dce_disp_clk_registers disp_clk_regs = {
  138. CLK_COMMON_REG_LIST_DCE_BASE()
  139. };
  140. static const struct dce_disp_clk_shift disp_clk_shift = {
  141. CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT)
  142. };
  143. static const struct dce_disp_clk_mask disp_clk_mask = {
  144. CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)
  145. };
  146. #define ipp_regs(id)\
  147. [id] = {\
  148. IPP_COMMON_REG_LIST_DCE_BASE(id)\
  149. }
  150. static const struct dce_ipp_registers ipp_regs[] = {
  151. ipp_regs(0),
  152. ipp_regs(1),
  153. ipp_regs(2),
  154. ipp_regs(3),
  155. ipp_regs(4),
  156. ipp_regs(5)
  157. };
  158. static const struct dce_ipp_shift ipp_shift = {
  159. IPP_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT)
  160. };
  161. static const struct dce_ipp_mask ipp_mask = {
  162. IPP_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)
  163. };
  164. #define transform_regs(id)\
  165. [id] = {\
  166. XFM_COMMON_REG_LIST_DCE80(id)\
  167. }
  168. static const struct dce_transform_registers xfm_regs[] = {
  169. transform_regs(0),
  170. transform_regs(1),
  171. transform_regs(2),
  172. transform_regs(3),
  173. transform_regs(4),
  174. transform_regs(5)
  175. };
  176. static const struct dce_transform_shift xfm_shift = {
  177. XFM_COMMON_MASK_SH_LIST_DCE80(__SHIFT)
  178. };
  179. static const struct dce_transform_mask xfm_mask = {
  180. XFM_COMMON_MASK_SH_LIST_DCE80(_MASK)
  181. };
  182. #define aux_regs(id)\
  183. [id] = {\
  184. AUX_REG_LIST(id)\
  185. }
  186. static const struct dce110_link_enc_aux_registers link_enc_aux_regs[] = {
  187. aux_regs(0),
  188. aux_regs(1),
  189. aux_regs(2),
  190. aux_regs(3),
  191. aux_regs(4),
  192. aux_regs(5)
  193. };
  194. #define hpd_regs(id)\
  195. [id] = {\
  196. HPD_REG_LIST(id)\
  197. }
  198. static const struct dce110_link_enc_hpd_registers link_enc_hpd_regs[] = {
  199. hpd_regs(0),
  200. hpd_regs(1),
  201. hpd_regs(2),
  202. hpd_regs(3),
  203. hpd_regs(4),
  204. hpd_regs(5)
  205. };
  206. #define link_regs(id)\
  207. [id] = {\
  208. LE_DCE80_REG_LIST(id)\
  209. }
  210. static const struct dce110_link_enc_registers link_enc_regs[] = {
  211. link_regs(0),
  212. link_regs(1),
  213. link_regs(2),
  214. link_regs(3),
  215. link_regs(4),
  216. link_regs(5),
  217. link_regs(6),
  218. };
  219. #define stream_enc_regs(id)\
  220. [id] = {\
  221. SE_COMMON_REG_LIST_DCE_BASE(id),\
  222. .AFMT_CNTL = 0,\
  223. }
  224. static const struct dce110_stream_enc_registers stream_enc_regs[] = {
  225. stream_enc_regs(0),
  226. stream_enc_regs(1),
  227. stream_enc_regs(2),
  228. stream_enc_regs(3),
  229. stream_enc_regs(4),
  230. stream_enc_regs(5),
  231. stream_enc_regs(6)
  232. };
  233. static const struct dce_stream_encoder_shift se_shift = {
  234. SE_COMMON_MASK_SH_LIST_DCE80_100(__SHIFT)
  235. };
  236. static const struct dce_stream_encoder_mask se_mask = {
  237. SE_COMMON_MASK_SH_LIST_DCE80_100(_MASK)
  238. };
  239. #define opp_regs(id)\
  240. [id] = {\
  241. OPP_DCE_80_REG_LIST(id),\
  242. }
  243. static const struct dce_opp_registers opp_regs[] = {
  244. opp_regs(0),
  245. opp_regs(1),
  246. opp_regs(2),
  247. opp_regs(3),
  248. opp_regs(4),
  249. opp_regs(5)
  250. };
  251. static const struct dce_opp_shift opp_shift = {
  252. OPP_COMMON_MASK_SH_LIST_DCE_80(__SHIFT)
  253. };
  254. static const struct dce_opp_mask opp_mask = {
  255. OPP_COMMON_MASK_SH_LIST_DCE_80(_MASK)
  256. };
  257. #define audio_regs(id)\
  258. [id] = {\
  259. AUD_COMMON_REG_LIST(id)\
  260. }
  261. static const struct dce_audio_registers audio_regs[] = {
  262. audio_regs(0),
  263. audio_regs(1),
  264. audio_regs(2),
  265. audio_regs(3),
  266. audio_regs(4),
  267. audio_regs(5),
  268. audio_regs(6),
  269. };
  270. static const struct dce_audio_shift audio_shift = {
  271. AUD_COMMON_MASK_SH_LIST(__SHIFT)
  272. };
  273. static const struct dce_aduio_mask audio_mask = {
  274. AUD_COMMON_MASK_SH_LIST(_MASK)
  275. };
  276. #define clk_src_regs(id)\
  277. [id] = {\
  278. CS_COMMON_REG_LIST_DCE_80(id),\
  279. }
  280. static const struct dce110_clk_src_regs clk_src_regs[] = {
  281. clk_src_regs(0),
  282. clk_src_regs(1),
  283. clk_src_regs(2)
  284. };
  285. static const struct dce110_clk_src_shift cs_shift = {
  286. CS_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT)
  287. };
  288. static const struct dce110_clk_src_mask cs_mask = {
  289. CS_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)
  290. };
  291. static const struct bios_registers bios_regs = {
  292. .BIOS_SCRATCH_6 = mmBIOS_SCRATCH_6
  293. };
  294. static const struct resource_caps res_cap = {
  295. .num_timing_generator = 6,
  296. .num_audio = 6,
  297. .num_stream_encoder = 6,
  298. .num_pll = 3,
  299. };
  300. static const struct resource_caps res_cap_81 = {
  301. .num_timing_generator = 4,
  302. .num_audio = 7,
  303. .num_stream_encoder = 7,
  304. .num_pll = 3,
  305. };
  306. static const struct resource_caps res_cap_83 = {
  307. .num_timing_generator = 2,
  308. .num_audio = 6,
  309. .num_stream_encoder = 6,
  310. .num_pll = 2,
  311. };
  312. static const struct dce_dmcu_registers dmcu_regs = {
  313. DMCU_DCE80_REG_LIST()
  314. };
  315. static const struct dce_dmcu_shift dmcu_shift = {
  316. DMCU_MASK_SH_LIST_DCE80(__SHIFT)
  317. };
  318. static const struct dce_dmcu_mask dmcu_mask = {
  319. DMCU_MASK_SH_LIST_DCE80(_MASK)
  320. };
  321. static const struct dce_abm_registers abm_regs = {
  322. ABM_DCE110_COMMON_REG_LIST()
  323. };
  324. static const struct dce_abm_shift abm_shift = {
  325. ABM_MASK_SH_LIST_DCE110(__SHIFT)
  326. };
  327. static const struct dce_abm_mask abm_mask = {
  328. ABM_MASK_SH_LIST_DCE110(_MASK)
  329. };
  330. #define CTX ctx
  331. #define REG(reg) mm ## reg
  332. #ifndef mmCC_DC_HDMI_STRAPS
  333. #define mmCC_DC_HDMI_STRAPS 0x1918
  334. #define CC_DC_HDMI_STRAPS__HDMI_DISABLE_MASK 0x40
  335. #define CC_DC_HDMI_STRAPS__HDMI_DISABLE__SHIFT 0x6
  336. #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER_MASK 0x700
  337. #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER__SHIFT 0x8
  338. #endif
  339. static void read_dce_straps(
  340. struct dc_context *ctx,
  341. struct resource_straps *straps)
  342. {
  343. REG_GET_2(CC_DC_HDMI_STRAPS,
  344. HDMI_DISABLE, &straps->hdmi_disable,
  345. AUDIO_STREAM_NUMBER, &straps->audio_stream_number);
  346. REG_GET(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO, &straps->dc_pinstraps_audio);
  347. }
  348. static struct audio *create_audio(
  349. struct dc_context *ctx, unsigned int inst)
  350. {
  351. return dce_audio_create(ctx, inst,
  352. &audio_regs[inst], &audio_shift, &audio_mask);
  353. }
  354. static struct timing_generator *dce80_timing_generator_create(
  355. struct dc_context *ctx,
  356. uint32_t instance,
  357. const struct dce110_timing_generator_offsets *offsets)
  358. {
  359. struct dce110_timing_generator *tg110 =
  360. kzalloc(sizeof(struct dce110_timing_generator), GFP_KERNEL);
  361. if (!tg110)
  362. return NULL;
  363. dce80_timing_generator_construct(tg110, ctx, instance, offsets);
  364. return &tg110->base;
  365. }
  366. static struct output_pixel_processor *dce80_opp_create(
  367. struct dc_context *ctx,
  368. uint32_t inst)
  369. {
  370. struct dce110_opp *opp =
  371. kzalloc(sizeof(struct dce110_opp), GFP_KERNEL);
  372. if (!opp)
  373. return NULL;
  374. dce110_opp_construct(opp,
  375. ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask);
  376. return &opp->base;
  377. }
  378. static struct stream_encoder *dce80_stream_encoder_create(
  379. enum engine_id eng_id,
  380. struct dc_context *ctx)
  381. {
  382. struct dce110_stream_encoder *enc110 =
  383. kzalloc(sizeof(struct dce110_stream_encoder), GFP_KERNEL);
  384. if (!enc110)
  385. return NULL;
  386. dce110_stream_encoder_construct(enc110, ctx, ctx->dc_bios, eng_id,
  387. &stream_enc_regs[eng_id],
  388. &se_shift, &se_mask);
  389. return &enc110->base;
  390. }
  391. #define SRII(reg_name, block, id)\
  392. .reg_name[id] = mm ## block ## id ## _ ## reg_name
  393. static const struct dce_hwseq_registers hwseq_reg = {
  394. HWSEQ_DCE8_REG_LIST()
  395. };
  396. static const struct dce_hwseq_shift hwseq_shift = {
  397. HWSEQ_DCE8_MASK_SH_LIST(__SHIFT)
  398. };
  399. static const struct dce_hwseq_mask hwseq_mask = {
  400. HWSEQ_DCE8_MASK_SH_LIST(_MASK)
  401. };
  402. static struct dce_hwseq *dce80_hwseq_create(
  403. struct dc_context *ctx)
  404. {
  405. struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
  406. if (hws) {
  407. hws->ctx = ctx;
  408. hws->regs = &hwseq_reg;
  409. hws->shifts = &hwseq_shift;
  410. hws->masks = &hwseq_mask;
  411. }
  412. return hws;
  413. }
  414. static const struct resource_create_funcs res_create_funcs = {
  415. .read_dce_straps = read_dce_straps,
  416. .create_audio = create_audio,
  417. .create_stream_encoder = dce80_stream_encoder_create,
  418. .create_hwseq = dce80_hwseq_create,
  419. };
  420. #define mi_inst_regs(id) { \
  421. MI_DCE8_REG_LIST(id), \
  422. .MC_HUB_RDREQ_DMIF_LIMIT = mmMC_HUB_RDREQ_DMIF_LIMIT \
  423. }
  424. static const struct dce_mem_input_registers mi_regs[] = {
  425. mi_inst_regs(0),
  426. mi_inst_regs(1),
  427. mi_inst_regs(2),
  428. mi_inst_regs(3),
  429. mi_inst_regs(4),
  430. mi_inst_regs(5),
  431. };
  432. static const struct dce_mem_input_shift mi_shifts = {
  433. MI_DCE8_MASK_SH_LIST(__SHIFT),
  434. .ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE__SHIFT
  435. };
  436. static const struct dce_mem_input_mask mi_masks = {
  437. MI_DCE8_MASK_SH_LIST(_MASK),
  438. .ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE_MASK
  439. };
  440. static struct mem_input *dce80_mem_input_create(
  441. struct dc_context *ctx,
  442. uint32_t inst)
  443. {
  444. struct dce_mem_input *dce_mi = kzalloc(sizeof(struct dce_mem_input),
  445. GFP_KERNEL);
  446. if (!dce_mi) {
  447. BREAK_TO_DEBUGGER();
  448. return NULL;
  449. }
  450. dce_mem_input_construct(dce_mi, ctx, inst, &mi_regs[inst], &mi_shifts, &mi_masks);
  451. dce_mi->wa.single_head_rdreq_dmif_limit = 2;
  452. return &dce_mi->base;
  453. }
  454. static void dce80_transform_destroy(struct transform **xfm)
  455. {
  456. kfree(TO_DCE_TRANSFORM(*xfm));
  457. *xfm = NULL;
  458. }
  459. static struct transform *dce80_transform_create(
  460. struct dc_context *ctx,
  461. uint32_t inst)
  462. {
  463. struct dce_transform *transform =
  464. kzalloc(sizeof(struct dce_transform), GFP_KERNEL);
  465. if (!transform)
  466. return NULL;
  467. dce_transform_construct(transform, ctx, inst,
  468. &xfm_regs[inst], &xfm_shift, &xfm_mask);
  469. transform->prescaler_on = false;
  470. return &transform->base;
  471. }
  472. static const struct encoder_feature_support link_enc_feature = {
  473. .max_hdmi_deep_color = COLOR_DEPTH_121212,
  474. .max_hdmi_pixel_clock = 297000,
  475. .flags.bits.IS_HBR2_CAPABLE = true,
  476. .flags.bits.IS_TPS3_CAPABLE = true,
  477. .flags.bits.IS_YCBCR_CAPABLE = true
  478. };
  479. struct link_encoder *dce80_link_encoder_create(
  480. const struct encoder_init_data *enc_init_data)
  481. {
  482. struct dce110_link_encoder *enc110 =
  483. kzalloc(sizeof(struct dce110_link_encoder), GFP_KERNEL);
  484. if (!enc110)
  485. return NULL;
  486. dce110_link_encoder_construct(enc110,
  487. enc_init_data,
  488. &link_enc_feature,
  489. &link_enc_regs[enc_init_data->transmitter],
  490. &link_enc_aux_regs[enc_init_data->channel - 1],
  491. &link_enc_hpd_regs[enc_init_data->hpd_source]);
  492. return &enc110->base;
  493. }
  494. struct clock_source *dce80_clock_source_create(
  495. struct dc_context *ctx,
  496. struct dc_bios *bios,
  497. enum clock_source_id id,
  498. const struct dce110_clk_src_regs *regs,
  499. bool dp_clk_src)
  500. {
  501. struct dce110_clk_src *clk_src =
  502. kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
  503. if (!clk_src)
  504. return NULL;
  505. if (dce110_clk_src_construct(clk_src, ctx, bios, id,
  506. regs, &cs_shift, &cs_mask)) {
  507. clk_src->base.dp_clk_src = dp_clk_src;
  508. return &clk_src->base;
  509. }
  510. BREAK_TO_DEBUGGER();
  511. return NULL;
  512. }
  513. void dce80_clock_source_destroy(struct clock_source **clk_src)
  514. {
  515. kfree(TO_DCE110_CLK_SRC(*clk_src));
  516. *clk_src = NULL;
  517. }
  518. static struct input_pixel_processor *dce80_ipp_create(
  519. struct dc_context *ctx, uint32_t inst)
  520. {
  521. struct dce_ipp *ipp = kzalloc(sizeof(struct dce_ipp), GFP_KERNEL);
  522. if (!ipp) {
  523. BREAK_TO_DEBUGGER();
  524. return NULL;
  525. }
  526. dce_ipp_construct(ipp, ctx, inst,
  527. &ipp_regs[inst], &ipp_shift, &ipp_mask);
  528. return &ipp->base;
  529. }
  530. static void destruct(struct dce110_resource_pool *pool)
  531. {
  532. unsigned int i;
  533. for (i = 0; i < pool->base.pipe_count; i++) {
  534. if (pool->base.opps[i] != NULL)
  535. dce110_opp_destroy(&pool->base.opps[i]);
  536. if (pool->base.transforms[i] != NULL)
  537. dce80_transform_destroy(&pool->base.transforms[i]);
  538. if (pool->base.ipps[i] != NULL)
  539. dce_ipp_destroy(&pool->base.ipps[i]);
  540. if (pool->base.mis[i] != NULL) {
  541. kfree(TO_DCE_MEM_INPUT(pool->base.mis[i]));
  542. pool->base.mis[i] = NULL;
  543. }
  544. if (pool->base.timing_generators[i] != NULL) {
  545. kfree(DCE110TG_FROM_TG(pool->base.timing_generators[i]));
  546. pool->base.timing_generators[i] = NULL;
  547. }
  548. }
  549. for (i = 0; i < pool->base.stream_enc_count; i++) {
  550. if (pool->base.stream_enc[i] != NULL)
  551. kfree(DCE110STRENC_FROM_STRENC(pool->base.stream_enc[i]));
  552. }
  553. for (i = 0; i < pool->base.clk_src_count; i++) {
  554. if (pool->base.clock_sources[i] != NULL) {
  555. dce80_clock_source_destroy(&pool->base.clock_sources[i]);
  556. }
  557. }
  558. if (pool->base.abm != NULL)
  559. dce_abm_destroy(&pool->base.abm);
  560. if (pool->base.dmcu != NULL)
  561. dce_dmcu_destroy(&pool->base.dmcu);
  562. if (pool->base.dp_clock_source != NULL)
  563. dce80_clock_source_destroy(&pool->base.dp_clock_source);
  564. for (i = 0; i < pool->base.audio_count; i++) {
  565. if (pool->base.audios[i] != NULL) {
  566. dce_aud_destroy(&pool->base.audios[i]);
  567. }
  568. }
  569. if (pool->base.display_clock != NULL)
  570. dce_disp_clk_destroy(&pool->base.display_clock);
  571. if (pool->base.irqs != NULL) {
  572. dal_irq_service_destroy(&pool->base.irqs);
  573. }
  574. }
  575. bool dce80_validate_bandwidth(
  576. struct dc *dc,
  577. struct dc_state *context)
  578. {
  579. /* TODO implement when needed but for now hardcode max value*/
  580. context->bw.dce.dispclk_khz = 681000;
  581. context->bw.dce.yclk_khz = 250000 * MEMORY_TYPE_MULTIPLIER;
  582. return true;
  583. }
  584. static bool dce80_validate_surface_sets(
  585. struct dc_state *context)
  586. {
  587. int i;
  588. for (i = 0; i < context->stream_count; i++) {
  589. if (context->stream_status[i].plane_count == 0)
  590. continue;
  591. if (context->stream_status[i].plane_count > 1)
  592. return false;
  593. if (context->stream_status[i].plane_states[0]->format
  594. >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)
  595. return false;
  596. }
  597. return true;
  598. }
  599. enum dc_status dce80_validate_global(
  600. struct dc *dc,
  601. struct dc_state *context)
  602. {
  603. if (!dce80_validate_surface_sets(context))
  604. return DC_FAIL_SURFACE_VALIDATE;
  605. return DC_OK;
  606. }
  607. static void dce80_destroy_resource_pool(struct resource_pool **pool)
  608. {
  609. struct dce110_resource_pool *dce110_pool = TO_DCE110_RES_POOL(*pool);
  610. destruct(dce110_pool);
  611. kfree(dce110_pool);
  612. *pool = NULL;
  613. }
  614. static const struct resource_funcs dce80_res_pool_funcs = {
  615. .destroy = dce80_destroy_resource_pool,
  616. .link_enc_create = dce80_link_encoder_create,
  617. .validate_bandwidth = dce80_validate_bandwidth,
  618. .validate_plane = dce100_validate_plane,
  619. .add_stream_to_ctx = dce100_add_stream_to_ctx,
  620. .validate_global = dce80_validate_global
  621. };
  622. static bool dce80_construct(
  623. uint8_t num_virtual_links,
  624. struct dc *dc,
  625. struct dce110_resource_pool *pool)
  626. {
  627. unsigned int i;
  628. struct dc_context *ctx = dc->ctx;
  629. struct dc_firmware_info info;
  630. struct dc_bios *bp;
  631. struct dm_pp_static_clock_info static_clk_info = {0};
  632. ctx->dc_bios->regs = &bios_regs;
  633. pool->base.res_cap = &res_cap;
  634. pool->base.funcs = &dce80_res_pool_funcs;
  635. /*************************************************
  636. * Resource + asic cap harcoding *
  637. *************************************************/
  638. pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
  639. pool->base.pipe_count = res_cap.num_timing_generator;
  640. pool->base.timing_generator_count = res_cap.num_timing_generator;
  641. dc->caps.max_downscale_ratio = 200;
  642. dc->caps.i2c_speed_in_khz = 40;
  643. dc->caps.max_cursor_size = 128;
  644. dc->caps.dual_link_dvi = true;
  645. /*************************************************
  646. * Create resources *
  647. *************************************************/
  648. bp = ctx->dc_bios;
  649. if ((bp->funcs->get_firmware_info(bp, &info) == BP_RESULT_OK) &&
  650. info.external_clock_source_frequency_for_dp != 0) {
  651. pool->base.dp_clock_source =
  652. dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true);
  653. pool->base.clock_sources[0] =
  654. dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], false);
  655. pool->base.clock_sources[1] =
  656. dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false);
  657. pool->base.clock_sources[2] =
  658. dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false);
  659. pool->base.clk_src_count = 3;
  660. } else {
  661. pool->base.dp_clock_source =
  662. dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], true);
  663. pool->base.clock_sources[0] =
  664. dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false);
  665. pool->base.clock_sources[1] =
  666. dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false);
  667. pool->base.clk_src_count = 2;
  668. }
  669. if (pool->base.dp_clock_source == NULL) {
  670. dm_error("DC: failed to create dp clock source!\n");
  671. BREAK_TO_DEBUGGER();
  672. goto res_create_fail;
  673. }
  674. for (i = 0; i < pool->base.clk_src_count; i++) {
  675. if (pool->base.clock_sources[i] == NULL) {
  676. dm_error("DC: failed to create clock sources!\n");
  677. BREAK_TO_DEBUGGER();
  678. goto res_create_fail;
  679. }
  680. }
  681. pool->base.display_clock = dce_disp_clk_create(ctx,
  682. &disp_clk_regs,
  683. &disp_clk_shift,
  684. &disp_clk_mask);
  685. if (pool->base.display_clock == NULL) {
  686. dm_error("DC: failed to create display clock!\n");
  687. BREAK_TO_DEBUGGER();
  688. goto res_create_fail;
  689. }
  690. pool->base.dmcu = dce_dmcu_create(ctx,
  691. &dmcu_regs,
  692. &dmcu_shift,
  693. &dmcu_mask);
  694. if (pool->base.dmcu == NULL) {
  695. dm_error("DC: failed to create dmcu!\n");
  696. BREAK_TO_DEBUGGER();
  697. goto res_create_fail;
  698. }
  699. pool->base.abm = dce_abm_create(ctx,
  700. &abm_regs,
  701. &abm_shift,
  702. &abm_mask);
  703. if (pool->base.abm == NULL) {
  704. dm_error("DC: failed to create abm!\n");
  705. BREAK_TO_DEBUGGER();
  706. goto res_create_fail;
  707. }
  708. if (dm_pp_get_static_clocks(ctx, &static_clk_info))
  709. pool->base.display_clock->max_clks_state =
  710. static_clk_info.max_clocks_state;
  711. {
  712. struct irq_service_init_data init_data;
  713. init_data.ctx = dc->ctx;
  714. pool->base.irqs = dal_irq_service_dce80_create(&init_data);
  715. if (!pool->base.irqs)
  716. goto res_create_fail;
  717. }
  718. for (i = 0; i < pool->base.pipe_count; i++) {
  719. pool->base.timing_generators[i] = dce80_timing_generator_create(
  720. ctx, i, &dce80_tg_offsets[i]);
  721. if (pool->base.timing_generators[i] == NULL) {
  722. BREAK_TO_DEBUGGER();
  723. dm_error("DC: failed to create tg!\n");
  724. goto res_create_fail;
  725. }
  726. pool->base.mis[i] = dce80_mem_input_create(ctx, i);
  727. if (pool->base.mis[i] == NULL) {
  728. BREAK_TO_DEBUGGER();
  729. dm_error("DC: failed to create memory input!\n");
  730. goto res_create_fail;
  731. }
  732. pool->base.ipps[i] = dce80_ipp_create(ctx, i);
  733. if (pool->base.ipps[i] == NULL) {
  734. BREAK_TO_DEBUGGER();
  735. dm_error("DC: failed to create input pixel processor!\n");
  736. goto res_create_fail;
  737. }
  738. pool->base.transforms[i] = dce80_transform_create(ctx, i);
  739. if (pool->base.transforms[i] == NULL) {
  740. BREAK_TO_DEBUGGER();
  741. dm_error("DC: failed to create transform!\n");
  742. goto res_create_fail;
  743. }
  744. pool->base.opps[i] = dce80_opp_create(ctx, i);
  745. if (pool->base.opps[i] == NULL) {
  746. BREAK_TO_DEBUGGER();
  747. dm_error("DC: failed to create output pixel processor!\n");
  748. goto res_create_fail;
  749. }
  750. }
  751. dc->caps.max_planes = pool->base.pipe_count;
  752. if (!resource_construct(num_virtual_links, dc, &pool->base,
  753. &res_create_funcs))
  754. goto res_create_fail;
  755. /* Create hardware sequencer */
  756. dce80_hw_sequencer_construct(dc);
  757. return true;
  758. res_create_fail:
  759. destruct(pool);
  760. return false;
  761. }
  762. struct resource_pool *dce80_create_resource_pool(
  763. uint8_t num_virtual_links,
  764. struct dc *dc)
  765. {
  766. struct dce110_resource_pool *pool =
  767. kzalloc(sizeof(struct dce110_resource_pool), GFP_KERNEL);
  768. if (!pool)
  769. return NULL;
  770. if (dce80_construct(num_virtual_links, dc, pool))
  771. return &pool->base;
  772. BREAK_TO_DEBUGGER();
  773. return NULL;
  774. }
  775. static bool dce81_construct(
  776. uint8_t num_virtual_links,
  777. struct dc *dc,
  778. struct dce110_resource_pool *pool)
  779. {
  780. unsigned int i;
  781. struct dc_context *ctx = dc->ctx;
  782. struct dc_firmware_info info;
  783. struct dc_bios *bp;
  784. struct dm_pp_static_clock_info static_clk_info = {0};
  785. ctx->dc_bios->regs = &bios_regs;
  786. pool->base.res_cap = &res_cap_81;
  787. pool->base.funcs = &dce80_res_pool_funcs;
  788. /*************************************************
  789. * Resource + asic cap harcoding *
  790. *************************************************/
  791. pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
  792. pool->base.pipe_count = res_cap_81.num_timing_generator;
  793. pool->base.timing_generator_count = res_cap_81.num_timing_generator;
  794. dc->caps.max_downscale_ratio = 200;
  795. dc->caps.i2c_speed_in_khz = 40;
  796. dc->caps.max_cursor_size = 128;
  797. dc->caps.is_apu = true;
  798. /*************************************************
  799. * Create resources *
  800. *************************************************/
  801. bp = ctx->dc_bios;
  802. if ((bp->funcs->get_firmware_info(bp, &info) == BP_RESULT_OK) &&
  803. info.external_clock_source_frequency_for_dp != 0) {
  804. pool->base.dp_clock_source =
  805. dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true);
  806. pool->base.clock_sources[0] =
  807. dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], false);
  808. pool->base.clock_sources[1] =
  809. dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false);
  810. pool->base.clock_sources[2] =
  811. dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false);
  812. pool->base.clk_src_count = 3;
  813. } else {
  814. pool->base.dp_clock_source =
  815. dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], true);
  816. pool->base.clock_sources[0] =
  817. dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false);
  818. pool->base.clock_sources[1] =
  819. dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false);
  820. pool->base.clk_src_count = 2;
  821. }
  822. if (pool->base.dp_clock_source == NULL) {
  823. dm_error("DC: failed to create dp clock source!\n");
  824. BREAK_TO_DEBUGGER();
  825. goto res_create_fail;
  826. }
  827. for (i = 0; i < pool->base.clk_src_count; i++) {
  828. if (pool->base.clock_sources[i] == NULL) {
  829. dm_error("DC: failed to create clock sources!\n");
  830. BREAK_TO_DEBUGGER();
  831. goto res_create_fail;
  832. }
  833. }
  834. pool->base.display_clock = dce_disp_clk_create(ctx,
  835. &disp_clk_regs,
  836. &disp_clk_shift,
  837. &disp_clk_mask);
  838. if (pool->base.display_clock == NULL) {
  839. dm_error("DC: failed to create display clock!\n");
  840. BREAK_TO_DEBUGGER();
  841. goto res_create_fail;
  842. }
  843. pool->base.dmcu = dce_dmcu_create(ctx,
  844. &dmcu_regs,
  845. &dmcu_shift,
  846. &dmcu_mask);
  847. if (pool->base.dmcu == NULL) {
  848. dm_error("DC: failed to create dmcu!\n");
  849. BREAK_TO_DEBUGGER();
  850. goto res_create_fail;
  851. }
  852. pool->base.abm = dce_abm_create(ctx,
  853. &abm_regs,
  854. &abm_shift,
  855. &abm_mask);
  856. if (pool->base.abm == NULL) {
  857. dm_error("DC: failed to create abm!\n");
  858. BREAK_TO_DEBUGGER();
  859. goto res_create_fail;
  860. }
  861. if (dm_pp_get_static_clocks(ctx, &static_clk_info))
  862. pool->base.display_clock->max_clks_state =
  863. static_clk_info.max_clocks_state;
  864. {
  865. struct irq_service_init_data init_data;
  866. init_data.ctx = dc->ctx;
  867. pool->base.irqs = dal_irq_service_dce80_create(&init_data);
  868. if (!pool->base.irqs)
  869. goto res_create_fail;
  870. }
  871. for (i = 0; i < pool->base.pipe_count; i++) {
  872. pool->base.timing_generators[i] = dce80_timing_generator_create(
  873. ctx, i, &dce80_tg_offsets[i]);
  874. if (pool->base.timing_generators[i] == NULL) {
  875. BREAK_TO_DEBUGGER();
  876. dm_error("DC: failed to create tg!\n");
  877. goto res_create_fail;
  878. }
  879. pool->base.mis[i] = dce80_mem_input_create(ctx, i);
  880. if (pool->base.mis[i] == NULL) {
  881. BREAK_TO_DEBUGGER();
  882. dm_error("DC: failed to create memory input!\n");
  883. goto res_create_fail;
  884. }
  885. pool->base.ipps[i] = dce80_ipp_create(ctx, i);
  886. if (pool->base.ipps[i] == NULL) {
  887. BREAK_TO_DEBUGGER();
  888. dm_error("DC: failed to create input pixel processor!\n");
  889. goto res_create_fail;
  890. }
  891. pool->base.transforms[i] = dce80_transform_create(ctx, i);
  892. if (pool->base.transforms[i] == NULL) {
  893. BREAK_TO_DEBUGGER();
  894. dm_error("DC: failed to create transform!\n");
  895. goto res_create_fail;
  896. }
  897. pool->base.opps[i] = dce80_opp_create(ctx, i);
  898. if (pool->base.opps[i] == NULL) {
  899. BREAK_TO_DEBUGGER();
  900. dm_error("DC: failed to create output pixel processor!\n");
  901. goto res_create_fail;
  902. }
  903. }
  904. dc->caps.max_planes = pool->base.pipe_count;
  905. if (!resource_construct(num_virtual_links, dc, &pool->base,
  906. &res_create_funcs))
  907. goto res_create_fail;
  908. /* Create hardware sequencer */
  909. dce80_hw_sequencer_construct(dc);
  910. return true;
  911. res_create_fail:
  912. destruct(pool);
  913. return false;
  914. }
  915. struct resource_pool *dce81_create_resource_pool(
  916. uint8_t num_virtual_links,
  917. struct dc *dc)
  918. {
  919. struct dce110_resource_pool *pool =
  920. kzalloc(sizeof(struct dce110_resource_pool), GFP_KERNEL);
  921. if (!pool)
  922. return NULL;
  923. if (dce81_construct(num_virtual_links, dc, pool))
  924. return &pool->base;
  925. BREAK_TO_DEBUGGER();
  926. return NULL;
  927. }
  928. static bool dce83_construct(
  929. uint8_t num_virtual_links,
  930. struct dc *dc,
  931. struct dce110_resource_pool *pool)
  932. {
  933. unsigned int i;
  934. struct dc_context *ctx = dc->ctx;
  935. struct dc_firmware_info info;
  936. struct dc_bios *bp;
  937. struct dm_pp_static_clock_info static_clk_info = {0};
  938. ctx->dc_bios->regs = &bios_regs;
  939. pool->base.res_cap = &res_cap_83;
  940. pool->base.funcs = &dce80_res_pool_funcs;
  941. /*************************************************
  942. * Resource + asic cap harcoding *
  943. *************************************************/
  944. pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
  945. pool->base.pipe_count = res_cap_83.num_timing_generator;
  946. pool->base.timing_generator_count = res_cap_83.num_timing_generator;
  947. dc->caps.max_downscale_ratio = 200;
  948. dc->caps.i2c_speed_in_khz = 40;
  949. dc->caps.max_cursor_size = 128;
  950. dc->caps.is_apu = true;
  951. /*************************************************
  952. * Create resources *
  953. *************************************************/
  954. bp = ctx->dc_bios;
  955. if ((bp->funcs->get_firmware_info(bp, &info) == BP_RESULT_OK) &&
  956. info.external_clock_source_frequency_for_dp != 0) {
  957. pool->base.dp_clock_source =
  958. dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true);
  959. pool->base.clock_sources[0] =
  960. dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[0], false);
  961. pool->base.clock_sources[1] =
  962. dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[1], false);
  963. pool->base.clk_src_count = 2;
  964. } else {
  965. pool->base.dp_clock_source =
  966. dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[0], true);
  967. pool->base.clock_sources[0] =
  968. dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[1], false);
  969. pool->base.clk_src_count = 1;
  970. }
  971. if (pool->base.dp_clock_source == NULL) {
  972. dm_error("DC: failed to create dp clock source!\n");
  973. BREAK_TO_DEBUGGER();
  974. goto res_create_fail;
  975. }
  976. for (i = 0; i < pool->base.clk_src_count; i++) {
  977. if (pool->base.clock_sources[i] == NULL) {
  978. dm_error("DC: failed to create clock sources!\n");
  979. BREAK_TO_DEBUGGER();
  980. goto res_create_fail;
  981. }
  982. }
  983. pool->base.display_clock = dce_disp_clk_create(ctx,
  984. &disp_clk_regs,
  985. &disp_clk_shift,
  986. &disp_clk_mask);
  987. if (pool->base.display_clock == NULL) {
  988. dm_error("DC: failed to create display clock!\n");
  989. BREAK_TO_DEBUGGER();
  990. goto res_create_fail;
  991. }
  992. pool->base.dmcu = dce_dmcu_create(ctx,
  993. &dmcu_regs,
  994. &dmcu_shift,
  995. &dmcu_mask);
  996. if (pool->base.dmcu == NULL) {
  997. dm_error("DC: failed to create dmcu!\n");
  998. BREAK_TO_DEBUGGER();
  999. goto res_create_fail;
  1000. }
  1001. pool->base.abm = dce_abm_create(ctx,
  1002. &abm_regs,
  1003. &abm_shift,
  1004. &abm_mask);
  1005. if (pool->base.abm == NULL) {
  1006. dm_error("DC: failed to create abm!\n");
  1007. BREAK_TO_DEBUGGER();
  1008. goto res_create_fail;
  1009. }
  1010. if (dm_pp_get_static_clocks(ctx, &static_clk_info))
  1011. pool->base.display_clock->max_clks_state =
  1012. static_clk_info.max_clocks_state;
  1013. {
  1014. struct irq_service_init_data init_data;
  1015. init_data.ctx = dc->ctx;
  1016. pool->base.irqs = dal_irq_service_dce80_create(&init_data);
  1017. if (!pool->base.irqs)
  1018. goto res_create_fail;
  1019. }
  1020. for (i = 0; i < pool->base.pipe_count; i++) {
  1021. pool->base.timing_generators[i] = dce80_timing_generator_create(
  1022. ctx, i, &dce80_tg_offsets[i]);
  1023. if (pool->base.timing_generators[i] == NULL) {
  1024. BREAK_TO_DEBUGGER();
  1025. dm_error("DC: failed to create tg!\n");
  1026. goto res_create_fail;
  1027. }
  1028. pool->base.mis[i] = dce80_mem_input_create(ctx, i);
  1029. if (pool->base.mis[i] == NULL) {
  1030. BREAK_TO_DEBUGGER();
  1031. dm_error("DC: failed to create memory input!\n");
  1032. goto res_create_fail;
  1033. }
  1034. pool->base.ipps[i] = dce80_ipp_create(ctx, i);
  1035. if (pool->base.ipps[i] == NULL) {
  1036. BREAK_TO_DEBUGGER();
  1037. dm_error("DC: failed to create input pixel processor!\n");
  1038. goto res_create_fail;
  1039. }
  1040. pool->base.transforms[i] = dce80_transform_create(ctx, i);
  1041. if (pool->base.transforms[i] == NULL) {
  1042. BREAK_TO_DEBUGGER();
  1043. dm_error("DC: failed to create transform!\n");
  1044. goto res_create_fail;
  1045. }
  1046. pool->base.opps[i] = dce80_opp_create(ctx, i);
  1047. if (pool->base.opps[i] == NULL) {
  1048. BREAK_TO_DEBUGGER();
  1049. dm_error("DC: failed to create output pixel processor!\n");
  1050. goto res_create_fail;
  1051. }
  1052. }
  1053. dc->caps.max_planes = pool->base.pipe_count;
  1054. if (!resource_construct(num_virtual_links, dc, &pool->base,
  1055. &res_create_funcs))
  1056. goto res_create_fail;
  1057. /* Create hardware sequencer */
  1058. dce80_hw_sequencer_construct(dc);
  1059. return true;
  1060. res_create_fail:
  1061. destruct(pool);
  1062. return false;
  1063. }
  1064. struct resource_pool *dce83_create_resource_pool(
  1065. uint8_t num_virtual_links,
  1066. struct dc *dc)
  1067. {
  1068. struct dce110_resource_pool *pool =
  1069. kzalloc(sizeof(struct dce110_resource_pool), GFP_KERNEL);
  1070. if (!pool)
  1071. return NULL;
  1072. if (dce83_construct(num_virtual_links, dc, pool))
  1073. return &pool->base;
  1074. BREAK_TO_DEBUGGER();
  1075. return NULL;
  1076. }