kfd_device_queue_manager.c 44 KB

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  1. /*
  2. * Copyright 2014 Advanced Micro Devices, Inc.
  3. *
  4. * Permission is hereby granted, free of charge, to any person obtaining a
  5. * copy of this software and associated documentation files (the "Software"),
  6. * to deal in the Software without restriction, including without limitation
  7. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8. * and/or sell copies of the Software, and to permit persons to whom the
  9. * Software is furnished to do so, subject to the following conditions:
  10. *
  11. * The above copyright notice and this permission notice shall be included in
  12. * all copies or substantial portions of the Software.
  13. *
  14. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  17. * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18. * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19. * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20. * OTHER DEALINGS IN THE SOFTWARE.
  21. *
  22. */
  23. #include <linux/ratelimit.h>
  24. #include <linux/printk.h>
  25. #include <linux/slab.h>
  26. #include <linux/list.h>
  27. #include <linux/types.h>
  28. #include <linux/bitops.h>
  29. #include <linux/sched.h>
  30. #include "kfd_priv.h"
  31. #include "kfd_device_queue_manager.h"
  32. #include "kfd_mqd_manager.h"
  33. #include "cik_regs.h"
  34. #include "kfd_kernel_queue.h"
  35. /* Size of the per-pipe EOP queue */
  36. #define CIK_HPD_EOP_BYTES_LOG2 11
  37. #define CIK_HPD_EOP_BYTES (1U << CIK_HPD_EOP_BYTES_LOG2)
  38. static int set_pasid_vmid_mapping(struct device_queue_manager *dqm,
  39. unsigned int pasid, unsigned int vmid);
  40. static int create_compute_queue_nocpsch(struct device_queue_manager *dqm,
  41. struct queue *q,
  42. struct qcm_process_device *qpd);
  43. static int execute_queues_cpsch(struct device_queue_manager *dqm,
  44. enum kfd_unmap_queues_filter filter,
  45. uint32_t filter_param);
  46. static int unmap_queues_cpsch(struct device_queue_manager *dqm,
  47. enum kfd_unmap_queues_filter filter,
  48. uint32_t filter_param);
  49. static int map_queues_cpsch(struct device_queue_manager *dqm);
  50. static int create_sdma_queue_nocpsch(struct device_queue_manager *dqm,
  51. struct queue *q,
  52. struct qcm_process_device *qpd);
  53. static void deallocate_sdma_queue(struct device_queue_manager *dqm,
  54. unsigned int sdma_queue_id);
  55. static inline
  56. enum KFD_MQD_TYPE get_mqd_type_from_queue_type(enum kfd_queue_type type)
  57. {
  58. if (type == KFD_QUEUE_TYPE_SDMA)
  59. return KFD_MQD_TYPE_SDMA;
  60. return KFD_MQD_TYPE_CP;
  61. }
  62. static bool is_pipe_enabled(struct device_queue_manager *dqm, int mec, int pipe)
  63. {
  64. int i;
  65. int pipe_offset = mec * dqm->dev->shared_resources.num_pipe_per_mec
  66. + pipe * dqm->dev->shared_resources.num_queue_per_pipe;
  67. /* queue is available for KFD usage if bit is 1 */
  68. for (i = 0; i < dqm->dev->shared_resources.num_queue_per_pipe; ++i)
  69. if (test_bit(pipe_offset + i,
  70. dqm->dev->shared_resources.queue_bitmap))
  71. return true;
  72. return false;
  73. }
  74. unsigned int get_queues_num(struct device_queue_manager *dqm)
  75. {
  76. return bitmap_weight(dqm->dev->shared_resources.queue_bitmap,
  77. KGD_MAX_QUEUES);
  78. }
  79. unsigned int get_queues_per_pipe(struct device_queue_manager *dqm)
  80. {
  81. return dqm->dev->shared_resources.num_queue_per_pipe;
  82. }
  83. unsigned int get_pipes_per_mec(struct device_queue_manager *dqm)
  84. {
  85. return dqm->dev->shared_resources.num_pipe_per_mec;
  86. }
  87. void program_sh_mem_settings(struct device_queue_manager *dqm,
  88. struct qcm_process_device *qpd)
  89. {
  90. return dqm->dev->kfd2kgd->program_sh_mem_settings(
  91. dqm->dev->kgd, qpd->vmid,
  92. qpd->sh_mem_config,
  93. qpd->sh_mem_ape1_base,
  94. qpd->sh_mem_ape1_limit,
  95. qpd->sh_mem_bases);
  96. }
  97. static int allocate_doorbell(struct qcm_process_device *qpd, struct queue *q)
  98. {
  99. struct kfd_dev *dev = qpd->dqm->dev;
  100. if (!KFD_IS_SOC15(dev->device_info->asic_family)) {
  101. /* On pre-SOC15 chips we need to use the queue ID to
  102. * preserve the user mode ABI.
  103. */
  104. q->doorbell_id = q->properties.queue_id;
  105. } else if (q->properties.type == KFD_QUEUE_TYPE_SDMA) {
  106. /* For SDMA queues on SOC15, use static doorbell
  107. * assignments based on the engine and queue.
  108. */
  109. q->doorbell_id = dev->shared_resources.sdma_doorbell
  110. [q->properties.sdma_engine_id]
  111. [q->properties.sdma_queue_id];
  112. } else {
  113. /* For CP queues on SOC15 reserve a free doorbell ID */
  114. unsigned int found;
  115. found = find_first_zero_bit(qpd->doorbell_bitmap,
  116. KFD_MAX_NUM_OF_QUEUES_PER_PROCESS);
  117. if (found >= KFD_MAX_NUM_OF_QUEUES_PER_PROCESS) {
  118. pr_debug("No doorbells available");
  119. return -EBUSY;
  120. }
  121. set_bit(found, qpd->doorbell_bitmap);
  122. q->doorbell_id = found;
  123. }
  124. q->properties.doorbell_off =
  125. kfd_doorbell_id_to_offset(dev, q->process,
  126. q->doorbell_id);
  127. return 0;
  128. }
  129. static void deallocate_doorbell(struct qcm_process_device *qpd,
  130. struct queue *q)
  131. {
  132. unsigned int old;
  133. struct kfd_dev *dev = qpd->dqm->dev;
  134. if (!KFD_IS_SOC15(dev->device_info->asic_family) ||
  135. q->properties.type == KFD_QUEUE_TYPE_SDMA)
  136. return;
  137. old = test_and_clear_bit(q->doorbell_id, qpd->doorbell_bitmap);
  138. WARN_ON(!old);
  139. }
  140. static int allocate_vmid(struct device_queue_manager *dqm,
  141. struct qcm_process_device *qpd,
  142. struct queue *q)
  143. {
  144. int bit, allocated_vmid;
  145. if (dqm->vmid_bitmap == 0)
  146. return -ENOMEM;
  147. bit = ffs(dqm->vmid_bitmap) - 1;
  148. dqm->vmid_bitmap &= ~(1 << bit);
  149. allocated_vmid = bit + dqm->dev->vm_info.first_vmid_kfd;
  150. pr_debug("vmid allocation %d\n", allocated_vmid);
  151. qpd->vmid = allocated_vmid;
  152. q->properties.vmid = allocated_vmid;
  153. set_pasid_vmid_mapping(dqm, q->process->pasid, q->properties.vmid);
  154. program_sh_mem_settings(dqm, qpd);
  155. /* qpd->page_table_base is set earlier when register_process()
  156. * is called, i.e. when the first queue is created.
  157. */
  158. dqm->dev->kfd2kgd->set_vm_context_page_table_base(dqm->dev->kgd,
  159. qpd->vmid,
  160. qpd->page_table_base);
  161. /* invalidate the VM context after pasid and vmid mapping is set up */
  162. kfd_flush_tlb(qpd_to_pdd(qpd));
  163. return 0;
  164. }
  165. static int flush_texture_cache_nocpsch(struct kfd_dev *kdev,
  166. struct qcm_process_device *qpd)
  167. {
  168. const struct packet_manager_funcs *pmf = qpd->dqm->packets.pmf;
  169. int ret;
  170. if (!qpd->ib_kaddr)
  171. return -ENOMEM;
  172. ret = pmf->release_mem(qpd->ib_base, (uint32_t *)qpd->ib_kaddr);
  173. if (ret)
  174. return ret;
  175. return kdev->kfd2kgd->submit_ib(kdev->kgd, KGD_ENGINE_MEC1, qpd->vmid,
  176. qpd->ib_base, (uint32_t *)qpd->ib_kaddr,
  177. pmf->release_mem_size / sizeof(uint32_t));
  178. }
  179. static void deallocate_vmid(struct device_queue_manager *dqm,
  180. struct qcm_process_device *qpd,
  181. struct queue *q)
  182. {
  183. int bit = qpd->vmid - dqm->dev->vm_info.first_vmid_kfd;
  184. /* On GFX v7, CP doesn't flush TC at dequeue */
  185. if (q->device->device_info->asic_family == CHIP_HAWAII)
  186. if (flush_texture_cache_nocpsch(q->device, qpd))
  187. pr_err("Failed to flush TC\n");
  188. kfd_flush_tlb(qpd_to_pdd(qpd));
  189. /* Release the vmid mapping */
  190. set_pasid_vmid_mapping(dqm, 0, qpd->vmid);
  191. dqm->vmid_bitmap |= (1 << bit);
  192. qpd->vmid = 0;
  193. q->properties.vmid = 0;
  194. }
  195. static int create_queue_nocpsch(struct device_queue_manager *dqm,
  196. struct queue *q,
  197. struct qcm_process_device *qpd)
  198. {
  199. int retval;
  200. print_queue(q);
  201. mutex_lock(&dqm->lock);
  202. if (dqm->total_queue_count >= max_num_of_queues_per_device) {
  203. pr_warn("Can't create new usermode queue because %d queues were already created\n",
  204. dqm->total_queue_count);
  205. retval = -EPERM;
  206. goto out_unlock;
  207. }
  208. if (list_empty(&qpd->queues_list)) {
  209. retval = allocate_vmid(dqm, qpd, q);
  210. if (retval)
  211. goto out_unlock;
  212. }
  213. q->properties.vmid = qpd->vmid;
  214. /*
  215. * Eviction state logic: we only mark active queues as evicted
  216. * to avoid the overhead of restoring inactive queues later
  217. */
  218. if (qpd->evicted)
  219. q->properties.is_evicted = (q->properties.queue_size > 0 &&
  220. q->properties.queue_percent > 0 &&
  221. q->properties.queue_address != 0);
  222. q->properties.tba_addr = qpd->tba_addr;
  223. q->properties.tma_addr = qpd->tma_addr;
  224. if (q->properties.type == KFD_QUEUE_TYPE_COMPUTE)
  225. retval = create_compute_queue_nocpsch(dqm, q, qpd);
  226. else if (q->properties.type == KFD_QUEUE_TYPE_SDMA)
  227. retval = create_sdma_queue_nocpsch(dqm, q, qpd);
  228. else
  229. retval = -EINVAL;
  230. if (retval) {
  231. if (list_empty(&qpd->queues_list))
  232. deallocate_vmid(dqm, qpd, q);
  233. goto out_unlock;
  234. }
  235. list_add(&q->list, &qpd->queues_list);
  236. qpd->queue_count++;
  237. if (q->properties.is_active)
  238. dqm->queue_count++;
  239. if (q->properties.type == KFD_QUEUE_TYPE_SDMA)
  240. dqm->sdma_queue_count++;
  241. /*
  242. * Unconditionally increment this counter, regardless of the queue's
  243. * type or whether the queue is active.
  244. */
  245. dqm->total_queue_count++;
  246. pr_debug("Total of %d queues are accountable so far\n",
  247. dqm->total_queue_count);
  248. out_unlock:
  249. mutex_unlock(&dqm->lock);
  250. return retval;
  251. }
  252. static int allocate_hqd(struct device_queue_manager *dqm, struct queue *q)
  253. {
  254. bool set;
  255. int pipe, bit, i;
  256. set = false;
  257. for (pipe = dqm->next_pipe_to_allocate, i = 0;
  258. i < get_pipes_per_mec(dqm);
  259. pipe = ((pipe + 1) % get_pipes_per_mec(dqm)), ++i) {
  260. if (!is_pipe_enabled(dqm, 0, pipe))
  261. continue;
  262. if (dqm->allocated_queues[pipe] != 0) {
  263. bit = ffs(dqm->allocated_queues[pipe]) - 1;
  264. dqm->allocated_queues[pipe] &= ~(1 << bit);
  265. q->pipe = pipe;
  266. q->queue = bit;
  267. set = true;
  268. break;
  269. }
  270. }
  271. if (!set)
  272. return -EBUSY;
  273. pr_debug("hqd slot - pipe %d, queue %d\n", q->pipe, q->queue);
  274. /* horizontal hqd allocation */
  275. dqm->next_pipe_to_allocate = (pipe + 1) % get_pipes_per_mec(dqm);
  276. return 0;
  277. }
  278. static inline void deallocate_hqd(struct device_queue_manager *dqm,
  279. struct queue *q)
  280. {
  281. dqm->allocated_queues[q->pipe] |= (1 << q->queue);
  282. }
  283. static int create_compute_queue_nocpsch(struct device_queue_manager *dqm,
  284. struct queue *q,
  285. struct qcm_process_device *qpd)
  286. {
  287. int retval;
  288. struct mqd_manager *mqd;
  289. mqd = dqm->ops.get_mqd_manager(dqm, KFD_MQD_TYPE_COMPUTE);
  290. if (!mqd)
  291. return -ENOMEM;
  292. retval = allocate_hqd(dqm, q);
  293. if (retval)
  294. return retval;
  295. retval = allocate_doorbell(qpd, q);
  296. if (retval)
  297. goto out_deallocate_hqd;
  298. retval = mqd->init_mqd(mqd, &q->mqd, &q->mqd_mem_obj,
  299. &q->gart_mqd_addr, &q->properties);
  300. if (retval)
  301. goto out_deallocate_doorbell;
  302. pr_debug("Loading mqd to hqd on pipe %d, queue %d\n",
  303. q->pipe, q->queue);
  304. dqm->dev->kfd2kgd->set_scratch_backing_va(
  305. dqm->dev->kgd, qpd->sh_hidden_private_base, qpd->vmid);
  306. if (!q->properties.is_active)
  307. return 0;
  308. retval = mqd->load_mqd(mqd, q->mqd, q->pipe, q->queue, &q->properties,
  309. q->process->mm);
  310. if (retval)
  311. goto out_uninit_mqd;
  312. return 0;
  313. out_uninit_mqd:
  314. mqd->uninit_mqd(mqd, q->mqd, q->mqd_mem_obj);
  315. out_deallocate_doorbell:
  316. deallocate_doorbell(qpd, q);
  317. out_deallocate_hqd:
  318. deallocate_hqd(dqm, q);
  319. return retval;
  320. }
  321. /* Access to DQM has to be locked before calling destroy_queue_nocpsch_locked
  322. * to avoid asynchronized access
  323. */
  324. static int destroy_queue_nocpsch_locked(struct device_queue_manager *dqm,
  325. struct qcm_process_device *qpd,
  326. struct queue *q)
  327. {
  328. int retval;
  329. struct mqd_manager *mqd;
  330. mqd = dqm->ops.get_mqd_manager(dqm,
  331. get_mqd_type_from_queue_type(q->properties.type));
  332. if (!mqd)
  333. return -ENOMEM;
  334. if (q->properties.type == KFD_QUEUE_TYPE_COMPUTE) {
  335. deallocate_hqd(dqm, q);
  336. } else if (q->properties.type == KFD_QUEUE_TYPE_SDMA) {
  337. dqm->sdma_queue_count--;
  338. deallocate_sdma_queue(dqm, q->sdma_id);
  339. } else {
  340. pr_debug("q->properties.type %d is invalid\n",
  341. q->properties.type);
  342. return -EINVAL;
  343. }
  344. dqm->total_queue_count--;
  345. deallocate_doorbell(qpd, q);
  346. retval = mqd->destroy_mqd(mqd, q->mqd,
  347. KFD_PREEMPT_TYPE_WAVEFRONT_RESET,
  348. KFD_UNMAP_LATENCY_MS,
  349. q->pipe, q->queue);
  350. if (retval == -ETIME)
  351. qpd->reset_wavefronts = true;
  352. mqd->uninit_mqd(mqd, q->mqd, q->mqd_mem_obj);
  353. list_del(&q->list);
  354. if (list_empty(&qpd->queues_list)) {
  355. if (qpd->reset_wavefronts) {
  356. pr_warn("Resetting wave fronts (nocpsch) on dev %p\n",
  357. dqm->dev);
  358. /* dbgdev_wave_reset_wavefronts has to be called before
  359. * deallocate_vmid(), i.e. when vmid is still in use.
  360. */
  361. dbgdev_wave_reset_wavefronts(dqm->dev,
  362. qpd->pqm->process);
  363. qpd->reset_wavefronts = false;
  364. }
  365. deallocate_vmid(dqm, qpd, q);
  366. }
  367. qpd->queue_count--;
  368. if (q->properties.is_active)
  369. dqm->queue_count--;
  370. return retval;
  371. }
  372. static int destroy_queue_nocpsch(struct device_queue_manager *dqm,
  373. struct qcm_process_device *qpd,
  374. struct queue *q)
  375. {
  376. int retval;
  377. mutex_lock(&dqm->lock);
  378. retval = destroy_queue_nocpsch_locked(dqm, qpd, q);
  379. mutex_unlock(&dqm->lock);
  380. return retval;
  381. }
  382. static int update_queue(struct device_queue_manager *dqm, struct queue *q)
  383. {
  384. int retval;
  385. struct mqd_manager *mqd;
  386. struct kfd_process_device *pdd;
  387. bool prev_active = false;
  388. mutex_lock(&dqm->lock);
  389. pdd = kfd_get_process_device_data(q->device, q->process);
  390. if (!pdd) {
  391. retval = -ENODEV;
  392. goto out_unlock;
  393. }
  394. mqd = dqm->ops.get_mqd_manager(dqm,
  395. get_mqd_type_from_queue_type(q->properties.type));
  396. if (!mqd) {
  397. retval = -ENOMEM;
  398. goto out_unlock;
  399. }
  400. /*
  401. * Eviction state logic: we only mark active queues as evicted
  402. * to avoid the overhead of restoring inactive queues later
  403. */
  404. if (pdd->qpd.evicted)
  405. q->properties.is_evicted = (q->properties.queue_size > 0 &&
  406. q->properties.queue_percent > 0 &&
  407. q->properties.queue_address != 0);
  408. /* Save previous activity state for counters */
  409. prev_active = q->properties.is_active;
  410. /* Make sure the queue is unmapped before updating the MQD */
  411. if (dqm->sched_policy != KFD_SCHED_POLICY_NO_HWS) {
  412. retval = unmap_queues_cpsch(dqm,
  413. KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0);
  414. if (retval) {
  415. pr_err("unmap queue failed\n");
  416. goto out_unlock;
  417. }
  418. } else if (prev_active &&
  419. (q->properties.type == KFD_QUEUE_TYPE_COMPUTE ||
  420. q->properties.type == KFD_QUEUE_TYPE_SDMA)) {
  421. retval = mqd->destroy_mqd(mqd, q->mqd,
  422. KFD_PREEMPT_TYPE_WAVEFRONT_DRAIN,
  423. KFD_UNMAP_LATENCY_MS, q->pipe, q->queue);
  424. if (retval) {
  425. pr_err("destroy mqd failed\n");
  426. goto out_unlock;
  427. }
  428. }
  429. retval = mqd->update_mqd(mqd, q->mqd, &q->properties);
  430. /*
  431. * check active state vs. the previous state and modify
  432. * counter accordingly. map_queues_cpsch uses the
  433. * dqm->queue_count to determine whether a new runlist must be
  434. * uploaded.
  435. */
  436. if (q->properties.is_active && !prev_active)
  437. dqm->queue_count++;
  438. else if (!q->properties.is_active && prev_active)
  439. dqm->queue_count--;
  440. if (dqm->sched_policy != KFD_SCHED_POLICY_NO_HWS)
  441. retval = map_queues_cpsch(dqm);
  442. else if (q->properties.is_active &&
  443. (q->properties.type == KFD_QUEUE_TYPE_COMPUTE ||
  444. q->properties.type == KFD_QUEUE_TYPE_SDMA))
  445. retval = mqd->load_mqd(mqd, q->mqd, q->pipe, q->queue,
  446. &q->properties, q->process->mm);
  447. out_unlock:
  448. mutex_unlock(&dqm->lock);
  449. return retval;
  450. }
  451. static struct mqd_manager *get_mqd_manager(
  452. struct device_queue_manager *dqm, enum KFD_MQD_TYPE type)
  453. {
  454. struct mqd_manager *mqd;
  455. if (WARN_ON(type >= KFD_MQD_TYPE_MAX))
  456. return NULL;
  457. pr_debug("mqd type %d\n", type);
  458. mqd = dqm->mqds[type];
  459. if (!mqd) {
  460. mqd = mqd_manager_init(type, dqm->dev);
  461. if (!mqd)
  462. pr_err("mqd manager is NULL");
  463. dqm->mqds[type] = mqd;
  464. }
  465. return mqd;
  466. }
  467. static int evict_process_queues_nocpsch(struct device_queue_manager *dqm,
  468. struct qcm_process_device *qpd)
  469. {
  470. struct queue *q;
  471. struct mqd_manager *mqd;
  472. struct kfd_process_device *pdd;
  473. int retval = 0;
  474. mutex_lock(&dqm->lock);
  475. if (qpd->evicted++ > 0) /* already evicted, do nothing */
  476. goto out;
  477. pdd = qpd_to_pdd(qpd);
  478. pr_info_ratelimited("Evicting PASID %u queues\n",
  479. pdd->process->pasid);
  480. /* unactivate all active queues on the qpd */
  481. list_for_each_entry(q, &qpd->queues_list, list) {
  482. if (!q->properties.is_active)
  483. continue;
  484. mqd = dqm->ops.get_mqd_manager(dqm,
  485. get_mqd_type_from_queue_type(q->properties.type));
  486. if (!mqd) { /* should not be here */
  487. pr_err("Cannot evict queue, mqd mgr is NULL\n");
  488. retval = -ENOMEM;
  489. goto out;
  490. }
  491. q->properties.is_evicted = true;
  492. q->properties.is_active = false;
  493. retval = mqd->destroy_mqd(mqd, q->mqd,
  494. KFD_PREEMPT_TYPE_WAVEFRONT_DRAIN,
  495. KFD_UNMAP_LATENCY_MS, q->pipe, q->queue);
  496. if (retval)
  497. goto out;
  498. dqm->queue_count--;
  499. }
  500. out:
  501. mutex_unlock(&dqm->lock);
  502. return retval;
  503. }
  504. static int evict_process_queues_cpsch(struct device_queue_manager *dqm,
  505. struct qcm_process_device *qpd)
  506. {
  507. struct queue *q;
  508. struct kfd_process_device *pdd;
  509. int retval = 0;
  510. mutex_lock(&dqm->lock);
  511. if (qpd->evicted++ > 0) /* already evicted, do nothing */
  512. goto out;
  513. pdd = qpd_to_pdd(qpd);
  514. pr_info_ratelimited("Evicting PASID %u queues\n",
  515. pdd->process->pasid);
  516. /* unactivate all active queues on the qpd */
  517. list_for_each_entry(q, &qpd->queues_list, list) {
  518. if (!q->properties.is_active)
  519. continue;
  520. q->properties.is_evicted = true;
  521. q->properties.is_active = false;
  522. dqm->queue_count--;
  523. }
  524. retval = execute_queues_cpsch(dqm,
  525. qpd->is_debug ?
  526. KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES :
  527. KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0);
  528. out:
  529. mutex_unlock(&dqm->lock);
  530. return retval;
  531. }
  532. static int restore_process_queues_nocpsch(struct device_queue_manager *dqm,
  533. struct qcm_process_device *qpd)
  534. {
  535. struct queue *q;
  536. struct mqd_manager *mqd;
  537. struct kfd_process_device *pdd;
  538. uint32_t pd_base;
  539. int retval = 0;
  540. pdd = qpd_to_pdd(qpd);
  541. /* Retrieve PD base */
  542. pd_base = dqm->dev->kfd2kgd->get_process_page_dir(pdd->vm);
  543. mutex_lock(&dqm->lock);
  544. if (WARN_ON_ONCE(!qpd->evicted)) /* already restored, do nothing */
  545. goto out;
  546. if (qpd->evicted > 1) { /* ref count still > 0, decrement & quit */
  547. qpd->evicted--;
  548. goto out;
  549. }
  550. pr_info_ratelimited("Restoring PASID %u queues\n",
  551. pdd->process->pasid);
  552. /* Update PD Base in QPD */
  553. qpd->page_table_base = pd_base;
  554. pr_debug("Updated PD address to 0x%08x\n", pd_base);
  555. if (!list_empty(&qpd->queues_list)) {
  556. dqm->dev->kfd2kgd->set_vm_context_page_table_base(
  557. dqm->dev->kgd,
  558. qpd->vmid,
  559. qpd->page_table_base);
  560. kfd_flush_tlb(pdd);
  561. }
  562. /* activate all active queues on the qpd */
  563. list_for_each_entry(q, &qpd->queues_list, list) {
  564. if (!q->properties.is_evicted)
  565. continue;
  566. mqd = dqm->ops.get_mqd_manager(dqm,
  567. get_mqd_type_from_queue_type(q->properties.type));
  568. if (!mqd) { /* should not be here */
  569. pr_err("Cannot restore queue, mqd mgr is NULL\n");
  570. retval = -ENOMEM;
  571. goto out;
  572. }
  573. q->properties.is_evicted = false;
  574. q->properties.is_active = true;
  575. retval = mqd->load_mqd(mqd, q->mqd, q->pipe,
  576. q->queue, &q->properties,
  577. q->process->mm);
  578. if (retval)
  579. goto out;
  580. dqm->queue_count++;
  581. }
  582. qpd->evicted = 0;
  583. out:
  584. mutex_unlock(&dqm->lock);
  585. return retval;
  586. }
  587. static int restore_process_queues_cpsch(struct device_queue_manager *dqm,
  588. struct qcm_process_device *qpd)
  589. {
  590. struct queue *q;
  591. struct kfd_process_device *pdd;
  592. uint32_t pd_base;
  593. int retval = 0;
  594. pdd = qpd_to_pdd(qpd);
  595. /* Retrieve PD base */
  596. pd_base = dqm->dev->kfd2kgd->get_process_page_dir(pdd->vm);
  597. mutex_lock(&dqm->lock);
  598. if (WARN_ON_ONCE(!qpd->evicted)) /* already restored, do nothing */
  599. goto out;
  600. if (qpd->evicted > 1) { /* ref count still > 0, decrement & quit */
  601. qpd->evicted--;
  602. goto out;
  603. }
  604. pr_info_ratelimited("Restoring PASID %u queues\n",
  605. pdd->process->pasid);
  606. /* Update PD Base in QPD */
  607. qpd->page_table_base = pd_base;
  608. pr_debug("Updated PD address to 0x%08x\n", pd_base);
  609. /* activate all active queues on the qpd */
  610. list_for_each_entry(q, &qpd->queues_list, list) {
  611. if (!q->properties.is_evicted)
  612. continue;
  613. q->properties.is_evicted = false;
  614. q->properties.is_active = true;
  615. dqm->queue_count++;
  616. }
  617. retval = execute_queues_cpsch(dqm,
  618. KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0);
  619. if (!retval)
  620. qpd->evicted = 0;
  621. out:
  622. mutex_unlock(&dqm->lock);
  623. return retval;
  624. }
  625. static int register_process(struct device_queue_manager *dqm,
  626. struct qcm_process_device *qpd)
  627. {
  628. struct device_process_node *n;
  629. struct kfd_process_device *pdd;
  630. uint32_t pd_base;
  631. int retval;
  632. n = kzalloc(sizeof(*n), GFP_KERNEL);
  633. if (!n)
  634. return -ENOMEM;
  635. n->qpd = qpd;
  636. pdd = qpd_to_pdd(qpd);
  637. /* Retrieve PD base */
  638. pd_base = dqm->dev->kfd2kgd->get_process_page_dir(pdd->vm);
  639. mutex_lock(&dqm->lock);
  640. list_add(&n->list, &dqm->queues);
  641. /* Update PD Base in QPD */
  642. qpd->page_table_base = pd_base;
  643. retval = dqm->asic_ops.update_qpd(dqm, qpd);
  644. dqm->processes_count++;
  645. mutex_unlock(&dqm->lock);
  646. return retval;
  647. }
  648. static int unregister_process(struct device_queue_manager *dqm,
  649. struct qcm_process_device *qpd)
  650. {
  651. int retval;
  652. struct device_process_node *cur, *next;
  653. pr_debug("qpd->queues_list is %s\n",
  654. list_empty(&qpd->queues_list) ? "empty" : "not empty");
  655. retval = 0;
  656. mutex_lock(&dqm->lock);
  657. list_for_each_entry_safe(cur, next, &dqm->queues, list) {
  658. if (qpd == cur->qpd) {
  659. list_del(&cur->list);
  660. kfree(cur);
  661. dqm->processes_count--;
  662. goto out;
  663. }
  664. }
  665. /* qpd not found in dqm list */
  666. retval = 1;
  667. out:
  668. mutex_unlock(&dqm->lock);
  669. return retval;
  670. }
  671. static int
  672. set_pasid_vmid_mapping(struct device_queue_manager *dqm, unsigned int pasid,
  673. unsigned int vmid)
  674. {
  675. uint32_t pasid_mapping;
  676. pasid_mapping = (pasid == 0) ? 0 :
  677. (uint32_t)pasid |
  678. ATC_VMID_PASID_MAPPING_VALID;
  679. return dqm->dev->kfd2kgd->set_pasid_vmid_mapping(
  680. dqm->dev->kgd, pasid_mapping,
  681. vmid);
  682. }
  683. static void init_interrupts(struct device_queue_manager *dqm)
  684. {
  685. unsigned int i;
  686. for (i = 0 ; i < get_pipes_per_mec(dqm) ; i++)
  687. if (is_pipe_enabled(dqm, 0, i))
  688. dqm->dev->kfd2kgd->init_interrupts(dqm->dev->kgd, i);
  689. }
  690. static int initialize_nocpsch(struct device_queue_manager *dqm)
  691. {
  692. int pipe, queue;
  693. pr_debug("num of pipes: %d\n", get_pipes_per_mec(dqm));
  694. dqm->allocated_queues = kcalloc(get_pipes_per_mec(dqm),
  695. sizeof(unsigned int), GFP_KERNEL);
  696. if (!dqm->allocated_queues)
  697. return -ENOMEM;
  698. mutex_init(&dqm->lock);
  699. INIT_LIST_HEAD(&dqm->queues);
  700. dqm->queue_count = dqm->next_pipe_to_allocate = 0;
  701. dqm->sdma_queue_count = 0;
  702. for (pipe = 0; pipe < get_pipes_per_mec(dqm); pipe++) {
  703. int pipe_offset = pipe * get_queues_per_pipe(dqm);
  704. for (queue = 0; queue < get_queues_per_pipe(dqm); queue++)
  705. if (test_bit(pipe_offset + queue,
  706. dqm->dev->shared_resources.queue_bitmap))
  707. dqm->allocated_queues[pipe] |= 1 << queue;
  708. }
  709. dqm->vmid_bitmap = (1 << dqm->dev->vm_info.vmid_num_kfd) - 1;
  710. dqm->sdma_bitmap = (1 << CIK_SDMA_QUEUES) - 1;
  711. return 0;
  712. }
  713. static void uninitialize(struct device_queue_manager *dqm)
  714. {
  715. int i;
  716. WARN_ON(dqm->queue_count > 0 || dqm->processes_count > 0);
  717. kfree(dqm->allocated_queues);
  718. for (i = 0 ; i < KFD_MQD_TYPE_MAX ; i++)
  719. kfree(dqm->mqds[i]);
  720. mutex_destroy(&dqm->lock);
  721. kfd_gtt_sa_free(dqm->dev, dqm->pipeline_mem);
  722. }
  723. static int start_nocpsch(struct device_queue_manager *dqm)
  724. {
  725. init_interrupts(dqm);
  726. return pm_init(&dqm->packets, dqm);
  727. }
  728. static int stop_nocpsch(struct device_queue_manager *dqm)
  729. {
  730. pm_uninit(&dqm->packets);
  731. return 0;
  732. }
  733. static int allocate_sdma_queue(struct device_queue_manager *dqm,
  734. unsigned int *sdma_queue_id)
  735. {
  736. int bit;
  737. if (dqm->sdma_bitmap == 0)
  738. return -ENOMEM;
  739. bit = ffs(dqm->sdma_bitmap) - 1;
  740. dqm->sdma_bitmap &= ~(1 << bit);
  741. *sdma_queue_id = bit;
  742. return 0;
  743. }
  744. static void deallocate_sdma_queue(struct device_queue_manager *dqm,
  745. unsigned int sdma_queue_id)
  746. {
  747. if (sdma_queue_id >= CIK_SDMA_QUEUES)
  748. return;
  749. dqm->sdma_bitmap |= (1 << sdma_queue_id);
  750. }
  751. static int create_sdma_queue_nocpsch(struct device_queue_manager *dqm,
  752. struct queue *q,
  753. struct qcm_process_device *qpd)
  754. {
  755. struct mqd_manager *mqd;
  756. int retval;
  757. mqd = dqm->ops.get_mqd_manager(dqm, KFD_MQD_TYPE_SDMA);
  758. if (!mqd)
  759. return -ENOMEM;
  760. retval = allocate_sdma_queue(dqm, &q->sdma_id);
  761. if (retval)
  762. return retval;
  763. q->properties.sdma_queue_id = q->sdma_id / CIK_SDMA_QUEUES_PER_ENGINE;
  764. q->properties.sdma_engine_id = q->sdma_id % CIK_SDMA_QUEUES_PER_ENGINE;
  765. retval = allocate_doorbell(qpd, q);
  766. if (retval)
  767. goto out_deallocate_sdma_queue;
  768. pr_debug("SDMA id is: %d\n", q->sdma_id);
  769. pr_debug("SDMA queue id: %d\n", q->properties.sdma_queue_id);
  770. pr_debug("SDMA engine id: %d\n", q->properties.sdma_engine_id);
  771. dqm->asic_ops.init_sdma_vm(dqm, q, qpd);
  772. retval = mqd->init_mqd(mqd, &q->mqd, &q->mqd_mem_obj,
  773. &q->gart_mqd_addr, &q->properties);
  774. if (retval)
  775. goto out_deallocate_doorbell;
  776. retval = mqd->load_mqd(mqd, q->mqd, 0, 0, &q->properties, NULL);
  777. if (retval)
  778. goto out_uninit_mqd;
  779. return 0;
  780. out_uninit_mqd:
  781. mqd->uninit_mqd(mqd, q->mqd, q->mqd_mem_obj);
  782. out_deallocate_doorbell:
  783. deallocate_doorbell(qpd, q);
  784. out_deallocate_sdma_queue:
  785. deallocate_sdma_queue(dqm, q->sdma_id);
  786. return retval;
  787. }
  788. /*
  789. * Device Queue Manager implementation for cp scheduler
  790. */
  791. static int set_sched_resources(struct device_queue_manager *dqm)
  792. {
  793. int i, mec;
  794. struct scheduling_resources res;
  795. res.vmid_mask = dqm->dev->shared_resources.compute_vmid_bitmap;
  796. res.queue_mask = 0;
  797. for (i = 0; i < KGD_MAX_QUEUES; ++i) {
  798. mec = (i / dqm->dev->shared_resources.num_queue_per_pipe)
  799. / dqm->dev->shared_resources.num_pipe_per_mec;
  800. if (!test_bit(i, dqm->dev->shared_resources.queue_bitmap))
  801. continue;
  802. /* only acquire queues from the first MEC */
  803. if (mec > 0)
  804. continue;
  805. /* This situation may be hit in the future if a new HW
  806. * generation exposes more than 64 queues. If so, the
  807. * definition of res.queue_mask needs updating
  808. */
  809. if (WARN_ON(i >= (sizeof(res.queue_mask)*8))) {
  810. pr_err("Invalid queue enabled by amdgpu: %d\n", i);
  811. break;
  812. }
  813. res.queue_mask |= (1ull << i);
  814. }
  815. res.gws_mask = res.oac_mask = res.gds_heap_base =
  816. res.gds_heap_size = 0;
  817. pr_debug("Scheduling resources:\n"
  818. "vmid mask: 0x%8X\n"
  819. "queue mask: 0x%8llX\n",
  820. res.vmid_mask, res.queue_mask);
  821. return pm_send_set_resources(&dqm->packets, &res);
  822. }
  823. static int initialize_cpsch(struct device_queue_manager *dqm)
  824. {
  825. pr_debug("num of pipes: %d\n", get_pipes_per_mec(dqm));
  826. mutex_init(&dqm->lock);
  827. INIT_LIST_HEAD(&dqm->queues);
  828. dqm->queue_count = dqm->processes_count = 0;
  829. dqm->sdma_queue_count = 0;
  830. dqm->active_runlist = false;
  831. dqm->sdma_bitmap = (1 << CIK_SDMA_QUEUES) - 1;
  832. return 0;
  833. }
  834. static int start_cpsch(struct device_queue_manager *dqm)
  835. {
  836. int retval;
  837. retval = 0;
  838. retval = pm_init(&dqm->packets, dqm);
  839. if (retval)
  840. goto fail_packet_manager_init;
  841. retval = set_sched_resources(dqm);
  842. if (retval)
  843. goto fail_set_sched_resources;
  844. pr_debug("Allocating fence memory\n");
  845. /* allocate fence memory on the gart */
  846. retval = kfd_gtt_sa_allocate(dqm->dev, sizeof(*dqm->fence_addr),
  847. &dqm->fence_mem);
  848. if (retval)
  849. goto fail_allocate_vidmem;
  850. dqm->fence_addr = dqm->fence_mem->cpu_ptr;
  851. dqm->fence_gpu_addr = dqm->fence_mem->gpu_addr;
  852. init_interrupts(dqm);
  853. mutex_lock(&dqm->lock);
  854. execute_queues_cpsch(dqm, KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0);
  855. mutex_unlock(&dqm->lock);
  856. return 0;
  857. fail_allocate_vidmem:
  858. fail_set_sched_resources:
  859. pm_uninit(&dqm->packets);
  860. fail_packet_manager_init:
  861. return retval;
  862. }
  863. static int stop_cpsch(struct device_queue_manager *dqm)
  864. {
  865. mutex_lock(&dqm->lock);
  866. unmap_queues_cpsch(dqm, KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES, 0);
  867. mutex_unlock(&dqm->lock);
  868. kfd_gtt_sa_free(dqm->dev, dqm->fence_mem);
  869. pm_uninit(&dqm->packets);
  870. return 0;
  871. }
  872. static int create_kernel_queue_cpsch(struct device_queue_manager *dqm,
  873. struct kernel_queue *kq,
  874. struct qcm_process_device *qpd)
  875. {
  876. mutex_lock(&dqm->lock);
  877. if (dqm->total_queue_count >= max_num_of_queues_per_device) {
  878. pr_warn("Can't create new kernel queue because %d queues were already created\n",
  879. dqm->total_queue_count);
  880. mutex_unlock(&dqm->lock);
  881. return -EPERM;
  882. }
  883. /*
  884. * Unconditionally increment this counter, regardless of the queue's
  885. * type or whether the queue is active.
  886. */
  887. dqm->total_queue_count++;
  888. pr_debug("Total of %d queues are accountable so far\n",
  889. dqm->total_queue_count);
  890. list_add(&kq->list, &qpd->priv_queue_list);
  891. dqm->queue_count++;
  892. qpd->is_debug = true;
  893. execute_queues_cpsch(dqm, KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0);
  894. mutex_unlock(&dqm->lock);
  895. return 0;
  896. }
  897. static void destroy_kernel_queue_cpsch(struct device_queue_manager *dqm,
  898. struct kernel_queue *kq,
  899. struct qcm_process_device *qpd)
  900. {
  901. mutex_lock(&dqm->lock);
  902. list_del(&kq->list);
  903. dqm->queue_count--;
  904. qpd->is_debug = false;
  905. execute_queues_cpsch(dqm, KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES, 0);
  906. /*
  907. * Unconditionally decrement this counter, regardless of the queue's
  908. * type.
  909. */
  910. dqm->total_queue_count--;
  911. pr_debug("Total of %d queues are accountable so far\n",
  912. dqm->total_queue_count);
  913. mutex_unlock(&dqm->lock);
  914. }
  915. static int create_queue_cpsch(struct device_queue_manager *dqm, struct queue *q,
  916. struct qcm_process_device *qpd)
  917. {
  918. int retval;
  919. struct mqd_manager *mqd;
  920. retval = 0;
  921. mutex_lock(&dqm->lock);
  922. if (dqm->total_queue_count >= max_num_of_queues_per_device) {
  923. pr_warn("Can't create new usermode queue because %d queues were already created\n",
  924. dqm->total_queue_count);
  925. retval = -EPERM;
  926. goto out_unlock;
  927. }
  928. if (q->properties.type == KFD_QUEUE_TYPE_SDMA) {
  929. retval = allocate_sdma_queue(dqm, &q->sdma_id);
  930. if (retval)
  931. goto out_unlock;
  932. q->properties.sdma_queue_id =
  933. q->sdma_id / CIK_SDMA_QUEUES_PER_ENGINE;
  934. q->properties.sdma_engine_id =
  935. q->sdma_id % CIK_SDMA_QUEUES_PER_ENGINE;
  936. }
  937. retval = allocate_doorbell(qpd, q);
  938. if (retval)
  939. goto out_deallocate_sdma_queue;
  940. mqd = dqm->ops.get_mqd_manager(dqm,
  941. get_mqd_type_from_queue_type(q->properties.type));
  942. if (!mqd) {
  943. retval = -ENOMEM;
  944. goto out_deallocate_doorbell;
  945. }
  946. /*
  947. * Eviction state logic: we only mark active queues as evicted
  948. * to avoid the overhead of restoring inactive queues later
  949. */
  950. if (qpd->evicted)
  951. q->properties.is_evicted = (q->properties.queue_size > 0 &&
  952. q->properties.queue_percent > 0 &&
  953. q->properties.queue_address != 0);
  954. dqm->asic_ops.init_sdma_vm(dqm, q, qpd);
  955. q->properties.tba_addr = qpd->tba_addr;
  956. q->properties.tma_addr = qpd->tma_addr;
  957. retval = mqd->init_mqd(mqd, &q->mqd, &q->mqd_mem_obj,
  958. &q->gart_mqd_addr, &q->properties);
  959. if (retval)
  960. goto out_deallocate_doorbell;
  961. list_add(&q->list, &qpd->queues_list);
  962. qpd->queue_count++;
  963. if (q->properties.is_active) {
  964. dqm->queue_count++;
  965. retval = execute_queues_cpsch(dqm,
  966. KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0);
  967. }
  968. if (q->properties.type == KFD_QUEUE_TYPE_SDMA)
  969. dqm->sdma_queue_count++;
  970. /*
  971. * Unconditionally increment this counter, regardless of the queue's
  972. * type or whether the queue is active.
  973. */
  974. dqm->total_queue_count++;
  975. pr_debug("Total of %d queues are accountable so far\n",
  976. dqm->total_queue_count);
  977. mutex_unlock(&dqm->lock);
  978. return retval;
  979. out_deallocate_doorbell:
  980. deallocate_doorbell(qpd, q);
  981. out_deallocate_sdma_queue:
  982. if (q->properties.type == KFD_QUEUE_TYPE_SDMA)
  983. deallocate_sdma_queue(dqm, q->sdma_id);
  984. out_unlock:
  985. mutex_unlock(&dqm->lock);
  986. return retval;
  987. }
  988. int amdkfd_fence_wait_timeout(unsigned int *fence_addr,
  989. unsigned int fence_value,
  990. unsigned int timeout_ms)
  991. {
  992. unsigned long end_jiffies = msecs_to_jiffies(timeout_ms) + jiffies;
  993. while (*fence_addr != fence_value) {
  994. if (time_after(jiffies, end_jiffies)) {
  995. pr_err("qcm fence wait loop timeout expired\n");
  996. return -ETIME;
  997. }
  998. schedule();
  999. }
  1000. return 0;
  1001. }
  1002. static int unmap_sdma_queues(struct device_queue_manager *dqm,
  1003. unsigned int sdma_engine)
  1004. {
  1005. return pm_send_unmap_queue(&dqm->packets, KFD_QUEUE_TYPE_SDMA,
  1006. KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0, false,
  1007. sdma_engine);
  1008. }
  1009. /* dqm->lock mutex has to be locked before calling this function */
  1010. static int map_queues_cpsch(struct device_queue_manager *dqm)
  1011. {
  1012. int retval;
  1013. if (dqm->queue_count <= 0 || dqm->processes_count <= 0)
  1014. return 0;
  1015. if (dqm->active_runlist)
  1016. return 0;
  1017. retval = pm_send_runlist(&dqm->packets, &dqm->queues);
  1018. if (retval) {
  1019. pr_err("failed to execute runlist\n");
  1020. return retval;
  1021. }
  1022. dqm->active_runlist = true;
  1023. return retval;
  1024. }
  1025. /* dqm->lock mutex has to be locked before calling this function */
  1026. static int unmap_queues_cpsch(struct device_queue_manager *dqm,
  1027. enum kfd_unmap_queues_filter filter,
  1028. uint32_t filter_param)
  1029. {
  1030. int retval = 0;
  1031. if (!dqm->active_runlist)
  1032. return retval;
  1033. pr_debug("Before destroying queues, sdma queue count is : %u\n",
  1034. dqm->sdma_queue_count);
  1035. if (dqm->sdma_queue_count > 0) {
  1036. unmap_sdma_queues(dqm, 0);
  1037. unmap_sdma_queues(dqm, 1);
  1038. }
  1039. retval = pm_send_unmap_queue(&dqm->packets, KFD_QUEUE_TYPE_COMPUTE,
  1040. filter, filter_param, false, 0);
  1041. if (retval)
  1042. return retval;
  1043. *dqm->fence_addr = KFD_FENCE_INIT;
  1044. pm_send_query_status(&dqm->packets, dqm->fence_gpu_addr,
  1045. KFD_FENCE_COMPLETED);
  1046. /* should be timed out */
  1047. retval = amdkfd_fence_wait_timeout(dqm->fence_addr, KFD_FENCE_COMPLETED,
  1048. QUEUE_PREEMPT_DEFAULT_TIMEOUT_MS);
  1049. if (retval)
  1050. return retval;
  1051. pm_release_ib(&dqm->packets);
  1052. dqm->active_runlist = false;
  1053. return retval;
  1054. }
  1055. /* dqm->lock mutex has to be locked before calling this function */
  1056. static int execute_queues_cpsch(struct device_queue_manager *dqm,
  1057. enum kfd_unmap_queues_filter filter,
  1058. uint32_t filter_param)
  1059. {
  1060. int retval;
  1061. retval = unmap_queues_cpsch(dqm, filter, filter_param);
  1062. if (retval) {
  1063. pr_err("The cp might be in an unrecoverable state due to an unsuccessful queues preemption\n");
  1064. return retval;
  1065. }
  1066. return map_queues_cpsch(dqm);
  1067. }
  1068. static int destroy_queue_cpsch(struct device_queue_manager *dqm,
  1069. struct qcm_process_device *qpd,
  1070. struct queue *q)
  1071. {
  1072. int retval;
  1073. struct mqd_manager *mqd;
  1074. bool preempt_all_queues;
  1075. preempt_all_queues = false;
  1076. retval = 0;
  1077. /* remove queue from list to prevent rescheduling after preemption */
  1078. mutex_lock(&dqm->lock);
  1079. if (qpd->is_debug) {
  1080. /*
  1081. * error, currently we do not allow to destroy a queue
  1082. * of a currently debugged process
  1083. */
  1084. retval = -EBUSY;
  1085. goto failed_try_destroy_debugged_queue;
  1086. }
  1087. mqd = dqm->ops.get_mqd_manager(dqm,
  1088. get_mqd_type_from_queue_type(q->properties.type));
  1089. if (!mqd) {
  1090. retval = -ENOMEM;
  1091. goto failed;
  1092. }
  1093. deallocate_doorbell(qpd, q);
  1094. if (q->properties.type == KFD_QUEUE_TYPE_SDMA) {
  1095. dqm->sdma_queue_count--;
  1096. deallocate_sdma_queue(dqm, q->sdma_id);
  1097. }
  1098. list_del(&q->list);
  1099. qpd->queue_count--;
  1100. if (q->properties.is_active) {
  1101. dqm->queue_count--;
  1102. retval = execute_queues_cpsch(dqm,
  1103. KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0);
  1104. if (retval == -ETIME)
  1105. qpd->reset_wavefronts = true;
  1106. }
  1107. mqd->uninit_mqd(mqd, q->mqd, q->mqd_mem_obj);
  1108. /*
  1109. * Unconditionally decrement this counter, regardless of the queue's
  1110. * type
  1111. */
  1112. dqm->total_queue_count--;
  1113. pr_debug("Total of %d queues are accountable so far\n",
  1114. dqm->total_queue_count);
  1115. mutex_unlock(&dqm->lock);
  1116. return retval;
  1117. failed:
  1118. failed_try_destroy_debugged_queue:
  1119. mutex_unlock(&dqm->lock);
  1120. return retval;
  1121. }
  1122. /*
  1123. * Low bits must be 0000/FFFF as required by HW, high bits must be 0 to
  1124. * stay in user mode.
  1125. */
  1126. #define APE1_FIXED_BITS_MASK 0xFFFF80000000FFFFULL
  1127. /* APE1 limit is inclusive and 64K aligned. */
  1128. #define APE1_LIMIT_ALIGNMENT 0xFFFF
  1129. static bool set_cache_memory_policy(struct device_queue_manager *dqm,
  1130. struct qcm_process_device *qpd,
  1131. enum cache_policy default_policy,
  1132. enum cache_policy alternate_policy,
  1133. void __user *alternate_aperture_base,
  1134. uint64_t alternate_aperture_size)
  1135. {
  1136. bool retval = true;
  1137. if (!dqm->asic_ops.set_cache_memory_policy)
  1138. return retval;
  1139. mutex_lock(&dqm->lock);
  1140. if (alternate_aperture_size == 0) {
  1141. /* base > limit disables APE1 */
  1142. qpd->sh_mem_ape1_base = 1;
  1143. qpd->sh_mem_ape1_limit = 0;
  1144. } else {
  1145. /*
  1146. * In FSA64, APE1_Base[63:0] = { 16{SH_MEM_APE1_BASE[31]},
  1147. * SH_MEM_APE1_BASE[31:0], 0x0000 }
  1148. * APE1_Limit[63:0] = { 16{SH_MEM_APE1_LIMIT[31]},
  1149. * SH_MEM_APE1_LIMIT[31:0], 0xFFFF }
  1150. * Verify that the base and size parameters can be
  1151. * represented in this format and convert them.
  1152. * Additionally restrict APE1 to user-mode addresses.
  1153. */
  1154. uint64_t base = (uintptr_t)alternate_aperture_base;
  1155. uint64_t limit = base + alternate_aperture_size - 1;
  1156. if (limit <= base || (base & APE1_FIXED_BITS_MASK) != 0 ||
  1157. (limit & APE1_FIXED_BITS_MASK) != APE1_LIMIT_ALIGNMENT) {
  1158. retval = false;
  1159. goto out;
  1160. }
  1161. qpd->sh_mem_ape1_base = base >> 16;
  1162. qpd->sh_mem_ape1_limit = limit >> 16;
  1163. }
  1164. retval = dqm->asic_ops.set_cache_memory_policy(
  1165. dqm,
  1166. qpd,
  1167. default_policy,
  1168. alternate_policy,
  1169. alternate_aperture_base,
  1170. alternate_aperture_size);
  1171. if ((dqm->sched_policy == KFD_SCHED_POLICY_NO_HWS) && (qpd->vmid != 0))
  1172. program_sh_mem_settings(dqm, qpd);
  1173. pr_debug("sh_mem_config: 0x%x, ape1_base: 0x%x, ape1_limit: 0x%x\n",
  1174. qpd->sh_mem_config, qpd->sh_mem_ape1_base,
  1175. qpd->sh_mem_ape1_limit);
  1176. out:
  1177. mutex_unlock(&dqm->lock);
  1178. return retval;
  1179. }
  1180. static int set_trap_handler(struct device_queue_manager *dqm,
  1181. struct qcm_process_device *qpd,
  1182. uint64_t tba_addr,
  1183. uint64_t tma_addr)
  1184. {
  1185. uint64_t *tma;
  1186. if (dqm->dev->cwsr_enabled) {
  1187. /* Jump from CWSR trap handler to user trap */
  1188. tma = (uint64_t *)(qpd->cwsr_kaddr + KFD_CWSR_TMA_OFFSET);
  1189. tma[0] = tba_addr;
  1190. tma[1] = tma_addr;
  1191. } else {
  1192. qpd->tba_addr = tba_addr;
  1193. qpd->tma_addr = tma_addr;
  1194. }
  1195. return 0;
  1196. }
  1197. static int process_termination_nocpsch(struct device_queue_manager *dqm,
  1198. struct qcm_process_device *qpd)
  1199. {
  1200. struct queue *q, *next;
  1201. struct device_process_node *cur, *next_dpn;
  1202. int retval = 0;
  1203. mutex_lock(&dqm->lock);
  1204. /* Clear all user mode queues */
  1205. list_for_each_entry_safe(q, next, &qpd->queues_list, list) {
  1206. int ret;
  1207. ret = destroy_queue_nocpsch_locked(dqm, qpd, q);
  1208. if (ret)
  1209. retval = ret;
  1210. }
  1211. /* Unregister process */
  1212. list_for_each_entry_safe(cur, next_dpn, &dqm->queues, list) {
  1213. if (qpd == cur->qpd) {
  1214. list_del(&cur->list);
  1215. kfree(cur);
  1216. dqm->processes_count--;
  1217. break;
  1218. }
  1219. }
  1220. mutex_unlock(&dqm->lock);
  1221. return retval;
  1222. }
  1223. static int process_termination_cpsch(struct device_queue_manager *dqm,
  1224. struct qcm_process_device *qpd)
  1225. {
  1226. int retval;
  1227. struct queue *q, *next;
  1228. struct kernel_queue *kq, *kq_next;
  1229. struct mqd_manager *mqd;
  1230. struct device_process_node *cur, *next_dpn;
  1231. enum kfd_unmap_queues_filter filter =
  1232. KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES;
  1233. retval = 0;
  1234. mutex_lock(&dqm->lock);
  1235. /* Clean all kernel queues */
  1236. list_for_each_entry_safe(kq, kq_next, &qpd->priv_queue_list, list) {
  1237. list_del(&kq->list);
  1238. dqm->queue_count--;
  1239. qpd->is_debug = false;
  1240. dqm->total_queue_count--;
  1241. filter = KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES;
  1242. }
  1243. /* Clear all user mode queues */
  1244. list_for_each_entry(q, &qpd->queues_list, list) {
  1245. if (q->properties.type == KFD_QUEUE_TYPE_SDMA) {
  1246. dqm->sdma_queue_count--;
  1247. deallocate_sdma_queue(dqm, q->sdma_id);
  1248. }
  1249. if (q->properties.is_active)
  1250. dqm->queue_count--;
  1251. dqm->total_queue_count--;
  1252. }
  1253. /* Unregister process */
  1254. list_for_each_entry_safe(cur, next_dpn, &dqm->queues, list) {
  1255. if (qpd == cur->qpd) {
  1256. list_del(&cur->list);
  1257. kfree(cur);
  1258. dqm->processes_count--;
  1259. break;
  1260. }
  1261. }
  1262. retval = execute_queues_cpsch(dqm, filter, 0);
  1263. if (retval || qpd->reset_wavefronts) {
  1264. pr_warn("Resetting wave fronts (cpsch) on dev %p\n", dqm->dev);
  1265. dbgdev_wave_reset_wavefronts(dqm->dev, qpd->pqm->process);
  1266. qpd->reset_wavefronts = false;
  1267. }
  1268. /* lastly, free mqd resources */
  1269. list_for_each_entry_safe(q, next, &qpd->queues_list, list) {
  1270. mqd = dqm->ops.get_mqd_manager(dqm,
  1271. get_mqd_type_from_queue_type(q->properties.type));
  1272. if (!mqd) {
  1273. retval = -ENOMEM;
  1274. goto out;
  1275. }
  1276. list_del(&q->list);
  1277. qpd->queue_count--;
  1278. mqd->uninit_mqd(mqd, q->mqd, q->mqd_mem_obj);
  1279. }
  1280. out:
  1281. mutex_unlock(&dqm->lock);
  1282. return retval;
  1283. }
  1284. struct device_queue_manager *device_queue_manager_init(struct kfd_dev *dev)
  1285. {
  1286. struct device_queue_manager *dqm;
  1287. pr_debug("Loading device queue manager\n");
  1288. dqm = kzalloc(sizeof(*dqm), GFP_KERNEL);
  1289. if (!dqm)
  1290. return NULL;
  1291. switch (dev->device_info->asic_family) {
  1292. /* HWS is not available on Hawaii. */
  1293. case CHIP_HAWAII:
  1294. /* HWS depends on CWSR for timely dequeue. CWSR is not
  1295. * available on Tonga.
  1296. *
  1297. * FIXME: This argument also applies to Kaveri.
  1298. */
  1299. case CHIP_TONGA:
  1300. dqm->sched_policy = KFD_SCHED_POLICY_NO_HWS;
  1301. break;
  1302. default:
  1303. dqm->sched_policy = sched_policy;
  1304. break;
  1305. }
  1306. dqm->dev = dev;
  1307. switch (dqm->sched_policy) {
  1308. case KFD_SCHED_POLICY_HWS:
  1309. case KFD_SCHED_POLICY_HWS_NO_OVERSUBSCRIPTION:
  1310. /* initialize dqm for cp scheduling */
  1311. dqm->ops.create_queue = create_queue_cpsch;
  1312. dqm->ops.initialize = initialize_cpsch;
  1313. dqm->ops.start = start_cpsch;
  1314. dqm->ops.stop = stop_cpsch;
  1315. dqm->ops.destroy_queue = destroy_queue_cpsch;
  1316. dqm->ops.update_queue = update_queue;
  1317. dqm->ops.get_mqd_manager = get_mqd_manager;
  1318. dqm->ops.register_process = register_process;
  1319. dqm->ops.unregister_process = unregister_process;
  1320. dqm->ops.uninitialize = uninitialize;
  1321. dqm->ops.create_kernel_queue = create_kernel_queue_cpsch;
  1322. dqm->ops.destroy_kernel_queue = destroy_kernel_queue_cpsch;
  1323. dqm->ops.set_cache_memory_policy = set_cache_memory_policy;
  1324. dqm->ops.set_trap_handler = set_trap_handler;
  1325. dqm->ops.process_termination = process_termination_cpsch;
  1326. dqm->ops.evict_process_queues = evict_process_queues_cpsch;
  1327. dqm->ops.restore_process_queues = restore_process_queues_cpsch;
  1328. break;
  1329. case KFD_SCHED_POLICY_NO_HWS:
  1330. /* initialize dqm for no cp scheduling */
  1331. dqm->ops.start = start_nocpsch;
  1332. dqm->ops.stop = stop_nocpsch;
  1333. dqm->ops.create_queue = create_queue_nocpsch;
  1334. dqm->ops.destroy_queue = destroy_queue_nocpsch;
  1335. dqm->ops.update_queue = update_queue;
  1336. dqm->ops.get_mqd_manager = get_mqd_manager;
  1337. dqm->ops.register_process = register_process;
  1338. dqm->ops.unregister_process = unregister_process;
  1339. dqm->ops.initialize = initialize_nocpsch;
  1340. dqm->ops.uninitialize = uninitialize;
  1341. dqm->ops.set_cache_memory_policy = set_cache_memory_policy;
  1342. dqm->ops.set_trap_handler = set_trap_handler;
  1343. dqm->ops.process_termination = process_termination_nocpsch;
  1344. dqm->ops.evict_process_queues = evict_process_queues_nocpsch;
  1345. dqm->ops.restore_process_queues =
  1346. restore_process_queues_nocpsch;
  1347. break;
  1348. default:
  1349. pr_err("Invalid scheduling policy %d\n", dqm->sched_policy);
  1350. goto out_free;
  1351. }
  1352. switch (dev->device_info->asic_family) {
  1353. case CHIP_CARRIZO:
  1354. device_queue_manager_init_vi(&dqm->asic_ops);
  1355. break;
  1356. case CHIP_KAVERI:
  1357. device_queue_manager_init_cik(&dqm->asic_ops);
  1358. break;
  1359. case CHIP_HAWAII:
  1360. device_queue_manager_init_cik_hawaii(&dqm->asic_ops);
  1361. break;
  1362. case CHIP_TONGA:
  1363. case CHIP_FIJI:
  1364. case CHIP_POLARIS10:
  1365. case CHIP_POLARIS11:
  1366. device_queue_manager_init_vi_tonga(&dqm->asic_ops);
  1367. break;
  1368. case CHIP_VEGA10:
  1369. case CHIP_RAVEN:
  1370. device_queue_manager_init_v9(&dqm->asic_ops);
  1371. break;
  1372. default:
  1373. WARN(1, "Unexpected ASIC family %u",
  1374. dev->device_info->asic_family);
  1375. goto out_free;
  1376. }
  1377. if (!dqm->ops.initialize(dqm))
  1378. return dqm;
  1379. out_free:
  1380. kfree(dqm);
  1381. return NULL;
  1382. }
  1383. void device_queue_manager_uninit(struct device_queue_manager *dqm)
  1384. {
  1385. dqm->ops.uninitialize(dqm);
  1386. kfree(dqm);
  1387. }
  1388. #if defined(CONFIG_DEBUG_FS)
  1389. static void seq_reg_dump(struct seq_file *m,
  1390. uint32_t (*dump)[2], uint32_t n_regs)
  1391. {
  1392. uint32_t i, count;
  1393. for (i = 0, count = 0; i < n_regs; i++) {
  1394. if (count == 0 ||
  1395. dump[i-1][0] + sizeof(uint32_t) != dump[i][0]) {
  1396. seq_printf(m, "%s %08x: %08x",
  1397. i ? "\n" : "",
  1398. dump[i][0], dump[i][1]);
  1399. count = 7;
  1400. } else {
  1401. seq_printf(m, " %08x", dump[i][1]);
  1402. count--;
  1403. }
  1404. }
  1405. seq_puts(m, "\n");
  1406. }
  1407. int dqm_debugfs_hqds(struct seq_file *m, void *data)
  1408. {
  1409. struct device_queue_manager *dqm = data;
  1410. uint32_t (*dump)[2], n_regs;
  1411. int pipe, queue;
  1412. int r = 0;
  1413. r = dqm->dev->kfd2kgd->hqd_dump(dqm->dev->kgd,
  1414. KFD_CIK_HIQ_PIPE, KFD_CIK_HIQ_QUEUE, &dump, &n_regs);
  1415. if (!r) {
  1416. seq_printf(m, " HIQ on MEC %d Pipe %d Queue %d\n",
  1417. KFD_CIK_HIQ_PIPE/get_pipes_per_mec(dqm)+1,
  1418. KFD_CIK_HIQ_PIPE%get_pipes_per_mec(dqm),
  1419. KFD_CIK_HIQ_QUEUE);
  1420. seq_reg_dump(m, dump, n_regs);
  1421. kfree(dump);
  1422. }
  1423. for (pipe = 0; pipe < get_pipes_per_mec(dqm); pipe++) {
  1424. int pipe_offset = pipe * get_queues_per_pipe(dqm);
  1425. for (queue = 0; queue < get_queues_per_pipe(dqm); queue++) {
  1426. if (!test_bit(pipe_offset + queue,
  1427. dqm->dev->shared_resources.queue_bitmap))
  1428. continue;
  1429. r = dqm->dev->kfd2kgd->hqd_dump(
  1430. dqm->dev->kgd, pipe, queue, &dump, &n_regs);
  1431. if (r)
  1432. break;
  1433. seq_printf(m, " CP Pipe %d, Queue %d\n",
  1434. pipe, queue);
  1435. seq_reg_dump(m, dump, n_regs);
  1436. kfree(dump);
  1437. }
  1438. }
  1439. for (pipe = 0; pipe < CIK_SDMA_ENGINE_NUM; pipe++) {
  1440. for (queue = 0; queue < CIK_SDMA_QUEUES_PER_ENGINE; queue++) {
  1441. r = dqm->dev->kfd2kgd->hqd_sdma_dump(
  1442. dqm->dev->kgd, pipe, queue, &dump, &n_regs);
  1443. if (r)
  1444. break;
  1445. seq_printf(m, " SDMA Engine %d, RLC %d\n",
  1446. pipe, queue);
  1447. seq_reg_dump(m, dump, n_regs);
  1448. kfree(dump);
  1449. }
  1450. }
  1451. return r;
  1452. }
  1453. #endif