clk.h 7.0 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. #ifndef __MACH_IMX_CLK_H
  3. #define __MACH_IMX_CLK_H
  4. #include <linux/spinlock.h>
  5. #include <linux/clk-provider.h>
  6. extern spinlock_t imx_ccm_lock;
  7. void imx_check_clocks(struct clk *clks[], unsigned int count);
  8. void imx_register_uart_clocks(struct clk ** const clks[]);
  9. extern void imx_cscmr1_fixup(u32 *val);
  10. enum imx_pllv1_type {
  11. IMX_PLLV1_IMX1,
  12. IMX_PLLV1_IMX21,
  13. IMX_PLLV1_IMX25,
  14. IMX_PLLV1_IMX27,
  15. IMX_PLLV1_IMX31,
  16. IMX_PLLV1_IMX35,
  17. };
  18. struct clk *imx_clk_pllv1(enum imx_pllv1_type type, const char *name,
  19. const char *parent, void __iomem *base);
  20. struct clk *imx_clk_pllv2(const char *name, const char *parent,
  21. void __iomem *base);
  22. enum imx_pllv3_type {
  23. IMX_PLLV3_GENERIC,
  24. IMX_PLLV3_SYS,
  25. IMX_PLLV3_USB,
  26. IMX_PLLV3_USB_VF610,
  27. IMX_PLLV3_AV,
  28. IMX_PLLV3_ENET,
  29. IMX_PLLV3_ENET_IMX7,
  30. IMX_PLLV3_SYS_VF610,
  31. IMX_PLLV3_DDR_IMX7,
  32. };
  33. struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,
  34. const char *parent_name, void __iomem *base, u32 div_mask);
  35. struct clk *clk_register_gate2(struct device *dev, const char *name,
  36. const char *parent_name, unsigned long flags,
  37. void __iomem *reg, u8 bit_idx, u8 cgr_val,
  38. u8 clk_gate_flags, spinlock_t *lock,
  39. unsigned int *share_count);
  40. struct clk * imx_obtain_fixed_clock(
  41. const char *name, unsigned long rate);
  42. struct clk *imx_clk_gate_exclusive(const char *name, const char *parent,
  43. void __iomem *reg, u8 shift, u32 exclusive_mask);
  44. struct clk *imx_clk_pfd(const char *name, const char *parent_name,
  45. void __iomem *reg, u8 idx);
  46. struct clk *imx_clk_busy_divider(const char *name, const char *parent_name,
  47. void __iomem *reg, u8 shift, u8 width,
  48. void __iomem *busy_reg, u8 busy_shift);
  49. struct clk *imx_clk_busy_mux(const char *name, void __iomem *reg, u8 shift,
  50. u8 width, void __iomem *busy_reg, u8 busy_shift,
  51. const char **parent_names, int num_parents);
  52. struct clk *imx_clk_fixup_divider(const char *name, const char *parent,
  53. void __iomem *reg, u8 shift, u8 width,
  54. void (*fixup)(u32 *val));
  55. struct clk *imx_clk_fixup_mux(const char *name, void __iomem *reg,
  56. u8 shift, u8 width, const char **parents,
  57. int num_parents, void (*fixup)(u32 *val));
  58. static inline struct clk *imx_clk_fixed(const char *name, int rate)
  59. {
  60. return clk_register_fixed_rate(NULL, name, NULL, 0, rate);
  61. }
  62. static inline struct clk *imx_clk_mux_ldb(const char *name, void __iomem *reg,
  63. u8 shift, u8 width, const char **parents, int num_parents)
  64. {
  65. return clk_register_mux(NULL, name, parents, num_parents,
  66. CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT, reg,
  67. shift, width, CLK_MUX_READ_ONLY, &imx_ccm_lock);
  68. }
  69. static inline struct clk *imx_clk_fixed_factor(const char *name,
  70. const char *parent, unsigned int mult, unsigned int div)
  71. {
  72. return clk_register_fixed_factor(NULL, name, parent,
  73. CLK_SET_RATE_PARENT, mult, div);
  74. }
  75. static inline struct clk *imx_clk_divider(const char *name, const char *parent,
  76. void __iomem *reg, u8 shift, u8 width)
  77. {
  78. return clk_register_divider(NULL, name, parent, CLK_SET_RATE_PARENT,
  79. reg, shift, width, 0, &imx_ccm_lock);
  80. }
  81. static inline struct clk *imx_clk_divider_flags(const char *name,
  82. const char *parent, void __iomem *reg, u8 shift, u8 width,
  83. unsigned long flags)
  84. {
  85. return clk_register_divider(NULL, name, parent, flags,
  86. reg, shift, width, 0, &imx_ccm_lock);
  87. }
  88. static inline struct clk *imx_clk_divider2(const char *name, const char *parent,
  89. void __iomem *reg, u8 shift, u8 width)
  90. {
  91. return clk_register_divider(NULL, name, parent,
  92. CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
  93. reg, shift, width, 0, &imx_ccm_lock);
  94. }
  95. static inline struct clk *imx_clk_gate(const char *name, const char *parent,
  96. void __iomem *reg, u8 shift)
  97. {
  98. return clk_register_gate(NULL, name, parent, CLK_SET_RATE_PARENT, reg,
  99. shift, 0, &imx_ccm_lock);
  100. }
  101. static inline struct clk *imx_clk_gate_flags(const char *name, const char *parent,
  102. void __iomem *reg, u8 shift, unsigned long flags)
  103. {
  104. return clk_register_gate(NULL, name, parent, flags | CLK_SET_RATE_PARENT, reg,
  105. shift, 0, &imx_ccm_lock);
  106. }
  107. static inline struct clk *imx_clk_gate_dis(const char *name, const char *parent,
  108. void __iomem *reg, u8 shift)
  109. {
  110. return clk_register_gate(NULL, name, parent, CLK_SET_RATE_PARENT, reg,
  111. shift, CLK_GATE_SET_TO_DISABLE, &imx_ccm_lock);
  112. }
  113. static inline struct clk *imx_clk_gate2(const char *name, const char *parent,
  114. void __iomem *reg, u8 shift)
  115. {
  116. return clk_register_gate2(NULL, name, parent, CLK_SET_RATE_PARENT, reg,
  117. shift, 0x3, 0, &imx_ccm_lock, NULL);
  118. }
  119. static inline struct clk *imx_clk_gate2_flags(const char *name, const char *parent,
  120. void __iomem *reg, u8 shift, unsigned long flags)
  121. {
  122. return clk_register_gate2(NULL, name, parent, flags | CLK_SET_RATE_PARENT, reg,
  123. shift, 0x3, 0, &imx_ccm_lock, NULL);
  124. }
  125. static inline struct clk *imx_clk_gate2_shared(const char *name,
  126. const char *parent, void __iomem *reg, u8 shift,
  127. unsigned int *share_count)
  128. {
  129. return clk_register_gate2(NULL, name, parent, CLK_SET_RATE_PARENT, reg,
  130. shift, 0x3, 0, &imx_ccm_lock, share_count);
  131. }
  132. static inline struct clk *imx_clk_gate2_shared2(const char *name,
  133. const char *parent, void __iomem *reg, u8 shift,
  134. unsigned int *share_count)
  135. {
  136. return clk_register_gate2(NULL, name, parent, CLK_SET_RATE_PARENT |
  137. CLK_OPS_PARENT_ENABLE, reg, shift, 0x3, 0,
  138. &imx_ccm_lock, share_count);
  139. }
  140. static inline struct clk *imx_clk_gate2_cgr(const char *name,
  141. const char *parent, void __iomem *reg, u8 shift, u8 cgr_val)
  142. {
  143. return clk_register_gate2(NULL, name, parent, CLK_SET_RATE_PARENT, reg,
  144. shift, cgr_val, 0, &imx_ccm_lock, NULL);
  145. }
  146. static inline struct clk *imx_clk_gate3(const char *name, const char *parent,
  147. void __iomem *reg, u8 shift)
  148. {
  149. return clk_register_gate(NULL, name, parent,
  150. CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
  151. reg, shift, 0, &imx_ccm_lock);
  152. }
  153. static inline struct clk *imx_clk_gate4(const char *name, const char *parent,
  154. void __iomem *reg, u8 shift)
  155. {
  156. return clk_register_gate2(NULL, name, parent,
  157. CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
  158. reg, shift, 0x3, 0, &imx_ccm_lock, NULL);
  159. }
  160. static inline struct clk *imx_clk_mux(const char *name, void __iomem *reg,
  161. u8 shift, u8 width, const char **parents, int num_parents)
  162. {
  163. return clk_register_mux(NULL, name, parents, num_parents,
  164. CLK_SET_RATE_NO_REPARENT, reg, shift,
  165. width, 0, &imx_ccm_lock);
  166. }
  167. static inline struct clk *imx_clk_mux2(const char *name, void __iomem *reg,
  168. u8 shift, u8 width, const char **parents, int num_parents)
  169. {
  170. return clk_register_mux(NULL, name, parents, num_parents,
  171. CLK_SET_RATE_NO_REPARENT | CLK_OPS_PARENT_ENABLE,
  172. reg, shift, width, 0, &imx_ccm_lock);
  173. }
  174. static inline struct clk *imx_clk_mux_flags(const char *name,
  175. void __iomem *reg, u8 shift, u8 width, const char **parents,
  176. int num_parents, unsigned long flags)
  177. {
  178. return clk_register_mux(NULL, name, parents, num_parents,
  179. flags | CLK_SET_RATE_NO_REPARENT, reg, shift, width, 0,
  180. &imx_ccm_lock);
  181. }
  182. struct clk *imx_clk_cpu(const char *name, const char *parent_name,
  183. struct clk *div, struct clk *mux, struct clk *pll,
  184. struct clk *step);
  185. #endif