eeh.c 48 KB

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  1. /*
  2. * Copyright IBM Corporation 2001, 2005, 2006
  3. * Copyright Dave Engebretsen & Todd Inglett 2001
  4. * Copyright Linas Vepstas 2005, 2006
  5. * Copyright 2001-2012 IBM Corporation.
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License as published by
  9. * the Free Software Foundation; either version 2 of the License, or
  10. * (at your option) any later version.
  11. *
  12. * This program is distributed in the hope that it will be useful,
  13. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15. * GNU General Public License for more details.
  16. *
  17. * You should have received a copy of the GNU General Public License
  18. * along with this program; if not, write to the Free Software
  19. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  20. *
  21. * Please address comments and feedback to Linas Vepstas <linas@austin.ibm.com>
  22. */
  23. #include <linux/delay.h>
  24. #include <linux/sched.h>
  25. #include <linux/init.h>
  26. #include <linux/list.h>
  27. #include <linux/pci.h>
  28. #include <linux/iommu.h>
  29. #include <linux/proc_fs.h>
  30. #include <linux/rbtree.h>
  31. #include <linux/reboot.h>
  32. #include <linux/seq_file.h>
  33. #include <linux/spinlock.h>
  34. #include <linux/export.h>
  35. #include <linux/of.h>
  36. #include <linux/atomic.h>
  37. #include <asm/debugfs.h>
  38. #include <asm/eeh.h>
  39. #include <asm/eeh_event.h>
  40. #include <asm/io.h>
  41. #include <asm/iommu.h>
  42. #include <asm/machdep.h>
  43. #include <asm/ppc-pci.h>
  44. #include <asm/rtas.h>
  45. #include <asm/pte-walk.h>
  46. /** Overview:
  47. * EEH, or "Enhanced Error Handling" is a PCI bridge technology for
  48. * dealing with PCI bus errors that can't be dealt with within the
  49. * usual PCI framework, except by check-stopping the CPU. Systems
  50. * that are designed for high-availability/reliability cannot afford
  51. * to crash due to a "mere" PCI error, thus the need for EEH.
  52. * An EEH-capable bridge operates by converting a detected error
  53. * into a "slot freeze", taking the PCI adapter off-line, making
  54. * the slot behave, from the OS'es point of view, as if the slot
  55. * were "empty": all reads return 0xff's and all writes are silently
  56. * ignored. EEH slot isolation events can be triggered by parity
  57. * errors on the address or data busses (e.g. during posted writes),
  58. * which in turn might be caused by low voltage on the bus, dust,
  59. * vibration, humidity, radioactivity or plain-old failed hardware.
  60. *
  61. * Note, however, that one of the leading causes of EEH slot
  62. * freeze events are buggy device drivers, buggy device microcode,
  63. * or buggy device hardware. This is because any attempt by the
  64. * device to bus-master data to a memory address that is not
  65. * assigned to the device will trigger a slot freeze. (The idea
  66. * is to prevent devices-gone-wild from corrupting system memory).
  67. * Buggy hardware/drivers will have a miserable time co-existing
  68. * with EEH.
  69. *
  70. * Ideally, a PCI device driver, when suspecting that an isolation
  71. * event has occurred (e.g. by reading 0xff's), will then ask EEH
  72. * whether this is the case, and then take appropriate steps to
  73. * reset the PCI slot, the PCI device, and then resume operations.
  74. * However, until that day, the checking is done here, with the
  75. * eeh_check_failure() routine embedded in the MMIO macros. If
  76. * the slot is found to be isolated, an "EEH Event" is synthesized
  77. * and sent out for processing.
  78. */
  79. /* If a device driver keeps reading an MMIO register in an interrupt
  80. * handler after a slot isolation event, it might be broken.
  81. * This sets the threshold for how many read attempts we allow
  82. * before printing an error message.
  83. */
  84. #define EEH_MAX_FAILS 2100000
  85. /* Time to wait for a PCI slot to report status, in milliseconds */
  86. #define PCI_BUS_RESET_WAIT_MSEC (5*60*1000)
  87. /*
  88. * EEH probe mode support, which is part of the flags,
  89. * is to support multiple platforms for EEH. Some platforms
  90. * like pSeries do PCI emunation based on device tree.
  91. * However, other platforms like powernv probe PCI devices
  92. * from hardware. The flag is used to distinguish that.
  93. * In addition, struct eeh_ops::probe would be invoked for
  94. * particular OF node or PCI device so that the corresponding
  95. * PE would be created there.
  96. */
  97. int eeh_subsystem_flags;
  98. EXPORT_SYMBOL(eeh_subsystem_flags);
  99. /*
  100. * EEH allowed maximal frozen times. If one particular PE's
  101. * frozen count in last hour exceeds this limit, the PE will
  102. * be forced to be offline permanently.
  103. */
  104. int eeh_max_freezes = 5;
  105. /* Platform dependent EEH operations */
  106. struct eeh_ops *eeh_ops = NULL;
  107. /* Lock to avoid races due to multiple reports of an error */
  108. DEFINE_RAW_SPINLOCK(confirm_error_lock);
  109. EXPORT_SYMBOL_GPL(confirm_error_lock);
  110. /* Lock to protect passed flags */
  111. static DEFINE_MUTEX(eeh_dev_mutex);
  112. /* Buffer for reporting pci register dumps. Its here in BSS, and
  113. * not dynamically alloced, so that it ends up in RMO where RTAS
  114. * can access it.
  115. */
  116. #define EEH_PCI_REGS_LOG_LEN 8192
  117. static unsigned char pci_regs_buf[EEH_PCI_REGS_LOG_LEN];
  118. /*
  119. * The struct is used to maintain the EEH global statistic
  120. * information. Besides, the EEH global statistics will be
  121. * exported to user space through procfs
  122. */
  123. struct eeh_stats {
  124. u64 no_device; /* PCI device not found */
  125. u64 no_dn; /* OF node not found */
  126. u64 no_cfg_addr; /* Config address not found */
  127. u64 ignored_check; /* EEH check skipped */
  128. u64 total_mmio_ffs; /* Total EEH checks */
  129. u64 false_positives; /* Unnecessary EEH checks */
  130. u64 slot_resets; /* PE reset */
  131. };
  132. static struct eeh_stats eeh_stats;
  133. static int __init eeh_setup(char *str)
  134. {
  135. if (!strcmp(str, "off"))
  136. eeh_add_flag(EEH_FORCE_DISABLED);
  137. else if (!strcmp(str, "early_log"))
  138. eeh_add_flag(EEH_EARLY_DUMP_LOG);
  139. return 1;
  140. }
  141. __setup("eeh=", eeh_setup);
  142. /*
  143. * This routine captures assorted PCI configuration space data
  144. * for the indicated PCI device, and puts them into a buffer
  145. * for RTAS error logging.
  146. */
  147. static size_t eeh_dump_dev_log(struct eeh_dev *edev, char *buf, size_t len)
  148. {
  149. struct pci_dn *pdn = eeh_dev_to_pdn(edev);
  150. u32 cfg;
  151. int cap, i;
  152. int n = 0, l = 0;
  153. char buffer[128];
  154. n += scnprintf(buf+n, len-n, "%04x:%02x:%02x.%01x\n",
  155. pdn->phb->global_number, pdn->busno,
  156. PCI_SLOT(pdn->devfn), PCI_FUNC(pdn->devfn));
  157. pr_warn("EEH: of node=%04x:%02x:%02x.%01x\n",
  158. pdn->phb->global_number, pdn->busno,
  159. PCI_SLOT(pdn->devfn), PCI_FUNC(pdn->devfn));
  160. eeh_ops->read_config(pdn, PCI_VENDOR_ID, 4, &cfg);
  161. n += scnprintf(buf+n, len-n, "dev/vend:%08x\n", cfg);
  162. pr_warn("EEH: PCI device/vendor: %08x\n", cfg);
  163. eeh_ops->read_config(pdn, PCI_COMMAND, 4, &cfg);
  164. n += scnprintf(buf+n, len-n, "cmd/stat:%x\n", cfg);
  165. pr_warn("EEH: PCI cmd/status register: %08x\n", cfg);
  166. /* Gather bridge-specific registers */
  167. if (edev->mode & EEH_DEV_BRIDGE) {
  168. eeh_ops->read_config(pdn, PCI_SEC_STATUS, 2, &cfg);
  169. n += scnprintf(buf+n, len-n, "sec stat:%x\n", cfg);
  170. pr_warn("EEH: Bridge secondary status: %04x\n", cfg);
  171. eeh_ops->read_config(pdn, PCI_BRIDGE_CONTROL, 2, &cfg);
  172. n += scnprintf(buf+n, len-n, "brdg ctl:%x\n", cfg);
  173. pr_warn("EEH: Bridge control: %04x\n", cfg);
  174. }
  175. /* Dump out the PCI-X command and status regs */
  176. cap = edev->pcix_cap;
  177. if (cap) {
  178. eeh_ops->read_config(pdn, cap, 4, &cfg);
  179. n += scnprintf(buf+n, len-n, "pcix-cmd:%x\n", cfg);
  180. pr_warn("EEH: PCI-X cmd: %08x\n", cfg);
  181. eeh_ops->read_config(pdn, cap+4, 4, &cfg);
  182. n += scnprintf(buf+n, len-n, "pcix-stat:%x\n", cfg);
  183. pr_warn("EEH: PCI-X status: %08x\n", cfg);
  184. }
  185. /* If PCI-E capable, dump PCI-E cap 10 */
  186. cap = edev->pcie_cap;
  187. if (cap) {
  188. n += scnprintf(buf+n, len-n, "pci-e cap10:\n");
  189. pr_warn("EEH: PCI-E capabilities and status follow:\n");
  190. for (i=0; i<=8; i++) {
  191. eeh_ops->read_config(pdn, cap+4*i, 4, &cfg);
  192. n += scnprintf(buf+n, len-n, "%02x:%x\n", 4*i, cfg);
  193. if ((i % 4) == 0) {
  194. if (i != 0)
  195. pr_warn("%s\n", buffer);
  196. l = scnprintf(buffer, sizeof(buffer),
  197. "EEH: PCI-E %02x: %08x ",
  198. 4*i, cfg);
  199. } else {
  200. l += scnprintf(buffer+l, sizeof(buffer)-l,
  201. "%08x ", cfg);
  202. }
  203. }
  204. pr_warn("%s\n", buffer);
  205. }
  206. /* If AER capable, dump it */
  207. cap = edev->aer_cap;
  208. if (cap) {
  209. n += scnprintf(buf+n, len-n, "pci-e AER:\n");
  210. pr_warn("EEH: PCI-E AER capability register set follows:\n");
  211. for (i=0; i<=13; i++) {
  212. eeh_ops->read_config(pdn, cap+4*i, 4, &cfg);
  213. n += scnprintf(buf+n, len-n, "%02x:%x\n", 4*i, cfg);
  214. if ((i % 4) == 0) {
  215. if (i != 0)
  216. pr_warn("%s\n", buffer);
  217. l = scnprintf(buffer, sizeof(buffer),
  218. "EEH: PCI-E AER %02x: %08x ",
  219. 4*i, cfg);
  220. } else {
  221. l += scnprintf(buffer+l, sizeof(buffer)-l,
  222. "%08x ", cfg);
  223. }
  224. }
  225. pr_warn("%s\n", buffer);
  226. }
  227. return n;
  228. }
  229. static void *eeh_dump_pe_log(struct eeh_pe *pe, void *flag)
  230. {
  231. struct eeh_dev *edev, *tmp;
  232. size_t *plen = flag;
  233. eeh_pe_for_each_dev(pe, edev, tmp)
  234. *plen += eeh_dump_dev_log(edev, pci_regs_buf + *plen,
  235. EEH_PCI_REGS_LOG_LEN - *plen);
  236. return NULL;
  237. }
  238. /**
  239. * eeh_slot_error_detail - Generate combined log including driver log and error log
  240. * @pe: EEH PE
  241. * @severity: temporary or permanent error log
  242. *
  243. * This routine should be called to generate the combined log, which
  244. * is comprised of driver log and error log. The driver log is figured
  245. * out from the config space of the corresponding PCI device, while
  246. * the error log is fetched through platform dependent function call.
  247. */
  248. void eeh_slot_error_detail(struct eeh_pe *pe, int severity)
  249. {
  250. size_t loglen = 0;
  251. /*
  252. * When the PHB is fenced or dead, it's pointless to collect
  253. * the data from PCI config space because it should return
  254. * 0xFF's. For ER, we still retrieve the data from the PCI
  255. * config space.
  256. *
  257. * For pHyp, we have to enable IO for log retrieval. Otherwise,
  258. * 0xFF's is always returned from PCI config space.
  259. *
  260. * When the @severity is EEH_LOG_PERM, the PE is going to be
  261. * removed. Prior to that, the drivers for devices included in
  262. * the PE will be closed. The drivers rely on working IO path
  263. * to bring the devices to quiet state. Otherwise, PCI traffic
  264. * from those devices after they are removed is like to cause
  265. * another unexpected EEH error.
  266. */
  267. if (!(pe->type & EEH_PE_PHB)) {
  268. if (eeh_has_flag(EEH_ENABLE_IO_FOR_LOG) ||
  269. severity == EEH_LOG_PERM)
  270. eeh_pci_enable(pe, EEH_OPT_THAW_MMIO);
  271. /*
  272. * The config space of some PCI devices can't be accessed
  273. * when their PEs are in frozen state. Otherwise, fenced
  274. * PHB might be seen. Those PEs are identified with flag
  275. * EEH_PE_CFG_RESTRICTED, indicating EEH_PE_CFG_BLOCKED
  276. * is set automatically when the PE is put to EEH_PE_ISOLATED.
  277. *
  278. * Restoring BARs possibly triggers PCI config access in
  279. * (OPAL) firmware and then causes fenced PHB. If the
  280. * PCI config is blocked with flag EEH_PE_CFG_BLOCKED, it's
  281. * pointless to restore BARs and dump config space.
  282. */
  283. eeh_ops->configure_bridge(pe);
  284. if (!(pe->state & EEH_PE_CFG_BLOCKED)) {
  285. eeh_pe_restore_bars(pe);
  286. pci_regs_buf[0] = 0;
  287. eeh_pe_traverse(pe, eeh_dump_pe_log, &loglen);
  288. }
  289. }
  290. eeh_ops->get_log(pe, severity, pci_regs_buf, loglen);
  291. }
  292. /**
  293. * eeh_token_to_phys - Convert EEH address token to phys address
  294. * @token: I/O token, should be address in the form 0xA....
  295. *
  296. * This routine should be called to convert virtual I/O address
  297. * to physical one.
  298. */
  299. static inline unsigned long eeh_token_to_phys(unsigned long token)
  300. {
  301. pte_t *ptep;
  302. unsigned long pa;
  303. int hugepage_shift;
  304. /*
  305. * We won't find hugepages here(this is iomem). Hence we are not
  306. * worried about _PAGE_SPLITTING/collapse. Also we will not hit
  307. * page table free, because of init_mm.
  308. */
  309. ptep = find_init_mm_pte(token, &hugepage_shift);
  310. if (!ptep)
  311. return token;
  312. WARN_ON(hugepage_shift);
  313. pa = pte_pfn(*ptep) << PAGE_SHIFT;
  314. return pa | (token & (PAGE_SIZE-1));
  315. }
  316. /*
  317. * On PowerNV platform, we might already have fenced PHB there.
  318. * For that case, it's meaningless to recover frozen PE. Intead,
  319. * We have to handle fenced PHB firstly.
  320. */
  321. static int eeh_phb_check_failure(struct eeh_pe *pe)
  322. {
  323. struct eeh_pe *phb_pe;
  324. unsigned long flags;
  325. int ret;
  326. if (!eeh_has_flag(EEH_PROBE_MODE_DEV))
  327. return -EPERM;
  328. /* Find the PHB PE */
  329. phb_pe = eeh_phb_pe_get(pe->phb);
  330. if (!phb_pe) {
  331. pr_warn("%s Can't find PE for PHB#%x\n",
  332. __func__, pe->phb->global_number);
  333. return -EEXIST;
  334. }
  335. /* If the PHB has been in problematic state */
  336. eeh_serialize_lock(&flags);
  337. if (phb_pe->state & EEH_PE_ISOLATED) {
  338. ret = 0;
  339. goto out;
  340. }
  341. /* Check PHB state */
  342. ret = eeh_ops->get_state(phb_pe, NULL);
  343. if ((ret < 0) ||
  344. (ret == EEH_STATE_NOT_SUPPORT) || eeh_state_active(ret)) {
  345. ret = 0;
  346. goto out;
  347. }
  348. /* Isolate the PHB and send event */
  349. eeh_pe_state_mark(phb_pe, EEH_PE_ISOLATED);
  350. eeh_serialize_unlock(flags);
  351. pr_err("EEH: PHB#%x failure detected, location: %s\n",
  352. phb_pe->phb->global_number, eeh_pe_loc_get(phb_pe));
  353. dump_stack();
  354. eeh_send_failure_event(phb_pe);
  355. return 1;
  356. out:
  357. eeh_serialize_unlock(flags);
  358. return ret;
  359. }
  360. /**
  361. * eeh_dev_check_failure - Check if all 1's data is due to EEH slot freeze
  362. * @edev: eeh device
  363. *
  364. * Check for an EEH failure for the given device node. Call this
  365. * routine if the result of a read was all 0xff's and you want to
  366. * find out if this is due to an EEH slot freeze. This routine
  367. * will query firmware for the EEH status.
  368. *
  369. * Returns 0 if there has not been an EEH error; otherwise returns
  370. * a non-zero value and queues up a slot isolation event notification.
  371. *
  372. * It is safe to call this routine in an interrupt context.
  373. */
  374. int eeh_dev_check_failure(struct eeh_dev *edev)
  375. {
  376. int ret;
  377. unsigned long flags;
  378. struct device_node *dn;
  379. struct pci_dev *dev;
  380. struct eeh_pe *pe, *parent_pe, *phb_pe;
  381. int rc = 0;
  382. const char *location = NULL;
  383. eeh_stats.total_mmio_ffs++;
  384. if (!eeh_enabled())
  385. return 0;
  386. if (!edev) {
  387. eeh_stats.no_dn++;
  388. return 0;
  389. }
  390. dev = eeh_dev_to_pci_dev(edev);
  391. pe = eeh_dev_to_pe(edev);
  392. /* Access to IO BARs might get this far and still not want checking. */
  393. if (!pe) {
  394. eeh_stats.ignored_check++;
  395. pr_debug("EEH: Ignored check for %s\n",
  396. eeh_pci_name(dev));
  397. return 0;
  398. }
  399. if (!pe->addr && !pe->config_addr) {
  400. eeh_stats.no_cfg_addr++;
  401. return 0;
  402. }
  403. /*
  404. * On PowerNV platform, we might already have fenced PHB
  405. * there and we need take care of that firstly.
  406. */
  407. ret = eeh_phb_check_failure(pe);
  408. if (ret > 0)
  409. return ret;
  410. /*
  411. * If the PE isn't owned by us, we shouldn't check the
  412. * state. Instead, let the owner handle it if the PE has
  413. * been frozen.
  414. */
  415. if (eeh_pe_passed(pe))
  416. return 0;
  417. /* If we already have a pending isolation event for this
  418. * slot, we know it's bad already, we don't need to check.
  419. * Do this checking under a lock; as multiple PCI devices
  420. * in one slot might report errors simultaneously, and we
  421. * only want one error recovery routine running.
  422. */
  423. eeh_serialize_lock(&flags);
  424. rc = 1;
  425. if (pe->state & EEH_PE_ISOLATED) {
  426. pe->check_count++;
  427. if (pe->check_count % EEH_MAX_FAILS == 0) {
  428. dn = pci_device_to_OF_node(dev);
  429. if (dn)
  430. location = of_get_property(dn, "ibm,loc-code",
  431. NULL);
  432. printk(KERN_ERR "EEH: %d reads ignored for recovering device at "
  433. "location=%s driver=%s pci addr=%s\n",
  434. pe->check_count,
  435. location ? location : "unknown",
  436. eeh_driver_name(dev), eeh_pci_name(dev));
  437. printk(KERN_ERR "EEH: Might be infinite loop in %s driver\n",
  438. eeh_driver_name(dev));
  439. dump_stack();
  440. }
  441. goto dn_unlock;
  442. }
  443. /*
  444. * Now test for an EEH failure. This is VERY expensive.
  445. * Note that the eeh_config_addr may be a parent device
  446. * in the case of a device behind a bridge, or it may be
  447. * function zero of a multi-function device.
  448. * In any case they must share a common PHB.
  449. */
  450. ret = eeh_ops->get_state(pe, NULL);
  451. /* Note that config-io to empty slots may fail;
  452. * they are empty when they don't have children.
  453. * We will punt with the following conditions: Failure to get
  454. * PE's state, EEH not support and Permanently unavailable
  455. * state, PE is in good state.
  456. */
  457. if ((ret < 0) ||
  458. (ret == EEH_STATE_NOT_SUPPORT) || eeh_state_active(ret)) {
  459. eeh_stats.false_positives++;
  460. pe->false_positives++;
  461. rc = 0;
  462. goto dn_unlock;
  463. }
  464. /*
  465. * It should be corner case that the parent PE has been
  466. * put into frozen state as well. We should take care
  467. * that at first.
  468. */
  469. parent_pe = pe->parent;
  470. while (parent_pe) {
  471. /* Hit the ceiling ? */
  472. if (parent_pe->type & EEH_PE_PHB)
  473. break;
  474. /* Frozen parent PE ? */
  475. ret = eeh_ops->get_state(parent_pe, NULL);
  476. if (ret > 0 && !eeh_state_active(ret)) {
  477. pe = parent_pe;
  478. pr_err("EEH: Failure of PHB#%x-PE#%x will be handled at parent PHB#%x-PE#%x.\n",
  479. pe->phb->global_number, pe->addr,
  480. pe->phb->global_number, parent_pe->addr);
  481. }
  482. /* Next parent level */
  483. parent_pe = parent_pe->parent;
  484. }
  485. eeh_stats.slot_resets++;
  486. /* Avoid repeated reports of this failure, including problems
  487. * with other functions on this device, and functions under
  488. * bridges.
  489. */
  490. eeh_pe_state_mark(pe, EEH_PE_ISOLATED);
  491. eeh_serialize_unlock(flags);
  492. /* Most EEH events are due to device driver bugs. Having
  493. * a stack trace will help the device-driver authors figure
  494. * out what happened. So print that out.
  495. */
  496. phb_pe = eeh_phb_pe_get(pe->phb);
  497. pr_err("EEH: Frozen PHB#%x-PE#%x detected\n",
  498. pe->phb->global_number, pe->addr);
  499. pr_err("EEH: PE location: %s, PHB location: %s\n",
  500. eeh_pe_loc_get(pe), eeh_pe_loc_get(phb_pe));
  501. dump_stack();
  502. eeh_send_failure_event(pe);
  503. return 1;
  504. dn_unlock:
  505. eeh_serialize_unlock(flags);
  506. return rc;
  507. }
  508. EXPORT_SYMBOL_GPL(eeh_dev_check_failure);
  509. /**
  510. * eeh_check_failure - Check if all 1's data is due to EEH slot freeze
  511. * @token: I/O address
  512. *
  513. * Check for an EEH failure at the given I/O address. Call this
  514. * routine if the result of a read was all 0xff's and you want to
  515. * find out if this is due to an EEH slot freeze event. This routine
  516. * will query firmware for the EEH status.
  517. *
  518. * Note this routine is safe to call in an interrupt context.
  519. */
  520. int eeh_check_failure(const volatile void __iomem *token)
  521. {
  522. unsigned long addr;
  523. struct eeh_dev *edev;
  524. /* Finding the phys addr + pci device; this is pretty quick. */
  525. addr = eeh_token_to_phys((unsigned long __force) token);
  526. edev = eeh_addr_cache_get_dev(addr);
  527. if (!edev) {
  528. eeh_stats.no_device++;
  529. return 0;
  530. }
  531. return eeh_dev_check_failure(edev);
  532. }
  533. EXPORT_SYMBOL(eeh_check_failure);
  534. /**
  535. * eeh_pci_enable - Enable MMIO or DMA transfers for this slot
  536. * @pe: EEH PE
  537. *
  538. * This routine should be called to reenable frozen MMIO or DMA
  539. * so that it would work correctly again. It's useful while doing
  540. * recovery or log collection on the indicated device.
  541. */
  542. int eeh_pci_enable(struct eeh_pe *pe, int function)
  543. {
  544. int active_flag, rc;
  545. /*
  546. * pHyp doesn't allow to enable IO or DMA on unfrozen PE.
  547. * Also, it's pointless to enable them on unfrozen PE. So
  548. * we have to check before enabling IO or DMA.
  549. */
  550. switch (function) {
  551. case EEH_OPT_THAW_MMIO:
  552. active_flag = EEH_STATE_MMIO_ACTIVE | EEH_STATE_MMIO_ENABLED;
  553. break;
  554. case EEH_OPT_THAW_DMA:
  555. active_flag = EEH_STATE_DMA_ACTIVE;
  556. break;
  557. case EEH_OPT_DISABLE:
  558. case EEH_OPT_ENABLE:
  559. case EEH_OPT_FREEZE_PE:
  560. active_flag = 0;
  561. break;
  562. default:
  563. pr_warn("%s: Invalid function %d\n",
  564. __func__, function);
  565. return -EINVAL;
  566. }
  567. /*
  568. * Check if IO or DMA has been enabled before
  569. * enabling them.
  570. */
  571. if (active_flag) {
  572. rc = eeh_ops->get_state(pe, NULL);
  573. if (rc < 0)
  574. return rc;
  575. /* Needn't enable it at all */
  576. if (rc == EEH_STATE_NOT_SUPPORT)
  577. return 0;
  578. /* It's already enabled */
  579. if (rc & active_flag)
  580. return 0;
  581. }
  582. /* Issue the request */
  583. rc = eeh_ops->set_option(pe, function);
  584. if (rc)
  585. pr_warn("%s: Unexpected state change %d on "
  586. "PHB#%x-PE#%x, err=%d\n",
  587. __func__, function, pe->phb->global_number,
  588. pe->addr, rc);
  589. /* Check if the request is finished successfully */
  590. if (active_flag) {
  591. rc = eeh_ops->wait_state(pe, PCI_BUS_RESET_WAIT_MSEC);
  592. if (rc < 0)
  593. return rc;
  594. if (rc & active_flag)
  595. return 0;
  596. return -EIO;
  597. }
  598. return rc;
  599. }
  600. static void *eeh_disable_and_save_dev_state(struct eeh_dev *edev,
  601. void *userdata)
  602. {
  603. struct pci_dev *pdev = eeh_dev_to_pci_dev(edev);
  604. struct pci_dev *dev = userdata;
  605. /*
  606. * The caller should have disabled and saved the
  607. * state for the specified device
  608. */
  609. if (!pdev || pdev == dev)
  610. return NULL;
  611. /* Ensure we have D0 power state */
  612. pci_set_power_state(pdev, PCI_D0);
  613. /* Save device state */
  614. pci_save_state(pdev);
  615. /*
  616. * Disable device to avoid any DMA traffic and
  617. * interrupt from the device
  618. */
  619. pci_write_config_word(pdev, PCI_COMMAND, PCI_COMMAND_INTX_DISABLE);
  620. return NULL;
  621. }
  622. static void *eeh_restore_dev_state(struct eeh_dev *edev, void *userdata)
  623. {
  624. struct pci_dn *pdn = eeh_dev_to_pdn(edev);
  625. struct pci_dev *pdev = eeh_dev_to_pci_dev(edev);
  626. struct pci_dev *dev = userdata;
  627. if (!pdev)
  628. return NULL;
  629. /* Apply customization from firmware */
  630. if (pdn && eeh_ops->restore_config)
  631. eeh_ops->restore_config(pdn);
  632. /* The caller should restore state for the specified device */
  633. if (pdev != dev)
  634. pci_restore_state(pdev);
  635. return NULL;
  636. }
  637. int eeh_restore_vf_config(struct pci_dn *pdn)
  638. {
  639. struct eeh_dev *edev = pdn_to_eeh_dev(pdn);
  640. u32 devctl, cmd, cap2, aer_capctl;
  641. int old_mps;
  642. if (edev->pcie_cap) {
  643. /* Restore MPS */
  644. old_mps = (ffs(pdn->mps) - 8) << 5;
  645. eeh_ops->read_config(pdn, edev->pcie_cap + PCI_EXP_DEVCTL,
  646. 2, &devctl);
  647. devctl &= ~PCI_EXP_DEVCTL_PAYLOAD;
  648. devctl |= old_mps;
  649. eeh_ops->write_config(pdn, edev->pcie_cap + PCI_EXP_DEVCTL,
  650. 2, devctl);
  651. /* Disable Completion Timeout if possible */
  652. eeh_ops->read_config(pdn, edev->pcie_cap + PCI_EXP_DEVCAP2,
  653. 4, &cap2);
  654. if (cap2 & PCI_EXP_DEVCAP2_COMP_TMOUT_DIS) {
  655. eeh_ops->read_config(pdn,
  656. edev->pcie_cap + PCI_EXP_DEVCTL2,
  657. 4, &cap2);
  658. cap2 |= PCI_EXP_DEVCTL2_COMP_TMOUT_DIS;
  659. eeh_ops->write_config(pdn,
  660. edev->pcie_cap + PCI_EXP_DEVCTL2,
  661. 4, cap2);
  662. }
  663. }
  664. /* Enable SERR and parity checking */
  665. eeh_ops->read_config(pdn, PCI_COMMAND, 2, &cmd);
  666. cmd |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
  667. eeh_ops->write_config(pdn, PCI_COMMAND, 2, cmd);
  668. /* Enable report various errors */
  669. if (edev->pcie_cap) {
  670. eeh_ops->read_config(pdn, edev->pcie_cap + PCI_EXP_DEVCTL,
  671. 2, &devctl);
  672. devctl &= ~PCI_EXP_DEVCTL_CERE;
  673. devctl |= (PCI_EXP_DEVCTL_NFERE |
  674. PCI_EXP_DEVCTL_FERE |
  675. PCI_EXP_DEVCTL_URRE);
  676. eeh_ops->write_config(pdn, edev->pcie_cap + PCI_EXP_DEVCTL,
  677. 2, devctl);
  678. }
  679. /* Enable ECRC generation and check */
  680. if (edev->pcie_cap && edev->aer_cap) {
  681. eeh_ops->read_config(pdn, edev->aer_cap + PCI_ERR_CAP,
  682. 4, &aer_capctl);
  683. aer_capctl |= (PCI_ERR_CAP_ECRC_GENE | PCI_ERR_CAP_ECRC_CHKE);
  684. eeh_ops->write_config(pdn, edev->aer_cap + PCI_ERR_CAP,
  685. 4, aer_capctl);
  686. }
  687. return 0;
  688. }
  689. /**
  690. * pcibios_set_pcie_reset_state - Set PCI-E reset state
  691. * @dev: pci device struct
  692. * @state: reset state to enter
  693. *
  694. * Return value:
  695. * 0 if success
  696. */
  697. int pcibios_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state)
  698. {
  699. struct eeh_dev *edev = pci_dev_to_eeh_dev(dev);
  700. struct eeh_pe *pe = eeh_dev_to_pe(edev);
  701. if (!pe) {
  702. pr_err("%s: No PE found on PCI device %s\n",
  703. __func__, pci_name(dev));
  704. return -EINVAL;
  705. }
  706. switch (state) {
  707. case pcie_deassert_reset:
  708. eeh_ops->reset(pe, EEH_RESET_DEACTIVATE);
  709. eeh_unfreeze_pe(pe, false);
  710. if (!(pe->type & EEH_PE_VF))
  711. eeh_pe_state_clear(pe, EEH_PE_CFG_BLOCKED);
  712. eeh_pe_dev_traverse(pe, eeh_restore_dev_state, dev);
  713. eeh_pe_state_clear(pe, EEH_PE_ISOLATED);
  714. break;
  715. case pcie_hot_reset:
  716. eeh_pe_state_mark_with_cfg(pe, EEH_PE_ISOLATED);
  717. eeh_ops->set_option(pe, EEH_OPT_FREEZE_PE);
  718. eeh_pe_dev_traverse(pe, eeh_disable_and_save_dev_state, dev);
  719. if (!(pe->type & EEH_PE_VF))
  720. eeh_pe_state_mark(pe, EEH_PE_CFG_BLOCKED);
  721. eeh_ops->reset(pe, EEH_RESET_HOT);
  722. break;
  723. case pcie_warm_reset:
  724. eeh_pe_state_mark_with_cfg(pe, EEH_PE_ISOLATED);
  725. eeh_ops->set_option(pe, EEH_OPT_FREEZE_PE);
  726. eeh_pe_dev_traverse(pe, eeh_disable_and_save_dev_state, dev);
  727. if (!(pe->type & EEH_PE_VF))
  728. eeh_pe_state_mark(pe, EEH_PE_CFG_BLOCKED);
  729. eeh_ops->reset(pe, EEH_RESET_FUNDAMENTAL);
  730. break;
  731. default:
  732. eeh_pe_state_clear(pe, EEH_PE_ISOLATED | EEH_PE_CFG_BLOCKED);
  733. return -EINVAL;
  734. };
  735. return 0;
  736. }
  737. /**
  738. * eeh_set_pe_freset - Check the required reset for the indicated device
  739. * @data: EEH device
  740. * @flag: return value
  741. *
  742. * Each device might have its preferred reset type: fundamental or
  743. * hot reset. The routine is used to collected the information for
  744. * the indicated device and its children so that the bunch of the
  745. * devices could be reset properly.
  746. */
  747. static void *eeh_set_dev_freset(struct eeh_dev *edev, void *flag)
  748. {
  749. struct pci_dev *dev;
  750. unsigned int *freset = (unsigned int *)flag;
  751. dev = eeh_dev_to_pci_dev(edev);
  752. if (dev)
  753. *freset |= dev->needs_freset;
  754. return NULL;
  755. }
  756. /**
  757. * eeh_pe_reset_full - Complete a full reset process on the indicated PE
  758. * @pe: EEH PE
  759. *
  760. * This function executes a full reset procedure on a PE, including setting
  761. * the appropriate flags, performing a fundamental or hot reset, and then
  762. * deactivating the reset status. It is designed to be used within the EEH
  763. * subsystem, as opposed to eeh_pe_reset which is exported to drivers and
  764. * only performs a single operation at a time.
  765. *
  766. * This function will attempt to reset a PE three times before failing.
  767. */
  768. int eeh_pe_reset_full(struct eeh_pe *pe)
  769. {
  770. int reset_state = (EEH_PE_RESET | EEH_PE_CFG_BLOCKED);
  771. int type = EEH_RESET_HOT;
  772. unsigned int freset = 0;
  773. int i, state, ret;
  774. /*
  775. * Determine the type of reset to perform - hot or fundamental.
  776. * Hot reset is the default operation, unless any device under the
  777. * PE requires a fundamental reset.
  778. */
  779. eeh_pe_dev_traverse(pe, eeh_set_dev_freset, &freset);
  780. if (freset)
  781. type = EEH_RESET_FUNDAMENTAL;
  782. /* Mark the PE as in reset state and block config space accesses */
  783. eeh_pe_state_mark(pe, reset_state);
  784. /* Make three attempts at resetting the bus */
  785. for (i = 0; i < 3; i++) {
  786. ret = eeh_pe_reset(pe, type);
  787. if (ret)
  788. break;
  789. ret = eeh_pe_reset(pe, EEH_RESET_DEACTIVATE);
  790. if (ret)
  791. break;
  792. /* Wait until the PE is in a functioning state */
  793. state = eeh_ops->wait_state(pe, PCI_BUS_RESET_WAIT_MSEC);
  794. if (eeh_state_active(state))
  795. break;
  796. if (state < 0) {
  797. pr_warn("%s: Unrecoverable slot failure on PHB#%x-PE#%x",
  798. __func__, pe->phb->global_number, pe->addr);
  799. ret = -ENOTRECOVERABLE;
  800. break;
  801. }
  802. /* Set error in case this is our last attempt */
  803. ret = -EIO;
  804. pr_warn("%s: Failure %d resetting PHB#%x-PE#%x\n (%d)\n",
  805. __func__, state, pe->phb->global_number, pe->addr, (i + 1));
  806. }
  807. eeh_pe_state_clear(pe, reset_state);
  808. return ret;
  809. }
  810. /**
  811. * eeh_save_bars - Save device bars
  812. * @edev: PCI device associated EEH device
  813. *
  814. * Save the values of the device bars. Unlike the restore
  815. * routine, this routine is *not* recursive. This is because
  816. * PCI devices are added individually; but, for the restore,
  817. * an entire slot is reset at a time.
  818. */
  819. void eeh_save_bars(struct eeh_dev *edev)
  820. {
  821. struct pci_dn *pdn;
  822. int i;
  823. pdn = eeh_dev_to_pdn(edev);
  824. if (!pdn)
  825. return;
  826. for (i = 0; i < 16; i++)
  827. eeh_ops->read_config(pdn, i * 4, 4, &edev->config_space[i]);
  828. /*
  829. * For PCI bridges including root port, we need enable bus
  830. * master explicitly. Otherwise, it can't fetch IODA table
  831. * entries correctly. So we cache the bit in advance so that
  832. * we can restore it after reset, either PHB range or PE range.
  833. */
  834. if (edev->mode & EEH_DEV_BRIDGE)
  835. edev->config_space[1] |= PCI_COMMAND_MASTER;
  836. }
  837. /**
  838. * eeh_ops_register - Register platform dependent EEH operations
  839. * @ops: platform dependent EEH operations
  840. *
  841. * Register the platform dependent EEH operation callback
  842. * functions. The platform should call this function before
  843. * any other EEH operations.
  844. */
  845. int __init eeh_ops_register(struct eeh_ops *ops)
  846. {
  847. if (!ops->name) {
  848. pr_warn("%s: Invalid EEH ops name for %p\n",
  849. __func__, ops);
  850. return -EINVAL;
  851. }
  852. if (eeh_ops && eeh_ops != ops) {
  853. pr_warn("%s: EEH ops of platform %s already existing (%s)\n",
  854. __func__, eeh_ops->name, ops->name);
  855. return -EEXIST;
  856. }
  857. eeh_ops = ops;
  858. return 0;
  859. }
  860. /**
  861. * eeh_ops_unregister - Unreigster platform dependent EEH operations
  862. * @name: name of EEH platform operations
  863. *
  864. * Unregister the platform dependent EEH operation callback
  865. * functions.
  866. */
  867. int __exit eeh_ops_unregister(const char *name)
  868. {
  869. if (!name || !strlen(name)) {
  870. pr_warn("%s: Invalid EEH ops name\n",
  871. __func__);
  872. return -EINVAL;
  873. }
  874. if (eeh_ops && !strcmp(eeh_ops->name, name)) {
  875. eeh_ops = NULL;
  876. return 0;
  877. }
  878. return -EEXIST;
  879. }
  880. static int eeh_reboot_notifier(struct notifier_block *nb,
  881. unsigned long action, void *unused)
  882. {
  883. eeh_clear_flag(EEH_ENABLED);
  884. return NOTIFY_DONE;
  885. }
  886. static struct notifier_block eeh_reboot_nb = {
  887. .notifier_call = eeh_reboot_notifier,
  888. };
  889. void eeh_probe_devices(void)
  890. {
  891. struct pci_controller *hose, *tmp;
  892. struct pci_dn *pdn;
  893. /* Enable EEH for all adapters */
  894. list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
  895. pdn = hose->pci_data;
  896. traverse_pci_dn(pdn, eeh_ops->probe, NULL);
  897. }
  898. }
  899. /**
  900. * eeh_init - EEH initialization
  901. *
  902. * Initialize EEH by trying to enable it for all of the adapters in the system.
  903. * As a side effect we can determine here if eeh is supported at all.
  904. * Note that we leave EEH on so failed config cycles won't cause a machine
  905. * check. If a user turns off EEH for a particular adapter they are really
  906. * telling Linux to ignore errors. Some hardware (e.g. POWER5) won't
  907. * grant access to a slot if EEH isn't enabled, and so we always enable
  908. * EEH for all slots/all devices.
  909. *
  910. * The eeh-force-off option disables EEH checking globally, for all slots.
  911. * Even if force-off is set, the EEH hardware is still enabled, so that
  912. * newer systems can boot.
  913. */
  914. static int eeh_init(void)
  915. {
  916. struct pci_controller *hose, *tmp;
  917. int ret = 0;
  918. /* Register reboot notifier */
  919. ret = register_reboot_notifier(&eeh_reboot_nb);
  920. if (ret) {
  921. pr_warn("%s: Failed to register notifier (%d)\n",
  922. __func__, ret);
  923. return ret;
  924. }
  925. /* call platform initialization function */
  926. if (!eeh_ops) {
  927. pr_warn("%s: Platform EEH operation not found\n",
  928. __func__);
  929. return -EEXIST;
  930. } else if ((ret = eeh_ops->init()))
  931. return ret;
  932. /* Initialize PHB PEs */
  933. list_for_each_entry_safe(hose, tmp, &hose_list, list_node)
  934. eeh_dev_phb_init_dynamic(hose);
  935. /* Initialize EEH event */
  936. ret = eeh_event_init();
  937. if (ret)
  938. return ret;
  939. eeh_probe_devices();
  940. if (eeh_enabled())
  941. pr_info("EEH: PCI Enhanced I/O Error Handling Enabled\n");
  942. else
  943. pr_info("EEH: No capable adapters found\n");
  944. return ret;
  945. }
  946. core_initcall_sync(eeh_init);
  947. /**
  948. * eeh_add_device_early - Enable EEH for the indicated device node
  949. * @pdn: PCI device node for which to set up EEH
  950. *
  951. * This routine must be used to perform EEH initialization for PCI
  952. * devices that were added after system boot (e.g. hotplug, dlpar).
  953. * This routine must be called before any i/o is performed to the
  954. * adapter (inluding any config-space i/o).
  955. * Whether this actually enables EEH or not for this device depends
  956. * on the CEC architecture, type of the device, on earlier boot
  957. * command-line arguments & etc.
  958. */
  959. void eeh_add_device_early(struct pci_dn *pdn)
  960. {
  961. struct pci_controller *phb = pdn ? pdn->phb : NULL;
  962. struct eeh_dev *edev = pdn_to_eeh_dev(pdn);
  963. if (!edev)
  964. return;
  965. if (!eeh_has_flag(EEH_PROBE_MODE_DEVTREE))
  966. return;
  967. /* USB Bus children of PCI devices will not have BUID's */
  968. if (NULL == phb ||
  969. (eeh_has_flag(EEH_PROBE_MODE_DEVTREE) && 0 == phb->buid))
  970. return;
  971. eeh_ops->probe(pdn, NULL);
  972. }
  973. /**
  974. * eeh_add_device_tree_early - Enable EEH for the indicated device
  975. * @pdn: PCI device node
  976. *
  977. * This routine must be used to perform EEH initialization for the
  978. * indicated PCI device that was added after system boot (e.g.
  979. * hotplug, dlpar).
  980. */
  981. void eeh_add_device_tree_early(struct pci_dn *pdn)
  982. {
  983. struct pci_dn *n;
  984. if (!pdn)
  985. return;
  986. list_for_each_entry(n, &pdn->child_list, list)
  987. eeh_add_device_tree_early(n);
  988. eeh_add_device_early(pdn);
  989. }
  990. EXPORT_SYMBOL_GPL(eeh_add_device_tree_early);
  991. /**
  992. * eeh_add_device_late - Perform EEH initialization for the indicated pci device
  993. * @dev: pci device for which to set up EEH
  994. *
  995. * This routine must be used to complete EEH initialization for PCI
  996. * devices that were added after system boot (e.g. hotplug, dlpar).
  997. */
  998. void eeh_add_device_late(struct pci_dev *dev)
  999. {
  1000. struct pci_dn *pdn;
  1001. struct eeh_dev *edev;
  1002. if (!dev || !eeh_enabled())
  1003. return;
  1004. pr_debug("EEH: Adding device %s\n", pci_name(dev));
  1005. pdn = pci_get_pdn_by_devfn(dev->bus, dev->devfn);
  1006. edev = pdn_to_eeh_dev(pdn);
  1007. if (edev->pdev == dev) {
  1008. pr_debug("EEH: Already referenced !\n");
  1009. return;
  1010. }
  1011. /*
  1012. * The EEH cache might not be removed correctly because of
  1013. * unbalanced kref to the device during unplug time, which
  1014. * relies on pcibios_release_device(). So we have to remove
  1015. * that here explicitly.
  1016. */
  1017. if (edev->pdev) {
  1018. eeh_rmv_from_parent_pe(edev);
  1019. eeh_addr_cache_rmv_dev(edev->pdev);
  1020. eeh_sysfs_remove_device(edev->pdev);
  1021. edev->mode &= ~EEH_DEV_SYSFS;
  1022. /*
  1023. * We definitely should have the PCI device removed
  1024. * though it wasn't correctly. So we needn't call
  1025. * into error handler afterwards.
  1026. */
  1027. edev->mode |= EEH_DEV_NO_HANDLER;
  1028. edev->pdev = NULL;
  1029. dev->dev.archdata.edev = NULL;
  1030. }
  1031. if (eeh_has_flag(EEH_PROBE_MODE_DEV))
  1032. eeh_ops->probe(pdn, NULL);
  1033. edev->pdev = dev;
  1034. dev->dev.archdata.edev = edev;
  1035. eeh_addr_cache_insert_dev(dev);
  1036. }
  1037. /**
  1038. * eeh_add_device_tree_late - Perform EEH initialization for the indicated PCI bus
  1039. * @bus: PCI bus
  1040. *
  1041. * This routine must be used to perform EEH initialization for PCI
  1042. * devices which are attached to the indicated PCI bus. The PCI bus
  1043. * is added after system boot through hotplug or dlpar.
  1044. */
  1045. void eeh_add_device_tree_late(struct pci_bus *bus)
  1046. {
  1047. struct pci_dev *dev;
  1048. list_for_each_entry(dev, &bus->devices, bus_list) {
  1049. eeh_add_device_late(dev);
  1050. if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) {
  1051. struct pci_bus *subbus = dev->subordinate;
  1052. if (subbus)
  1053. eeh_add_device_tree_late(subbus);
  1054. }
  1055. }
  1056. }
  1057. EXPORT_SYMBOL_GPL(eeh_add_device_tree_late);
  1058. /**
  1059. * eeh_add_sysfs_files - Add EEH sysfs files for the indicated PCI bus
  1060. * @bus: PCI bus
  1061. *
  1062. * This routine must be used to add EEH sysfs files for PCI
  1063. * devices which are attached to the indicated PCI bus. The PCI bus
  1064. * is added after system boot through hotplug or dlpar.
  1065. */
  1066. void eeh_add_sysfs_files(struct pci_bus *bus)
  1067. {
  1068. struct pci_dev *dev;
  1069. list_for_each_entry(dev, &bus->devices, bus_list) {
  1070. eeh_sysfs_add_device(dev);
  1071. if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) {
  1072. struct pci_bus *subbus = dev->subordinate;
  1073. if (subbus)
  1074. eeh_add_sysfs_files(subbus);
  1075. }
  1076. }
  1077. }
  1078. EXPORT_SYMBOL_GPL(eeh_add_sysfs_files);
  1079. /**
  1080. * eeh_remove_device - Undo EEH setup for the indicated pci device
  1081. * @dev: pci device to be removed
  1082. *
  1083. * This routine should be called when a device is removed from
  1084. * a running system (e.g. by hotplug or dlpar). It unregisters
  1085. * the PCI device from the EEH subsystem. I/O errors affecting
  1086. * this device will no longer be detected after this call; thus,
  1087. * i/o errors affecting this slot may leave this device unusable.
  1088. */
  1089. void eeh_remove_device(struct pci_dev *dev)
  1090. {
  1091. struct eeh_dev *edev;
  1092. if (!dev || !eeh_enabled())
  1093. return;
  1094. edev = pci_dev_to_eeh_dev(dev);
  1095. /* Unregister the device with the EEH/PCI address search system */
  1096. pr_debug("EEH: Removing device %s\n", pci_name(dev));
  1097. if (!edev || !edev->pdev || !edev->pe) {
  1098. pr_debug("EEH: Not referenced !\n");
  1099. return;
  1100. }
  1101. /*
  1102. * During the hotplug for EEH error recovery, we need the EEH
  1103. * device attached to the parent PE in order for BAR restore
  1104. * a bit later. So we keep it for BAR restore and remove it
  1105. * from the parent PE during the BAR resotre.
  1106. */
  1107. edev->pdev = NULL;
  1108. /*
  1109. * The flag "in_error" is used to trace EEH devices for VFs
  1110. * in error state or not. It's set in eeh_report_error(). If
  1111. * it's not set, eeh_report_{reset,resume}() won't be called
  1112. * for the VF EEH device.
  1113. */
  1114. edev->in_error = false;
  1115. dev->dev.archdata.edev = NULL;
  1116. if (!(edev->pe->state & EEH_PE_KEEP))
  1117. eeh_rmv_from_parent_pe(edev);
  1118. else
  1119. edev->mode |= EEH_DEV_DISCONNECTED;
  1120. /*
  1121. * We're removing from the PCI subsystem, that means
  1122. * the PCI device driver can't support EEH or not
  1123. * well. So we rely on hotplug completely to do recovery
  1124. * for the specific PCI device.
  1125. */
  1126. edev->mode |= EEH_DEV_NO_HANDLER;
  1127. eeh_addr_cache_rmv_dev(dev);
  1128. eeh_sysfs_remove_device(dev);
  1129. edev->mode &= ~EEH_DEV_SYSFS;
  1130. }
  1131. int eeh_unfreeze_pe(struct eeh_pe *pe, bool sw_state)
  1132. {
  1133. int ret;
  1134. ret = eeh_pci_enable(pe, EEH_OPT_THAW_MMIO);
  1135. if (ret) {
  1136. pr_warn("%s: Failure %d enabling IO on PHB#%x-PE#%x\n",
  1137. __func__, ret, pe->phb->global_number, pe->addr);
  1138. return ret;
  1139. }
  1140. ret = eeh_pci_enable(pe, EEH_OPT_THAW_DMA);
  1141. if (ret) {
  1142. pr_warn("%s: Failure %d enabling DMA on PHB#%x-PE#%x\n",
  1143. __func__, ret, pe->phb->global_number, pe->addr);
  1144. return ret;
  1145. }
  1146. /* Clear software isolated state */
  1147. if (sw_state && (pe->state & EEH_PE_ISOLATED))
  1148. eeh_pe_state_clear(pe, EEH_PE_ISOLATED);
  1149. return ret;
  1150. }
  1151. static struct pci_device_id eeh_reset_ids[] = {
  1152. { PCI_DEVICE(0x19a2, 0x0710) }, /* Emulex, BE */
  1153. { PCI_DEVICE(0x10df, 0xe220) }, /* Emulex, Lancer */
  1154. { PCI_DEVICE(0x14e4, 0x1657) }, /* Broadcom BCM5719 */
  1155. { 0 }
  1156. };
  1157. static int eeh_pe_change_owner(struct eeh_pe *pe)
  1158. {
  1159. struct eeh_dev *edev, *tmp;
  1160. struct pci_dev *pdev;
  1161. struct pci_device_id *id;
  1162. int ret;
  1163. /* Check PE state */
  1164. ret = eeh_ops->get_state(pe, NULL);
  1165. if (ret < 0 || ret == EEH_STATE_NOT_SUPPORT)
  1166. return 0;
  1167. /* Unfrozen PE, nothing to do */
  1168. if (eeh_state_active(ret))
  1169. return 0;
  1170. /* Frozen PE, check if it needs PE level reset */
  1171. eeh_pe_for_each_dev(pe, edev, tmp) {
  1172. pdev = eeh_dev_to_pci_dev(edev);
  1173. if (!pdev)
  1174. continue;
  1175. for (id = &eeh_reset_ids[0]; id->vendor != 0; id++) {
  1176. if (id->vendor != PCI_ANY_ID &&
  1177. id->vendor != pdev->vendor)
  1178. continue;
  1179. if (id->device != PCI_ANY_ID &&
  1180. id->device != pdev->device)
  1181. continue;
  1182. if (id->subvendor != PCI_ANY_ID &&
  1183. id->subvendor != pdev->subsystem_vendor)
  1184. continue;
  1185. if (id->subdevice != PCI_ANY_ID &&
  1186. id->subdevice != pdev->subsystem_device)
  1187. continue;
  1188. return eeh_pe_reset_and_recover(pe);
  1189. }
  1190. }
  1191. return eeh_unfreeze_pe(pe, true);
  1192. }
  1193. /**
  1194. * eeh_dev_open - Increase count of pass through devices for PE
  1195. * @pdev: PCI device
  1196. *
  1197. * Increase count of passed through devices for the indicated
  1198. * PE. In the result, the EEH errors detected on the PE won't be
  1199. * reported. The PE owner will be responsible for detection
  1200. * and recovery.
  1201. */
  1202. int eeh_dev_open(struct pci_dev *pdev)
  1203. {
  1204. struct eeh_dev *edev;
  1205. int ret = -ENODEV;
  1206. mutex_lock(&eeh_dev_mutex);
  1207. /* No PCI device ? */
  1208. if (!pdev)
  1209. goto out;
  1210. /* No EEH device or PE ? */
  1211. edev = pci_dev_to_eeh_dev(pdev);
  1212. if (!edev || !edev->pe)
  1213. goto out;
  1214. /*
  1215. * The PE might have been put into frozen state, but we
  1216. * didn't detect that yet. The passed through PCI devices
  1217. * in frozen PE won't work properly. Clear the frozen state
  1218. * in advance.
  1219. */
  1220. ret = eeh_pe_change_owner(edev->pe);
  1221. if (ret)
  1222. goto out;
  1223. /* Increase PE's pass through count */
  1224. atomic_inc(&edev->pe->pass_dev_cnt);
  1225. mutex_unlock(&eeh_dev_mutex);
  1226. return 0;
  1227. out:
  1228. mutex_unlock(&eeh_dev_mutex);
  1229. return ret;
  1230. }
  1231. EXPORT_SYMBOL_GPL(eeh_dev_open);
  1232. /**
  1233. * eeh_dev_release - Decrease count of pass through devices for PE
  1234. * @pdev: PCI device
  1235. *
  1236. * Decrease count of pass through devices for the indicated PE. If
  1237. * there is no passed through device in PE, the EEH errors detected
  1238. * on the PE will be reported and handled as usual.
  1239. */
  1240. void eeh_dev_release(struct pci_dev *pdev)
  1241. {
  1242. struct eeh_dev *edev;
  1243. mutex_lock(&eeh_dev_mutex);
  1244. /* No PCI device ? */
  1245. if (!pdev)
  1246. goto out;
  1247. /* No EEH device ? */
  1248. edev = pci_dev_to_eeh_dev(pdev);
  1249. if (!edev || !edev->pe || !eeh_pe_passed(edev->pe))
  1250. goto out;
  1251. /* Decrease PE's pass through count */
  1252. WARN_ON(atomic_dec_if_positive(&edev->pe->pass_dev_cnt) < 0);
  1253. eeh_pe_change_owner(edev->pe);
  1254. out:
  1255. mutex_unlock(&eeh_dev_mutex);
  1256. }
  1257. EXPORT_SYMBOL(eeh_dev_release);
  1258. #ifdef CONFIG_IOMMU_API
  1259. static int dev_has_iommu_table(struct device *dev, void *data)
  1260. {
  1261. struct pci_dev *pdev = to_pci_dev(dev);
  1262. struct pci_dev **ppdev = data;
  1263. if (!dev)
  1264. return 0;
  1265. if (dev->iommu_group) {
  1266. *ppdev = pdev;
  1267. return 1;
  1268. }
  1269. return 0;
  1270. }
  1271. /**
  1272. * eeh_iommu_group_to_pe - Convert IOMMU group to EEH PE
  1273. * @group: IOMMU group
  1274. *
  1275. * The routine is called to convert IOMMU group to EEH PE.
  1276. */
  1277. struct eeh_pe *eeh_iommu_group_to_pe(struct iommu_group *group)
  1278. {
  1279. struct pci_dev *pdev = NULL;
  1280. struct eeh_dev *edev;
  1281. int ret;
  1282. /* No IOMMU group ? */
  1283. if (!group)
  1284. return NULL;
  1285. ret = iommu_group_for_each_dev(group, &pdev, dev_has_iommu_table);
  1286. if (!ret || !pdev)
  1287. return NULL;
  1288. /* No EEH device or PE ? */
  1289. edev = pci_dev_to_eeh_dev(pdev);
  1290. if (!edev || !edev->pe)
  1291. return NULL;
  1292. return edev->pe;
  1293. }
  1294. EXPORT_SYMBOL_GPL(eeh_iommu_group_to_pe);
  1295. #endif /* CONFIG_IOMMU_API */
  1296. /**
  1297. * eeh_pe_set_option - Set options for the indicated PE
  1298. * @pe: EEH PE
  1299. * @option: requested option
  1300. *
  1301. * The routine is called to enable or disable EEH functionality
  1302. * on the indicated PE, to enable IO or DMA for the frozen PE.
  1303. */
  1304. int eeh_pe_set_option(struct eeh_pe *pe, int option)
  1305. {
  1306. int ret = 0;
  1307. /* Invalid PE ? */
  1308. if (!pe)
  1309. return -ENODEV;
  1310. /*
  1311. * EEH functionality could possibly be disabled, just
  1312. * return error for the case. And the EEH functinality
  1313. * isn't expected to be disabled on one specific PE.
  1314. */
  1315. switch (option) {
  1316. case EEH_OPT_ENABLE:
  1317. if (eeh_enabled()) {
  1318. ret = eeh_pe_change_owner(pe);
  1319. break;
  1320. }
  1321. ret = -EIO;
  1322. break;
  1323. case EEH_OPT_DISABLE:
  1324. break;
  1325. case EEH_OPT_THAW_MMIO:
  1326. case EEH_OPT_THAW_DMA:
  1327. case EEH_OPT_FREEZE_PE:
  1328. if (!eeh_ops || !eeh_ops->set_option) {
  1329. ret = -ENOENT;
  1330. break;
  1331. }
  1332. ret = eeh_pci_enable(pe, option);
  1333. break;
  1334. default:
  1335. pr_debug("%s: Option %d out of range (%d, %d)\n",
  1336. __func__, option, EEH_OPT_DISABLE, EEH_OPT_THAW_DMA);
  1337. ret = -EINVAL;
  1338. }
  1339. return ret;
  1340. }
  1341. EXPORT_SYMBOL_GPL(eeh_pe_set_option);
  1342. /**
  1343. * eeh_pe_get_state - Retrieve PE's state
  1344. * @pe: EEH PE
  1345. *
  1346. * Retrieve the PE's state, which includes 3 aspects: enabled
  1347. * DMA, enabled IO and asserted reset.
  1348. */
  1349. int eeh_pe_get_state(struct eeh_pe *pe)
  1350. {
  1351. int result, ret = 0;
  1352. bool rst_active, dma_en, mmio_en;
  1353. /* Existing PE ? */
  1354. if (!pe)
  1355. return -ENODEV;
  1356. if (!eeh_ops || !eeh_ops->get_state)
  1357. return -ENOENT;
  1358. /*
  1359. * If the parent PE is owned by the host kernel and is undergoing
  1360. * error recovery, we should return the PE state as temporarily
  1361. * unavailable so that the error recovery on the guest is suspended
  1362. * until the recovery completes on the host.
  1363. */
  1364. if (pe->parent &&
  1365. !(pe->state & EEH_PE_REMOVED) &&
  1366. (pe->parent->state & (EEH_PE_ISOLATED | EEH_PE_RECOVERING)))
  1367. return EEH_PE_STATE_UNAVAIL;
  1368. result = eeh_ops->get_state(pe, NULL);
  1369. rst_active = !!(result & EEH_STATE_RESET_ACTIVE);
  1370. dma_en = !!(result & EEH_STATE_DMA_ENABLED);
  1371. mmio_en = !!(result & EEH_STATE_MMIO_ENABLED);
  1372. if (rst_active)
  1373. ret = EEH_PE_STATE_RESET;
  1374. else if (dma_en && mmio_en)
  1375. ret = EEH_PE_STATE_NORMAL;
  1376. else if (!dma_en && !mmio_en)
  1377. ret = EEH_PE_STATE_STOPPED_IO_DMA;
  1378. else if (!dma_en && mmio_en)
  1379. ret = EEH_PE_STATE_STOPPED_DMA;
  1380. else
  1381. ret = EEH_PE_STATE_UNAVAIL;
  1382. return ret;
  1383. }
  1384. EXPORT_SYMBOL_GPL(eeh_pe_get_state);
  1385. static int eeh_pe_reenable_devices(struct eeh_pe *pe)
  1386. {
  1387. struct eeh_dev *edev, *tmp;
  1388. struct pci_dev *pdev;
  1389. int ret = 0;
  1390. /* Restore config space */
  1391. eeh_pe_restore_bars(pe);
  1392. /*
  1393. * Reenable PCI devices as the devices passed
  1394. * through are always enabled before the reset.
  1395. */
  1396. eeh_pe_for_each_dev(pe, edev, tmp) {
  1397. pdev = eeh_dev_to_pci_dev(edev);
  1398. if (!pdev)
  1399. continue;
  1400. ret = pci_reenable_device(pdev);
  1401. if (ret) {
  1402. pr_warn("%s: Failure %d reenabling %s\n",
  1403. __func__, ret, pci_name(pdev));
  1404. return ret;
  1405. }
  1406. }
  1407. /* The PE is still in frozen state */
  1408. return eeh_unfreeze_pe(pe, true);
  1409. }
  1410. /**
  1411. * eeh_pe_reset - Issue PE reset according to specified type
  1412. * @pe: EEH PE
  1413. * @option: reset type
  1414. *
  1415. * The routine is called to reset the specified PE with the
  1416. * indicated type, either fundamental reset or hot reset.
  1417. * PE reset is the most important part for error recovery.
  1418. */
  1419. int eeh_pe_reset(struct eeh_pe *pe, int option)
  1420. {
  1421. int ret = 0;
  1422. /* Invalid PE ? */
  1423. if (!pe)
  1424. return -ENODEV;
  1425. if (!eeh_ops || !eeh_ops->set_option || !eeh_ops->reset)
  1426. return -ENOENT;
  1427. switch (option) {
  1428. case EEH_RESET_DEACTIVATE:
  1429. ret = eeh_ops->reset(pe, option);
  1430. eeh_pe_state_clear(pe, EEH_PE_CFG_BLOCKED);
  1431. if (ret)
  1432. break;
  1433. ret = eeh_pe_reenable_devices(pe);
  1434. break;
  1435. case EEH_RESET_HOT:
  1436. case EEH_RESET_FUNDAMENTAL:
  1437. /*
  1438. * Proactively freeze the PE to drop all MMIO access
  1439. * during reset, which should be banned as it's always
  1440. * cause recursive EEH error.
  1441. */
  1442. eeh_ops->set_option(pe, EEH_OPT_FREEZE_PE);
  1443. eeh_pe_state_mark(pe, EEH_PE_CFG_BLOCKED);
  1444. ret = eeh_ops->reset(pe, option);
  1445. break;
  1446. default:
  1447. pr_debug("%s: Unsupported option %d\n",
  1448. __func__, option);
  1449. ret = -EINVAL;
  1450. }
  1451. return ret;
  1452. }
  1453. EXPORT_SYMBOL_GPL(eeh_pe_reset);
  1454. /**
  1455. * eeh_pe_configure - Configure PCI bridges after PE reset
  1456. * @pe: EEH PE
  1457. *
  1458. * The routine is called to restore the PCI config space for
  1459. * those PCI devices, especially PCI bridges affected by PE
  1460. * reset issued previously.
  1461. */
  1462. int eeh_pe_configure(struct eeh_pe *pe)
  1463. {
  1464. int ret = 0;
  1465. /* Invalid PE ? */
  1466. if (!pe)
  1467. return -ENODEV;
  1468. return ret;
  1469. }
  1470. EXPORT_SYMBOL_GPL(eeh_pe_configure);
  1471. /**
  1472. * eeh_pe_inject_err - Injecting the specified PCI error to the indicated PE
  1473. * @pe: the indicated PE
  1474. * @type: error type
  1475. * @function: error function
  1476. * @addr: address
  1477. * @mask: address mask
  1478. *
  1479. * The routine is called to inject the specified PCI error, which
  1480. * is determined by @type and @function, to the indicated PE for
  1481. * testing purpose.
  1482. */
  1483. int eeh_pe_inject_err(struct eeh_pe *pe, int type, int func,
  1484. unsigned long addr, unsigned long mask)
  1485. {
  1486. /* Invalid PE ? */
  1487. if (!pe)
  1488. return -ENODEV;
  1489. /* Unsupported operation ? */
  1490. if (!eeh_ops || !eeh_ops->err_inject)
  1491. return -ENOENT;
  1492. /* Check on PCI error type */
  1493. if (type != EEH_ERR_TYPE_32 && type != EEH_ERR_TYPE_64)
  1494. return -EINVAL;
  1495. /* Check on PCI error function */
  1496. if (func < EEH_ERR_FUNC_MIN || func > EEH_ERR_FUNC_MAX)
  1497. return -EINVAL;
  1498. return eeh_ops->err_inject(pe, type, func, addr, mask);
  1499. }
  1500. EXPORT_SYMBOL_GPL(eeh_pe_inject_err);
  1501. static int proc_eeh_show(struct seq_file *m, void *v)
  1502. {
  1503. if (!eeh_enabled()) {
  1504. seq_printf(m, "EEH Subsystem is globally disabled\n");
  1505. seq_printf(m, "eeh_total_mmio_ffs=%llu\n", eeh_stats.total_mmio_ffs);
  1506. } else {
  1507. seq_printf(m, "EEH Subsystem is enabled\n");
  1508. seq_printf(m,
  1509. "no device=%llu\n"
  1510. "no device node=%llu\n"
  1511. "no config address=%llu\n"
  1512. "check not wanted=%llu\n"
  1513. "eeh_total_mmio_ffs=%llu\n"
  1514. "eeh_false_positives=%llu\n"
  1515. "eeh_slot_resets=%llu\n",
  1516. eeh_stats.no_device,
  1517. eeh_stats.no_dn,
  1518. eeh_stats.no_cfg_addr,
  1519. eeh_stats.ignored_check,
  1520. eeh_stats.total_mmio_ffs,
  1521. eeh_stats.false_positives,
  1522. eeh_stats.slot_resets);
  1523. }
  1524. return 0;
  1525. }
  1526. #ifdef CONFIG_DEBUG_FS
  1527. static int eeh_enable_dbgfs_set(void *data, u64 val)
  1528. {
  1529. if (val)
  1530. eeh_clear_flag(EEH_FORCE_DISABLED);
  1531. else
  1532. eeh_add_flag(EEH_FORCE_DISABLED);
  1533. return 0;
  1534. }
  1535. static int eeh_enable_dbgfs_get(void *data, u64 *val)
  1536. {
  1537. if (eeh_enabled())
  1538. *val = 0x1ul;
  1539. else
  1540. *val = 0x0ul;
  1541. return 0;
  1542. }
  1543. static int eeh_freeze_dbgfs_set(void *data, u64 val)
  1544. {
  1545. eeh_max_freezes = val;
  1546. return 0;
  1547. }
  1548. static int eeh_freeze_dbgfs_get(void *data, u64 *val)
  1549. {
  1550. *val = eeh_max_freezes;
  1551. return 0;
  1552. }
  1553. DEFINE_SIMPLE_ATTRIBUTE(eeh_enable_dbgfs_ops, eeh_enable_dbgfs_get,
  1554. eeh_enable_dbgfs_set, "0x%llx\n");
  1555. DEFINE_SIMPLE_ATTRIBUTE(eeh_freeze_dbgfs_ops, eeh_freeze_dbgfs_get,
  1556. eeh_freeze_dbgfs_set, "0x%llx\n");
  1557. #endif
  1558. static int __init eeh_init_proc(void)
  1559. {
  1560. if (machine_is(pseries) || machine_is(powernv)) {
  1561. proc_create_single("powerpc/eeh", 0, NULL, proc_eeh_show);
  1562. #ifdef CONFIG_DEBUG_FS
  1563. debugfs_create_file("eeh_enable", 0600,
  1564. powerpc_debugfs_root, NULL,
  1565. &eeh_enable_dbgfs_ops);
  1566. debugfs_create_file("eeh_max_freezes", 0600,
  1567. powerpc_debugfs_root, NULL,
  1568. &eeh_freeze_dbgfs_ops);
  1569. #endif
  1570. }
  1571. return 0;
  1572. }
  1573. __initcall(eeh_init_proc);