devices.c 25 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. #include <linux/module.h>
  3. #include <linux/kernel.h>
  4. #include <linux/init.h>
  5. #include <linux/platform_device.h>
  6. #include <linux/dma-mapping.h>
  7. #include <linux/spi/pxa2xx_spi.h>
  8. #include <linux/platform_data/i2c-pxa.h>
  9. #include "udc.h"
  10. #include <linux/platform_data/usb-pxa3xx-ulpi.h>
  11. #include <linux/platform_data/video-pxafb.h>
  12. #include <linux/platform_data/mmc-pxamci.h>
  13. #include <linux/platform_data/irda-pxaficp.h>
  14. #include <mach/irqs.h>
  15. #include <linux/platform_data/usb-ohci-pxa27x.h>
  16. #include <linux/platform_data/keypad-pxa27x.h>
  17. #include <linux/platform_data/media/camera-pxa.h>
  18. #include <mach/audio.h>
  19. #include <mach/hardware.h>
  20. #include <linux/platform_data/mmp_dma.h>
  21. #include <linux/platform_data/mtd-nand-pxa3xx.h>
  22. #include "devices.h"
  23. #include "generic.h"
  24. void __init pxa_register_device(struct platform_device *dev, void *data)
  25. {
  26. int ret;
  27. dev->dev.platform_data = data;
  28. ret = platform_device_register(dev);
  29. if (ret)
  30. dev_err(&dev->dev, "unable to register device: %d\n", ret);
  31. }
  32. static struct resource pxa_resource_pmu = {
  33. .start = IRQ_PMU,
  34. .end = IRQ_PMU,
  35. .flags = IORESOURCE_IRQ,
  36. };
  37. struct platform_device pxa_device_pmu = {
  38. .name = "xscale-pmu",
  39. .id = -1,
  40. .resource = &pxa_resource_pmu,
  41. .num_resources = 1,
  42. };
  43. static struct resource pxamci_resources[] = {
  44. [0] = {
  45. .start = 0x41100000,
  46. .end = 0x41100fff,
  47. .flags = IORESOURCE_MEM,
  48. },
  49. [1] = {
  50. .start = IRQ_MMC,
  51. .end = IRQ_MMC,
  52. .flags = IORESOURCE_IRQ,
  53. },
  54. [2] = {
  55. .start = 21,
  56. .end = 21,
  57. .flags = IORESOURCE_DMA,
  58. },
  59. [3] = {
  60. .start = 22,
  61. .end = 22,
  62. .flags = IORESOURCE_DMA,
  63. },
  64. };
  65. static u64 pxamci_dmamask = 0xffffffffUL;
  66. struct platform_device pxa_device_mci = {
  67. .name = "pxa2xx-mci",
  68. .id = 0,
  69. .dev = {
  70. .dma_mask = &pxamci_dmamask,
  71. .coherent_dma_mask = 0xffffffff,
  72. },
  73. .num_resources = ARRAY_SIZE(pxamci_resources),
  74. .resource = pxamci_resources,
  75. };
  76. void __init pxa_set_mci_info(struct pxamci_platform_data *info)
  77. {
  78. pxa_register_device(&pxa_device_mci, info);
  79. }
  80. static struct pxa2xx_udc_mach_info pxa_udc_info = {
  81. .gpio_pullup = -1,
  82. };
  83. void __init pxa_set_udc_info(struct pxa2xx_udc_mach_info *info)
  84. {
  85. memcpy(&pxa_udc_info, info, sizeof *info);
  86. }
  87. static struct resource pxa2xx_udc_resources[] = {
  88. [0] = {
  89. .start = 0x40600000,
  90. .end = 0x4060ffff,
  91. .flags = IORESOURCE_MEM,
  92. },
  93. [1] = {
  94. .start = IRQ_USB,
  95. .end = IRQ_USB,
  96. .flags = IORESOURCE_IRQ,
  97. },
  98. };
  99. static u64 udc_dma_mask = ~(u32)0;
  100. struct platform_device pxa25x_device_udc = {
  101. .name = "pxa25x-udc",
  102. .id = -1,
  103. .resource = pxa2xx_udc_resources,
  104. .num_resources = ARRAY_SIZE(pxa2xx_udc_resources),
  105. .dev = {
  106. .platform_data = &pxa_udc_info,
  107. .dma_mask = &udc_dma_mask,
  108. }
  109. };
  110. struct platform_device pxa27x_device_udc = {
  111. .name = "pxa27x-udc",
  112. .id = -1,
  113. .resource = pxa2xx_udc_resources,
  114. .num_resources = ARRAY_SIZE(pxa2xx_udc_resources),
  115. .dev = {
  116. .platform_data = &pxa_udc_info,
  117. .dma_mask = &udc_dma_mask,
  118. }
  119. };
  120. #ifdef CONFIG_PXA3xx
  121. static struct resource pxa3xx_u2d_resources[] = {
  122. [0] = {
  123. .start = 0x54100000,
  124. .end = 0x54100fff,
  125. .flags = IORESOURCE_MEM,
  126. },
  127. [1] = {
  128. .start = IRQ_USB2,
  129. .end = IRQ_USB2,
  130. .flags = IORESOURCE_IRQ,
  131. },
  132. };
  133. struct platform_device pxa3xx_device_u2d = {
  134. .name = "pxa3xx-u2d",
  135. .id = -1,
  136. .resource = pxa3xx_u2d_resources,
  137. .num_resources = ARRAY_SIZE(pxa3xx_u2d_resources),
  138. };
  139. void __init pxa3xx_set_u2d_info(struct pxa3xx_u2d_platform_data *info)
  140. {
  141. pxa_register_device(&pxa3xx_device_u2d, info);
  142. }
  143. #endif /* CONFIG_PXA3xx */
  144. static struct resource pxafb_resources[] = {
  145. [0] = {
  146. .start = 0x44000000,
  147. .end = 0x4400ffff,
  148. .flags = IORESOURCE_MEM,
  149. },
  150. [1] = {
  151. .start = IRQ_LCD,
  152. .end = IRQ_LCD,
  153. .flags = IORESOURCE_IRQ,
  154. },
  155. };
  156. static u64 fb_dma_mask = ~(u64)0;
  157. struct platform_device pxa_device_fb = {
  158. .name = "pxa2xx-fb",
  159. .id = -1,
  160. .dev = {
  161. .dma_mask = &fb_dma_mask,
  162. .coherent_dma_mask = 0xffffffff,
  163. },
  164. .num_resources = ARRAY_SIZE(pxafb_resources),
  165. .resource = pxafb_resources,
  166. };
  167. void __init pxa_set_fb_info(struct device *parent, struct pxafb_mach_info *info)
  168. {
  169. pxa_device_fb.dev.parent = parent;
  170. pxa_register_device(&pxa_device_fb, info);
  171. }
  172. static struct resource pxa_resource_ffuart[] = {
  173. {
  174. .start = 0x40100000,
  175. .end = 0x40100023,
  176. .flags = IORESOURCE_MEM,
  177. }, {
  178. .start = IRQ_FFUART,
  179. .end = IRQ_FFUART,
  180. .flags = IORESOURCE_IRQ,
  181. }
  182. };
  183. struct platform_device pxa_device_ffuart = {
  184. .name = "pxa2xx-uart",
  185. .id = 0,
  186. .resource = pxa_resource_ffuart,
  187. .num_resources = ARRAY_SIZE(pxa_resource_ffuart),
  188. };
  189. void __init pxa_set_ffuart_info(void *info)
  190. {
  191. pxa_register_device(&pxa_device_ffuart, info);
  192. }
  193. static struct resource pxa_resource_btuart[] = {
  194. {
  195. .start = 0x40200000,
  196. .end = 0x40200023,
  197. .flags = IORESOURCE_MEM,
  198. }, {
  199. .start = IRQ_BTUART,
  200. .end = IRQ_BTUART,
  201. .flags = IORESOURCE_IRQ,
  202. }
  203. };
  204. struct platform_device pxa_device_btuart = {
  205. .name = "pxa2xx-uart",
  206. .id = 1,
  207. .resource = pxa_resource_btuart,
  208. .num_resources = ARRAY_SIZE(pxa_resource_btuart),
  209. };
  210. void __init pxa_set_btuart_info(void *info)
  211. {
  212. pxa_register_device(&pxa_device_btuart, info);
  213. }
  214. static struct resource pxa_resource_stuart[] = {
  215. {
  216. .start = 0x40700000,
  217. .end = 0x40700023,
  218. .flags = IORESOURCE_MEM,
  219. }, {
  220. .start = IRQ_STUART,
  221. .end = IRQ_STUART,
  222. .flags = IORESOURCE_IRQ,
  223. }
  224. };
  225. struct platform_device pxa_device_stuart = {
  226. .name = "pxa2xx-uart",
  227. .id = 2,
  228. .resource = pxa_resource_stuart,
  229. .num_resources = ARRAY_SIZE(pxa_resource_stuart),
  230. };
  231. void __init pxa_set_stuart_info(void *info)
  232. {
  233. pxa_register_device(&pxa_device_stuart, info);
  234. }
  235. static struct resource pxa_resource_hwuart[] = {
  236. {
  237. .start = 0x41600000,
  238. .end = 0x4160002F,
  239. .flags = IORESOURCE_MEM,
  240. }, {
  241. .start = IRQ_HWUART,
  242. .end = IRQ_HWUART,
  243. .flags = IORESOURCE_IRQ,
  244. }
  245. };
  246. struct platform_device pxa_device_hwuart = {
  247. .name = "pxa2xx-uart",
  248. .id = 3,
  249. .resource = pxa_resource_hwuart,
  250. .num_resources = ARRAY_SIZE(pxa_resource_hwuart),
  251. };
  252. void __init pxa_set_hwuart_info(void *info)
  253. {
  254. if (cpu_is_pxa255())
  255. pxa_register_device(&pxa_device_hwuart, info);
  256. else
  257. pr_info("UART: Ignoring attempt to register HWUART on non-PXA255 hardware");
  258. }
  259. static struct resource pxai2c_resources[] = {
  260. {
  261. .start = 0x40301680,
  262. .end = 0x403016a3,
  263. .flags = IORESOURCE_MEM,
  264. }, {
  265. .start = IRQ_I2C,
  266. .end = IRQ_I2C,
  267. .flags = IORESOURCE_IRQ,
  268. },
  269. };
  270. struct platform_device pxa_device_i2c = {
  271. .name = "pxa2xx-i2c",
  272. .id = 0,
  273. .resource = pxai2c_resources,
  274. .num_resources = ARRAY_SIZE(pxai2c_resources),
  275. };
  276. void __init pxa_set_i2c_info(struct i2c_pxa_platform_data *info)
  277. {
  278. pxa_register_device(&pxa_device_i2c, info);
  279. }
  280. #ifdef CONFIG_PXA27x
  281. static struct resource pxa27x_resources_i2c_power[] = {
  282. {
  283. .start = 0x40f00180,
  284. .end = 0x40f001a3,
  285. .flags = IORESOURCE_MEM,
  286. }, {
  287. .start = IRQ_PWRI2C,
  288. .end = IRQ_PWRI2C,
  289. .flags = IORESOURCE_IRQ,
  290. },
  291. };
  292. struct platform_device pxa27x_device_i2c_power = {
  293. .name = "pxa2xx-i2c",
  294. .id = 1,
  295. .resource = pxa27x_resources_i2c_power,
  296. .num_resources = ARRAY_SIZE(pxa27x_resources_i2c_power),
  297. };
  298. #endif
  299. static struct resource pxai2s_resources[] = {
  300. {
  301. .start = 0x40400000,
  302. .end = 0x40400083,
  303. .flags = IORESOURCE_MEM,
  304. }, {
  305. .start = IRQ_I2S,
  306. .end = IRQ_I2S,
  307. .flags = IORESOURCE_IRQ,
  308. },
  309. };
  310. struct platform_device pxa_device_i2s = {
  311. .name = "pxa2xx-i2s",
  312. .id = -1,
  313. .resource = pxai2s_resources,
  314. .num_resources = ARRAY_SIZE(pxai2s_resources),
  315. };
  316. struct platform_device pxa_device_asoc_ssp1 = {
  317. .name = "pxa-ssp-dai",
  318. .id = 0,
  319. };
  320. struct platform_device pxa_device_asoc_ssp2= {
  321. .name = "pxa-ssp-dai",
  322. .id = 1,
  323. };
  324. struct platform_device pxa_device_asoc_ssp3 = {
  325. .name = "pxa-ssp-dai",
  326. .id = 2,
  327. };
  328. struct platform_device pxa_device_asoc_ssp4 = {
  329. .name = "pxa-ssp-dai",
  330. .id = 3,
  331. };
  332. struct platform_device pxa_device_asoc_platform = {
  333. .name = "pxa-pcm-audio",
  334. .id = -1,
  335. };
  336. static u64 pxaficp_dmamask = ~(u32)0;
  337. static struct resource pxa_ir_resources[] = {
  338. [0] = {
  339. .start = IRQ_STUART,
  340. .end = IRQ_STUART,
  341. .flags = IORESOURCE_IRQ,
  342. },
  343. [1] = {
  344. .start = IRQ_ICP,
  345. .end = IRQ_ICP,
  346. .flags = IORESOURCE_IRQ,
  347. },
  348. [3] = {
  349. .start = 0x40800000,
  350. .end = 0x4080001b,
  351. .flags = IORESOURCE_MEM,
  352. },
  353. [4] = {
  354. .start = 0x40700000,
  355. .end = 0x40700023,
  356. .flags = IORESOURCE_MEM,
  357. },
  358. [5] = {
  359. .start = 17,
  360. .end = 17,
  361. .flags = IORESOURCE_DMA,
  362. },
  363. [6] = {
  364. .start = 18,
  365. .end = 18,
  366. .flags = IORESOURCE_DMA,
  367. },
  368. };
  369. struct platform_device pxa_device_ficp = {
  370. .name = "pxa2xx-ir",
  371. .id = -1,
  372. .num_resources = ARRAY_SIZE(pxa_ir_resources),
  373. .resource = pxa_ir_resources,
  374. .dev = {
  375. .dma_mask = &pxaficp_dmamask,
  376. .coherent_dma_mask = 0xffffffff,
  377. },
  378. };
  379. void __init pxa_set_ficp_info(struct pxaficp_platform_data *info)
  380. {
  381. pxa_register_device(&pxa_device_ficp, info);
  382. }
  383. static struct resource pxa_rtc_resources[] = {
  384. [0] = {
  385. .start = 0x40900000,
  386. .end = 0x40900000 + 0x3b,
  387. .flags = IORESOURCE_MEM,
  388. },
  389. [1] = {
  390. .start = IRQ_RTC1Hz,
  391. .end = IRQ_RTC1Hz,
  392. .name = "rtc 1Hz",
  393. .flags = IORESOURCE_IRQ,
  394. },
  395. [2] = {
  396. .start = IRQ_RTCAlrm,
  397. .end = IRQ_RTCAlrm,
  398. .name = "rtc alarm",
  399. .flags = IORESOURCE_IRQ,
  400. },
  401. };
  402. struct platform_device pxa_device_rtc = {
  403. .name = "pxa-rtc",
  404. .id = -1,
  405. .num_resources = ARRAY_SIZE(pxa_rtc_resources),
  406. .resource = pxa_rtc_resources,
  407. };
  408. struct platform_device sa1100_device_rtc = {
  409. .name = "sa1100-rtc",
  410. .id = -1,
  411. .num_resources = ARRAY_SIZE(pxa_rtc_resources),
  412. .resource = pxa_rtc_resources,
  413. };
  414. static struct resource pxa_ac97_resources[] = {
  415. [0] = {
  416. .start = 0x40500000,
  417. .end = 0x40500000 + 0xfff,
  418. .flags = IORESOURCE_MEM,
  419. },
  420. [1] = {
  421. .start = IRQ_AC97,
  422. .end = IRQ_AC97,
  423. .flags = IORESOURCE_IRQ,
  424. },
  425. };
  426. static u64 pxa_ac97_dmamask = 0xffffffffUL;
  427. struct platform_device pxa_device_ac97 = {
  428. .name = "pxa2xx-ac97",
  429. .id = -1,
  430. .dev = {
  431. .dma_mask = &pxa_ac97_dmamask,
  432. .coherent_dma_mask = 0xffffffff,
  433. },
  434. .num_resources = ARRAY_SIZE(pxa_ac97_resources),
  435. .resource = pxa_ac97_resources,
  436. };
  437. void __init pxa_set_ac97_info(pxa2xx_audio_ops_t *ops)
  438. {
  439. pxa_register_device(&pxa_device_ac97, ops);
  440. }
  441. #ifdef CONFIG_PXA25x
  442. static struct resource pxa25x_resource_pwm0[] = {
  443. [0] = {
  444. .start = 0x40b00000,
  445. .end = 0x40b0000f,
  446. .flags = IORESOURCE_MEM,
  447. },
  448. };
  449. struct platform_device pxa25x_device_pwm0 = {
  450. .name = "pxa25x-pwm",
  451. .id = 0,
  452. .resource = pxa25x_resource_pwm0,
  453. .num_resources = ARRAY_SIZE(pxa25x_resource_pwm0),
  454. };
  455. static struct resource pxa25x_resource_pwm1[] = {
  456. [0] = {
  457. .start = 0x40c00000,
  458. .end = 0x40c0000f,
  459. .flags = IORESOURCE_MEM,
  460. },
  461. };
  462. struct platform_device pxa25x_device_pwm1 = {
  463. .name = "pxa25x-pwm",
  464. .id = 1,
  465. .resource = pxa25x_resource_pwm1,
  466. .num_resources = ARRAY_SIZE(pxa25x_resource_pwm1),
  467. };
  468. static u64 pxa25x_ssp_dma_mask = DMA_BIT_MASK(32);
  469. static struct resource pxa25x_resource_ssp[] = {
  470. [0] = {
  471. .start = 0x41000000,
  472. .end = 0x4100001f,
  473. .flags = IORESOURCE_MEM,
  474. },
  475. [1] = {
  476. .start = IRQ_SSP,
  477. .end = IRQ_SSP,
  478. .flags = IORESOURCE_IRQ,
  479. },
  480. [2] = {
  481. /* DRCMR for RX */
  482. .start = 13,
  483. .end = 13,
  484. .flags = IORESOURCE_DMA,
  485. },
  486. [3] = {
  487. /* DRCMR for TX */
  488. .start = 14,
  489. .end = 14,
  490. .flags = IORESOURCE_DMA,
  491. },
  492. };
  493. struct platform_device pxa25x_device_ssp = {
  494. .name = "pxa25x-ssp",
  495. .id = 0,
  496. .dev = {
  497. .dma_mask = &pxa25x_ssp_dma_mask,
  498. .coherent_dma_mask = DMA_BIT_MASK(32),
  499. },
  500. .resource = pxa25x_resource_ssp,
  501. .num_resources = ARRAY_SIZE(pxa25x_resource_ssp),
  502. };
  503. static u64 pxa25x_nssp_dma_mask = DMA_BIT_MASK(32);
  504. static struct resource pxa25x_resource_nssp[] = {
  505. [0] = {
  506. .start = 0x41400000,
  507. .end = 0x4140002f,
  508. .flags = IORESOURCE_MEM,
  509. },
  510. [1] = {
  511. .start = IRQ_NSSP,
  512. .end = IRQ_NSSP,
  513. .flags = IORESOURCE_IRQ,
  514. },
  515. [2] = {
  516. /* DRCMR for RX */
  517. .start = 15,
  518. .end = 15,
  519. .flags = IORESOURCE_DMA,
  520. },
  521. [3] = {
  522. /* DRCMR for TX */
  523. .start = 16,
  524. .end = 16,
  525. .flags = IORESOURCE_DMA,
  526. },
  527. };
  528. struct platform_device pxa25x_device_nssp = {
  529. .name = "pxa25x-nssp",
  530. .id = 1,
  531. .dev = {
  532. .dma_mask = &pxa25x_nssp_dma_mask,
  533. .coherent_dma_mask = DMA_BIT_MASK(32),
  534. },
  535. .resource = pxa25x_resource_nssp,
  536. .num_resources = ARRAY_SIZE(pxa25x_resource_nssp),
  537. };
  538. static u64 pxa25x_assp_dma_mask = DMA_BIT_MASK(32);
  539. static struct resource pxa25x_resource_assp[] = {
  540. [0] = {
  541. .start = 0x41500000,
  542. .end = 0x4150002f,
  543. .flags = IORESOURCE_MEM,
  544. },
  545. [1] = {
  546. .start = IRQ_ASSP,
  547. .end = IRQ_ASSP,
  548. .flags = IORESOURCE_IRQ,
  549. },
  550. [2] = {
  551. /* DRCMR for RX */
  552. .start = 23,
  553. .end = 23,
  554. .flags = IORESOURCE_DMA,
  555. },
  556. [3] = {
  557. /* DRCMR for TX */
  558. .start = 24,
  559. .end = 24,
  560. .flags = IORESOURCE_DMA,
  561. },
  562. };
  563. struct platform_device pxa25x_device_assp = {
  564. /* ASSP is basically equivalent to NSSP */
  565. .name = "pxa25x-nssp",
  566. .id = 2,
  567. .dev = {
  568. .dma_mask = &pxa25x_assp_dma_mask,
  569. .coherent_dma_mask = DMA_BIT_MASK(32),
  570. },
  571. .resource = pxa25x_resource_assp,
  572. .num_resources = ARRAY_SIZE(pxa25x_resource_assp),
  573. };
  574. #endif /* CONFIG_PXA25x */
  575. #if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
  576. static struct resource pxa27x_resource_camera[] = {
  577. [0] = {
  578. .start = 0x50000000,
  579. .end = 0x50000fff,
  580. .flags = IORESOURCE_MEM,
  581. },
  582. [1] = {
  583. .start = IRQ_CAMERA,
  584. .end = IRQ_CAMERA,
  585. .flags = IORESOURCE_IRQ,
  586. },
  587. };
  588. static u64 pxa27x_dma_mask_camera = DMA_BIT_MASK(32);
  589. static struct platform_device pxa27x_device_camera = {
  590. .name = "pxa27x-camera",
  591. .id = 0, /* This is used to put cameras on this interface */
  592. .dev = {
  593. .dma_mask = &pxa27x_dma_mask_camera,
  594. .coherent_dma_mask = 0xffffffff,
  595. },
  596. .num_resources = ARRAY_SIZE(pxa27x_resource_camera),
  597. .resource = pxa27x_resource_camera,
  598. };
  599. void __init pxa_set_camera_info(struct pxacamera_platform_data *info)
  600. {
  601. pxa_register_device(&pxa27x_device_camera, info);
  602. }
  603. static u64 pxa27x_ohci_dma_mask = DMA_BIT_MASK(32);
  604. static struct resource pxa27x_resource_ohci[] = {
  605. [0] = {
  606. .start = 0x4C000000,
  607. .end = 0x4C00ff6f,
  608. .flags = IORESOURCE_MEM,
  609. },
  610. [1] = {
  611. .start = IRQ_USBH1,
  612. .end = IRQ_USBH1,
  613. .flags = IORESOURCE_IRQ,
  614. },
  615. };
  616. struct platform_device pxa27x_device_ohci = {
  617. .name = "pxa27x-ohci",
  618. .id = -1,
  619. .dev = {
  620. .dma_mask = &pxa27x_ohci_dma_mask,
  621. .coherent_dma_mask = DMA_BIT_MASK(32),
  622. },
  623. .num_resources = ARRAY_SIZE(pxa27x_resource_ohci),
  624. .resource = pxa27x_resource_ohci,
  625. };
  626. void __init pxa_set_ohci_info(struct pxaohci_platform_data *info)
  627. {
  628. pxa_register_device(&pxa27x_device_ohci, info);
  629. }
  630. #endif /* CONFIG_PXA27x || CONFIG_PXA3xx */
  631. #if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
  632. static struct resource pxa27x_resource_keypad[] = {
  633. [0] = {
  634. .start = 0x41500000,
  635. .end = 0x4150004c,
  636. .flags = IORESOURCE_MEM,
  637. },
  638. [1] = {
  639. .start = IRQ_KEYPAD,
  640. .end = IRQ_KEYPAD,
  641. .flags = IORESOURCE_IRQ,
  642. },
  643. };
  644. struct platform_device pxa27x_device_keypad = {
  645. .name = "pxa27x-keypad",
  646. .id = -1,
  647. .resource = pxa27x_resource_keypad,
  648. .num_resources = ARRAY_SIZE(pxa27x_resource_keypad),
  649. };
  650. void __init pxa_set_keypad_info(struct pxa27x_keypad_platform_data *info)
  651. {
  652. pxa_register_device(&pxa27x_device_keypad, info);
  653. }
  654. static u64 pxa27x_ssp1_dma_mask = DMA_BIT_MASK(32);
  655. static struct resource pxa27x_resource_ssp1[] = {
  656. [0] = {
  657. .start = 0x41000000,
  658. .end = 0x4100003f,
  659. .flags = IORESOURCE_MEM,
  660. },
  661. [1] = {
  662. .start = IRQ_SSP,
  663. .end = IRQ_SSP,
  664. .flags = IORESOURCE_IRQ,
  665. },
  666. [2] = {
  667. /* DRCMR for RX */
  668. .start = 13,
  669. .end = 13,
  670. .flags = IORESOURCE_DMA,
  671. },
  672. [3] = {
  673. /* DRCMR for TX */
  674. .start = 14,
  675. .end = 14,
  676. .flags = IORESOURCE_DMA,
  677. },
  678. };
  679. struct platform_device pxa27x_device_ssp1 = {
  680. .name = "pxa27x-ssp",
  681. .id = 0,
  682. .dev = {
  683. .dma_mask = &pxa27x_ssp1_dma_mask,
  684. .coherent_dma_mask = DMA_BIT_MASK(32),
  685. },
  686. .resource = pxa27x_resource_ssp1,
  687. .num_resources = ARRAY_SIZE(pxa27x_resource_ssp1),
  688. };
  689. static u64 pxa27x_ssp2_dma_mask = DMA_BIT_MASK(32);
  690. static struct resource pxa27x_resource_ssp2[] = {
  691. [0] = {
  692. .start = 0x41700000,
  693. .end = 0x4170003f,
  694. .flags = IORESOURCE_MEM,
  695. },
  696. [1] = {
  697. .start = IRQ_SSP2,
  698. .end = IRQ_SSP2,
  699. .flags = IORESOURCE_IRQ,
  700. },
  701. [2] = {
  702. /* DRCMR for RX */
  703. .start = 15,
  704. .end = 15,
  705. .flags = IORESOURCE_DMA,
  706. },
  707. [3] = {
  708. /* DRCMR for TX */
  709. .start = 16,
  710. .end = 16,
  711. .flags = IORESOURCE_DMA,
  712. },
  713. };
  714. struct platform_device pxa27x_device_ssp2 = {
  715. .name = "pxa27x-ssp",
  716. .id = 1,
  717. .dev = {
  718. .dma_mask = &pxa27x_ssp2_dma_mask,
  719. .coherent_dma_mask = DMA_BIT_MASK(32),
  720. },
  721. .resource = pxa27x_resource_ssp2,
  722. .num_resources = ARRAY_SIZE(pxa27x_resource_ssp2),
  723. };
  724. static u64 pxa27x_ssp3_dma_mask = DMA_BIT_MASK(32);
  725. static struct resource pxa27x_resource_ssp3[] = {
  726. [0] = {
  727. .start = 0x41900000,
  728. .end = 0x4190003f,
  729. .flags = IORESOURCE_MEM,
  730. },
  731. [1] = {
  732. .start = IRQ_SSP3,
  733. .end = IRQ_SSP3,
  734. .flags = IORESOURCE_IRQ,
  735. },
  736. [2] = {
  737. /* DRCMR for RX */
  738. .start = 66,
  739. .end = 66,
  740. .flags = IORESOURCE_DMA,
  741. },
  742. [3] = {
  743. /* DRCMR for TX */
  744. .start = 67,
  745. .end = 67,
  746. .flags = IORESOURCE_DMA,
  747. },
  748. };
  749. struct platform_device pxa27x_device_ssp3 = {
  750. .name = "pxa27x-ssp",
  751. .id = 2,
  752. .dev = {
  753. .dma_mask = &pxa27x_ssp3_dma_mask,
  754. .coherent_dma_mask = DMA_BIT_MASK(32),
  755. },
  756. .resource = pxa27x_resource_ssp3,
  757. .num_resources = ARRAY_SIZE(pxa27x_resource_ssp3),
  758. };
  759. static struct resource pxa27x_resource_pwm0[] = {
  760. [0] = {
  761. .start = 0x40b00000,
  762. .end = 0x40b0001f,
  763. .flags = IORESOURCE_MEM,
  764. },
  765. };
  766. struct platform_device pxa27x_device_pwm0 = {
  767. .name = "pxa27x-pwm",
  768. .id = 0,
  769. .resource = pxa27x_resource_pwm0,
  770. .num_resources = ARRAY_SIZE(pxa27x_resource_pwm0),
  771. };
  772. static struct resource pxa27x_resource_pwm1[] = {
  773. [0] = {
  774. .start = 0x40c00000,
  775. .end = 0x40c0001f,
  776. .flags = IORESOURCE_MEM,
  777. },
  778. };
  779. struct platform_device pxa27x_device_pwm1 = {
  780. .name = "pxa27x-pwm",
  781. .id = 1,
  782. .resource = pxa27x_resource_pwm1,
  783. .num_resources = ARRAY_SIZE(pxa27x_resource_pwm1),
  784. };
  785. #endif /* CONFIG_PXA27x || CONFIG_PXA3xx */
  786. #ifdef CONFIG_PXA3xx
  787. static struct resource pxa3xx_resources_mci2[] = {
  788. [0] = {
  789. .start = 0x42000000,
  790. .end = 0x42000fff,
  791. .flags = IORESOURCE_MEM,
  792. },
  793. [1] = {
  794. .start = IRQ_MMC2,
  795. .end = IRQ_MMC2,
  796. .flags = IORESOURCE_IRQ,
  797. },
  798. [2] = {
  799. .start = 93,
  800. .end = 93,
  801. .flags = IORESOURCE_DMA,
  802. },
  803. [3] = {
  804. .start = 94,
  805. .end = 94,
  806. .flags = IORESOURCE_DMA,
  807. },
  808. };
  809. struct platform_device pxa3xx_device_mci2 = {
  810. .name = "pxa2xx-mci",
  811. .id = 1,
  812. .dev = {
  813. .dma_mask = &pxamci_dmamask,
  814. .coherent_dma_mask = 0xffffffff,
  815. },
  816. .num_resources = ARRAY_SIZE(pxa3xx_resources_mci2),
  817. .resource = pxa3xx_resources_mci2,
  818. };
  819. void __init pxa3xx_set_mci2_info(struct pxamci_platform_data *info)
  820. {
  821. pxa_register_device(&pxa3xx_device_mci2, info);
  822. }
  823. static struct resource pxa3xx_resources_mci3[] = {
  824. [0] = {
  825. .start = 0x42500000,
  826. .end = 0x42500fff,
  827. .flags = IORESOURCE_MEM,
  828. },
  829. [1] = {
  830. .start = IRQ_MMC3,
  831. .end = IRQ_MMC3,
  832. .flags = IORESOURCE_IRQ,
  833. },
  834. [2] = {
  835. .start = 100,
  836. .end = 100,
  837. .flags = IORESOURCE_DMA,
  838. },
  839. [3] = {
  840. .start = 101,
  841. .end = 101,
  842. .flags = IORESOURCE_DMA,
  843. },
  844. };
  845. struct platform_device pxa3xx_device_mci3 = {
  846. .name = "pxa2xx-mci",
  847. .id = 2,
  848. .dev = {
  849. .dma_mask = &pxamci_dmamask,
  850. .coherent_dma_mask = 0xffffffff,
  851. },
  852. .num_resources = ARRAY_SIZE(pxa3xx_resources_mci3),
  853. .resource = pxa3xx_resources_mci3,
  854. };
  855. void __init pxa3xx_set_mci3_info(struct pxamci_platform_data *info)
  856. {
  857. pxa_register_device(&pxa3xx_device_mci3, info);
  858. }
  859. static struct resource pxa3xx_resources_gcu[] = {
  860. {
  861. .start = 0x54000000,
  862. .end = 0x54000fff,
  863. .flags = IORESOURCE_MEM,
  864. },
  865. {
  866. .start = IRQ_GCU,
  867. .end = IRQ_GCU,
  868. .flags = IORESOURCE_IRQ,
  869. },
  870. };
  871. static u64 pxa3xx_gcu_dmamask = DMA_BIT_MASK(32);
  872. struct platform_device pxa3xx_device_gcu = {
  873. .name = "pxa3xx-gcu",
  874. .id = -1,
  875. .num_resources = ARRAY_SIZE(pxa3xx_resources_gcu),
  876. .resource = pxa3xx_resources_gcu,
  877. .dev = {
  878. .dma_mask = &pxa3xx_gcu_dmamask,
  879. .coherent_dma_mask = 0xffffffff,
  880. },
  881. };
  882. #endif /* CONFIG_PXA3xx */
  883. #if defined(CONFIG_PXA3xx)
  884. static struct resource pxa3xx_resources_i2c_power[] = {
  885. {
  886. .start = 0x40f500c0,
  887. .end = 0x40f500d3,
  888. .flags = IORESOURCE_MEM,
  889. }, {
  890. .start = IRQ_PWRI2C,
  891. .end = IRQ_PWRI2C,
  892. .flags = IORESOURCE_IRQ,
  893. },
  894. };
  895. struct platform_device pxa3xx_device_i2c_power = {
  896. .name = "pxa3xx-pwri2c",
  897. .id = 1,
  898. .resource = pxa3xx_resources_i2c_power,
  899. .num_resources = ARRAY_SIZE(pxa3xx_resources_i2c_power),
  900. };
  901. static struct resource pxa3xx_resources_nand[] = {
  902. [0] = {
  903. .start = 0x43100000,
  904. .end = 0x43100053,
  905. .flags = IORESOURCE_MEM,
  906. },
  907. [1] = {
  908. .start = IRQ_NAND,
  909. .end = IRQ_NAND,
  910. .flags = IORESOURCE_IRQ,
  911. },
  912. [2] = {
  913. /* DRCMR for Data DMA */
  914. .start = 97,
  915. .end = 97,
  916. .flags = IORESOURCE_DMA,
  917. },
  918. [3] = {
  919. /* DRCMR for Command DMA */
  920. .start = 99,
  921. .end = 99,
  922. .flags = IORESOURCE_DMA,
  923. },
  924. };
  925. static u64 pxa3xx_nand_dma_mask = DMA_BIT_MASK(32);
  926. struct platform_device pxa3xx_device_nand = {
  927. .name = "pxa3xx-nand",
  928. .id = -1,
  929. .dev = {
  930. .dma_mask = &pxa3xx_nand_dma_mask,
  931. .coherent_dma_mask = DMA_BIT_MASK(32),
  932. },
  933. .num_resources = ARRAY_SIZE(pxa3xx_resources_nand),
  934. .resource = pxa3xx_resources_nand,
  935. };
  936. void __init pxa3xx_set_nand_info(struct pxa3xx_nand_platform_data *info)
  937. {
  938. pxa_register_device(&pxa3xx_device_nand, info);
  939. }
  940. static u64 pxa3xx_ssp4_dma_mask = DMA_BIT_MASK(32);
  941. static struct resource pxa3xx_resource_ssp4[] = {
  942. [0] = {
  943. .start = 0x41a00000,
  944. .end = 0x41a0003f,
  945. .flags = IORESOURCE_MEM,
  946. },
  947. [1] = {
  948. .start = IRQ_SSP4,
  949. .end = IRQ_SSP4,
  950. .flags = IORESOURCE_IRQ,
  951. },
  952. [2] = {
  953. /* DRCMR for RX */
  954. .start = 2,
  955. .end = 2,
  956. .flags = IORESOURCE_DMA,
  957. },
  958. [3] = {
  959. /* DRCMR for TX */
  960. .start = 3,
  961. .end = 3,
  962. .flags = IORESOURCE_DMA,
  963. },
  964. };
  965. /*
  966. * PXA3xx SSP is basically equivalent to PXA27x.
  967. * However, we need to register the device by the correct name in order to
  968. * make the driver set the correct internal type, hence we provide specific
  969. * platform_devices for each of them.
  970. */
  971. struct platform_device pxa3xx_device_ssp1 = {
  972. .name = "pxa3xx-ssp",
  973. .id = 0,
  974. .dev = {
  975. .dma_mask = &pxa27x_ssp1_dma_mask,
  976. .coherent_dma_mask = DMA_BIT_MASK(32),
  977. },
  978. .resource = pxa27x_resource_ssp1,
  979. .num_resources = ARRAY_SIZE(pxa27x_resource_ssp1),
  980. };
  981. struct platform_device pxa3xx_device_ssp2 = {
  982. .name = "pxa3xx-ssp",
  983. .id = 1,
  984. .dev = {
  985. .dma_mask = &pxa27x_ssp2_dma_mask,
  986. .coherent_dma_mask = DMA_BIT_MASK(32),
  987. },
  988. .resource = pxa27x_resource_ssp2,
  989. .num_resources = ARRAY_SIZE(pxa27x_resource_ssp2),
  990. };
  991. struct platform_device pxa3xx_device_ssp3 = {
  992. .name = "pxa3xx-ssp",
  993. .id = 2,
  994. .dev = {
  995. .dma_mask = &pxa27x_ssp3_dma_mask,
  996. .coherent_dma_mask = DMA_BIT_MASK(32),
  997. },
  998. .resource = pxa27x_resource_ssp3,
  999. .num_resources = ARRAY_SIZE(pxa27x_resource_ssp3),
  1000. };
  1001. struct platform_device pxa3xx_device_ssp4 = {
  1002. .name = "pxa3xx-ssp",
  1003. .id = 3,
  1004. .dev = {
  1005. .dma_mask = &pxa3xx_ssp4_dma_mask,
  1006. .coherent_dma_mask = DMA_BIT_MASK(32),
  1007. },
  1008. .resource = pxa3xx_resource_ssp4,
  1009. .num_resources = ARRAY_SIZE(pxa3xx_resource_ssp4),
  1010. };
  1011. #endif /* CONFIG_PXA3xx */
  1012. struct resource pxa_resource_gpio[] = {
  1013. {
  1014. .start = 0x40e00000,
  1015. .end = 0x40e0ffff,
  1016. .flags = IORESOURCE_MEM,
  1017. }, {
  1018. .start = IRQ_GPIO0,
  1019. .end = IRQ_GPIO0,
  1020. .name = "gpio0",
  1021. .flags = IORESOURCE_IRQ,
  1022. }, {
  1023. .start = IRQ_GPIO1,
  1024. .end = IRQ_GPIO1,
  1025. .name = "gpio1",
  1026. .flags = IORESOURCE_IRQ,
  1027. }, {
  1028. .start = IRQ_GPIO_2_x,
  1029. .end = IRQ_GPIO_2_x,
  1030. .name = "gpio_mux",
  1031. .flags = IORESOURCE_IRQ,
  1032. },
  1033. };
  1034. struct platform_device pxa25x_device_gpio = {
  1035. #ifdef CONFIG_CPU_PXA26x
  1036. .name = "pxa26x-gpio",
  1037. #else
  1038. .name = "pxa25x-gpio",
  1039. #endif
  1040. .id = -1,
  1041. .num_resources = ARRAY_SIZE(pxa_resource_gpio),
  1042. .resource = pxa_resource_gpio,
  1043. };
  1044. struct platform_device pxa27x_device_gpio = {
  1045. .name = "pxa27x-gpio",
  1046. .id = -1,
  1047. .num_resources = ARRAY_SIZE(pxa_resource_gpio),
  1048. .resource = pxa_resource_gpio,
  1049. };
  1050. struct platform_device pxa3xx_device_gpio = {
  1051. .name = "pxa3xx-gpio",
  1052. .id = -1,
  1053. .num_resources = ARRAY_SIZE(pxa_resource_gpio),
  1054. .resource = pxa_resource_gpio,
  1055. };
  1056. struct platform_device pxa93x_device_gpio = {
  1057. .name = "pxa93x-gpio",
  1058. .id = -1,
  1059. .num_resources = ARRAY_SIZE(pxa_resource_gpio),
  1060. .resource = pxa_resource_gpio,
  1061. };
  1062. /* pxa2xx-spi platform-device ID equals respective SSP platform-device ID + 1.
  1063. * See comment in arch/arm/mach-pxa/ssp.c::ssp_probe() */
  1064. void __init pxa2xx_set_spi_info(unsigned id, struct pxa2xx_spi_master *info)
  1065. {
  1066. struct platform_device *pd;
  1067. pd = platform_device_alloc("pxa2xx-spi", id);
  1068. if (pd == NULL) {
  1069. printk(KERN_ERR "pxa2xx-spi: failed to allocate device id %d\n",
  1070. id);
  1071. return;
  1072. }
  1073. pd->dev.platform_data = info;
  1074. platform_device_add(pd);
  1075. }
  1076. static struct mmp_dma_platdata pxa_dma_pdata = {
  1077. .dma_channels = 0,
  1078. .nb_requestors = 0,
  1079. };
  1080. static struct resource pxa_dma_resource[] = {
  1081. [0] = {
  1082. .start = 0x40000000,
  1083. .end = 0x4000ffff,
  1084. .flags = IORESOURCE_MEM,
  1085. },
  1086. [1] = {
  1087. .start = IRQ_DMA,
  1088. .end = IRQ_DMA,
  1089. .flags = IORESOURCE_IRQ,
  1090. },
  1091. };
  1092. static u64 pxadma_dmamask = 0xffffffffUL;
  1093. static struct platform_device pxa2xx_pxa_dma = {
  1094. .name = "pxa-dma",
  1095. .id = 0,
  1096. .dev = {
  1097. .dma_mask = &pxadma_dmamask,
  1098. .coherent_dma_mask = 0xffffffff,
  1099. },
  1100. .num_resources = ARRAY_SIZE(pxa_dma_resource),
  1101. .resource = pxa_dma_resource,
  1102. };
  1103. void __init pxa2xx_set_dmac_info(int nb_channels, int nb_requestors)
  1104. {
  1105. pxa_dma_pdata.dma_channels = nb_channels;
  1106. pxa_dma_pdata.nb_requestors = nb_requestors;
  1107. pxa_register_device(&pxa2xx_pxa_dma, &pxa_dma_pdata);
  1108. }