amdgpu_gart.c 10 KB

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  1. /*
  2. * Copyright 2008 Advanced Micro Devices, Inc.
  3. * Copyright 2008 Red Hat Inc.
  4. * Copyright 2009 Jerome Glisse.
  5. *
  6. * Permission is hereby granted, free of charge, to any person obtaining a
  7. * copy of this software and associated documentation files (the "Software"),
  8. * to deal in the Software without restriction, including without limitation
  9. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10. * and/or sell copies of the Software, and to permit persons to whom the
  11. * Software is furnished to do so, subject to the following conditions:
  12. *
  13. * The above copyright notice and this permission notice shall be included in
  14. * all copies or substantial portions of the Software.
  15. *
  16. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19. * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20. * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21. * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22. * OTHER DEALINGS IN THE SOFTWARE.
  23. *
  24. * Authors: Dave Airlie
  25. * Alex Deucher
  26. * Jerome Glisse
  27. */
  28. #include <drm/drmP.h>
  29. #include <drm/amdgpu_drm.h>
  30. #ifdef CONFIG_X86
  31. #include <asm/set_memory.h>
  32. #endif
  33. #include "amdgpu.h"
  34. /*
  35. * GART
  36. * The GART (Graphics Aperture Remapping Table) is an aperture
  37. * in the GPU's address space. System pages can be mapped into
  38. * the aperture and look like contiguous pages from the GPU's
  39. * perspective. A page table maps the pages in the aperture
  40. * to the actual backing pages in system memory.
  41. *
  42. * Radeon GPUs support both an internal GART, as described above,
  43. * and AGP. AGP works similarly, but the GART table is configured
  44. * and maintained by the northbridge rather than the driver.
  45. * Radeon hw has a separate AGP aperture that is programmed to
  46. * point to the AGP aperture provided by the northbridge and the
  47. * requests are passed through to the northbridge aperture.
  48. * Both AGP and internal GART can be used at the same time, however
  49. * that is not currently supported by the driver.
  50. *
  51. * This file handles the common internal GART management.
  52. */
  53. /*
  54. * Common GART table functions.
  55. */
  56. /**
  57. * amdgpu_dummy_page_init - init dummy page used by the driver
  58. *
  59. * @adev: amdgpu_device pointer
  60. *
  61. * Allocate the dummy page used by the driver (all asics).
  62. * This dummy page is used by the driver as a filler for gart entries
  63. * when pages are taken out of the GART
  64. * Returns 0 on sucess, -ENOMEM on failure.
  65. */
  66. static int amdgpu_gart_dummy_page_init(struct amdgpu_device *adev)
  67. {
  68. struct page *dummy_page = adev->mman.bdev.glob->dummy_read_page;
  69. if (adev->dummy_page_addr)
  70. return 0;
  71. adev->dummy_page_addr = pci_map_page(adev->pdev, dummy_page, 0,
  72. PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
  73. if (pci_dma_mapping_error(adev->pdev, adev->dummy_page_addr)) {
  74. dev_err(&adev->pdev->dev, "Failed to DMA MAP the dummy page\n");
  75. adev->dummy_page_addr = 0;
  76. return -ENOMEM;
  77. }
  78. return 0;
  79. }
  80. /**
  81. * amdgpu_dummy_page_fini - free dummy page used by the driver
  82. *
  83. * @adev: amdgpu_device pointer
  84. *
  85. * Frees the dummy page used by the driver (all asics).
  86. */
  87. static void amdgpu_gart_dummy_page_fini(struct amdgpu_device *adev)
  88. {
  89. if (!adev->dummy_page_addr)
  90. return;
  91. pci_unmap_page(adev->pdev, adev->dummy_page_addr,
  92. PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
  93. adev->dummy_page_addr = 0;
  94. }
  95. /**
  96. * amdgpu_gart_table_vram_alloc - allocate vram for gart page table
  97. *
  98. * @adev: amdgpu_device pointer
  99. *
  100. * Allocate video memory for GART page table
  101. * (pcie r4xx, r5xx+). These asics require the
  102. * gart table to be in video memory.
  103. * Returns 0 for success, error for failure.
  104. */
  105. int amdgpu_gart_table_vram_alloc(struct amdgpu_device *adev)
  106. {
  107. int r;
  108. if (adev->gart.bo == NULL) {
  109. struct amdgpu_bo_param bp;
  110. memset(&bp, 0, sizeof(bp));
  111. bp.size = adev->gart.table_size;
  112. bp.byte_align = PAGE_SIZE;
  113. bp.domain = AMDGPU_GEM_DOMAIN_VRAM;
  114. bp.flags = AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
  115. AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
  116. bp.type = ttm_bo_type_kernel;
  117. bp.resv = NULL;
  118. r = amdgpu_bo_create(adev, &bp, &adev->gart.bo);
  119. if (r) {
  120. return r;
  121. }
  122. }
  123. return 0;
  124. }
  125. /**
  126. * amdgpu_gart_table_vram_pin - pin gart page table in vram
  127. *
  128. * @adev: amdgpu_device pointer
  129. *
  130. * Pin the GART page table in vram so it will not be moved
  131. * by the memory manager (pcie r4xx, r5xx+). These asics require the
  132. * gart table to be in video memory.
  133. * Returns 0 for success, error for failure.
  134. */
  135. int amdgpu_gart_table_vram_pin(struct amdgpu_device *adev)
  136. {
  137. int r;
  138. r = amdgpu_bo_reserve(adev->gart.bo, false);
  139. if (unlikely(r != 0))
  140. return r;
  141. r = amdgpu_bo_pin(adev->gart.bo, AMDGPU_GEM_DOMAIN_VRAM);
  142. if (r) {
  143. amdgpu_bo_unreserve(adev->gart.bo);
  144. return r;
  145. }
  146. r = amdgpu_bo_kmap(adev->gart.bo, &adev->gart.ptr);
  147. if (r)
  148. amdgpu_bo_unpin(adev->gart.bo);
  149. amdgpu_bo_unreserve(adev->gart.bo);
  150. return r;
  151. }
  152. /**
  153. * amdgpu_gart_table_vram_unpin - unpin gart page table in vram
  154. *
  155. * @adev: amdgpu_device pointer
  156. *
  157. * Unpin the GART page table in vram (pcie r4xx, r5xx+).
  158. * These asics require the gart table to be in video memory.
  159. */
  160. void amdgpu_gart_table_vram_unpin(struct amdgpu_device *adev)
  161. {
  162. int r;
  163. if (adev->gart.bo == NULL) {
  164. return;
  165. }
  166. r = amdgpu_bo_reserve(adev->gart.bo, true);
  167. if (likely(r == 0)) {
  168. amdgpu_bo_kunmap(adev->gart.bo);
  169. amdgpu_bo_unpin(adev->gart.bo);
  170. amdgpu_bo_unreserve(adev->gart.bo);
  171. adev->gart.ptr = NULL;
  172. }
  173. }
  174. /**
  175. * amdgpu_gart_table_vram_free - free gart page table vram
  176. *
  177. * @adev: amdgpu_device pointer
  178. *
  179. * Free the video memory used for the GART page table
  180. * (pcie r4xx, r5xx+). These asics require the gart table to
  181. * be in video memory.
  182. */
  183. void amdgpu_gart_table_vram_free(struct amdgpu_device *adev)
  184. {
  185. if (adev->gart.bo == NULL) {
  186. return;
  187. }
  188. amdgpu_bo_unref(&adev->gart.bo);
  189. }
  190. /*
  191. * Common gart functions.
  192. */
  193. /**
  194. * amdgpu_gart_unbind - unbind pages from the gart page table
  195. *
  196. * @adev: amdgpu_device pointer
  197. * @offset: offset into the GPU's gart aperture
  198. * @pages: number of pages to unbind
  199. *
  200. * Unbinds the requested pages from the gart page table and
  201. * replaces them with the dummy page (all asics).
  202. * Returns 0 for success, -EINVAL for failure.
  203. */
  204. int amdgpu_gart_unbind(struct amdgpu_device *adev, uint64_t offset,
  205. int pages)
  206. {
  207. unsigned t;
  208. unsigned p;
  209. int i, j;
  210. u64 page_base;
  211. /* Starting from VEGA10, system bit must be 0 to mean invalid. */
  212. uint64_t flags = 0;
  213. if (!adev->gart.ready) {
  214. WARN(1, "trying to unbind memory from uninitialized GART !\n");
  215. return -EINVAL;
  216. }
  217. t = offset / AMDGPU_GPU_PAGE_SIZE;
  218. p = t / AMDGPU_GPU_PAGES_IN_CPU_PAGE;
  219. for (i = 0; i < pages; i++, p++) {
  220. #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
  221. adev->gart.pages[p] = NULL;
  222. #endif
  223. page_base = adev->dummy_page_addr;
  224. if (!adev->gart.ptr)
  225. continue;
  226. for (j = 0; j < AMDGPU_GPU_PAGES_IN_CPU_PAGE; j++, t++) {
  227. amdgpu_gmc_set_pte_pde(adev, adev->gart.ptr,
  228. t, page_base, flags);
  229. page_base += AMDGPU_GPU_PAGE_SIZE;
  230. }
  231. }
  232. mb();
  233. amdgpu_asic_flush_hdp(adev, NULL);
  234. amdgpu_gmc_flush_gpu_tlb(adev, 0);
  235. return 0;
  236. }
  237. /**
  238. * amdgpu_gart_map - map dma_addresses into GART entries
  239. *
  240. * @adev: amdgpu_device pointer
  241. * @offset: offset into the GPU's gart aperture
  242. * @pages: number of pages to bind
  243. * @dma_addr: DMA addresses of pages
  244. *
  245. * Map the dma_addresses into GART entries (all asics).
  246. * Returns 0 for success, -EINVAL for failure.
  247. */
  248. int amdgpu_gart_map(struct amdgpu_device *adev, uint64_t offset,
  249. int pages, dma_addr_t *dma_addr, uint64_t flags,
  250. void *dst)
  251. {
  252. uint64_t page_base;
  253. unsigned i, j, t;
  254. if (!adev->gart.ready) {
  255. WARN(1, "trying to bind memory to uninitialized GART !\n");
  256. return -EINVAL;
  257. }
  258. t = offset / AMDGPU_GPU_PAGE_SIZE;
  259. for (i = 0; i < pages; i++) {
  260. page_base = dma_addr[i];
  261. for (j = 0; j < AMDGPU_GPU_PAGES_IN_CPU_PAGE; j++, t++) {
  262. amdgpu_gmc_set_pte_pde(adev, dst, t, page_base, flags);
  263. page_base += AMDGPU_GPU_PAGE_SIZE;
  264. }
  265. }
  266. return 0;
  267. }
  268. /**
  269. * amdgpu_gart_bind - bind pages into the gart page table
  270. *
  271. * @adev: amdgpu_device pointer
  272. * @offset: offset into the GPU's gart aperture
  273. * @pages: number of pages to bind
  274. * @pagelist: pages to bind
  275. * @dma_addr: DMA addresses of pages
  276. *
  277. * Binds the requested pages to the gart page table
  278. * (all asics).
  279. * Returns 0 for success, -EINVAL for failure.
  280. */
  281. int amdgpu_gart_bind(struct amdgpu_device *adev, uint64_t offset,
  282. int pages, struct page **pagelist, dma_addr_t *dma_addr,
  283. uint64_t flags)
  284. {
  285. #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
  286. unsigned i,t,p;
  287. #endif
  288. int r;
  289. if (!adev->gart.ready) {
  290. WARN(1, "trying to bind memory to uninitialized GART !\n");
  291. return -EINVAL;
  292. }
  293. #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
  294. t = offset / AMDGPU_GPU_PAGE_SIZE;
  295. p = t / AMDGPU_GPU_PAGES_IN_CPU_PAGE;
  296. for (i = 0; i < pages; i++, p++)
  297. adev->gart.pages[p] = pagelist ? pagelist[i] : NULL;
  298. #endif
  299. if (!adev->gart.ptr)
  300. return 0;
  301. r = amdgpu_gart_map(adev, offset, pages, dma_addr, flags,
  302. adev->gart.ptr);
  303. if (r)
  304. return r;
  305. mb();
  306. amdgpu_asic_flush_hdp(adev, NULL);
  307. amdgpu_gmc_flush_gpu_tlb(adev, 0);
  308. return 0;
  309. }
  310. /**
  311. * amdgpu_gart_init - init the driver info for managing the gart
  312. *
  313. * @adev: amdgpu_device pointer
  314. *
  315. * Allocate the dummy page and init the gart driver info (all asics).
  316. * Returns 0 for success, error for failure.
  317. */
  318. int amdgpu_gart_init(struct amdgpu_device *adev)
  319. {
  320. int r;
  321. if (adev->dummy_page_addr)
  322. return 0;
  323. /* We need PAGE_SIZE >= AMDGPU_GPU_PAGE_SIZE */
  324. if (PAGE_SIZE < AMDGPU_GPU_PAGE_SIZE) {
  325. DRM_ERROR("Page size is smaller than GPU page size!\n");
  326. return -EINVAL;
  327. }
  328. r = amdgpu_gart_dummy_page_init(adev);
  329. if (r)
  330. return r;
  331. /* Compute table size */
  332. adev->gart.num_cpu_pages = adev->gmc.gart_size / PAGE_SIZE;
  333. adev->gart.num_gpu_pages = adev->gmc.gart_size / AMDGPU_GPU_PAGE_SIZE;
  334. DRM_INFO("GART: num cpu pages %u, num gpu pages %u\n",
  335. adev->gart.num_cpu_pages, adev->gart.num_gpu_pages);
  336. #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
  337. /* Allocate pages table */
  338. adev->gart.pages = vzalloc(array_size(sizeof(void *),
  339. adev->gart.num_cpu_pages));
  340. if (adev->gart.pages == NULL)
  341. return -ENOMEM;
  342. #endif
  343. return 0;
  344. }
  345. /**
  346. * amdgpu_gart_fini - tear down the driver info for managing the gart
  347. *
  348. * @adev: amdgpu_device pointer
  349. *
  350. * Tear down the gart driver info and free the dummy page (all asics).
  351. */
  352. void amdgpu_gart_fini(struct amdgpu_device *adev)
  353. {
  354. #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
  355. vfree(adev->gart.pages);
  356. adev->gart.pages = NULL;
  357. #endif
  358. amdgpu_gart_dummy_page_fini(adev);
  359. }