amdgpu_fb.c 10 KB

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  1. /*
  2. * Copyright © 2007 David Airlie
  3. *
  4. * Permission is hereby granted, free of charge, to any person obtaining a
  5. * copy of this software and associated documentation files (the "Software"),
  6. * to deal in the Software without restriction, including without limitation
  7. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8. * and/or sell copies of the Software, and to permit persons to whom the
  9. * Software is furnished to do so, subject to the following conditions:
  10. *
  11. * The above copyright notice and this permission notice (including the next
  12. * paragraph) shall be included in all copies or substantial portions of the
  13. * Software.
  14. *
  15. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  18. * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20. * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21. * DEALINGS IN THE SOFTWARE.
  22. *
  23. * Authors:
  24. * David Airlie
  25. */
  26. #include <linux/module.h>
  27. #include <linux/slab.h>
  28. #include <linux/pm_runtime.h>
  29. #include <drm/drmP.h>
  30. #include <drm/drm_crtc.h>
  31. #include <drm/drm_crtc_helper.h>
  32. #include <drm/amdgpu_drm.h>
  33. #include "amdgpu.h"
  34. #include "cikd.h"
  35. #include "amdgpu_gem.h"
  36. #include <drm/drm_fb_helper.h>
  37. #include <linux/vga_switcheroo.h>
  38. #include "amdgpu_display.h"
  39. /* object hierarchy -
  40. this contains a helper + a amdgpu fb
  41. the helper contains a pointer to amdgpu framebuffer baseclass.
  42. */
  43. static int
  44. amdgpufb_open(struct fb_info *info, int user)
  45. {
  46. struct amdgpu_fbdev *rfbdev = info->par;
  47. struct amdgpu_device *adev = rfbdev->adev;
  48. int ret = pm_runtime_get_sync(adev->ddev->dev);
  49. if (ret < 0 && ret != -EACCES) {
  50. pm_runtime_mark_last_busy(adev->ddev->dev);
  51. pm_runtime_put_autosuspend(adev->ddev->dev);
  52. return ret;
  53. }
  54. return 0;
  55. }
  56. static int
  57. amdgpufb_release(struct fb_info *info, int user)
  58. {
  59. struct amdgpu_fbdev *rfbdev = info->par;
  60. struct amdgpu_device *adev = rfbdev->adev;
  61. pm_runtime_mark_last_busy(adev->ddev->dev);
  62. pm_runtime_put_autosuspend(adev->ddev->dev);
  63. return 0;
  64. }
  65. static struct fb_ops amdgpufb_ops = {
  66. .owner = THIS_MODULE,
  67. DRM_FB_HELPER_DEFAULT_OPS,
  68. .fb_open = amdgpufb_open,
  69. .fb_release = amdgpufb_release,
  70. .fb_fillrect = drm_fb_helper_cfb_fillrect,
  71. .fb_copyarea = drm_fb_helper_cfb_copyarea,
  72. .fb_imageblit = drm_fb_helper_cfb_imageblit,
  73. };
  74. int amdgpu_align_pitch(struct amdgpu_device *adev, int width, int cpp, bool tiled)
  75. {
  76. int aligned = width;
  77. int pitch_mask = 0;
  78. switch (cpp) {
  79. case 1:
  80. pitch_mask = 255;
  81. break;
  82. case 2:
  83. pitch_mask = 127;
  84. break;
  85. case 3:
  86. case 4:
  87. pitch_mask = 63;
  88. break;
  89. }
  90. aligned += pitch_mask;
  91. aligned &= ~pitch_mask;
  92. return aligned * cpp;
  93. }
  94. static void amdgpufb_destroy_pinned_object(struct drm_gem_object *gobj)
  95. {
  96. struct amdgpu_bo *abo = gem_to_amdgpu_bo(gobj);
  97. int ret;
  98. ret = amdgpu_bo_reserve(abo, true);
  99. if (likely(ret == 0)) {
  100. amdgpu_bo_kunmap(abo);
  101. amdgpu_bo_unpin(abo);
  102. amdgpu_bo_unreserve(abo);
  103. }
  104. drm_gem_object_put_unlocked(gobj);
  105. }
  106. static int amdgpufb_create_pinned_object(struct amdgpu_fbdev *rfbdev,
  107. struct drm_mode_fb_cmd2 *mode_cmd,
  108. struct drm_gem_object **gobj_p)
  109. {
  110. struct amdgpu_device *adev = rfbdev->adev;
  111. struct drm_gem_object *gobj = NULL;
  112. struct amdgpu_bo *abo = NULL;
  113. bool fb_tiled = false; /* useful for testing */
  114. u32 tiling_flags = 0, domain;
  115. int ret;
  116. int aligned_size, size;
  117. int height = mode_cmd->height;
  118. u32 cpp;
  119. cpp = drm_format_plane_cpp(mode_cmd->pixel_format, 0);
  120. /* need to align pitch with crtc limits */
  121. mode_cmd->pitches[0] = amdgpu_align_pitch(adev, mode_cmd->width, cpp,
  122. fb_tiled);
  123. domain = amdgpu_display_supported_domains(adev);
  124. height = ALIGN(mode_cmd->height, 8);
  125. size = mode_cmd->pitches[0] * height;
  126. aligned_size = ALIGN(size, PAGE_SIZE);
  127. ret = amdgpu_gem_object_create(adev, aligned_size, 0, domain,
  128. AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
  129. AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS |
  130. AMDGPU_GEM_CREATE_VRAM_CLEARED,
  131. ttm_bo_type_kernel, NULL, &gobj);
  132. if (ret) {
  133. pr_err("failed to allocate framebuffer (%d)\n", aligned_size);
  134. return -ENOMEM;
  135. }
  136. abo = gem_to_amdgpu_bo(gobj);
  137. if (fb_tiled)
  138. tiling_flags = AMDGPU_TILING_SET(ARRAY_MODE, GRPH_ARRAY_2D_TILED_THIN1);
  139. ret = amdgpu_bo_reserve(abo, false);
  140. if (unlikely(ret != 0))
  141. goto out_unref;
  142. if (tiling_flags) {
  143. ret = amdgpu_bo_set_tiling_flags(abo,
  144. tiling_flags);
  145. if (ret)
  146. dev_err(adev->dev, "FB failed to set tiling flags\n");
  147. }
  148. ret = amdgpu_bo_pin(abo, domain);
  149. if (ret) {
  150. amdgpu_bo_unreserve(abo);
  151. goto out_unref;
  152. }
  153. ret = amdgpu_ttm_alloc_gart(&abo->tbo);
  154. if (ret) {
  155. amdgpu_bo_unreserve(abo);
  156. dev_err(adev->dev, "%p bind failed\n", abo);
  157. goto out_unref;
  158. }
  159. ret = amdgpu_bo_kmap(abo, NULL);
  160. amdgpu_bo_unreserve(abo);
  161. if (ret) {
  162. goto out_unref;
  163. }
  164. *gobj_p = gobj;
  165. return 0;
  166. out_unref:
  167. amdgpufb_destroy_pinned_object(gobj);
  168. *gobj_p = NULL;
  169. return ret;
  170. }
  171. static int amdgpufb_create(struct drm_fb_helper *helper,
  172. struct drm_fb_helper_surface_size *sizes)
  173. {
  174. struct amdgpu_fbdev *rfbdev = (struct amdgpu_fbdev *)helper;
  175. struct amdgpu_device *adev = rfbdev->adev;
  176. struct fb_info *info;
  177. struct drm_framebuffer *fb = NULL;
  178. struct drm_mode_fb_cmd2 mode_cmd;
  179. struct drm_gem_object *gobj = NULL;
  180. struct amdgpu_bo *abo = NULL;
  181. int ret;
  182. unsigned long tmp;
  183. mode_cmd.width = sizes->surface_width;
  184. mode_cmd.height = sizes->surface_height;
  185. if (sizes->surface_bpp == 24)
  186. sizes->surface_bpp = 32;
  187. mode_cmd.pixel_format = drm_mode_legacy_fb_format(sizes->surface_bpp,
  188. sizes->surface_depth);
  189. ret = amdgpufb_create_pinned_object(rfbdev, &mode_cmd, &gobj);
  190. if (ret) {
  191. DRM_ERROR("failed to create fbcon object %d\n", ret);
  192. return ret;
  193. }
  194. abo = gem_to_amdgpu_bo(gobj);
  195. /* okay we have an object now allocate the framebuffer */
  196. info = drm_fb_helper_alloc_fbi(helper);
  197. if (IS_ERR(info)) {
  198. ret = PTR_ERR(info);
  199. goto out;
  200. }
  201. info->par = rfbdev;
  202. info->skip_vt_switch = true;
  203. ret = amdgpu_display_framebuffer_init(adev->ddev, &rfbdev->rfb,
  204. &mode_cmd, gobj);
  205. if (ret) {
  206. DRM_ERROR("failed to initialize framebuffer %d\n", ret);
  207. goto out;
  208. }
  209. fb = &rfbdev->rfb.base;
  210. /* setup helper */
  211. rfbdev->helper.fb = fb;
  212. strcpy(info->fix.id, "amdgpudrmfb");
  213. drm_fb_helper_fill_fix(info, fb->pitches[0], fb->format->depth);
  214. info->fbops = &amdgpufb_ops;
  215. tmp = amdgpu_bo_gpu_offset(abo) - adev->gmc.vram_start;
  216. info->fix.smem_start = adev->gmc.aper_base + tmp;
  217. info->fix.smem_len = amdgpu_bo_size(abo);
  218. info->screen_base = amdgpu_bo_kptr(abo);
  219. info->screen_size = amdgpu_bo_size(abo);
  220. drm_fb_helper_fill_var(info, &rfbdev->helper, sizes->fb_width, sizes->fb_height);
  221. /* setup aperture base/size for vesafb takeover */
  222. info->apertures->ranges[0].base = adev->ddev->mode_config.fb_base;
  223. info->apertures->ranges[0].size = adev->gmc.aper_size;
  224. /* Use default scratch pixmap (info->pixmap.flags = FB_PIXMAP_SYSTEM) */
  225. if (info->screen_base == NULL) {
  226. ret = -ENOSPC;
  227. goto out;
  228. }
  229. DRM_INFO("fb mappable at 0x%lX\n", info->fix.smem_start);
  230. DRM_INFO("vram apper at 0x%lX\n", (unsigned long)adev->gmc.aper_base);
  231. DRM_INFO("size %lu\n", (unsigned long)amdgpu_bo_size(abo));
  232. DRM_INFO("fb depth is %d\n", fb->format->depth);
  233. DRM_INFO(" pitch is %d\n", fb->pitches[0]);
  234. vga_switcheroo_client_fb_set(adev->ddev->pdev, info);
  235. return 0;
  236. out:
  237. if (abo) {
  238. }
  239. if (fb && ret) {
  240. drm_gem_object_put_unlocked(gobj);
  241. drm_framebuffer_unregister_private(fb);
  242. drm_framebuffer_cleanup(fb);
  243. kfree(fb);
  244. }
  245. return ret;
  246. }
  247. static int amdgpu_fbdev_destroy(struct drm_device *dev, struct amdgpu_fbdev *rfbdev)
  248. {
  249. struct amdgpu_framebuffer *rfb = &rfbdev->rfb;
  250. drm_fb_helper_unregister_fbi(&rfbdev->helper);
  251. if (rfb->base.obj[0]) {
  252. amdgpufb_destroy_pinned_object(rfb->base.obj[0]);
  253. rfb->base.obj[0] = NULL;
  254. drm_framebuffer_unregister_private(&rfb->base);
  255. drm_framebuffer_cleanup(&rfb->base);
  256. }
  257. drm_fb_helper_fini(&rfbdev->helper);
  258. return 0;
  259. }
  260. static const struct drm_fb_helper_funcs amdgpu_fb_helper_funcs = {
  261. .fb_probe = amdgpufb_create,
  262. };
  263. int amdgpu_fbdev_init(struct amdgpu_device *adev)
  264. {
  265. struct amdgpu_fbdev *rfbdev;
  266. int bpp_sel = 32;
  267. int ret;
  268. /* don't init fbdev on hw without DCE */
  269. if (!adev->mode_info.mode_config_initialized)
  270. return 0;
  271. /* don't init fbdev if there are no connectors */
  272. if (list_empty(&adev->ddev->mode_config.connector_list))
  273. return 0;
  274. /* select 8 bpp console on low vram cards */
  275. if (adev->gmc.real_vram_size <= (32*1024*1024))
  276. bpp_sel = 8;
  277. rfbdev = kzalloc(sizeof(struct amdgpu_fbdev), GFP_KERNEL);
  278. if (!rfbdev)
  279. return -ENOMEM;
  280. rfbdev->adev = adev;
  281. adev->mode_info.rfbdev = rfbdev;
  282. drm_fb_helper_prepare(adev->ddev, &rfbdev->helper,
  283. &amdgpu_fb_helper_funcs);
  284. ret = drm_fb_helper_init(adev->ddev, &rfbdev->helper,
  285. AMDGPUFB_CONN_LIMIT);
  286. if (ret) {
  287. kfree(rfbdev);
  288. return ret;
  289. }
  290. drm_fb_helper_single_add_all_connectors(&rfbdev->helper);
  291. /* disable all the possible outputs/crtcs before entering KMS mode */
  292. if (!amdgpu_device_has_dc_support(adev))
  293. drm_helper_disable_unused_functions(adev->ddev);
  294. drm_fb_helper_initial_config(&rfbdev->helper, bpp_sel);
  295. return 0;
  296. }
  297. void amdgpu_fbdev_fini(struct amdgpu_device *adev)
  298. {
  299. if (!adev->mode_info.rfbdev)
  300. return;
  301. amdgpu_fbdev_destroy(adev->ddev, adev->mode_info.rfbdev);
  302. kfree(adev->mode_info.rfbdev);
  303. adev->mode_info.rfbdev = NULL;
  304. }
  305. void amdgpu_fbdev_set_suspend(struct amdgpu_device *adev, int state)
  306. {
  307. if (adev->mode_info.rfbdev)
  308. drm_fb_helper_set_suspend_unlocked(&adev->mode_info.rfbdev->helper,
  309. state);
  310. }
  311. int amdgpu_fbdev_total_size(struct amdgpu_device *adev)
  312. {
  313. struct amdgpu_bo *robj;
  314. int size = 0;
  315. if (!adev->mode_info.rfbdev)
  316. return 0;
  317. robj = gem_to_amdgpu_bo(adev->mode_info.rfbdev->rfb.base.obj[0]);
  318. size += amdgpu_bo_size(robj);
  319. return size;
  320. }
  321. bool amdgpu_fbdev_robj_is_fb(struct amdgpu_device *adev, struct amdgpu_bo *robj)
  322. {
  323. if (!adev->mode_info.rfbdev)
  324. return false;
  325. if (robj == gem_to_amdgpu_bo(adev->mode_info.rfbdev->rfb.base.obj[0]))
  326. return true;
  327. return false;
  328. }