r8152.c 91 KB

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  1. /*
  2. * Copyright (c) 2014 Realtek Semiconductor Corp. All rights reserved.
  3. *
  4. * This program is free software; you can redistribute it and/or
  5. * modify it under the terms of the GNU General Public License
  6. * version 2 as published by the Free Software Foundation.
  7. *
  8. */
  9. #include <linux/signal.h>
  10. #include <linux/slab.h>
  11. #include <linux/module.h>
  12. #include <linux/netdevice.h>
  13. #include <linux/etherdevice.h>
  14. #include <linux/mii.h>
  15. #include <linux/ethtool.h>
  16. #include <linux/usb.h>
  17. #include <linux/crc32.h>
  18. #include <linux/if_vlan.h>
  19. #include <linux/uaccess.h>
  20. #include <linux/list.h>
  21. #include <linux/ip.h>
  22. #include <linux/ipv6.h>
  23. #include <net/ip6_checksum.h>
  24. #include <uapi/linux/mdio.h>
  25. #include <linux/mdio.h>
  26. #include <linux/usb/cdc.h>
  27. /* Version Information */
  28. #define DRIVER_VERSION "v1.08.0 (2015/01/13)"
  29. #define DRIVER_AUTHOR "Realtek linux nic maintainers <nic_swsd@realtek.com>"
  30. #define DRIVER_DESC "Realtek RTL8152/RTL8153 Based USB Ethernet Adapters"
  31. #define MODULENAME "r8152"
  32. #define R8152_PHY_ID 32
  33. #define PLA_IDR 0xc000
  34. #define PLA_RCR 0xc010
  35. #define PLA_RMS 0xc016
  36. #define PLA_RXFIFO_CTRL0 0xc0a0
  37. #define PLA_RXFIFO_CTRL1 0xc0a4
  38. #define PLA_RXFIFO_CTRL2 0xc0a8
  39. #define PLA_FMC 0xc0b4
  40. #define PLA_CFG_WOL 0xc0b6
  41. #define PLA_TEREDO_CFG 0xc0bc
  42. #define PLA_MAR 0xcd00
  43. #define PLA_BACKUP 0xd000
  44. #define PAL_BDC_CR 0xd1a0
  45. #define PLA_TEREDO_TIMER 0xd2cc
  46. #define PLA_REALWOW_TIMER 0xd2e8
  47. #define PLA_LEDSEL 0xdd90
  48. #define PLA_LED_FEATURE 0xdd92
  49. #define PLA_PHYAR 0xde00
  50. #define PLA_BOOT_CTRL 0xe004
  51. #define PLA_GPHY_INTR_IMR 0xe022
  52. #define PLA_EEE_CR 0xe040
  53. #define PLA_EEEP_CR 0xe080
  54. #define PLA_MAC_PWR_CTRL 0xe0c0
  55. #define PLA_MAC_PWR_CTRL2 0xe0ca
  56. #define PLA_MAC_PWR_CTRL3 0xe0cc
  57. #define PLA_MAC_PWR_CTRL4 0xe0ce
  58. #define PLA_WDT6_CTRL 0xe428
  59. #define PLA_TCR0 0xe610
  60. #define PLA_TCR1 0xe612
  61. #define PLA_MTPS 0xe615
  62. #define PLA_TXFIFO_CTRL 0xe618
  63. #define PLA_RSTTALLY 0xe800
  64. #define PLA_CR 0xe813
  65. #define PLA_CRWECR 0xe81c
  66. #define PLA_CONFIG12 0xe81e /* CONFIG1, CONFIG2 */
  67. #define PLA_CONFIG34 0xe820 /* CONFIG3, CONFIG4 */
  68. #define PLA_CONFIG5 0xe822
  69. #define PLA_PHY_PWR 0xe84c
  70. #define PLA_OOB_CTRL 0xe84f
  71. #define PLA_CPCR 0xe854
  72. #define PLA_MISC_0 0xe858
  73. #define PLA_MISC_1 0xe85a
  74. #define PLA_OCP_GPHY_BASE 0xe86c
  75. #define PLA_TALLYCNT 0xe890
  76. #define PLA_SFF_STS_7 0xe8de
  77. #define PLA_PHYSTATUS 0xe908
  78. #define PLA_BP_BA 0xfc26
  79. #define PLA_BP_0 0xfc28
  80. #define PLA_BP_1 0xfc2a
  81. #define PLA_BP_2 0xfc2c
  82. #define PLA_BP_3 0xfc2e
  83. #define PLA_BP_4 0xfc30
  84. #define PLA_BP_5 0xfc32
  85. #define PLA_BP_6 0xfc34
  86. #define PLA_BP_7 0xfc36
  87. #define PLA_BP_EN 0xfc38
  88. #define USB_U2P3_CTRL 0xb460
  89. #define USB_DEV_STAT 0xb808
  90. #define USB_USB_CTRL 0xd406
  91. #define USB_PHY_CTRL 0xd408
  92. #define USB_TX_AGG 0xd40a
  93. #define USB_RX_BUF_TH 0xd40c
  94. #define USB_USB_TIMER 0xd428
  95. #define USB_RX_EARLY_AGG 0xd42c
  96. #define USB_PM_CTRL_STATUS 0xd432
  97. #define USB_TX_DMA 0xd434
  98. #define USB_TOLERANCE 0xd490
  99. #define USB_LPM_CTRL 0xd41a
  100. #define USB_UPS_CTRL 0xd800
  101. #define USB_MISC_0 0xd81a
  102. #define USB_POWER_CUT 0xd80a
  103. #define USB_AFE_CTRL2 0xd824
  104. #define USB_WDT11_CTRL 0xe43c
  105. #define USB_BP_BA 0xfc26
  106. #define USB_BP_0 0xfc28
  107. #define USB_BP_1 0xfc2a
  108. #define USB_BP_2 0xfc2c
  109. #define USB_BP_3 0xfc2e
  110. #define USB_BP_4 0xfc30
  111. #define USB_BP_5 0xfc32
  112. #define USB_BP_6 0xfc34
  113. #define USB_BP_7 0xfc36
  114. #define USB_BP_EN 0xfc38
  115. /* OCP Registers */
  116. #define OCP_ALDPS_CONFIG 0x2010
  117. #define OCP_EEE_CONFIG1 0x2080
  118. #define OCP_EEE_CONFIG2 0x2092
  119. #define OCP_EEE_CONFIG3 0x2094
  120. #define OCP_BASE_MII 0xa400
  121. #define OCP_EEE_AR 0xa41a
  122. #define OCP_EEE_DATA 0xa41c
  123. #define OCP_PHY_STATUS 0xa420
  124. #define OCP_POWER_CFG 0xa430
  125. #define OCP_EEE_CFG 0xa432
  126. #define OCP_SRAM_ADDR 0xa436
  127. #define OCP_SRAM_DATA 0xa438
  128. #define OCP_DOWN_SPEED 0xa442
  129. #define OCP_EEE_ABLE 0xa5c4
  130. #define OCP_EEE_ADV 0xa5d0
  131. #define OCP_EEE_LPABLE 0xa5d2
  132. #define OCP_ADC_CFG 0xbc06
  133. /* SRAM Register */
  134. #define SRAM_LPF_CFG 0x8012
  135. #define SRAM_10M_AMP1 0x8080
  136. #define SRAM_10M_AMP2 0x8082
  137. #define SRAM_IMPEDANCE 0x8084
  138. /* PLA_RCR */
  139. #define RCR_AAP 0x00000001
  140. #define RCR_APM 0x00000002
  141. #define RCR_AM 0x00000004
  142. #define RCR_AB 0x00000008
  143. #define RCR_ACPT_ALL (RCR_AAP | RCR_APM | RCR_AM | RCR_AB)
  144. /* PLA_RXFIFO_CTRL0 */
  145. #define RXFIFO_THR1_NORMAL 0x00080002
  146. #define RXFIFO_THR1_OOB 0x01800003
  147. /* PLA_RXFIFO_CTRL1 */
  148. #define RXFIFO_THR2_FULL 0x00000060
  149. #define RXFIFO_THR2_HIGH 0x00000038
  150. #define RXFIFO_THR2_OOB 0x0000004a
  151. #define RXFIFO_THR2_NORMAL 0x00a0
  152. /* PLA_RXFIFO_CTRL2 */
  153. #define RXFIFO_THR3_FULL 0x00000078
  154. #define RXFIFO_THR3_HIGH 0x00000048
  155. #define RXFIFO_THR3_OOB 0x0000005a
  156. #define RXFIFO_THR3_NORMAL 0x0110
  157. /* PLA_TXFIFO_CTRL */
  158. #define TXFIFO_THR_NORMAL 0x00400008
  159. #define TXFIFO_THR_NORMAL2 0x01000008
  160. /* PLA_FMC */
  161. #define FMC_FCR_MCU_EN 0x0001
  162. /* PLA_EEEP_CR */
  163. #define EEEP_CR_EEEP_TX 0x0002
  164. /* PLA_WDT6_CTRL */
  165. #define WDT6_SET_MODE 0x0010
  166. /* PLA_TCR0 */
  167. #define TCR0_TX_EMPTY 0x0800
  168. #define TCR0_AUTO_FIFO 0x0080
  169. /* PLA_TCR1 */
  170. #define VERSION_MASK 0x7cf0
  171. /* PLA_MTPS */
  172. #define MTPS_JUMBO (12 * 1024 / 64)
  173. #define MTPS_DEFAULT (6 * 1024 / 64)
  174. /* PLA_RSTTALLY */
  175. #define TALLY_RESET 0x0001
  176. /* PLA_CR */
  177. #define CR_RST 0x10
  178. #define CR_RE 0x08
  179. #define CR_TE 0x04
  180. /* PLA_CRWECR */
  181. #define CRWECR_NORAML 0x00
  182. #define CRWECR_CONFIG 0xc0
  183. /* PLA_OOB_CTRL */
  184. #define NOW_IS_OOB 0x80
  185. #define TXFIFO_EMPTY 0x20
  186. #define RXFIFO_EMPTY 0x10
  187. #define LINK_LIST_READY 0x02
  188. #define DIS_MCU_CLROOB 0x01
  189. #define FIFO_EMPTY (TXFIFO_EMPTY | RXFIFO_EMPTY)
  190. /* PLA_MISC_1 */
  191. #define RXDY_GATED_EN 0x0008
  192. /* PLA_SFF_STS_7 */
  193. #define RE_INIT_LL 0x8000
  194. #define MCU_BORW_EN 0x4000
  195. /* PLA_CPCR */
  196. #define CPCR_RX_VLAN 0x0040
  197. /* PLA_CFG_WOL */
  198. #define MAGIC_EN 0x0001
  199. /* PLA_TEREDO_CFG */
  200. #define TEREDO_SEL 0x8000
  201. #define TEREDO_WAKE_MASK 0x7f00
  202. #define TEREDO_RS_EVENT_MASK 0x00fe
  203. #define OOB_TEREDO_EN 0x0001
  204. /* PAL_BDC_CR */
  205. #define ALDPS_PROXY_MODE 0x0001
  206. /* PLA_CONFIG34 */
  207. #define LINK_ON_WAKE_EN 0x0010
  208. #define LINK_OFF_WAKE_EN 0x0008
  209. /* PLA_CONFIG5 */
  210. #define BWF_EN 0x0040
  211. #define MWF_EN 0x0020
  212. #define UWF_EN 0x0010
  213. #define LAN_WAKE_EN 0x0002
  214. /* PLA_LED_FEATURE */
  215. #define LED_MODE_MASK 0x0700
  216. /* PLA_PHY_PWR */
  217. #define TX_10M_IDLE_EN 0x0080
  218. #define PFM_PWM_SWITCH 0x0040
  219. /* PLA_MAC_PWR_CTRL */
  220. #define D3_CLK_GATED_EN 0x00004000
  221. #define MCU_CLK_RATIO 0x07010f07
  222. #define MCU_CLK_RATIO_MASK 0x0f0f0f0f
  223. #define ALDPS_SPDWN_RATIO 0x0f87
  224. /* PLA_MAC_PWR_CTRL2 */
  225. #define EEE_SPDWN_RATIO 0x8007
  226. /* PLA_MAC_PWR_CTRL3 */
  227. #define PKT_AVAIL_SPDWN_EN 0x0100
  228. #define SUSPEND_SPDWN_EN 0x0004
  229. #define U1U2_SPDWN_EN 0x0002
  230. #define L1_SPDWN_EN 0x0001
  231. /* PLA_MAC_PWR_CTRL4 */
  232. #define PWRSAVE_SPDWN_EN 0x1000
  233. #define RXDV_SPDWN_EN 0x0800
  234. #define TX10MIDLE_EN 0x0100
  235. #define TP100_SPDWN_EN 0x0020
  236. #define TP500_SPDWN_EN 0x0010
  237. #define TP1000_SPDWN_EN 0x0008
  238. #define EEE_SPDWN_EN 0x0001
  239. /* PLA_GPHY_INTR_IMR */
  240. #define GPHY_STS_MSK 0x0001
  241. #define SPEED_DOWN_MSK 0x0002
  242. #define SPDWN_RXDV_MSK 0x0004
  243. #define SPDWN_LINKCHG_MSK 0x0008
  244. /* PLA_PHYAR */
  245. #define PHYAR_FLAG 0x80000000
  246. /* PLA_EEE_CR */
  247. #define EEE_RX_EN 0x0001
  248. #define EEE_TX_EN 0x0002
  249. /* PLA_BOOT_CTRL */
  250. #define AUTOLOAD_DONE 0x0002
  251. /* USB_DEV_STAT */
  252. #define STAT_SPEED_MASK 0x0006
  253. #define STAT_SPEED_HIGH 0x0000
  254. #define STAT_SPEED_FULL 0x0002
  255. /* USB_TX_AGG */
  256. #define TX_AGG_MAX_THRESHOLD 0x03
  257. /* USB_RX_BUF_TH */
  258. #define RX_THR_SUPPER 0x0c350180
  259. #define RX_THR_HIGH 0x7a120180
  260. #define RX_THR_SLOW 0xffff0180
  261. /* USB_TX_DMA */
  262. #define TEST_MODE_DISABLE 0x00000001
  263. #define TX_SIZE_ADJUST1 0x00000100
  264. /* USB_UPS_CTRL */
  265. #define POWER_CUT 0x0100
  266. /* USB_PM_CTRL_STATUS */
  267. #define RESUME_INDICATE 0x0001
  268. /* USB_USB_CTRL */
  269. #define RX_AGG_DISABLE 0x0010
  270. /* USB_U2P3_CTRL */
  271. #define U2P3_ENABLE 0x0001
  272. /* USB_POWER_CUT */
  273. #define PWR_EN 0x0001
  274. #define PHASE2_EN 0x0008
  275. /* USB_MISC_0 */
  276. #define PCUT_STATUS 0x0001
  277. /* USB_RX_EARLY_AGG */
  278. #define EARLY_AGG_SUPPER 0x0e832981
  279. #define EARLY_AGG_HIGH 0x0e837a12
  280. #define EARLY_AGG_SLOW 0x0e83ffff
  281. /* USB_WDT11_CTRL */
  282. #define TIMER11_EN 0x0001
  283. /* USB_LPM_CTRL */
  284. #define LPM_TIMER_MASK 0x0c
  285. #define LPM_TIMER_500MS 0x04 /* 500 ms */
  286. #define LPM_TIMER_500US 0x0c /* 500 us */
  287. /* USB_AFE_CTRL2 */
  288. #define SEN_VAL_MASK 0xf800
  289. #define SEN_VAL_NORMAL 0xa000
  290. #define SEL_RXIDLE 0x0100
  291. /* OCP_ALDPS_CONFIG */
  292. #define ENPWRSAVE 0x8000
  293. #define ENPDNPS 0x0200
  294. #define LINKENA 0x0100
  295. #define DIS_SDSAVE 0x0010
  296. /* OCP_PHY_STATUS */
  297. #define PHY_STAT_MASK 0x0007
  298. #define PHY_STAT_LAN_ON 3
  299. #define PHY_STAT_PWRDN 5
  300. /* OCP_POWER_CFG */
  301. #define EEE_CLKDIV_EN 0x8000
  302. #define EN_ALDPS 0x0004
  303. #define EN_10M_PLLOFF 0x0001
  304. /* OCP_EEE_CONFIG1 */
  305. #define RG_TXLPI_MSK_HFDUP 0x8000
  306. #define RG_MATCLR_EN 0x4000
  307. #define EEE_10_CAP 0x2000
  308. #define EEE_NWAY_EN 0x1000
  309. #define TX_QUIET_EN 0x0200
  310. #define RX_QUIET_EN 0x0100
  311. #define sd_rise_time_mask 0x0070
  312. #define sd_rise_time(x) (min(x, 7) << 4) /* bit 4 ~ 6 */
  313. #define RG_RXLPI_MSK_HFDUP 0x0008
  314. #define SDFALLTIME 0x0007 /* bit 0 ~ 2 */
  315. /* OCP_EEE_CONFIG2 */
  316. #define RG_LPIHYS_NUM 0x7000 /* bit 12 ~ 15 */
  317. #define RG_DACQUIET_EN 0x0400
  318. #define RG_LDVQUIET_EN 0x0200
  319. #define RG_CKRSEL 0x0020
  320. #define RG_EEEPRG_EN 0x0010
  321. /* OCP_EEE_CONFIG3 */
  322. #define fast_snr_mask 0xff80
  323. #define fast_snr(x) (min(x, 0x1ff) << 7) /* bit 7 ~ 15 */
  324. #define RG_LFS_SEL 0x0060 /* bit 6 ~ 5 */
  325. #define MSK_PH 0x0006 /* bit 0 ~ 3 */
  326. /* OCP_EEE_AR */
  327. /* bit[15:14] function */
  328. #define FUN_ADDR 0x0000
  329. #define FUN_DATA 0x4000
  330. /* bit[4:0] device addr */
  331. /* OCP_EEE_CFG */
  332. #define CTAP_SHORT_EN 0x0040
  333. #define EEE10_EN 0x0010
  334. /* OCP_DOWN_SPEED */
  335. #define EN_10M_BGOFF 0x0080
  336. /* OCP_ADC_CFG */
  337. #define CKADSEL_L 0x0100
  338. #define ADC_EN 0x0080
  339. #define EN_EMI_L 0x0040
  340. /* SRAM_LPF_CFG */
  341. #define LPF_AUTO_TUNE 0x8000
  342. /* SRAM_10M_AMP1 */
  343. #define GDAC_IB_UPALL 0x0008
  344. /* SRAM_10M_AMP2 */
  345. #define AMP_DN 0x0200
  346. /* SRAM_IMPEDANCE */
  347. #define RX_DRIVING_MASK 0x6000
  348. enum rtl_register_content {
  349. _1000bps = 0x10,
  350. _100bps = 0x08,
  351. _10bps = 0x04,
  352. LINK_STATUS = 0x02,
  353. FULL_DUP = 0x01,
  354. };
  355. #define RTL8152_MAX_TX 4
  356. #define RTL8152_MAX_RX 10
  357. #define INTBUFSIZE 2
  358. #define CRC_SIZE 4
  359. #define TX_ALIGN 4
  360. #define RX_ALIGN 8
  361. #define INTR_LINK 0x0004
  362. #define RTL8152_REQT_READ 0xc0
  363. #define RTL8152_REQT_WRITE 0x40
  364. #define RTL8152_REQ_GET_REGS 0x05
  365. #define RTL8152_REQ_SET_REGS 0x05
  366. #define BYTE_EN_DWORD 0xff
  367. #define BYTE_EN_WORD 0x33
  368. #define BYTE_EN_BYTE 0x11
  369. #define BYTE_EN_SIX_BYTES 0x3f
  370. #define BYTE_EN_START_MASK 0x0f
  371. #define BYTE_EN_END_MASK 0xf0
  372. #define RTL8153_MAX_PACKET 9216 /* 9K */
  373. #define RTL8153_MAX_MTU (RTL8153_MAX_PACKET - VLAN_ETH_HLEN - VLAN_HLEN)
  374. #define RTL8152_RMS (VLAN_ETH_FRAME_LEN + VLAN_HLEN)
  375. #define RTL8153_RMS RTL8153_MAX_PACKET
  376. #define RTL8152_TX_TIMEOUT (5 * HZ)
  377. #define RTL8152_NAPI_WEIGHT 64
  378. /* rtl8152 flags */
  379. enum rtl8152_flags {
  380. RTL8152_UNPLUG = 0,
  381. RTL8152_SET_RX_MODE,
  382. WORK_ENABLE,
  383. RTL8152_LINK_CHG,
  384. SELECTIVE_SUSPEND,
  385. PHY_RESET,
  386. SCHEDULE_NAPI,
  387. };
  388. /* Define these values to match your device */
  389. #define VENDOR_ID_REALTEK 0x0bda
  390. #define VENDOR_ID_SAMSUNG 0x04e8
  391. #define MCU_TYPE_PLA 0x0100
  392. #define MCU_TYPE_USB 0x0000
  393. struct tally_counter {
  394. __le64 tx_packets;
  395. __le64 rx_packets;
  396. __le64 tx_errors;
  397. __le32 rx_errors;
  398. __le16 rx_missed;
  399. __le16 align_errors;
  400. __le32 tx_one_collision;
  401. __le32 tx_multi_collision;
  402. __le64 rx_unicast;
  403. __le64 rx_broadcast;
  404. __le32 rx_multicast;
  405. __le16 tx_aborted;
  406. __le16 tx_underrun;
  407. };
  408. struct rx_desc {
  409. __le32 opts1;
  410. #define RX_LEN_MASK 0x7fff
  411. __le32 opts2;
  412. #define RD_UDP_CS (1 << 23)
  413. #define RD_TCP_CS (1 << 22)
  414. #define RD_IPV6_CS (1 << 20)
  415. #define RD_IPV4_CS (1 << 19)
  416. __le32 opts3;
  417. #define IPF (1 << 23) /* IP checksum fail */
  418. #define UDPF (1 << 22) /* UDP checksum fail */
  419. #define TCPF (1 << 21) /* TCP checksum fail */
  420. #define RX_VLAN_TAG (1 << 16)
  421. __le32 opts4;
  422. __le32 opts5;
  423. __le32 opts6;
  424. };
  425. struct tx_desc {
  426. __le32 opts1;
  427. #define TX_FS (1 << 31) /* First segment of a packet */
  428. #define TX_LS (1 << 30) /* Final segment of a packet */
  429. #define GTSENDV4 (1 << 28)
  430. #define GTSENDV6 (1 << 27)
  431. #define GTTCPHO_SHIFT 18
  432. #define GTTCPHO_MAX 0x7fU
  433. #define TX_LEN_MAX 0x3ffffU
  434. __le32 opts2;
  435. #define UDP_CS (1 << 31) /* Calculate UDP/IP checksum */
  436. #define TCP_CS (1 << 30) /* Calculate TCP/IP checksum */
  437. #define IPV4_CS (1 << 29) /* Calculate IPv4 checksum */
  438. #define IPV6_CS (1 << 28) /* Calculate IPv6 checksum */
  439. #define MSS_SHIFT 17
  440. #define MSS_MAX 0x7ffU
  441. #define TCPHO_SHIFT 17
  442. #define TCPHO_MAX 0x7ffU
  443. #define TX_VLAN_TAG (1 << 16)
  444. };
  445. struct r8152;
  446. struct rx_agg {
  447. struct list_head list;
  448. struct urb *urb;
  449. struct r8152 *context;
  450. void *buffer;
  451. void *head;
  452. };
  453. struct tx_agg {
  454. struct list_head list;
  455. struct urb *urb;
  456. struct r8152 *context;
  457. void *buffer;
  458. void *head;
  459. u32 skb_num;
  460. u32 skb_len;
  461. };
  462. struct r8152 {
  463. unsigned long flags;
  464. struct usb_device *udev;
  465. struct napi_struct napi;
  466. struct usb_interface *intf;
  467. struct net_device *netdev;
  468. struct urb *intr_urb;
  469. struct tx_agg tx_info[RTL8152_MAX_TX];
  470. struct rx_agg rx_info[RTL8152_MAX_RX];
  471. struct list_head rx_done, tx_free;
  472. struct sk_buff_head tx_queue, rx_queue;
  473. spinlock_t rx_lock, tx_lock;
  474. struct delayed_work schedule;
  475. struct mii_if_info mii;
  476. struct mutex control; /* use for hw setting */
  477. struct rtl_ops {
  478. void (*init)(struct r8152 *);
  479. int (*enable)(struct r8152 *);
  480. void (*disable)(struct r8152 *);
  481. void (*up)(struct r8152 *);
  482. void (*down)(struct r8152 *);
  483. void (*unload)(struct r8152 *);
  484. int (*eee_get)(struct r8152 *, struct ethtool_eee *);
  485. int (*eee_set)(struct r8152 *, struct ethtool_eee *);
  486. } rtl_ops;
  487. int intr_interval;
  488. u32 saved_wolopts;
  489. u32 msg_enable;
  490. u32 tx_qlen;
  491. u16 ocp_base;
  492. u8 *intr_buff;
  493. u8 version;
  494. u8 speed;
  495. };
  496. enum rtl_version {
  497. RTL_VER_UNKNOWN = 0,
  498. RTL_VER_01,
  499. RTL_VER_02,
  500. RTL_VER_03,
  501. RTL_VER_04,
  502. RTL_VER_05,
  503. RTL_VER_MAX
  504. };
  505. enum tx_csum_stat {
  506. TX_CSUM_SUCCESS = 0,
  507. TX_CSUM_TSO,
  508. TX_CSUM_NONE
  509. };
  510. /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
  511. * The RTL chips use a 64 element hash table based on the Ethernet CRC.
  512. */
  513. static const int multicast_filter_limit = 32;
  514. static unsigned int agg_buf_sz = 16384;
  515. #define RTL_LIMITED_TSO_SIZE (agg_buf_sz - sizeof(struct tx_desc) - \
  516. VLAN_ETH_HLEN - VLAN_HLEN)
  517. static
  518. int get_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
  519. {
  520. int ret;
  521. void *tmp;
  522. tmp = kmalloc(size, GFP_KERNEL);
  523. if (!tmp)
  524. return -ENOMEM;
  525. ret = usb_control_msg(tp->udev, usb_rcvctrlpipe(tp->udev, 0),
  526. RTL8152_REQ_GET_REGS, RTL8152_REQT_READ,
  527. value, index, tmp, size, 500);
  528. memcpy(data, tmp, size);
  529. kfree(tmp);
  530. return ret;
  531. }
  532. static
  533. int set_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
  534. {
  535. int ret;
  536. void *tmp;
  537. tmp = kmemdup(data, size, GFP_KERNEL);
  538. if (!tmp)
  539. return -ENOMEM;
  540. ret = usb_control_msg(tp->udev, usb_sndctrlpipe(tp->udev, 0),
  541. RTL8152_REQ_SET_REGS, RTL8152_REQT_WRITE,
  542. value, index, tmp, size, 500);
  543. kfree(tmp);
  544. return ret;
  545. }
  546. static int generic_ocp_read(struct r8152 *tp, u16 index, u16 size,
  547. void *data, u16 type)
  548. {
  549. u16 limit = 64;
  550. int ret = 0;
  551. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  552. return -ENODEV;
  553. /* both size and indix must be 4 bytes align */
  554. if ((size & 3) || !size || (index & 3) || !data)
  555. return -EPERM;
  556. if ((u32)index + (u32)size > 0xffff)
  557. return -EPERM;
  558. while (size) {
  559. if (size > limit) {
  560. ret = get_registers(tp, index, type, limit, data);
  561. if (ret < 0)
  562. break;
  563. index += limit;
  564. data += limit;
  565. size -= limit;
  566. } else {
  567. ret = get_registers(tp, index, type, size, data);
  568. if (ret < 0)
  569. break;
  570. index += size;
  571. data += size;
  572. size = 0;
  573. break;
  574. }
  575. }
  576. if (ret == -ENODEV)
  577. set_bit(RTL8152_UNPLUG, &tp->flags);
  578. return ret;
  579. }
  580. static int generic_ocp_write(struct r8152 *tp, u16 index, u16 byteen,
  581. u16 size, void *data, u16 type)
  582. {
  583. int ret;
  584. u16 byteen_start, byteen_end, byen;
  585. u16 limit = 512;
  586. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  587. return -ENODEV;
  588. /* both size and indix must be 4 bytes align */
  589. if ((size & 3) || !size || (index & 3) || !data)
  590. return -EPERM;
  591. if ((u32)index + (u32)size > 0xffff)
  592. return -EPERM;
  593. byteen_start = byteen & BYTE_EN_START_MASK;
  594. byteen_end = byteen & BYTE_EN_END_MASK;
  595. byen = byteen_start | (byteen_start << 4);
  596. ret = set_registers(tp, index, type | byen, 4, data);
  597. if (ret < 0)
  598. goto error1;
  599. index += 4;
  600. data += 4;
  601. size -= 4;
  602. if (size) {
  603. size -= 4;
  604. while (size) {
  605. if (size > limit) {
  606. ret = set_registers(tp, index,
  607. type | BYTE_EN_DWORD,
  608. limit, data);
  609. if (ret < 0)
  610. goto error1;
  611. index += limit;
  612. data += limit;
  613. size -= limit;
  614. } else {
  615. ret = set_registers(tp, index,
  616. type | BYTE_EN_DWORD,
  617. size, data);
  618. if (ret < 0)
  619. goto error1;
  620. index += size;
  621. data += size;
  622. size = 0;
  623. break;
  624. }
  625. }
  626. byen = byteen_end | (byteen_end >> 4);
  627. ret = set_registers(tp, index, type | byen, 4, data);
  628. if (ret < 0)
  629. goto error1;
  630. }
  631. error1:
  632. if (ret == -ENODEV)
  633. set_bit(RTL8152_UNPLUG, &tp->flags);
  634. return ret;
  635. }
  636. static inline
  637. int pla_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data)
  638. {
  639. return generic_ocp_read(tp, index, size, data, MCU_TYPE_PLA);
  640. }
  641. static inline
  642. int pla_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
  643. {
  644. return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_PLA);
  645. }
  646. static inline
  647. int usb_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data)
  648. {
  649. return generic_ocp_read(tp, index, size, data, MCU_TYPE_USB);
  650. }
  651. static inline
  652. int usb_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
  653. {
  654. return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_USB);
  655. }
  656. static u32 ocp_read_dword(struct r8152 *tp, u16 type, u16 index)
  657. {
  658. __le32 data;
  659. generic_ocp_read(tp, index, sizeof(data), &data, type);
  660. return __le32_to_cpu(data);
  661. }
  662. static void ocp_write_dword(struct r8152 *tp, u16 type, u16 index, u32 data)
  663. {
  664. __le32 tmp = __cpu_to_le32(data);
  665. generic_ocp_write(tp, index, BYTE_EN_DWORD, sizeof(tmp), &tmp, type);
  666. }
  667. static u16 ocp_read_word(struct r8152 *tp, u16 type, u16 index)
  668. {
  669. u32 data;
  670. __le32 tmp;
  671. u8 shift = index & 2;
  672. index &= ~3;
  673. generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
  674. data = __le32_to_cpu(tmp);
  675. data >>= (shift * 8);
  676. data &= 0xffff;
  677. return (u16)data;
  678. }
  679. static void ocp_write_word(struct r8152 *tp, u16 type, u16 index, u32 data)
  680. {
  681. u32 mask = 0xffff;
  682. __le32 tmp;
  683. u16 byen = BYTE_EN_WORD;
  684. u8 shift = index & 2;
  685. data &= mask;
  686. if (index & 2) {
  687. byen <<= shift;
  688. mask <<= (shift * 8);
  689. data <<= (shift * 8);
  690. index &= ~3;
  691. }
  692. generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
  693. data |= __le32_to_cpu(tmp) & ~mask;
  694. tmp = __cpu_to_le32(data);
  695. generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
  696. }
  697. static u8 ocp_read_byte(struct r8152 *tp, u16 type, u16 index)
  698. {
  699. u32 data;
  700. __le32 tmp;
  701. u8 shift = index & 3;
  702. index &= ~3;
  703. generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
  704. data = __le32_to_cpu(tmp);
  705. data >>= (shift * 8);
  706. data &= 0xff;
  707. return (u8)data;
  708. }
  709. static void ocp_write_byte(struct r8152 *tp, u16 type, u16 index, u32 data)
  710. {
  711. u32 mask = 0xff;
  712. __le32 tmp;
  713. u16 byen = BYTE_EN_BYTE;
  714. u8 shift = index & 3;
  715. data &= mask;
  716. if (index & 3) {
  717. byen <<= shift;
  718. mask <<= (shift * 8);
  719. data <<= (shift * 8);
  720. index &= ~3;
  721. }
  722. generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
  723. data |= __le32_to_cpu(tmp) & ~mask;
  724. tmp = __cpu_to_le32(data);
  725. generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
  726. }
  727. static u16 ocp_reg_read(struct r8152 *tp, u16 addr)
  728. {
  729. u16 ocp_base, ocp_index;
  730. ocp_base = addr & 0xf000;
  731. if (ocp_base != tp->ocp_base) {
  732. ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base);
  733. tp->ocp_base = ocp_base;
  734. }
  735. ocp_index = (addr & 0x0fff) | 0xb000;
  736. return ocp_read_word(tp, MCU_TYPE_PLA, ocp_index);
  737. }
  738. static void ocp_reg_write(struct r8152 *tp, u16 addr, u16 data)
  739. {
  740. u16 ocp_base, ocp_index;
  741. ocp_base = addr & 0xf000;
  742. if (ocp_base != tp->ocp_base) {
  743. ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base);
  744. tp->ocp_base = ocp_base;
  745. }
  746. ocp_index = (addr & 0x0fff) | 0xb000;
  747. ocp_write_word(tp, MCU_TYPE_PLA, ocp_index, data);
  748. }
  749. static inline void r8152_mdio_write(struct r8152 *tp, u32 reg_addr, u32 value)
  750. {
  751. ocp_reg_write(tp, OCP_BASE_MII + reg_addr * 2, value);
  752. }
  753. static inline int r8152_mdio_read(struct r8152 *tp, u32 reg_addr)
  754. {
  755. return ocp_reg_read(tp, OCP_BASE_MII + reg_addr * 2);
  756. }
  757. static void sram_write(struct r8152 *tp, u16 addr, u16 data)
  758. {
  759. ocp_reg_write(tp, OCP_SRAM_ADDR, addr);
  760. ocp_reg_write(tp, OCP_SRAM_DATA, data);
  761. }
  762. static u16 sram_read(struct r8152 *tp, u16 addr)
  763. {
  764. ocp_reg_write(tp, OCP_SRAM_ADDR, addr);
  765. return ocp_reg_read(tp, OCP_SRAM_DATA);
  766. }
  767. static int read_mii_word(struct net_device *netdev, int phy_id, int reg)
  768. {
  769. struct r8152 *tp = netdev_priv(netdev);
  770. int ret;
  771. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  772. return -ENODEV;
  773. if (phy_id != R8152_PHY_ID)
  774. return -EINVAL;
  775. ret = r8152_mdio_read(tp, reg);
  776. return ret;
  777. }
  778. static
  779. void write_mii_word(struct net_device *netdev, int phy_id, int reg, int val)
  780. {
  781. struct r8152 *tp = netdev_priv(netdev);
  782. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  783. return;
  784. if (phy_id != R8152_PHY_ID)
  785. return;
  786. r8152_mdio_write(tp, reg, val);
  787. }
  788. static int
  789. r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags);
  790. static int rtl8152_set_mac_address(struct net_device *netdev, void *p)
  791. {
  792. struct r8152 *tp = netdev_priv(netdev);
  793. struct sockaddr *addr = p;
  794. int ret = -EADDRNOTAVAIL;
  795. if (!is_valid_ether_addr(addr->sa_data))
  796. goto out1;
  797. ret = usb_autopm_get_interface(tp->intf);
  798. if (ret < 0)
  799. goto out1;
  800. mutex_lock(&tp->control);
  801. memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
  802. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
  803. pla_ocp_write(tp, PLA_IDR, BYTE_EN_SIX_BYTES, 8, addr->sa_data);
  804. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
  805. mutex_unlock(&tp->control);
  806. usb_autopm_put_interface(tp->intf);
  807. out1:
  808. return ret;
  809. }
  810. static int set_ethernet_addr(struct r8152 *tp)
  811. {
  812. struct net_device *dev = tp->netdev;
  813. struct sockaddr sa;
  814. int ret;
  815. if (tp->version == RTL_VER_01)
  816. ret = pla_ocp_read(tp, PLA_IDR, 8, sa.sa_data);
  817. else
  818. ret = pla_ocp_read(tp, PLA_BACKUP, 8, sa.sa_data);
  819. if (ret < 0) {
  820. netif_err(tp, probe, dev, "Get ether addr fail\n");
  821. } else if (!is_valid_ether_addr(sa.sa_data)) {
  822. netif_err(tp, probe, dev, "Invalid ether addr %pM\n",
  823. sa.sa_data);
  824. eth_hw_addr_random(dev);
  825. ether_addr_copy(sa.sa_data, dev->dev_addr);
  826. ret = rtl8152_set_mac_address(dev, &sa);
  827. netif_info(tp, probe, dev, "Random ether addr %pM\n",
  828. sa.sa_data);
  829. } else {
  830. if (tp->version == RTL_VER_01)
  831. ether_addr_copy(dev->dev_addr, sa.sa_data);
  832. else
  833. ret = rtl8152_set_mac_address(dev, &sa);
  834. }
  835. return ret;
  836. }
  837. static void read_bulk_callback(struct urb *urb)
  838. {
  839. struct net_device *netdev;
  840. int status = urb->status;
  841. struct rx_agg *agg;
  842. struct r8152 *tp;
  843. agg = urb->context;
  844. if (!agg)
  845. return;
  846. tp = agg->context;
  847. if (!tp)
  848. return;
  849. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  850. return;
  851. if (!test_bit(WORK_ENABLE, &tp->flags))
  852. return;
  853. netdev = tp->netdev;
  854. /* When link down, the driver would cancel all bulks. */
  855. /* This avoid the re-submitting bulk */
  856. if (!netif_carrier_ok(netdev))
  857. return;
  858. usb_mark_last_busy(tp->udev);
  859. switch (status) {
  860. case 0:
  861. if (urb->actual_length < ETH_ZLEN)
  862. break;
  863. spin_lock(&tp->rx_lock);
  864. list_add_tail(&agg->list, &tp->rx_done);
  865. spin_unlock(&tp->rx_lock);
  866. napi_schedule(&tp->napi);
  867. return;
  868. case -ESHUTDOWN:
  869. set_bit(RTL8152_UNPLUG, &tp->flags);
  870. netif_device_detach(tp->netdev);
  871. return;
  872. case -ENOENT:
  873. return; /* the urb is in unlink state */
  874. case -ETIME:
  875. if (net_ratelimit())
  876. netdev_warn(netdev, "maybe reset is needed?\n");
  877. break;
  878. default:
  879. if (net_ratelimit())
  880. netdev_warn(netdev, "Rx status %d\n", status);
  881. break;
  882. }
  883. r8152_submit_rx(tp, agg, GFP_ATOMIC);
  884. }
  885. static void write_bulk_callback(struct urb *urb)
  886. {
  887. struct net_device_stats *stats;
  888. struct net_device *netdev;
  889. struct tx_agg *agg;
  890. struct r8152 *tp;
  891. int status = urb->status;
  892. agg = urb->context;
  893. if (!agg)
  894. return;
  895. tp = agg->context;
  896. if (!tp)
  897. return;
  898. netdev = tp->netdev;
  899. stats = &netdev->stats;
  900. if (status) {
  901. if (net_ratelimit())
  902. netdev_warn(netdev, "Tx status %d\n", status);
  903. stats->tx_errors += agg->skb_num;
  904. } else {
  905. stats->tx_packets += agg->skb_num;
  906. stats->tx_bytes += agg->skb_len;
  907. }
  908. spin_lock(&tp->tx_lock);
  909. list_add_tail(&agg->list, &tp->tx_free);
  910. spin_unlock(&tp->tx_lock);
  911. usb_autopm_put_interface_async(tp->intf);
  912. if (!netif_carrier_ok(netdev))
  913. return;
  914. if (!test_bit(WORK_ENABLE, &tp->flags))
  915. return;
  916. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  917. return;
  918. if (!skb_queue_empty(&tp->tx_queue))
  919. napi_schedule(&tp->napi);
  920. }
  921. static void intr_callback(struct urb *urb)
  922. {
  923. struct r8152 *tp;
  924. __le16 *d;
  925. int status = urb->status;
  926. int res;
  927. tp = urb->context;
  928. if (!tp)
  929. return;
  930. if (!test_bit(WORK_ENABLE, &tp->flags))
  931. return;
  932. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  933. return;
  934. switch (status) {
  935. case 0: /* success */
  936. break;
  937. case -ECONNRESET: /* unlink */
  938. case -ESHUTDOWN:
  939. netif_device_detach(tp->netdev);
  940. case -ENOENT:
  941. case -EPROTO:
  942. netif_info(tp, intr, tp->netdev,
  943. "Stop submitting intr, status %d\n", status);
  944. return;
  945. case -EOVERFLOW:
  946. netif_info(tp, intr, tp->netdev, "intr status -EOVERFLOW\n");
  947. goto resubmit;
  948. /* -EPIPE: should clear the halt */
  949. default:
  950. netif_info(tp, intr, tp->netdev, "intr status %d\n", status);
  951. goto resubmit;
  952. }
  953. d = urb->transfer_buffer;
  954. if (INTR_LINK & __le16_to_cpu(d[0])) {
  955. if (!(tp->speed & LINK_STATUS)) {
  956. set_bit(RTL8152_LINK_CHG, &tp->flags);
  957. schedule_delayed_work(&tp->schedule, 0);
  958. }
  959. } else {
  960. if (tp->speed & LINK_STATUS) {
  961. set_bit(RTL8152_LINK_CHG, &tp->flags);
  962. schedule_delayed_work(&tp->schedule, 0);
  963. }
  964. }
  965. resubmit:
  966. res = usb_submit_urb(urb, GFP_ATOMIC);
  967. if (res == -ENODEV) {
  968. set_bit(RTL8152_UNPLUG, &tp->flags);
  969. netif_device_detach(tp->netdev);
  970. } else if (res) {
  971. netif_err(tp, intr, tp->netdev,
  972. "can't resubmit intr, status %d\n", res);
  973. }
  974. }
  975. static inline void *rx_agg_align(void *data)
  976. {
  977. return (void *)ALIGN((uintptr_t)data, RX_ALIGN);
  978. }
  979. static inline void *tx_agg_align(void *data)
  980. {
  981. return (void *)ALIGN((uintptr_t)data, TX_ALIGN);
  982. }
  983. static void free_all_mem(struct r8152 *tp)
  984. {
  985. int i;
  986. for (i = 0; i < RTL8152_MAX_RX; i++) {
  987. usb_free_urb(tp->rx_info[i].urb);
  988. tp->rx_info[i].urb = NULL;
  989. kfree(tp->rx_info[i].buffer);
  990. tp->rx_info[i].buffer = NULL;
  991. tp->rx_info[i].head = NULL;
  992. }
  993. for (i = 0; i < RTL8152_MAX_TX; i++) {
  994. usb_free_urb(tp->tx_info[i].urb);
  995. tp->tx_info[i].urb = NULL;
  996. kfree(tp->tx_info[i].buffer);
  997. tp->tx_info[i].buffer = NULL;
  998. tp->tx_info[i].head = NULL;
  999. }
  1000. usb_free_urb(tp->intr_urb);
  1001. tp->intr_urb = NULL;
  1002. kfree(tp->intr_buff);
  1003. tp->intr_buff = NULL;
  1004. }
  1005. static int alloc_all_mem(struct r8152 *tp)
  1006. {
  1007. struct net_device *netdev = tp->netdev;
  1008. struct usb_interface *intf = tp->intf;
  1009. struct usb_host_interface *alt = intf->cur_altsetting;
  1010. struct usb_host_endpoint *ep_intr = alt->endpoint + 2;
  1011. struct urb *urb;
  1012. int node, i;
  1013. u8 *buf;
  1014. node = netdev->dev.parent ? dev_to_node(netdev->dev.parent) : -1;
  1015. spin_lock_init(&tp->rx_lock);
  1016. spin_lock_init(&tp->tx_lock);
  1017. INIT_LIST_HEAD(&tp->tx_free);
  1018. skb_queue_head_init(&tp->tx_queue);
  1019. skb_queue_head_init(&tp->rx_queue);
  1020. for (i = 0; i < RTL8152_MAX_RX; i++) {
  1021. buf = kmalloc_node(agg_buf_sz, GFP_KERNEL, node);
  1022. if (!buf)
  1023. goto err1;
  1024. if (buf != rx_agg_align(buf)) {
  1025. kfree(buf);
  1026. buf = kmalloc_node(agg_buf_sz + RX_ALIGN, GFP_KERNEL,
  1027. node);
  1028. if (!buf)
  1029. goto err1;
  1030. }
  1031. urb = usb_alloc_urb(0, GFP_KERNEL);
  1032. if (!urb) {
  1033. kfree(buf);
  1034. goto err1;
  1035. }
  1036. INIT_LIST_HEAD(&tp->rx_info[i].list);
  1037. tp->rx_info[i].context = tp;
  1038. tp->rx_info[i].urb = urb;
  1039. tp->rx_info[i].buffer = buf;
  1040. tp->rx_info[i].head = rx_agg_align(buf);
  1041. }
  1042. for (i = 0; i < RTL8152_MAX_TX; i++) {
  1043. buf = kmalloc_node(agg_buf_sz, GFP_KERNEL, node);
  1044. if (!buf)
  1045. goto err1;
  1046. if (buf != tx_agg_align(buf)) {
  1047. kfree(buf);
  1048. buf = kmalloc_node(agg_buf_sz + TX_ALIGN, GFP_KERNEL,
  1049. node);
  1050. if (!buf)
  1051. goto err1;
  1052. }
  1053. urb = usb_alloc_urb(0, GFP_KERNEL);
  1054. if (!urb) {
  1055. kfree(buf);
  1056. goto err1;
  1057. }
  1058. INIT_LIST_HEAD(&tp->tx_info[i].list);
  1059. tp->tx_info[i].context = tp;
  1060. tp->tx_info[i].urb = urb;
  1061. tp->tx_info[i].buffer = buf;
  1062. tp->tx_info[i].head = tx_agg_align(buf);
  1063. list_add_tail(&tp->tx_info[i].list, &tp->tx_free);
  1064. }
  1065. tp->intr_urb = usb_alloc_urb(0, GFP_KERNEL);
  1066. if (!tp->intr_urb)
  1067. goto err1;
  1068. tp->intr_buff = kmalloc(INTBUFSIZE, GFP_KERNEL);
  1069. if (!tp->intr_buff)
  1070. goto err1;
  1071. tp->intr_interval = (int)ep_intr->desc.bInterval;
  1072. usb_fill_int_urb(tp->intr_urb, tp->udev, usb_rcvintpipe(tp->udev, 3),
  1073. tp->intr_buff, INTBUFSIZE, intr_callback,
  1074. tp, tp->intr_interval);
  1075. return 0;
  1076. err1:
  1077. free_all_mem(tp);
  1078. return -ENOMEM;
  1079. }
  1080. static struct tx_agg *r8152_get_tx_agg(struct r8152 *tp)
  1081. {
  1082. struct tx_agg *agg = NULL;
  1083. unsigned long flags;
  1084. if (list_empty(&tp->tx_free))
  1085. return NULL;
  1086. spin_lock_irqsave(&tp->tx_lock, flags);
  1087. if (!list_empty(&tp->tx_free)) {
  1088. struct list_head *cursor;
  1089. cursor = tp->tx_free.next;
  1090. list_del_init(cursor);
  1091. agg = list_entry(cursor, struct tx_agg, list);
  1092. }
  1093. spin_unlock_irqrestore(&tp->tx_lock, flags);
  1094. return agg;
  1095. }
  1096. static inline __be16 get_protocol(struct sk_buff *skb)
  1097. {
  1098. __be16 protocol;
  1099. if (skb->protocol == htons(ETH_P_8021Q))
  1100. protocol = vlan_eth_hdr(skb)->h_vlan_encapsulated_proto;
  1101. else
  1102. protocol = skb->protocol;
  1103. return protocol;
  1104. }
  1105. /* r8152_csum_workaround()
  1106. * The hw limites the value the transport offset. When the offset is out of the
  1107. * range, calculate the checksum by sw.
  1108. */
  1109. static void r8152_csum_workaround(struct r8152 *tp, struct sk_buff *skb,
  1110. struct sk_buff_head *list)
  1111. {
  1112. if (skb_shinfo(skb)->gso_size) {
  1113. netdev_features_t features = tp->netdev->features;
  1114. struct sk_buff_head seg_list;
  1115. struct sk_buff *segs, *nskb;
  1116. features &= ~(NETIF_F_SG | NETIF_F_IPV6_CSUM | NETIF_F_TSO6);
  1117. segs = skb_gso_segment(skb, features);
  1118. if (IS_ERR(segs) || !segs)
  1119. goto drop;
  1120. __skb_queue_head_init(&seg_list);
  1121. do {
  1122. nskb = segs;
  1123. segs = segs->next;
  1124. nskb->next = NULL;
  1125. __skb_queue_tail(&seg_list, nskb);
  1126. } while (segs);
  1127. skb_queue_splice(&seg_list, list);
  1128. dev_kfree_skb(skb);
  1129. } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
  1130. if (skb_checksum_help(skb) < 0)
  1131. goto drop;
  1132. __skb_queue_head(list, skb);
  1133. } else {
  1134. struct net_device_stats *stats;
  1135. drop:
  1136. stats = &tp->netdev->stats;
  1137. stats->tx_dropped++;
  1138. dev_kfree_skb(skb);
  1139. }
  1140. }
  1141. /* msdn_giant_send_check()
  1142. * According to the document of microsoft, the TCP Pseudo Header excludes the
  1143. * packet length for IPv6 TCP large packets.
  1144. */
  1145. static int msdn_giant_send_check(struct sk_buff *skb)
  1146. {
  1147. const struct ipv6hdr *ipv6h;
  1148. struct tcphdr *th;
  1149. int ret;
  1150. ret = skb_cow_head(skb, 0);
  1151. if (ret)
  1152. return ret;
  1153. ipv6h = ipv6_hdr(skb);
  1154. th = tcp_hdr(skb);
  1155. th->check = 0;
  1156. th->check = ~tcp_v6_check(0, &ipv6h->saddr, &ipv6h->daddr, 0);
  1157. return ret;
  1158. }
  1159. static inline void rtl_tx_vlan_tag(struct tx_desc *desc, struct sk_buff *skb)
  1160. {
  1161. if (skb_vlan_tag_present(skb)) {
  1162. u32 opts2;
  1163. opts2 = TX_VLAN_TAG | swab16(skb_vlan_tag_get(skb));
  1164. desc->opts2 |= cpu_to_le32(opts2);
  1165. }
  1166. }
  1167. static inline void rtl_rx_vlan_tag(struct rx_desc *desc, struct sk_buff *skb)
  1168. {
  1169. u32 opts2 = le32_to_cpu(desc->opts2);
  1170. if (opts2 & RX_VLAN_TAG)
  1171. __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
  1172. swab16(opts2 & 0xffff));
  1173. }
  1174. static int r8152_tx_csum(struct r8152 *tp, struct tx_desc *desc,
  1175. struct sk_buff *skb, u32 len, u32 transport_offset)
  1176. {
  1177. u32 mss = skb_shinfo(skb)->gso_size;
  1178. u32 opts1, opts2 = 0;
  1179. int ret = TX_CSUM_SUCCESS;
  1180. WARN_ON_ONCE(len > TX_LEN_MAX);
  1181. opts1 = len | TX_FS | TX_LS;
  1182. if (mss) {
  1183. if (transport_offset > GTTCPHO_MAX) {
  1184. netif_warn(tp, tx_err, tp->netdev,
  1185. "Invalid transport offset 0x%x for TSO\n",
  1186. transport_offset);
  1187. ret = TX_CSUM_TSO;
  1188. goto unavailable;
  1189. }
  1190. switch (get_protocol(skb)) {
  1191. case htons(ETH_P_IP):
  1192. opts1 |= GTSENDV4;
  1193. break;
  1194. case htons(ETH_P_IPV6):
  1195. if (msdn_giant_send_check(skb)) {
  1196. ret = TX_CSUM_TSO;
  1197. goto unavailable;
  1198. }
  1199. opts1 |= GTSENDV6;
  1200. break;
  1201. default:
  1202. WARN_ON_ONCE(1);
  1203. break;
  1204. }
  1205. opts1 |= transport_offset << GTTCPHO_SHIFT;
  1206. opts2 |= min(mss, MSS_MAX) << MSS_SHIFT;
  1207. } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
  1208. u8 ip_protocol;
  1209. if (transport_offset > TCPHO_MAX) {
  1210. netif_warn(tp, tx_err, tp->netdev,
  1211. "Invalid transport offset 0x%x\n",
  1212. transport_offset);
  1213. ret = TX_CSUM_NONE;
  1214. goto unavailable;
  1215. }
  1216. switch (get_protocol(skb)) {
  1217. case htons(ETH_P_IP):
  1218. opts2 |= IPV4_CS;
  1219. ip_protocol = ip_hdr(skb)->protocol;
  1220. break;
  1221. case htons(ETH_P_IPV6):
  1222. opts2 |= IPV6_CS;
  1223. ip_protocol = ipv6_hdr(skb)->nexthdr;
  1224. break;
  1225. default:
  1226. ip_protocol = IPPROTO_RAW;
  1227. break;
  1228. }
  1229. if (ip_protocol == IPPROTO_TCP)
  1230. opts2 |= TCP_CS;
  1231. else if (ip_protocol == IPPROTO_UDP)
  1232. opts2 |= UDP_CS;
  1233. else
  1234. WARN_ON_ONCE(1);
  1235. opts2 |= transport_offset << TCPHO_SHIFT;
  1236. }
  1237. desc->opts2 = cpu_to_le32(opts2);
  1238. desc->opts1 = cpu_to_le32(opts1);
  1239. unavailable:
  1240. return ret;
  1241. }
  1242. static int r8152_tx_agg_fill(struct r8152 *tp, struct tx_agg *agg)
  1243. {
  1244. struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue;
  1245. int remain, ret;
  1246. u8 *tx_data;
  1247. __skb_queue_head_init(&skb_head);
  1248. spin_lock(&tx_queue->lock);
  1249. skb_queue_splice_init(tx_queue, &skb_head);
  1250. spin_unlock(&tx_queue->lock);
  1251. tx_data = agg->head;
  1252. agg->skb_num = 0;
  1253. agg->skb_len = 0;
  1254. remain = agg_buf_sz;
  1255. while (remain >= ETH_ZLEN + sizeof(struct tx_desc)) {
  1256. struct tx_desc *tx_desc;
  1257. struct sk_buff *skb;
  1258. unsigned int len;
  1259. u32 offset;
  1260. skb = __skb_dequeue(&skb_head);
  1261. if (!skb)
  1262. break;
  1263. len = skb->len + sizeof(*tx_desc);
  1264. if (len > remain) {
  1265. __skb_queue_head(&skb_head, skb);
  1266. break;
  1267. }
  1268. tx_data = tx_agg_align(tx_data);
  1269. tx_desc = (struct tx_desc *)tx_data;
  1270. offset = (u32)skb_transport_offset(skb);
  1271. if (r8152_tx_csum(tp, tx_desc, skb, skb->len, offset)) {
  1272. r8152_csum_workaround(tp, skb, &skb_head);
  1273. continue;
  1274. }
  1275. rtl_tx_vlan_tag(tx_desc, skb);
  1276. tx_data += sizeof(*tx_desc);
  1277. len = skb->len;
  1278. if (skb_copy_bits(skb, 0, tx_data, len) < 0) {
  1279. struct net_device_stats *stats = &tp->netdev->stats;
  1280. stats->tx_dropped++;
  1281. dev_kfree_skb_any(skb);
  1282. tx_data -= sizeof(*tx_desc);
  1283. continue;
  1284. }
  1285. tx_data += len;
  1286. agg->skb_len += len;
  1287. agg->skb_num++;
  1288. dev_kfree_skb_any(skb);
  1289. remain = agg_buf_sz - (int)(tx_agg_align(tx_data) - agg->head);
  1290. }
  1291. if (!skb_queue_empty(&skb_head)) {
  1292. spin_lock(&tx_queue->lock);
  1293. skb_queue_splice(&skb_head, tx_queue);
  1294. spin_unlock(&tx_queue->lock);
  1295. }
  1296. netif_tx_lock(tp->netdev);
  1297. if (netif_queue_stopped(tp->netdev) &&
  1298. skb_queue_len(&tp->tx_queue) < tp->tx_qlen)
  1299. netif_wake_queue(tp->netdev);
  1300. netif_tx_unlock(tp->netdev);
  1301. ret = usb_autopm_get_interface_async(tp->intf);
  1302. if (ret < 0)
  1303. goto out_tx_fill;
  1304. usb_fill_bulk_urb(agg->urb, tp->udev, usb_sndbulkpipe(tp->udev, 2),
  1305. agg->head, (int)(tx_data - (u8 *)agg->head),
  1306. (usb_complete_t)write_bulk_callback, agg);
  1307. ret = usb_submit_urb(agg->urb, GFP_ATOMIC);
  1308. if (ret < 0)
  1309. usb_autopm_put_interface_async(tp->intf);
  1310. out_tx_fill:
  1311. return ret;
  1312. }
  1313. static u8 r8152_rx_csum(struct r8152 *tp, struct rx_desc *rx_desc)
  1314. {
  1315. u8 checksum = CHECKSUM_NONE;
  1316. u32 opts2, opts3;
  1317. if (tp->version == RTL_VER_01)
  1318. goto return_result;
  1319. opts2 = le32_to_cpu(rx_desc->opts2);
  1320. opts3 = le32_to_cpu(rx_desc->opts3);
  1321. if (opts2 & RD_IPV4_CS) {
  1322. if (opts3 & IPF)
  1323. checksum = CHECKSUM_NONE;
  1324. else if ((opts2 & RD_UDP_CS) && (opts3 & UDPF))
  1325. checksum = CHECKSUM_NONE;
  1326. else if ((opts2 & RD_TCP_CS) && (opts3 & TCPF))
  1327. checksum = CHECKSUM_NONE;
  1328. else
  1329. checksum = CHECKSUM_UNNECESSARY;
  1330. } else if (RD_IPV6_CS) {
  1331. if ((opts2 & RD_UDP_CS) && !(opts3 & UDPF))
  1332. checksum = CHECKSUM_UNNECESSARY;
  1333. else if ((opts2 & RD_TCP_CS) && !(opts3 & TCPF))
  1334. checksum = CHECKSUM_UNNECESSARY;
  1335. }
  1336. return_result:
  1337. return checksum;
  1338. }
  1339. static int rx_bottom(struct r8152 *tp, int budget)
  1340. {
  1341. unsigned long flags;
  1342. struct list_head *cursor, *next, rx_queue;
  1343. int work_done = 0;
  1344. if (!skb_queue_empty(&tp->rx_queue)) {
  1345. while (work_done < budget) {
  1346. struct sk_buff *skb = __skb_dequeue(&tp->rx_queue);
  1347. struct net_device *netdev = tp->netdev;
  1348. struct net_device_stats *stats = &netdev->stats;
  1349. unsigned int pkt_len;
  1350. if (!skb)
  1351. break;
  1352. pkt_len = skb->len;
  1353. napi_gro_receive(&tp->napi, skb);
  1354. work_done++;
  1355. stats->rx_packets++;
  1356. stats->rx_bytes += pkt_len;
  1357. }
  1358. }
  1359. if (list_empty(&tp->rx_done))
  1360. goto out1;
  1361. INIT_LIST_HEAD(&rx_queue);
  1362. spin_lock_irqsave(&tp->rx_lock, flags);
  1363. list_splice_init(&tp->rx_done, &rx_queue);
  1364. spin_unlock_irqrestore(&tp->rx_lock, flags);
  1365. list_for_each_safe(cursor, next, &rx_queue) {
  1366. struct rx_desc *rx_desc;
  1367. struct rx_agg *agg;
  1368. int len_used = 0;
  1369. struct urb *urb;
  1370. u8 *rx_data;
  1371. list_del_init(cursor);
  1372. agg = list_entry(cursor, struct rx_agg, list);
  1373. urb = agg->urb;
  1374. if (urb->actual_length < ETH_ZLEN)
  1375. goto submit;
  1376. rx_desc = agg->head;
  1377. rx_data = agg->head;
  1378. len_used += sizeof(struct rx_desc);
  1379. while (urb->actual_length > len_used) {
  1380. struct net_device *netdev = tp->netdev;
  1381. struct net_device_stats *stats = &netdev->stats;
  1382. unsigned int pkt_len;
  1383. struct sk_buff *skb;
  1384. pkt_len = le32_to_cpu(rx_desc->opts1) & RX_LEN_MASK;
  1385. if (pkt_len < ETH_ZLEN)
  1386. break;
  1387. len_used += pkt_len;
  1388. if (urb->actual_length < len_used)
  1389. break;
  1390. pkt_len -= CRC_SIZE;
  1391. rx_data += sizeof(struct rx_desc);
  1392. skb = netdev_alloc_skb_ip_align(netdev, pkt_len);
  1393. if (!skb) {
  1394. stats->rx_dropped++;
  1395. goto find_next_rx;
  1396. }
  1397. skb->ip_summed = r8152_rx_csum(tp, rx_desc);
  1398. memcpy(skb->data, rx_data, pkt_len);
  1399. skb_put(skb, pkt_len);
  1400. skb->protocol = eth_type_trans(skb, netdev);
  1401. rtl_rx_vlan_tag(rx_desc, skb);
  1402. if (work_done < budget) {
  1403. napi_gro_receive(&tp->napi, skb);
  1404. work_done++;
  1405. stats->rx_packets++;
  1406. stats->rx_bytes += pkt_len;
  1407. } else {
  1408. __skb_queue_tail(&tp->rx_queue, skb);
  1409. }
  1410. find_next_rx:
  1411. rx_data = rx_agg_align(rx_data + pkt_len + CRC_SIZE);
  1412. rx_desc = (struct rx_desc *)rx_data;
  1413. len_used = (int)(rx_data - (u8 *)agg->head);
  1414. len_used += sizeof(struct rx_desc);
  1415. }
  1416. submit:
  1417. r8152_submit_rx(tp, agg, GFP_ATOMIC);
  1418. }
  1419. out1:
  1420. return work_done;
  1421. }
  1422. static void tx_bottom(struct r8152 *tp)
  1423. {
  1424. int res;
  1425. do {
  1426. struct tx_agg *agg;
  1427. if (skb_queue_empty(&tp->tx_queue))
  1428. break;
  1429. agg = r8152_get_tx_agg(tp);
  1430. if (!agg)
  1431. break;
  1432. res = r8152_tx_agg_fill(tp, agg);
  1433. if (res) {
  1434. struct net_device *netdev = tp->netdev;
  1435. if (res == -ENODEV) {
  1436. set_bit(RTL8152_UNPLUG, &tp->flags);
  1437. netif_device_detach(netdev);
  1438. } else {
  1439. struct net_device_stats *stats = &netdev->stats;
  1440. unsigned long flags;
  1441. netif_warn(tp, tx_err, netdev,
  1442. "failed tx_urb %d\n", res);
  1443. stats->tx_dropped += agg->skb_num;
  1444. spin_lock_irqsave(&tp->tx_lock, flags);
  1445. list_add_tail(&agg->list, &tp->tx_free);
  1446. spin_unlock_irqrestore(&tp->tx_lock, flags);
  1447. }
  1448. }
  1449. } while (res == 0);
  1450. }
  1451. static void bottom_half(struct r8152 *tp)
  1452. {
  1453. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  1454. return;
  1455. if (!test_bit(WORK_ENABLE, &tp->flags))
  1456. return;
  1457. /* When link down, the driver would cancel all bulks. */
  1458. /* This avoid the re-submitting bulk */
  1459. if (!netif_carrier_ok(tp->netdev))
  1460. return;
  1461. clear_bit(SCHEDULE_NAPI, &tp->flags);
  1462. tx_bottom(tp);
  1463. }
  1464. static int r8152_poll(struct napi_struct *napi, int budget)
  1465. {
  1466. struct r8152 *tp = container_of(napi, struct r8152, napi);
  1467. int work_done;
  1468. work_done = rx_bottom(tp, budget);
  1469. bottom_half(tp);
  1470. if (work_done < budget) {
  1471. napi_complete(napi);
  1472. if (!list_empty(&tp->rx_done))
  1473. napi_schedule(napi);
  1474. }
  1475. return work_done;
  1476. }
  1477. static
  1478. int r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags)
  1479. {
  1480. int ret;
  1481. /* The rx would be stopped, so skip submitting */
  1482. if (test_bit(RTL8152_UNPLUG, &tp->flags) ||
  1483. !test_bit(WORK_ENABLE, &tp->flags) || !netif_carrier_ok(tp->netdev))
  1484. return 0;
  1485. usb_fill_bulk_urb(agg->urb, tp->udev, usb_rcvbulkpipe(tp->udev, 1),
  1486. agg->head, agg_buf_sz,
  1487. (usb_complete_t)read_bulk_callback, agg);
  1488. ret = usb_submit_urb(agg->urb, mem_flags);
  1489. if (ret == -ENODEV) {
  1490. set_bit(RTL8152_UNPLUG, &tp->flags);
  1491. netif_device_detach(tp->netdev);
  1492. } else if (ret) {
  1493. struct urb *urb = agg->urb;
  1494. unsigned long flags;
  1495. urb->actual_length = 0;
  1496. spin_lock_irqsave(&tp->rx_lock, flags);
  1497. list_add_tail(&agg->list, &tp->rx_done);
  1498. spin_unlock_irqrestore(&tp->rx_lock, flags);
  1499. netif_err(tp, rx_err, tp->netdev,
  1500. "Couldn't submit rx[%p], ret = %d\n", agg, ret);
  1501. napi_schedule(&tp->napi);
  1502. }
  1503. return ret;
  1504. }
  1505. static void rtl_drop_queued_tx(struct r8152 *tp)
  1506. {
  1507. struct net_device_stats *stats = &tp->netdev->stats;
  1508. struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue;
  1509. struct sk_buff *skb;
  1510. if (skb_queue_empty(tx_queue))
  1511. return;
  1512. __skb_queue_head_init(&skb_head);
  1513. spin_lock_bh(&tx_queue->lock);
  1514. skb_queue_splice_init(tx_queue, &skb_head);
  1515. spin_unlock_bh(&tx_queue->lock);
  1516. while ((skb = __skb_dequeue(&skb_head))) {
  1517. dev_kfree_skb(skb);
  1518. stats->tx_dropped++;
  1519. }
  1520. }
  1521. static void rtl8152_tx_timeout(struct net_device *netdev)
  1522. {
  1523. struct r8152 *tp = netdev_priv(netdev);
  1524. int i;
  1525. netif_warn(tp, tx_err, netdev, "Tx timeout\n");
  1526. for (i = 0; i < RTL8152_MAX_TX; i++)
  1527. usb_unlink_urb(tp->tx_info[i].urb);
  1528. }
  1529. static void rtl8152_set_rx_mode(struct net_device *netdev)
  1530. {
  1531. struct r8152 *tp = netdev_priv(netdev);
  1532. if (tp->speed & LINK_STATUS) {
  1533. set_bit(RTL8152_SET_RX_MODE, &tp->flags);
  1534. schedule_delayed_work(&tp->schedule, 0);
  1535. }
  1536. }
  1537. static void _rtl8152_set_rx_mode(struct net_device *netdev)
  1538. {
  1539. struct r8152 *tp = netdev_priv(netdev);
  1540. u32 mc_filter[2]; /* Multicast hash filter */
  1541. __le32 tmp[2];
  1542. u32 ocp_data;
  1543. clear_bit(RTL8152_SET_RX_MODE, &tp->flags);
  1544. netif_stop_queue(netdev);
  1545. ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
  1546. ocp_data &= ~RCR_ACPT_ALL;
  1547. ocp_data |= RCR_AB | RCR_APM;
  1548. if (netdev->flags & IFF_PROMISC) {
  1549. /* Unconditionally log net taps. */
  1550. netif_notice(tp, link, netdev, "Promiscuous mode enabled\n");
  1551. ocp_data |= RCR_AM | RCR_AAP;
  1552. mc_filter[1] = 0xffffffff;
  1553. mc_filter[0] = 0xffffffff;
  1554. } else if ((netdev_mc_count(netdev) > multicast_filter_limit) ||
  1555. (netdev->flags & IFF_ALLMULTI)) {
  1556. /* Too many to filter perfectly -- accept all multicasts. */
  1557. ocp_data |= RCR_AM;
  1558. mc_filter[1] = 0xffffffff;
  1559. mc_filter[0] = 0xffffffff;
  1560. } else {
  1561. struct netdev_hw_addr *ha;
  1562. mc_filter[1] = 0;
  1563. mc_filter[0] = 0;
  1564. netdev_for_each_mc_addr(ha, netdev) {
  1565. int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
  1566. mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
  1567. ocp_data |= RCR_AM;
  1568. }
  1569. }
  1570. tmp[0] = __cpu_to_le32(swab32(mc_filter[1]));
  1571. tmp[1] = __cpu_to_le32(swab32(mc_filter[0]));
  1572. pla_ocp_write(tp, PLA_MAR, BYTE_EN_DWORD, sizeof(tmp), tmp);
  1573. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
  1574. netif_wake_queue(netdev);
  1575. }
  1576. static netdev_features_t
  1577. rtl8152_features_check(struct sk_buff *skb, struct net_device *dev,
  1578. netdev_features_t features)
  1579. {
  1580. u32 mss = skb_shinfo(skb)->gso_size;
  1581. int max_offset = mss ? GTTCPHO_MAX : TCPHO_MAX;
  1582. int offset = skb_transport_offset(skb);
  1583. if ((mss || skb->ip_summed == CHECKSUM_PARTIAL) && offset > max_offset)
  1584. features &= ~(NETIF_F_ALL_CSUM | NETIF_F_GSO_MASK);
  1585. else if ((skb->len + sizeof(struct tx_desc)) > agg_buf_sz)
  1586. features &= ~NETIF_F_GSO_MASK;
  1587. return features;
  1588. }
  1589. static netdev_tx_t rtl8152_start_xmit(struct sk_buff *skb,
  1590. struct net_device *netdev)
  1591. {
  1592. struct r8152 *tp = netdev_priv(netdev);
  1593. skb_tx_timestamp(skb);
  1594. skb_queue_tail(&tp->tx_queue, skb);
  1595. if (!list_empty(&tp->tx_free)) {
  1596. if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
  1597. set_bit(SCHEDULE_NAPI, &tp->flags);
  1598. schedule_delayed_work(&tp->schedule, 0);
  1599. } else {
  1600. usb_mark_last_busy(tp->udev);
  1601. napi_schedule(&tp->napi);
  1602. }
  1603. } else if (skb_queue_len(&tp->tx_queue) > tp->tx_qlen) {
  1604. netif_stop_queue(netdev);
  1605. }
  1606. return NETDEV_TX_OK;
  1607. }
  1608. static void r8152b_reset_packet_filter(struct r8152 *tp)
  1609. {
  1610. u32 ocp_data;
  1611. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_FMC);
  1612. ocp_data &= ~FMC_FCR_MCU_EN;
  1613. ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
  1614. ocp_data |= FMC_FCR_MCU_EN;
  1615. ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
  1616. }
  1617. static void rtl8152_nic_reset(struct r8152 *tp)
  1618. {
  1619. int i;
  1620. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, CR_RST);
  1621. for (i = 0; i < 1000; i++) {
  1622. if (!(ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR) & CR_RST))
  1623. break;
  1624. usleep_range(100, 400);
  1625. }
  1626. }
  1627. static void set_tx_qlen(struct r8152 *tp)
  1628. {
  1629. struct net_device *netdev = tp->netdev;
  1630. tp->tx_qlen = agg_buf_sz / (netdev->mtu + VLAN_ETH_HLEN + VLAN_HLEN +
  1631. sizeof(struct tx_desc));
  1632. }
  1633. static inline u8 rtl8152_get_speed(struct r8152 *tp)
  1634. {
  1635. return ocp_read_byte(tp, MCU_TYPE_PLA, PLA_PHYSTATUS);
  1636. }
  1637. static void rtl_set_eee_plus(struct r8152 *tp)
  1638. {
  1639. u32 ocp_data;
  1640. u8 speed;
  1641. speed = rtl8152_get_speed(tp);
  1642. if (speed & _10bps) {
  1643. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR);
  1644. ocp_data |= EEEP_CR_EEEP_TX;
  1645. ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data);
  1646. } else {
  1647. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR);
  1648. ocp_data &= ~EEEP_CR_EEEP_TX;
  1649. ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data);
  1650. }
  1651. }
  1652. static void rxdy_gated_en(struct r8152 *tp, bool enable)
  1653. {
  1654. u32 ocp_data;
  1655. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1);
  1656. if (enable)
  1657. ocp_data |= RXDY_GATED_EN;
  1658. else
  1659. ocp_data &= ~RXDY_GATED_EN;
  1660. ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data);
  1661. }
  1662. static int rtl_start_rx(struct r8152 *tp)
  1663. {
  1664. int i, ret = 0;
  1665. napi_disable(&tp->napi);
  1666. INIT_LIST_HEAD(&tp->rx_done);
  1667. for (i = 0; i < RTL8152_MAX_RX; i++) {
  1668. INIT_LIST_HEAD(&tp->rx_info[i].list);
  1669. ret = r8152_submit_rx(tp, &tp->rx_info[i], GFP_KERNEL);
  1670. if (ret)
  1671. break;
  1672. }
  1673. napi_enable(&tp->napi);
  1674. if (ret && ++i < RTL8152_MAX_RX) {
  1675. struct list_head rx_queue;
  1676. unsigned long flags;
  1677. INIT_LIST_HEAD(&rx_queue);
  1678. do {
  1679. struct rx_agg *agg = &tp->rx_info[i++];
  1680. struct urb *urb = agg->urb;
  1681. urb->actual_length = 0;
  1682. list_add_tail(&agg->list, &rx_queue);
  1683. } while (i < RTL8152_MAX_RX);
  1684. spin_lock_irqsave(&tp->rx_lock, flags);
  1685. list_splice_tail(&rx_queue, &tp->rx_done);
  1686. spin_unlock_irqrestore(&tp->rx_lock, flags);
  1687. }
  1688. return ret;
  1689. }
  1690. static int rtl_stop_rx(struct r8152 *tp)
  1691. {
  1692. int i;
  1693. for (i = 0; i < RTL8152_MAX_RX; i++)
  1694. usb_kill_urb(tp->rx_info[i].urb);
  1695. while (!skb_queue_empty(&tp->rx_queue))
  1696. dev_kfree_skb(__skb_dequeue(&tp->rx_queue));
  1697. return 0;
  1698. }
  1699. static int rtl_enable(struct r8152 *tp)
  1700. {
  1701. u32 ocp_data;
  1702. r8152b_reset_packet_filter(tp);
  1703. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR);
  1704. ocp_data |= CR_RE | CR_TE;
  1705. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data);
  1706. rxdy_gated_en(tp, false);
  1707. return 0;
  1708. }
  1709. static int rtl8152_enable(struct r8152 *tp)
  1710. {
  1711. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  1712. return -ENODEV;
  1713. set_tx_qlen(tp);
  1714. rtl_set_eee_plus(tp);
  1715. return rtl_enable(tp);
  1716. }
  1717. static void r8153_set_rx_agg(struct r8152 *tp)
  1718. {
  1719. u8 speed;
  1720. speed = rtl8152_get_speed(tp);
  1721. if (speed & _1000bps) {
  1722. if (tp->udev->speed == USB_SPEED_SUPER) {
  1723. ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH,
  1724. RX_THR_SUPPER);
  1725. ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_EARLY_AGG,
  1726. EARLY_AGG_SUPPER);
  1727. } else {
  1728. ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH,
  1729. RX_THR_HIGH);
  1730. ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_EARLY_AGG,
  1731. EARLY_AGG_HIGH);
  1732. }
  1733. } else {
  1734. ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_SLOW);
  1735. ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_EARLY_AGG,
  1736. EARLY_AGG_SLOW);
  1737. }
  1738. }
  1739. static int rtl8153_enable(struct r8152 *tp)
  1740. {
  1741. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  1742. return -ENODEV;
  1743. set_tx_qlen(tp);
  1744. rtl_set_eee_plus(tp);
  1745. r8153_set_rx_agg(tp);
  1746. return rtl_enable(tp);
  1747. }
  1748. static void rtl_disable(struct r8152 *tp)
  1749. {
  1750. u32 ocp_data;
  1751. int i;
  1752. if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
  1753. rtl_drop_queued_tx(tp);
  1754. return;
  1755. }
  1756. ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
  1757. ocp_data &= ~RCR_ACPT_ALL;
  1758. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
  1759. rtl_drop_queued_tx(tp);
  1760. for (i = 0; i < RTL8152_MAX_TX; i++)
  1761. usb_kill_urb(tp->tx_info[i].urb);
  1762. rxdy_gated_en(tp, true);
  1763. for (i = 0; i < 1000; i++) {
  1764. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  1765. if ((ocp_data & FIFO_EMPTY) == FIFO_EMPTY)
  1766. break;
  1767. usleep_range(1000, 2000);
  1768. }
  1769. for (i = 0; i < 1000; i++) {
  1770. if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0) & TCR0_TX_EMPTY)
  1771. break;
  1772. usleep_range(1000, 2000);
  1773. }
  1774. rtl_stop_rx(tp);
  1775. rtl8152_nic_reset(tp);
  1776. }
  1777. static void r8152_power_cut_en(struct r8152 *tp, bool enable)
  1778. {
  1779. u32 ocp_data;
  1780. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CTRL);
  1781. if (enable)
  1782. ocp_data |= POWER_CUT;
  1783. else
  1784. ocp_data &= ~POWER_CUT;
  1785. ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CTRL, ocp_data);
  1786. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS);
  1787. ocp_data &= ~RESUME_INDICATE;
  1788. ocp_write_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS, ocp_data);
  1789. }
  1790. static void rtl_rx_vlan_en(struct r8152 *tp, bool enable)
  1791. {
  1792. u32 ocp_data;
  1793. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR);
  1794. if (enable)
  1795. ocp_data |= CPCR_RX_VLAN;
  1796. else
  1797. ocp_data &= ~CPCR_RX_VLAN;
  1798. ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data);
  1799. }
  1800. static int rtl8152_set_features(struct net_device *dev,
  1801. netdev_features_t features)
  1802. {
  1803. netdev_features_t changed = features ^ dev->features;
  1804. struct r8152 *tp = netdev_priv(dev);
  1805. int ret;
  1806. ret = usb_autopm_get_interface(tp->intf);
  1807. if (ret < 0)
  1808. goto out;
  1809. mutex_lock(&tp->control);
  1810. if (changed & NETIF_F_HW_VLAN_CTAG_RX) {
  1811. if (features & NETIF_F_HW_VLAN_CTAG_RX)
  1812. rtl_rx_vlan_en(tp, true);
  1813. else
  1814. rtl_rx_vlan_en(tp, false);
  1815. }
  1816. mutex_unlock(&tp->control);
  1817. usb_autopm_put_interface(tp->intf);
  1818. out:
  1819. return ret;
  1820. }
  1821. #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
  1822. static u32 __rtl_get_wol(struct r8152 *tp)
  1823. {
  1824. u32 ocp_data;
  1825. u32 wolopts = 0;
  1826. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CONFIG5);
  1827. if (!(ocp_data & LAN_WAKE_EN))
  1828. return 0;
  1829. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
  1830. if (ocp_data & LINK_ON_WAKE_EN)
  1831. wolopts |= WAKE_PHY;
  1832. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5);
  1833. if (ocp_data & UWF_EN)
  1834. wolopts |= WAKE_UCAST;
  1835. if (ocp_data & BWF_EN)
  1836. wolopts |= WAKE_BCAST;
  1837. if (ocp_data & MWF_EN)
  1838. wolopts |= WAKE_MCAST;
  1839. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL);
  1840. if (ocp_data & MAGIC_EN)
  1841. wolopts |= WAKE_MAGIC;
  1842. return wolopts;
  1843. }
  1844. static void __rtl_set_wol(struct r8152 *tp, u32 wolopts)
  1845. {
  1846. u32 ocp_data;
  1847. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
  1848. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
  1849. ocp_data &= ~LINK_ON_WAKE_EN;
  1850. if (wolopts & WAKE_PHY)
  1851. ocp_data |= LINK_ON_WAKE_EN;
  1852. ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
  1853. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5);
  1854. ocp_data &= ~(UWF_EN | BWF_EN | MWF_EN | LAN_WAKE_EN);
  1855. if (wolopts & WAKE_UCAST)
  1856. ocp_data |= UWF_EN;
  1857. if (wolopts & WAKE_BCAST)
  1858. ocp_data |= BWF_EN;
  1859. if (wolopts & WAKE_MCAST)
  1860. ocp_data |= MWF_EN;
  1861. if (wolopts & WAKE_ANY)
  1862. ocp_data |= LAN_WAKE_EN;
  1863. ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG5, ocp_data);
  1864. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
  1865. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL);
  1866. ocp_data &= ~MAGIC_EN;
  1867. if (wolopts & WAKE_MAGIC)
  1868. ocp_data |= MAGIC_EN;
  1869. ocp_write_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL, ocp_data);
  1870. if (wolopts & WAKE_ANY)
  1871. device_set_wakeup_enable(&tp->udev->dev, true);
  1872. else
  1873. device_set_wakeup_enable(&tp->udev->dev, false);
  1874. }
  1875. static void rtl_runtime_suspend_enable(struct r8152 *tp, bool enable)
  1876. {
  1877. if (enable) {
  1878. u32 ocp_data;
  1879. __rtl_set_wol(tp, WAKE_ANY);
  1880. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
  1881. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
  1882. ocp_data |= LINK_OFF_WAKE_EN;
  1883. ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
  1884. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
  1885. } else {
  1886. __rtl_set_wol(tp, tp->saved_wolopts);
  1887. }
  1888. }
  1889. static void rtl_phy_reset(struct r8152 *tp)
  1890. {
  1891. u16 data;
  1892. int i;
  1893. clear_bit(PHY_RESET, &tp->flags);
  1894. data = r8152_mdio_read(tp, MII_BMCR);
  1895. /* don't reset again before the previous one complete */
  1896. if (data & BMCR_RESET)
  1897. return;
  1898. data |= BMCR_RESET;
  1899. r8152_mdio_write(tp, MII_BMCR, data);
  1900. for (i = 0; i < 50; i++) {
  1901. msleep(20);
  1902. if ((r8152_mdio_read(tp, MII_BMCR) & BMCR_RESET) == 0)
  1903. break;
  1904. }
  1905. }
  1906. static void r8153_teredo_off(struct r8152 *tp)
  1907. {
  1908. u32 ocp_data;
  1909. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG);
  1910. ocp_data &= ~(TEREDO_SEL | TEREDO_RS_EVENT_MASK | OOB_TEREDO_EN);
  1911. ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data);
  1912. ocp_write_word(tp, MCU_TYPE_PLA, PLA_WDT6_CTRL, WDT6_SET_MODE);
  1913. ocp_write_word(tp, MCU_TYPE_PLA, PLA_REALWOW_TIMER, 0);
  1914. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TEREDO_TIMER, 0);
  1915. }
  1916. static void r8152b_disable_aldps(struct r8152 *tp)
  1917. {
  1918. ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPDNPS | LINKENA | DIS_SDSAVE);
  1919. msleep(20);
  1920. }
  1921. static inline void r8152b_enable_aldps(struct r8152 *tp)
  1922. {
  1923. ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPWRSAVE | ENPDNPS |
  1924. LINKENA | DIS_SDSAVE);
  1925. }
  1926. static void rtl8152_disable(struct r8152 *tp)
  1927. {
  1928. r8152b_disable_aldps(tp);
  1929. rtl_disable(tp);
  1930. r8152b_enable_aldps(tp);
  1931. }
  1932. static void r8152b_hw_phy_cfg(struct r8152 *tp)
  1933. {
  1934. u16 data;
  1935. data = r8152_mdio_read(tp, MII_BMCR);
  1936. if (data & BMCR_PDOWN) {
  1937. data &= ~BMCR_PDOWN;
  1938. r8152_mdio_write(tp, MII_BMCR, data);
  1939. }
  1940. set_bit(PHY_RESET, &tp->flags);
  1941. }
  1942. static void r8152b_exit_oob(struct r8152 *tp)
  1943. {
  1944. u32 ocp_data;
  1945. int i;
  1946. ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
  1947. ocp_data &= ~RCR_ACPT_ALL;
  1948. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
  1949. rxdy_gated_en(tp, true);
  1950. r8153_teredo_off(tp);
  1951. r8152b_hw_phy_cfg(tp);
  1952. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
  1953. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, 0x00);
  1954. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  1955. ocp_data &= ~NOW_IS_OOB;
  1956. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
  1957. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
  1958. ocp_data &= ~MCU_BORW_EN;
  1959. ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
  1960. for (i = 0; i < 1000; i++) {
  1961. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  1962. if (ocp_data & LINK_LIST_READY)
  1963. break;
  1964. usleep_range(1000, 2000);
  1965. }
  1966. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
  1967. ocp_data |= RE_INIT_LL;
  1968. ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
  1969. for (i = 0; i < 1000; i++) {
  1970. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  1971. if (ocp_data & LINK_LIST_READY)
  1972. break;
  1973. usleep_range(1000, 2000);
  1974. }
  1975. rtl8152_nic_reset(tp);
  1976. /* rx share fifo credit full threshold */
  1977. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);
  1978. if (tp->udev->speed == USB_SPEED_FULL ||
  1979. tp->udev->speed == USB_SPEED_LOW) {
  1980. /* rx share fifo credit near full threshold */
  1981. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
  1982. RXFIFO_THR2_FULL);
  1983. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
  1984. RXFIFO_THR3_FULL);
  1985. } else {
  1986. /* rx share fifo credit near full threshold */
  1987. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
  1988. RXFIFO_THR2_HIGH);
  1989. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
  1990. RXFIFO_THR3_HIGH);
  1991. }
  1992. /* TX share fifo free credit full threshold */
  1993. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL);
  1994. ocp_write_byte(tp, MCU_TYPE_USB, USB_TX_AGG, TX_AGG_MAX_THRESHOLD);
  1995. ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_HIGH);
  1996. ocp_write_dword(tp, MCU_TYPE_USB, USB_TX_DMA,
  1997. TEST_MODE_DISABLE | TX_SIZE_ADJUST1);
  1998. rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX);
  1999. ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
  2000. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
  2001. ocp_data |= TCR0_AUTO_FIFO;
  2002. ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data);
  2003. }
  2004. static void r8152b_enter_oob(struct r8152 *tp)
  2005. {
  2006. u32 ocp_data;
  2007. int i;
  2008. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  2009. ocp_data &= ~NOW_IS_OOB;
  2010. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
  2011. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_OOB);
  2012. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_OOB);
  2013. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_OOB);
  2014. rtl_disable(tp);
  2015. for (i = 0; i < 1000; i++) {
  2016. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  2017. if (ocp_data & LINK_LIST_READY)
  2018. break;
  2019. usleep_range(1000, 2000);
  2020. }
  2021. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
  2022. ocp_data |= RE_INIT_LL;
  2023. ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
  2024. for (i = 0; i < 1000; i++) {
  2025. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  2026. if (ocp_data & LINK_LIST_READY)
  2027. break;
  2028. usleep_range(1000, 2000);
  2029. }
  2030. ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
  2031. rtl_rx_vlan_en(tp, true);
  2032. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PAL_BDC_CR);
  2033. ocp_data |= ALDPS_PROXY_MODE;
  2034. ocp_write_word(tp, MCU_TYPE_PLA, PAL_BDC_CR, ocp_data);
  2035. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  2036. ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
  2037. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
  2038. rxdy_gated_en(tp, false);
  2039. ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
  2040. ocp_data |= RCR_APM | RCR_AM | RCR_AB;
  2041. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
  2042. }
  2043. static void r8153_hw_phy_cfg(struct r8152 *tp)
  2044. {
  2045. u32 ocp_data;
  2046. u16 data;
  2047. ocp_reg_write(tp, OCP_ADC_CFG, CKADSEL_L | ADC_EN | EN_EMI_L);
  2048. data = r8152_mdio_read(tp, MII_BMCR);
  2049. if (data & BMCR_PDOWN) {
  2050. data &= ~BMCR_PDOWN;
  2051. r8152_mdio_write(tp, MII_BMCR, data);
  2052. }
  2053. if (tp->version == RTL_VER_03) {
  2054. data = ocp_reg_read(tp, OCP_EEE_CFG);
  2055. data &= ~CTAP_SHORT_EN;
  2056. ocp_reg_write(tp, OCP_EEE_CFG, data);
  2057. }
  2058. data = ocp_reg_read(tp, OCP_POWER_CFG);
  2059. data |= EEE_CLKDIV_EN;
  2060. ocp_reg_write(tp, OCP_POWER_CFG, data);
  2061. data = ocp_reg_read(tp, OCP_DOWN_SPEED);
  2062. data |= EN_10M_BGOFF;
  2063. ocp_reg_write(tp, OCP_DOWN_SPEED, data);
  2064. data = ocp_reg_read(tp, OCP_POWER_CFG);
  2065. data |= EN_10M_PLLOFF;
  2066. ocp_reg_write(tp, OCP_POWER_CFG, data);
  2067. data = sram_read(tp, SRAM_IMPEDANCE);
  2068. data &= ~RX_DRIVING_MASK;
  2069. sram_write(tp, SRAM_IMPEDANCE, data);
  2070. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
  2071. ocp_data |= PFM_PWM_SWITCH;
  2072. ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
  2073. data = sram_read(tp, SRAM_LPF_CFG);
  2074. data |= LPF_AUTO_TUNE;
  2075. sram_write(tp, SRAM_LPF_CFG, data);
  2076. data = sram_read(tp, SRAM_10M_AMP1);
  2077. data |= GDAC_IB_UPALL;
  2078. sram_write(tp, SRAM_10M_AMP1, data);
  2079. data = sram_read(tp, SRAM_10M_AMP2);
  2080. data |= AMP_DN;
  2081. sram_write(tp, SRAM_10M_AMP2, data);
  2082. set_bit(PHY_RESET, &tp->flags);
  2083. }
  2084. static void r8153_u1u2en(struct r8152 *tp, bool enable)
  2085. {
  2086. u8 u1u2[8];
  2087. if (enable)
  2088. memset(u1u2, 0xff, sizeof(u1u2));
  2089. else
  2090. memset(u1u2, 0x00, sizeof(u1u2));
  2091. usb_ocp_write(tp, USB_TOLERANCE, BYTE_EN_SIX_BYTES, sizeof(u1u2), u1u2);
  2092. }
  2093. static void r8153_u2p3en(struct r8152 *tp, bool enable)
  2094. {
  2095. u32 ocp_data;
  2096. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL);
  2097. if (enable)
  2098. ocp_data |= U2P3_ENABLE;
  2099. else
  2100. ocp_data &= ~U2P3_ENABLE;
  2101. ocp_write_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL, ocp_data);
  2102. }
  2103. static void r8153_power_cut_en(struct r8152 *tp, bool enable)
  2104. {
  2105. u32 ocp_data;
  2106. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_POWER_CUT);
  2107. if (enable)
  2108. ocp_data |= PWR_EN | PHASE2_EN;
  2109. else
  2110. ocp_data &= ~(PWR_EN | PHASE2_EN);
  2111. ocp_write_word(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
  2112. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
  2113. ocp_data &= ~PCUT_STATUS;
  2114. ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);
  2115. }
  2116. static void r8153_first_init(struct r8152 *tp)
  2117. {
  2118. u32 ocp_data;
  2119. int i;
  2120. rxdy_gated_en(tp, true);
  2121. r8153_teredo_off(tp);
  2122. ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
  2123. ocp_data &= ~RCR_ACPT_ALL;
  2124. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
  2125. r8153_hw_phy_cfg(tp);
  2126. rtl8152_nic_reset(tp);
  2127. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  2128. ocp_data &= ~NOW_IS_OOB;
  2129. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
  2130. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
  2131. ocp_data &= ~MCU_BORW_EN;
  2132. ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
  2133. for (i = 0; i < 1000; i++) {
  2134. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  2135. if (ocp_data & LINK_LIST_READY)
  2136. break;
  2137. usleep_range(1000, 2000);
  2138. }
  2139. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
  2140. ocp_data |= RE_INIT_LL;
  2141. ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
  2142. for (i = 0; i < 1000; i++) {
  2143. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  2144. if (ocp_data & LINK_LIST_READY)
  2145. break;
  2146. usleep_range(1000, 2000);
  2147. }
  2148. rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX);
  2149. ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8153_RMS);
  2150. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_MTPS, MTPS_JUMBO);
  2151. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
  2152. ocp_data |= TCR0_AUTO_FIFO;
  2153. ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data);
  2154. rtl8152_nic_reset(tp);
  2155. /* rx share fifo credit full threshold */
  2156. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);
  2157. ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_NORMAL);
  2158. ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_NORMAL);
  2159. /* TX share fifo free credit full threshold */
  2160. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL2);
  2161. /* rx aggregation */
  2162. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
  2163. ocp_data &= ~RX_AGG_DISABLE;
  2164. ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
  2165. }
  2166. static void r8153_enter_oob(struct r8152 *tp)
  2167. {
  2168. u32 ocp_data;
  2169. int i;
  2170. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  2171. ocp_data &= ~NOW_IS_OOB;
  2172. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
  2173. rtl_disable(tp);
  2174. for (i = 0; i < 1000; i++) {
  2175. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  2176. if (ocp_data & LINK_LIST_READY)
  2177. break;
  2178. usleep_range(1000, 2000);
  2179. }
  2180. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
  2181. ocp_data |= RE_INIT_LL;
  2182. ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
  2183. for (i = 0; i < 1000; i++) {
  2184. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  2185. if (ocp_data & LINK_LIST_READY)
  2186. break;
  2187. usleep_range(1000, 2000);
  2188. }
  2189. ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8153_RMS);
  2190. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG);
  2191. ocp_data &= ~TEREDO_WAKE_MASK;
  2192. ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data);
  2193. rtl_rx_vlan_en(tp, true);
  2194. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PAL_BDC_CR);
  2195. ocp_data |= ALDPS_PROXY_MODE;
  2196. ocp_write_word(tp, MCU_TYPE_PLA, PAL_BDC_CR, ocp_data);
  2197. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  2198. ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
  2199. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
  2200. rxdy_gated_en(tp, false);
  2201. ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
  2202. ocp_data |= RCR_APM | RCR_AM | RCR_AB;
  2203. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
  2204. }
  2205. static void r8153_disable_aldps(struct r8152 *tp)
  2206. {
  2207. u16 data;
  2208. data = ocp_reg_read(tp, OCP_POWER_CFG);
  2209. data &= ~EN_ALDPS;
  2210. ocp_reg_write(tp, OCP_POWER_CFG, data);
  2211. msleep(20);
  2212. }
  2213. static void r8153_enable_aldps(struct r8152 *tp)
  2214. {
  2215. u16 data;
  2216. data = ocp_reg_read(tp, OCP_POWER_CFG);
  2217. data |= EN_ALDPS;
  2218. ocp_reg_write(tp, OCP_POWER_CFG, data);
  2219. }
  2220. static void rtl8153_disable(struct r8152 *tp)
  2221. {
  2222. r8153_disable_aldps(tp);
  2223. rtl_disable(tp);
  2224. r8153_enable_aldps(tp);
  2225. }
  2226. static int rtl8152_set_speed(struct r8152 *tp, u8 autoneg, u16 speed, u8 duplex)
  2227. {
  2228. u16 bmcr, anar, gbcr;
  2229. int ret = 0;
  2230. cancel_delayed_work_sync(&tp->schedule);
  2231. anar = r8152_mdio_read(tp, MII_ADVERTISE);
  2232. anar &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
  2233. ADVERTISE_100HALF | ADVERTISE_100FULL);
  2234. if (tp->mii.supports_gmii) {
  2235. gbcr = r8152_mdio_read(tp, MII_CTRL1000);
  2236. gbcr &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
  2237. } else {
  2238. gbcr = 0;
  2239. }
  2240. if (autoneg == AUTONEG_DISABLE) {
  2241. if (speed == SPEED_10) {
  2242. bmcr = 0;
  2243. anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
  2244. } else if (speed == SPEED_100) {
  2245. bmcr = BMCR_SPEED100;
  2246. anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
  2247. } else if (speed == SPEED_1000 && tp->mii.supports_gmii) {
  2248. bmcr = BMCR_SPEED1000;
  2249. gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
  2250. } else {
  2251. ret = -EINVAL;
  2252. goto out;
  2253. }
  2254. if (duplex == DUPLEX_FULL)
  2255. bmcr |= BMCR_FULLDPLX;
  2256. } else {
  2257. if (speed == SPEED_10) {
  2258. if (duplex == DUPLEX_FULL)
  2259. anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
  2260. else
  2261. anar |= ADVERTISE_10HALF;
  2262. } else if (speed == SPEED_100) {
  2263. if (duplex == DUPLEX_FULL) {
  2264. anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
  2265. anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
  2266. } else {
  2267. anar |= ADVERTISE_10HALF;
  2268. anar |= ADVERTISE_100HALF;
  2269. }
  2270. } else if (speed == SPEED_1000 && tp->mii.supports_gmii) {
  2271. if (duplex == DUPLEX_FULL) {
  2272. anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
  2273. anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
  2274. gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
  2275. } else {
  2276. anar |= ADVERTISE_10HALF;
  2277. anar |= ADVERTISE_100HALF;
  2278. gbcr |= ADVERTISE_1000HALF;
  2279. }
  2280. } else {
  2281. ret = -EINVAL;
  2282. goto out;
  2283. }
  2284. bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
  2285. }
  2286. if (test_bit(PHY_RESET, &tp->flags))
  2287. bmcr |= BMCR_RESET;
  2288. if (tp->mii.supports_gmii)
  2289. r8152_mdio_write(tp, MII_CTRL1000, gbcr);
  2290. r8152_mdio_write(tp, MII_ADVERTISE, anar);
  2291. r8152_mdio_write(tp, MII_BMCR, bmcr);
  2292. if (test_bit(PHY_RESET, &tp->flags)) {
  2293. int i;
  2294. clear_bit(PHY_RESET, &tp->flags);
  2295. for (i = 0; i < 50; i++) {
  2296. msleep(20);
  2297. if ((r8152_mdio_read(tp, MII_BMCR) & BMCR_RESET) == 0)
  2298. break;
  2299. }
  2300. }
  2301. out:
  2302. return ret;
  2303. }
  2304. static void rtl8152_up(struct r8152 *tp)
  2305. {
  2306. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  2307. return;
  2308. r8152b_disable_aldps(tp);
  2309. r8152b_exit_oob(tp);
  2310. r8152b_enable_aldps(tp);
  2311. }
  2312. static void rtl8152_down(struct r8152 *tp)
  2313. {
  2314. if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
  2315. rtl_drop_queued_tx(tp);
  2316. return;
  2317. }
  2318. r8152_power_cut_en(tp, false);
  2319. r8152b_disable_aldps(tp);
  2320. r8152b_enter_oob(tp);
  2321. r8152b_enable_aldps(tp);
  2322. }
  2323. static void rtl8153_up(struct r8152 *tp)
  2324. {
  2325. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  2326. return;
  2327. r8153_disable_aldps(tp);
  2328. r8153_first_init(tp);
  2329. r8153_enable_aldps(tp);
  2330. }
  2331. static void rtl8153_down(struct r8152 *tp)
  2332. {
  2333. if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
  2334. rtl_drop_queued_tx(tp);
  2335. return;
  2336. }
  2337. r8153_u1u2en(tp, false);
  2338. r8153_power_cut_en(tp, false);
  2339. r8153_disable_aldps(tp);
  2340. r8153_enter_oob(tp);
  2341. r8153_enable_aldps(tp);
  2342. }
  2343. static void set_carrier(struct r8152 *tp)
  2344. {
  2345. struct net_device *netdev = tp->netdev;
  2346. u8 speed;
  2347. clear_bit(RTL8152_LINK_CHG, &tp->flags);
  2348. speed = rtl8152_get_speed(tp);
  2349. if (speed & LINK_STATUS) {
  2350. if (!(tp->speed & LINK_STATUS)) {
  2351. tp->rtl_ops.enable(tp);
  2352. set_bit(RTL8152_SET_RX_MODE, &tp->flags);
  2353. netif_carrier_on(netdev);
  2354. rtl_start_rx(tp);
  2355. }
  2356. } else {
  2357. if (tp->speed & LINK_STATUS) {
  2358. netif_carrier_off(netdev);
  2359. napi_disable(&tp->napi);
  2360. tp->rtl_ops.disable(tp);
  2361. napi_enable(&tp->napi);
  2362. }
  2363. }
  2364. tp->speed = speed;
  2365. }
  2366. static void rtl_work_func_t(struct work_struct *work)
  2367. {
  2368. struct r8152 *tp = container_of(work, struct r8152, schedule.work);
  2369. /* If the device is unplugged or !netif_running(), the workqueue
  2370. * doesn't need to wake the device, and could return directly.
  2371. */
  2372. if (test_bit(RTL8152_UNPLUG, &tp->flags) || !netif_running(tp->netdev))
  2373. return;
  2374. if (usb_autopm_get_interface(tp->intf) < 0)
  2375. return;
  2376. if (!test_bit(WORK_ENABLE, &tp->flags))
  2377. goto out1;
  2378. if (!mutex_trylock(&tp->control)) {
  2379. schedule_delayed_work(&tp->schedule, 0);
  2380. goto out1;
  2381. }
  2382. if (test_bit(RTL8152_LINK_CHG, &tp->flags))
  2383. set_carrier(tp);
  2384. if (test_bit(RTL8152_SET_RX_MODE, &tp->flags))
  2385. _rtl8152_set_rx_mode(tp->netdev);
  2386. /* don't schedule napi before linking */
  2387. if (test_bit(SCHEDULE_NAPI, &tp->flags) &&
  2388. (tp->speed & LINK_STATUS)) {
  2389. clear_bit(SCHEDULE_NAPI, &tp->flags);
  2390. napi_schedule(&tp->napi);
  2391. }
  2392. if (test_bit(PHY_RESET, &tp->flags))
  2393. rtl_phy_reset(tp);
  2394. mutex_unlock(&tp->control);
  2395. out1:
  2396. usb_autopm_put_interface(tp->intf);
  2397. }
  2398. static int rtl8152_open(struct net_device *netdev)
  2399. {
  2400. struct r8152 *tp = netdev_priv(netdev);
  2401. int res = 0;
  2402. res = alloc_all_mem(tp);
  2403. if (res)
  2404. goto out;
  2405. /* set speed to 0 to avoid autoresume try to submit rx */
  2406. tp->speed = 0;
  2407. res = usb_autopm_get_interface(tp->intf);
  2408. if (res < 0) {
  2409. free_all_mem(tp);
  2410. goto out;
  2411. }
  2412. mutex_lock(&tp->control);
  2413. /* The WORK_ENABLE may be set when autoresume occurs */
  2414. if (test_bit(WORK_ENABLE, &tp->flags)) {
  2415. clear_bit(WORK_ENABLE, &tp->flags);
  2416. usb_kill_urb(tp->intr_urb);
  2417. cancel_delayed_work_sync(&tp->schedule);
  2418. /* disable the tx/rx, if the workqueue has enabled them. */
  2419. if (tp->speed & LINK_STATUS)
  2420. tp->rtl_ops.disable(tp);
  2421. }
  2422. tp->rtl_ops.up(tp);
  2423. rtl8152_set_speed(tp, AUTONEG_ENABLE,
  2424. tp->mii.supports_gmii ? SPEED_1000 : SPEED_100,
  2425. DUPLEX_FULL);
  2426. tp->speed = 0;
  2427. netif_carrier_off(netdev);
  2428. netif_start_queue(netdev);
  2429. set_bit(WORK_ENABLE, &tp->flags);
  2430. res = usb_submit_urb(tp->intr_urb, GFP_KERNEL);
  2431. if (res) {
  2432. if (res == -ENODEV)
  2433. netif_device_detach(tp->netdev);
  2434. netif_warn(tp, ifup, netdev, "intr_urb submit failed: %d\n",
  2435. res);
  2436. free_all_mem(tp);
  2437. } else {
  2438. napi_enable(&tp->napi);
  2439. }
  2440. mutex_unlock(&tp->control);
  2441. usb_autopm_put_interface(tp->intf);
  2442. out:
  2443. return res;
  2444. }
  2445. static int rtl8152_close(struct net_device *netdev)
  2446. {
  2447. struct r8152 *tp = netdev_priv(netdev);
  2448. int res = 0;
  2449. napi_disable(&tp->napi);
  2450. clear_bit(WORK_ENABLE, &tp->flags);
  2451. usb_kill_urb(tp->intr_urb);
  2452. cancel_delayed_work_sync(&tp->schedule);
  2453. netif_stop_queue(netdev);
  2454. res = usb_autopm_get_interface(tp->intf);
  2455. if (res < 0) {
  2456. rtl_drop_queued_tx(tp);
  2457. rtl_stop_rx(tp);
  2458. } else {
  2459. mutex_lock(&tp->control);
  2460. /* The autosuspend may have been enabled and wouldn't
  2461. * be disable when autoresume occurs, because the
  2462. * netif_running() would be false.
  2463. */
  2464. rtl_runtime_suspend_enable(tp, false);
  2465. tp->rtl_ops.down(tp);
  2466. mutex_unlock(&tp->control);
  2467. usb_autopm_put_interface(tp->intf);
  2468. }
  2469. free_all_mem(tp);
  2470. return res;
  2471. }
  2472. static inline void r8152_mmd_indirect(struct r8152 *tp, u16 dev, u16 reg)
  2473. {
  2474. ocp_reg_write(tp, OCP_EEE_AR, FUN_ADDR | dev);
  2475. ocp_reg_write(tp, OCP_EEE_DATA, reg);
  2476. ocp_reg_write(tp, OCP_EEE_AR, FUN_DATA | dev);
  2477. }
  2478. static u16 r8152_mmd_read(struct r8152 *tp, u16 dev, u16 reg)
  2479. {
  2480. u16 data;
  2481. r8152_mmd_indirect(tp, dev, reg);
  2482. data = ocp_reg_read(tp, OCP_EEE_DATA);
  2483. ocp_reg_write(tp, OCP_EEE_AR, 0x0000);
  2484. return data;
  2485. }
  2486. static void r8152_mmd_write(struct r8152 *tp, u16 dev, u16 reg, u16 data)
  2487. {
  2488. r8152_mmd_indirect(tp, dev, reg);
  2489. ocp_reg_write(tp, OCP_EEE_DATA, data);
  2490. ocp_reg_write(tp, OCP_EEE_AR, 0x0000);
  2491. }
  2492. static void r8152_eee_en(struct r8152 *tp, bool enable)
  2493. {
  2494. u16 config1, config2, config3;
  2495. u32 ocp_data;
  2496. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
  2497. config1 = ocp_reg_read(tp, OCP_EEE_CONFIG1) & ~sd_rise_time_mask;
  2498. config2 = ocp_reg_read(tp, OCP_EEE_CONFIG2);
  2499. config3 = ocp_reg_read(tp, OCP_EEE_CONFIG3) & ~fast_snr_mask;
  2500. if (enable) {
  2501. ocp_data |= EEE_RX_EN | EEE_TX_EN;
  2502. config1 |= EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN | RX_QUIET_EN;
  2503. config1 |= sd_rise_time(1);
  2504. config2 |= RG_DACQUIET_EN | RG_LDVQUIET_EN;
  2505. config3 |= fast_snr(42);
  2506. } else {
  2507. ocp_data &= ~(EEE_RX_EN | EEE_TX_EN);
  2508. config1 &= ~(EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN |
  2509. RX_QUIET_EN);
  2510. config1 |= sd_rise_time(7);
  2511. config2 &= ~(RG_DACQUIET_EN | RG_LDVQUIET_EN);
  2512. config3 |= fast_snr(511);
  2513. }
  2514. ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data);
  2515. ocp_reg_write(tp, OCP_EEE_CONFIG1, config1);
  2516. ocp_reg_write(tp, OCP_EEE_CONFIG2, config2);
  2517. ocp_reg_write(tp, OCP_EEE_CONFIG3, config3);
  2518. }
  2519. static void r8152b_enable_eee(struct r8152 *tp)
  2520. {
  2521. r8152_eee_en(tp, true);
  2522. r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, MDIO_EEE_100TX);
  2523. }
  2524. static void r8153_eee_en(struct r8152 *tp, bool enable)
  2525. {
  2526. u32 ocp_data;
  2527. u16 config;
  2528. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
  2529. config = ocp_reg_read(tp, OCP_EEE_CFG);
  2530. if (enable) {
  2531. ocp_data |= EEE_RX_EN | EEE_TX_EN;
  2532. config |= EEE10_EN;
  2533. } else {
  2534. ocp_data &= ~(EEE_RX_EN | EEE_TX_EN);
  2535. config &= ~EEE10_EN;
  2536. }
  2537. ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data);
  2538. ocp_reg_write(tp, OCP_EEE_CFG, config);
  2539. }
  2540. static void r8153_enable_eee(struct r8152 *tp)
  2541. {
  2542. r8153_eee_en(tp, true);
  2543. ocp_reg_write(tp, OCP_EEE_ADV, MDIO_EEE_1000T | MDIO_EEE_100TX);
  2544. }
  2545. static void r8152b_enable_fc(struct r8152 *tp)
  2546. {
  2547. u16 anar;
  2548. anar = r8152_mdio_read(tp, MII_ADVERTISE);
  2549. anar |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
  2550. r8152_mdio_write(tp, MII_ADVERTISE, anar);
  2551. }
  2552. static void rtl_tally_reset(struct r8152 *tp)
  2553. {
  2554. u32 ocp_data;
  2555. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY);
  2556. ocp_data |= TALLY_RESET;
  2557. ocp_write_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY, ocp_data);
  2558. }
  2559. static void r8152b_init(struct r8152 *tp)
  2560. {
  2561. u32 ocp_data;
  2562. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  2563. return;
  2564. r8152b_disable_aldps(tp);
  2565. if (tp->version == RTL_VER_01) {
  2566. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
  2567. ocp_data &= ~LED_MODE_MASK;
  2568. ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data);
  2569. }
  2570. r8152_power_cut_en(tp, false);
  2571. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
  2572. ocp_data |= TX_10M_IDLE_EN | PFM_PWM_SWITCH;
  2573. ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
  2574. ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL);
  2575. ocp_data &= ~MCU_CLK_RATIO_MASK;
  2576. ocp_data |= MCU_CLK_RATIO | D3_CLK_GATED_EN;
  2577. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ocp_data);
  2578. ocp_data = GPHY_STS_MSK | SPEED_DOWN_MSK |
  2579. SPDWN_RXDV_MSK | SPDWN_LINKCHG_MSK;
  2580. ocp_write_word(tp, MCU_TYPE_PLA, PLA_GPHY_INTR_IMR, ocp_data);
  2581. r8152b_enable_eee(tp);
  2582. r8152b_enable_aldps(tp);
  2583. r8152b_enable_fc(tp);
  2584. rtl_tally_reset(tp);
  2585. /* enable rx aggregation */
  2586. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
  2587. ocp_data &= ~RX_AGG_DISABLE;
  2588. ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
  2589. }
  2590. static void r8153_init(struct r8152 *tp)
  2591. {
  2592. u32 ocp_data;
  2593. int i;
  2594. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  2595. return;
  2596. r8153_disable_aldps(tp);
  2597. r8153_u1u2en(tp, false);
  2598. for (i = 0; i < 500; i++) {
  2599. if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
  2600. AUTOLOAD_DONE)
  2601. break;
  2602. msleep(20);
  2603. }
  2604. for (i = 0; i < 500; i++) {
  2605. ocp_data = ocp_reg_read(tp, OCP_PHY_STATUS) & PHY_STAT_MASK;
  2606. if (ocp_data == PHY_STAT_LAN_ON || ocp_data == PHY_STAT_PWRDN)
  2607. break;
  2608. msleep(20);
  2609. }
  2610. r8153_u2p3en(tp, false);
  2611. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL);
  2612. ocp_data &= ~TIMER11_EN;
  2613. ocp_write_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL, ocp_data);
  2614. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
  2615. ocp_data &= ~LED_MODE_MASK;
  2616. ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data);
  2617. ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_LPM_CTRL);
  2618. ocp_data &= ~LPM_TIMER_MASK;
  2619. if (tp->udev->speed == USB_SPEED_SUPER)
  2620. ocp_data |= LPM_TIMER_500US;
  2621. else
  2622. ocp_data |= LPM_TIMER_500MS;
  2623. ocp_write_byte(tp, MCU_TYPE_USB, USB_LPM_CTRL, ocp_data);
  2624. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2);
  2625. ocp_data &= ~SEN_VAL_MASK;
  2626. ocp_data |= SEN_VAL_NORMAL | SEL_RXIDLE;
  2627. ocp_write_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2, ocp_data);
  2628. r8153_power_cut_en(tp, false);
  2629. r8153_u1u2en(tp, true);
  2630. ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ALDPS_SPDWN_RATIO);
  2631. ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, EEE_SPDWN_RATIO);
  2632. ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3,
  2633. PKT_AVAIL_SPDWN_EN | SUSPEND_SPDWN_EN |
  2634. U1U2_SPDWN_EN | L1_SPDWN_EN);
  2635. ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4,
  2636. PWRSAVE_SPDWN_EN | RXDV_SPDWN_EN | TX10MIDLE_EN |
  2637. TP100_SPDWN_EN | TP500_SPDWN_EN | TP1000_SPDWN_EN |
  2638. EEE_SPDWN_EN);
  2639. r8153_enable_eee(tp);
  2640. r8153_enable_aldps(tp);
  2641. r8152b_enable_fc(tp);
  2642. rtl_tally_reset(tp);
  2643. }
  2644. static int rtl8152_suspend(struct usb_interface *intf, pm_message_t message)
  2645. {
  2646. struct r8152 *tp = usb_get_intfdata(intf);
  2647. struct net_device *netdev = tp->netdev;
  2648. int ret = 0;
  2649. mutex_lock(&tp->control);
  2650. if (PMSG_IS_AUTO(message)) {
  2651. if (netif_running(netdev) && work_busy(&tp->schedule.work)) {
  2652. ret = -EBUSY;
  2653. goto out1;
  2654. }
  2655. set_bit(SELECTIVE_SUSPEND, &tp->flags);
  2656. } else {
  2657. netif_device_detach(netdev);
  2658. }
  2659. if (netif_running(netdev) && test_bit(WORK_ENABLE, &tp->flags)) {
  2660. clear_bit(WORK_ENABLE, &tp->flags);
  2661. usb_kill_urb(tp->intr_urb);
  2662. napi_disable(&tp->napi);
  2663. if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
  2664. rtl_stop_rx(tp);
  2665. rtl_runtime_suspend_enable(tp, true);
  2666. } else {
  2667. cancel_delayed_work_sync(&tp->schedule);
  2668. tp->rtl_ops.down(tp);
  2669. }
  2670. napi_enable(&tp->napi);
  2671. }
  2672. out1:
  2673. mutex_unlock(&tp->control);
  2674. return ret;
  2675. }
  2676. static int rtl8152_resume(struct usb_interface *intf)
  2677. {
  2678. struct r8152 *tp = usb_get_intfdata(intf);
  2679. mutex_lock(&tp->control);
  2680. if (!test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
  2681. tp->rtl_ops.init(tp);
  2682. netif_device_attach(tp->netdev);
  2683. }
  2684. if (netif_running(tp->netdev)) {
  2685. if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
  2686. rtl_runtime_suspend_enable(tp, false);
  2687. clear_bit(SELECTIVE_SUSPEND, &tp->flags);
  2688. set_bit(WORK_ENABLE, &tp->flags);
  2689. if (tp->speed & LINK_STATUS)
  2690. rtl_start_rx(tp);
  2691. } else {
  2692. tp->rtl_ops.up(tp);
  2693. rtl8152_set_speed(tp, AUTONEG_ENABLE,
  2694. tp->mii.supports_gmii ?
  2695. SPEED_1000 : SPEED_100,
  2696. DUPLEX_FULL);
  2697. tp->speed = 0;
  2698. netif_carrier_off(tp->netdev);
  2699. set_bit(WORK_ENABLE, &tp->flags);
  2700. }
  2701. usb_submit_urb(tp->intr_urb, GFP_KERNEL);
  2702. } else if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
  2703. clear_bit(SELECTIVE_SUSPEND, &tp->flags);
  2704. }
  2705. mutex_unlock(&tp->control);
  2706. return 0;
  2707. }
  2708. static void rtl8152_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
  2709. {
  2710. struct r8152 *tp = netdev_priv(dev);
  2711. if (usb_autopm_get_interface(tp->intf) < 0)
  2712. return;
  2713. mutex_lock(&tp->control);
  2714. wol->supported = WAKE_ANY;
  2715. wol->wolopts = __rtl_get_wol(tp);
  2716. mutex_unlock(&tp->control);
  2717. usb_autopm_put_interface(tp->intf);
  2718. }
  2719. static int rtl8152_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
  2720. {
  2721. struct r8152 *tp = netdev_priv(dev);
  2722. int ret;
  2723. ret = usb_autopm_get_interface(tp->intf);
  2724. if (ret < 0)
  2725. goto out_set_wol;
  2726. mutex_lock(&tp->control);
  2727. __rtl_set_wol(tp, wol->wolopts);
  2728. tp->saved_wolopts = wol->wolopts & WAKE_ANY;
  2729. mutex_unlock(&tp->control);
  2730. usb_autopm_put_interface(tp->intf);
  2731. out_set_wol:
  2732. return ret;
  2733. }
  2734. static u32 rtl8152_get_msglevel(struct net_device *dev)
  2735. {
  2736. struct r8152 *tp = netdev_priv(dev);
  2737. return tp->msg_enable;
  2738. }
  2739. static void rtl8152_set_msglevel(struct net_device *dev, u32 value)
  2740. {
  2741. struct r8152 *tp = netdev_priv(dev);
  2742. tp->msg_enable = value;
  2743. }
  2744. static void rtl8152_get_drvinfo(struct net_device *netdev,
  2745. struct ethtool_drvinfo *info)
  2746. {
  2747. struct r8152 *tp = netdev_priv(netdev);
  2748. strlcpy(info->driver, MODULENAME, sizeof(info->driver));
  2749. strlcpy(info->version, DRIVER_VERSION, sizeof(info->version));
  2750. usb_make_path(tp->udev, info->bus_info, sizeof(info->bus_info));
  2751. }
  2752. static
  2753. int rtl8152_get_settings(struct net_device *netdev, struct ethtool_cmd *cmd)
  2754. {
  2755. struct r8152 *tp = netdev_priv(netdev);
  2756. int ret;
  2757. if (!tp->mii.mdio_read)
  2758. return -EOPNOTSUPP;
  2759. ret = usb_autopm_get_interface(tp->intf);
  2760. if (ret < 0)
  2761. goto out;
  2762. mutex_lock(&tp->control);
  2763. ret = mii_ethtool_gset(&tp->mii, cmd);
  2764. mutex_unlock(&tp->control);
  2765. usb_autopm_put_interface(tp->intf);
  2766. out:
  2767. return ret;
  2768. }
  2769. static int rtl8152_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
  2770. {
  2771. struct r8152 *tp = netdev_priv(dev);
  2772. int ret;
  2773. ret = usb_autopm_get_interface(tp->intf);
  2774. if (ret < 0)
  2775. goto out;
  2776. mutex_lock(&tp->control);
  2777. ret = rtl8152_set_speed(tp, cmd->autoneg, cmd->speed, cmd->duplex);
  2778. mutex_unlock(&tp->control);
  2779. usb_autopm_put_interface(tp->intf);
  2780. out:
  2781. return ret;
  2782. }
  2783. static const char rtl8152_gstrings[][ETH_GSTRING_LEN] = {
  2784. "tx_packets",
  2785. "rx_packets",
  2786. "tx_errors",
  2787. "rx_errors",
  2788. "rx_missed",
  2789. "align_errors",
  2790. "tx_single_collisions",
  2791. "tx_multi_collisions",
  2792. "rx_unicast",
  2793. "rx_broadcast",
  2794. "rx_multicast",
  2795. "tx_aborted",
  2796. "tx_underrun",
  2797. };
  2798. static int rtl8152_get_sset_count(struct net_device *dev, int sset)
  2799. {
  2800. switch (sset) {
  2801. case ETH_SS_STATS:
  2802. return ARRAY_SIZE(rtl8152_gstrings);
  2803. default:
  2804. return -EOPNOTSUPP;
  2805. }
  2806. }
  2807. static void rtl8152_get_ethtool_stats(struct net_device *dev,
  2808. struct ethtool_stats *stats, u64 *data)
  2809. {
  2810. struct r8152 *tp = netdev_priv(dev);
  2811. struct tally_counter tally;
  2812. if (usb_autopm_get_interface(tp->intf) < 0)
  2813. return;
  2814. generic_ocp_read(tp, PLA_TALLYCNT, sizeof(tally), &tally, MCU_TYPE_PLA);
  2815. usb_autopm_put_interface(tp->intf);
  2816. data[0] = le64_to_cpu(tally.tx_packets);
  2817. data[1] = le64_to_cpu(tally.rx_packets);
  2818. data[2] = le64_to_cpu(tally.tx_errors);
  2819. data[3] = le32_to_cpu(tally.rx_errors);
  2820. data[4] = le16_to_cpu(tally.rx_missed);
  2821. data[5] = le16_to_cpu(tally.align_errors);
  2822. data[6] = le32_to_cpu(tally.tx_one_collision);
  2823. data[7] = le32_to_cpu(tally.tx_multi_collision);
  2824. data[8] = le64_to_cpu(tally.rx_unicast);
  2825. data[9] = le64_to_cpu(tally.rx_broadcast);
  2826. data[10] = le32_to_cpu(tally.rx_multicast);
  2827. data[11] = le16_to_cpu(tally.tx_aborted);
  2828. data[12] = le16_to_cpu(tally.tx_underrun);
  2829. }
  2830. static void rtl8152_get_strings(struct net_device *dev, u32 stringset, u8 *data)
  2831. {
  2832. switch (stringset) {
  2833. case ETH_SS_STATS:
  2834. memcpy(data, *rtl8152_gstrings, sizeof(rtl8152_gstrings));
  2835. break;
  2836. }
  2837. }
  2838. static int r8152_get_eee(struct r8152 *tp, struct ethtool_eee *eee)
  2839. {
  2840. u32 ocp_data, lp, adv, supported = 0;
  2841. u16 val;
  2842. val = r8152_mmd_read(tp, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE);
  2843. supported = mmd_eee_cap_to_ethtool_sup_t(val);
  2844. val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV);
  2845. adv = mmd_eee_adv_to_ethtool_adv_t(val);
  2846. val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_LPABLE);
  2847. lp = mmd_eee_adv_to_ethtool_adv_t(val);
  2848. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
  2849. ocp_data &= EEE_RX_EN | EEE_TX_EN;
  2850. eee->eee_enabled = !!ocp_data;
  2851. eee->eee_active = !!(supported & adv & lp);
  2852. eee->supported = supported;
  2853. eee->advertised = adv;
  2854. eee->lp_advertised = lp;
  2855. return 0;
  2856. }
  2857. static int r8152_set_eee(struct r8152 *tp, struct ethtool_eee *eee)
  2858. {
  2859. u16 val = ethtool_adv_to_mmd_eee_adv_t(eee->advertised);
  2860. r8152_eee_en(tp, eee->eee_enabled);
  2861. if (!eee->eee_enabled)
  2862. val = 0;
  2863. r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val);
  2864. return 0;
  2865. }
  2866. static int r8153_get_eee(struct r8152 *tp, struct ethtool_eee *eee)
  2867. {
  2868. u32 ocp_data, lp, adv, supported = 0;
  2869. u16 val;
  2870. val = ocp_reg_read(tp, OCP_EEE_ABLE);
  2871. supported = mmd_eee_cap_to_ethtool_sup_t(val);
  2872. val = ocp_reg_read(tp, OCP_EEE_ADV);
  2873. adv = mmd_eee_adv_to_ethtool_adv_t(val);
  2874. val = ocp_reg_read(tp, OCP_EEE_LPABLE);
  2875. lp = mmd_eee_adv_to_ethtool_adv_t(val);
  2876. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
  2877. ocp_data &= EEE_RX_EN | EEE_TX_EN;
  2878. eee->eee_enabled = !!ocp_data;
  2879. eee->eee_active = !!(supported & adv & lp);
  2880. eee->supported = supported;
  2881. eee->advertised = adv;
  2882. eee->lp_advertised = lp;
  2883. return 0;
  2884. }
  2885. static int r8153_set_eee(struct r8152 *tp, struct ethtool_eee *eee)
  2886. {
  2887. u16 val = ethtool_adv_to_mmd_eee_adv_t(eee->advertised);
  2888. r8153_eee_en(tp, eee->eee_enabled);
  2889. if (!eee->eee_enabled)
  2890. val = 0;
  2891. ocp_reg_write(tp, OCP_EEE_ADV, val);
  2892. return 0;
  2893. }
  2894. static int
  2895. rtl_ethtool_get_eee(struct net_device *net, struct ethtool_eee *edata)
  2896. {
  2897. struct r8152 *tp = netdev_priv(net);
  2898. int ret;
  2899. ret = usb_autopm_get_interface(tp->intf);
  2900. if (ret < 0)
  2901. goto out;
  2902. mutex_lock(&tp->control);
  2903. ret = tp->rtl_ops.eee_get(tp, edata);
  2904. mutex_unlock(&tp->control);
  2905. usb_autopm_put_interface(tp->intf);
  2906. out:
  2907. return ret;
  2908. }
  2909. static int
  2910. rtl_ethtool_set_eee(struct net_device *net, struct ethtool_eee *edata)
  2911. {
  2912. struct r8152 *tp = netdev_priv(net);
  2913. int ret;
  2914. ret = usb_autopm_get_interface(tp->intf);
  2915. if (ret < 0)
  2916. goto out;
  2917. mutex_lock(&tp->control);
  2918. ret = tp->rtl_ops.eee_set(tp, edata);
  2919. if (!ret)
  2920. ret = mii_nway_restart(&tp->mii);
  2921. mutex_unlock(&tp->control);
  2922. usb_autopm_put_interface(tp->intf);
  2923. out:
  2924. return ret;
  2925. }
  2926. static int rtl8152_nway_reset(struct net_device *dev)
  2927. {
  2928. struct r8152 *tp = netdev_priv(dev);
  2929. int ret;
  2930. ret = usb_autopm_get_interface(tp->intf);
  2931. if (ret < 0)
  2932. goto out;
  2933. mutex_lock(&tp->control);
  2934. ret = mii_nway_restart(&tp->mii);
  2935. mutex_unlock(&tp->control);
  2936. usb_autopm_put_interface(tp->intf);
  2937. out:
  2938. return ret;
  2939. }
  2940. static struct ethtool_ops ops = {
  2941. .get_drvinfo = rtl8152_get_drvinfo,
  2942. .get_settings = rtl8152_get_settings,
  2943. .set_settings = rtl8152_set_settings,
  2944. .get_link = ethtool_op_get_link,
  2945. .nway_reset = rtl8152_nway_reset,
  2946. .get_msglevel = rtl8152_get_msglevel,
  2947. .set_msglevel = rtl8152_set_msglevel,
  2948. .get_wol = rtl8152_get_wol,
  2949. .set_wol = rtl8152_set_wol,
  2950. .get_strings = rtl8152_get_strings,
  2951. .get_sset_count = rtl8152_get_sset_count,
  2952. .get_ethtool_stats = rtl8152_get_ethtool_stats,
  2953. .get_eee = rtl_ethtool_get_eee,
  2954. .set_eee = rtl_ethtool_set_eee,
  2955. };
  2956. static int rtl8152_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd)
  2957. {
  2958. struct r8152 *tp = netdev_priv(netdev);
  2959. struct mii_ioctl_data *data = if_mii(rq);
  2960. int res;
  2961. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  2962. return -ENODEV;
  2963. res = usb_autopm_get_interface(tp->intf);
  2964. if (res < 0)
  2965. goto out;
  2966. switch (cmd) {
  2967. case SIOCGMIIPHY:
  2968. data->phy_id = R8152_PHY_ID; /* Internal PHY */
  2969. break;
  2970. case SIOCGMIIREG:
  2971. mutex_lock(&tp->control);
  2972. data->val_out = r8152_mdio_read(tp, data->reg_num);
  2973. mutex_unlock(&tp->control);
  2974. break;
  2975. case SIOCSMIIREG:
  2976. if (!capable(CAP_NET_ADMIN)) {
  2977. res = -EPERM;
  2978. break;
  2979. }
  2980. mutex_lock(&tp->control);
  2981. r8152_mdio_write(tp, data->reg_num, data->val_in);
  2982. mutex_unlock(&tp->control);
  2983. break;
  2984. default:
  2985. res = -EOPNOTSUPP;
  2986. }
  2987. usb_autopm_put_interface(tp->intf);
  2988. out:
  2989. return res;
  2990. }
  2991. static int rtl8152_change_mtu(struct net_device *dev, int new_mtu)
  2992. {
  2993. struct r8152 *tp = netdev_priv(dev);
  2994. switch (tp->version) {
  2995. case RTL_VER_01:
  2996. case RTL_VER_02:
  2997. return eth_change_mtu(dev, new_mtu);
  2998. default:
  2999. break;
  3000. }
  3001. if (new_mtu < 68 || new_mtu > RTL8153_MAX_MTU)
  3002. return -EINVAL;
  3003. dev->mtu = new_mtu;
  3004. return 0;
  3005. }
  3006. static const struct net_device_ops rtl8152_netdev_ops = {
  3007. .ndo_open = rtl8152_open,
  3008. .ndo_stop = rtl8152_close,
  3009. .ndo_do_ioctl = rtl8152_ioctl,
  3010. .ndo_start_xmit = rtl8152_start_xmit,
  3011. .ndo_tx_timeout = rtl8152_tx_timeout,
  3012. .ndo_set_features = rtl8152_set_features,
  3013. .ndo_set_rx_mode = rtl8152_set_rx_mode,
  3014. .ndo_set_mac_address = rtl8152_set_mac_address,
  3015. .ndo_change_mtu = rtl8152_change_mtu,
  3016. .ndo_validate_addr = eth_validate_addr,
  3017. .ndo_features_check = rtl8152_features_check,
  3018. };
  3019. static void r8152b_get_version(struct r8152 *tp)
  3020. {
  3021. u32 ocp_data;
  3022. u16 version;
  3023. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR1);
  3024. version = (u16)(ocp_data & VERSION_MASK);
  3025. switch (version) {
  3026. case 0x4c00:
  3027. tp->version = RTL_VER_01;
  3028. break;
  3029. case 0x4c10:
  3030. tp->version = RTL_VER_02;
  3031. break;
  3032. case 0x5c00:
  3033. tp->version = RTL_VER_03;
  3034. tp->mii.supports_gmii = 1;
  3035. break;
  3036. case 0x5c10:
  3037. tp->version = RTL_VER_04;
  3038. tp->mii.supports_gmii = 1;
  3039. break;
  3040. case 0x5c20:
  3041. tp->version = RTL_VER_05;
  3042. tp->mii.supports_gmii = 1;
  3043. break;
  3044. default:
  3045. netif_info(tp, probe, tp->netdev,
  3046. "Unknown version 0x%04x\n", version);
  3047. break;
  3048. }
  3049. }
  3050. static void rtl8152_unload(struct r8152 *tp)
  3051. {
  3052. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  3053. return;
  3054. if (tp->version != RTL_VER_01)
  3055. r8152_power_cut_en(tp, true);
  3056. }
  3057. static void rtl8153_unload(struct r8152 *tp)
  3058. {
  3059. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  3060. return;
  3061. r8153_power_cut_en(tp, false);
  3062. }
  3063. static int rtl_ops_init(struct r8152 *tp)
  3064. {
  3065. struct rtl_ops *ops = &tp->rtl_ops;
  3066. int ret = 0;
  3067. switch (tp->version) {
  3068. case RTL_VER_01:
  3069. case RTL_VER_02:
  3070. ops->init = r8152b_init;
  3071. ops->enable = rtl8152_enable;
  3072. ops->disable = rtl8152_disable;
  3073. ops->up = rtl8152_up;
  3074. ops->down = rtl8152_down;
  3075. ops->unload = rtl8152_unload;
  3076. ops->eee_get = r8152_get_eee;
  3077. ops->eee_set = r8152_set_eee;
  3078. break;
  3079. case RTL_VER_03:
  3080. case RTL_VER_04:
  3081. case RTL_VER_05:
  3082. ops->init = r8153_init;
  3083. ops->enable = rtl8153_enable;
  3084. ops->disable = rtl8153_disable;
  3085. ops->up = rtl8153_up;
  3086. ops->down = rtl8153_down;
  3087. ops->unload = rtl8153_unload;
  3088. ops->eee_get = r8153_get_eee;
  3089. ops->eee_set = r8153_set_eee;
  3090. break;
  3091. default:
  3092. ret = -ENODEV;
  3093. netif_err(tp, probe, tp->netdev, "Unknown Device\n");
  3094. break;
  3095. }
  3096. return ret;
  3097. }
  3098. static int rtl8152_probe(struct usb_interface *intf,
  3099. const struct usb_device_id *id)
  3100. {
  3101. struct usb_device *udev = interface_to_usbdev(intf);
  3102. struct r8152 *tp;
  3103. struct net_device *netdev;
  3104. int ret;
  3105. if (udev->actconfig->desc.bConfigurationValue != 1) {
  3106. usb_driver_set_configuration(udev, 1);
  3107. return -ENODEV;
  3108. }
  3109. usb_reset_device(udev);
  3110. netdev = alloc_etherdev(sizeof(struct r8152));
  3111. if (!netdev) {
  3112. dev_err(&intf->dev, "Out of memory\n");
  3113. return -ENOMEM;
  3114. }
  3115. SET_NETDEV_DEV(netdev, &intf->dev);
  3116. tp = netdev_priv(netdev);
  3117. tp->msg_enable = 0x7FFF;
  3118. tp->udev = udev;
  3119. tp->netdev = netdev;
  3120. tp->intf = intf;
  3121. r8152b_get_version(tp);
  3122. ret = rtl_ops_init(tp);
  3123. if (ret)
  3124. goto out;
  3125. mutex_init(&tp->control);
  3126. INIT_DELAYED_WORK(&tp->schedule, rtl_work_func_t);
  3127. netdev->netdev_ops = &rtl8152_netdev_ops;
  3128. netdev->watchdog_timeo = RTL8152_TX_TIMEOUT;
  3129. netdev->features |= NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG |
  3130. NETIF_F_TSO | NETIF_F_FRAGLIST | NETIF_F_IPV6_CSUM |
  3131. NETIF_F_TSO6 | NETIF_F_HW_VLAN_CTAG_RX |
  3132. NETIF_F_HW_VLAN_CTAG_TX;
  3133. netdev->hw_features = NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG |
  3134. NETIF_F_TSO | NETIF_F_FRAGLIST |
  3135. NETIF_F_IPV6_CSUM | NETIF_F_TSO6 |
  3136. NETIF_F_HW_VLAN_CTAG_RX |
  3137. NETIF_F_HW_VLAN_CTAG_TX;
  3138. netdev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
  3139. NETIF_F_HIGHDMA | NETIF_F_FRAGLIST |
  3140. NETIF_F_IPV6_CSUM | NETIF_F_TSO6;
  3141. netdev->ethtool_ops = &ops;
  3142. netif_set_gso_max_size(netdev, RTL_LIMITED_TSO_SIZE);
  3143. tp->mii.dev = netdev;
  3144. tp->mii.mdio_read = read_mii_word;
  3145. tp->mii.mdio_write = write_mii_word;
  3146. tp->mii.phy_id_mask = 0x3f;
  3147. tp->mii.reg_num_mask = 0x1f;
  3148. tp->mii.phy_id = R8152_PHY_ID;
  3149. intf->needs_remote_wakeup = 1;
  3150. tp->rtl_ops.init(tp);
  3151. set_ethernet_addr(tp);
  3152. usb_set_intfdata(intf, tp);
  3153. netif_napi_add(netdev, &tp->napi, r8152_poll, RTL8152_NAPI_WEIGHT);
  3154. ret = register_netdev(netdev);
  3155. if (ret != 0) {
  3156. netif_err(tp, probe, netdev, "couldn't register the device\n");
  3157. goto out1;
  3158. }
  3159. tp->saved_wolopts = __rtl_get_wol(tp);
  3160. if (tp->saved_wolopts)
  3161. device_set_wakeup_enable(&udev->dev, true);
  3162. else
  3163. device_set_wakeup_enable(&udev->dev, false);
  3164. netif_info(tp, probe, netdev, "%s\n", DRIVER_VERSION);
  3165. return 0;
  3166. out1:
  3167. netif_napi_del(&tp->napi);
  3168. usb_set_intfdata(intf, NULL);
  3169. out:
  3170. free_netdev(netdev);
  3171. return ret;
  3172. }
  3173. static void rtl8152_disconnect(struct usb_interface *intf)
  3174. {
  3175. struct r8152 *tp = usb_get_intfdata(intf);
  3176. usb_set_intfdata(intf, NULL);
  3177. if (tp) {
  3178. struct usb_device *udev = tp->udev;
  3179. if (udev->state == USB_STATE_NOTATTACHED)
  3180. set_bit(RTL8152_UNPLUG, &tp->flags);
  3181. netif_napi_del(&tp->napi);
  3182. unregister_netdev(tp->netdev);
  3183. tp->rtl_ops.unload(tp);
  3184. free_netdev(tp->netdev);
  3185. }
  3186. }
  3187. #define REALTEK_USB_DEVICE(vend, prod) \
  3188. .match_flags = USB_DEVICE_ID_MATCH_DEVICE | \
  3189. USB_DEVICE_ID_MATCH_INT_CLASS, \
  3190. .idVendor = (vend), \
  3191. .idProduct = (prod), \
  3192. .bInterfaceClass = USB_CLASS_VENDOR_SPEC \
  3193. }, \
  3194. { \
  3195. .match_flags = USB_DEVICE_ID_MATCH_INT_INFO | \
  3196. USB_DEVICE_ID_MATCH_DEVICE, \
  3197. .idVendor = (vend), \
  3198. .idProduct = (prod), \
  3199. .bInterfaceClass = USB_CLASS_COMM, \
  3200. .bInterfaceSubClass = USB_CDC_SUBCLASS_ETHERNET, \
  3201. .bInterfaceProtocol = USB_CDC_PROTO_NONE
  3202. /* table of devices that work with this driver */
  3203. static struct usb_device_id rtl8152_table[] = {
  3204. {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8152)},
  3205. {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8153)},
  3206. {REALTEK_USB_DEVICE(VENDOR_ID_SAMSUNG, 0xa101)},
  3207. {}
  3208. };
  3209. MODULE_DEVICE_TABLE(usb, rtl8152_table);
  3210. static struct usb_driver rtl8152_driver = {
  3211. .name = MODULENAME,
  3212. .id_table = rtl8152_table,
  3213. .probe = rtl8152_probe,
  3214. .disconnect = rtl8152_disconnect,
  3215. .suspend = rtl8152_suspend,
  3216. .resume = rtl8152_resume,
  3217. .reset_resume = rtl8152_resume,
  3218. .supports_autosuspend = 1,
  3219. .disable_hub_initiated_lpm = 1,
  3220. };
  3221. module_usb_driver(rtl8152_driver);
  3222. MODULE_AUTHOR(DRIVER_AUTHOR);
  3223. MODULE_DESCRIPTION(DRIVER_DESC);
  3224. MODULE_LICENSE("GPL");