sh_eth.c 71 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273747576777879808182838485868788899091929394959697989910010110210310410510610710810911011111211311411511611711811912012112212312412512612712812913013113213313413513613713813914014114214314414514614714814915015115215315415515615715815916016116216316416516616716816917017117217317417517617717817918018118218318418518618718818919019119219319419519619719819920020120220320420520620720820921021121221321421521621721821922022122222322422522622722822923023123223323423523623723823924024124224324424524624724824925025125225325425525625725825926026126226326426526626726826927027127227327427527627727827928028128228328428528628728828929029129229329429529629729829930030130230330430530630730830931031131231331431531631731831932032132232332432532632732832933033133233333433533633733833934034134234334434534634734834935035135235335435535635735835936036136236336436536636736836937037137237337437537637737837938038138238338438538638738838939039139239339439539639739839940040140240340440540640740840941041141241341441541641741841942042142242342442542642742842943043143243343443543643743843944044144244344444544644744844945045145245345445545645745845946046146246346446546646746846947047147247347447547647747847948048148248348448548648748848949049149249349449549649749849950050150250350450550650750850951051151251351451551651751851952052152252352452552652752852953053153253353453553653753853954054154254354454554654754854955055155255355455555655755855956056156256356456556656756856957057157257357457557657757857958058158258358458558658758858959059159259359459559659759859960060160260360460560660760860961061161261361461561661761861962062162262362462562662762862963063163263363463563663763863964064164264364464564664764864965065165265365465565665765865966066166266366466566666766866967067167267367467567667767867968068168268368468568668768868969069169269369469569669769869970070170270370470570670770870971071171271371471571671771871972072172272372472572672772872973073173273373473573673773873974074174274374474574674774874975075175275375475575675775875976076176276376476576676776876977077177277377477577677777877978078178278378478578678778878979079179279379479579679779879980080180280380480580680780880981081181281381481581681781881982082182282382482582682782882983083183283383483583683783883984084184284384484584684784884985085185285385485585685785885986086186286386486586686786886987087187287387487587687787887988088188288388488588688788888989089189289389489589689789889990090190290390490590690790890991091191291391491591691791891992092192292392492592692792892993093193293393493593693793893994094194294394494594694794894995095195295395495595695795895996096196296396496596696796896997097197297397497597697797897998098198298398498598698798898999099199299399499599699799899910001001100210031004100510061007100810091010101110121013101410151016101710181019102010211022102310241025102610271028102910301031103210331034103510361037103810391040104110421043104410451046104710481049105010511052105310541055105610571058105910601061106210631064106510661067106810691070107110721073107410751076107710781079108010811082108310841085108610871088108910901091109210931094109510961097109810991100110111021103110411051106110711081109111011111112111311141115111611171118111911201121112211231124112511261127112811291130113111321133113411351136113711381139114011411142114311441145114611471148114911501151115211531154115511561157115811591160116111621163116411651166116711681169117011711172117311741175117611771178117911801181118211831184118511861187118811891190119111921193119411951196119711981199120012011202120312041205120612071208120912101211121212131214121512161217121812191220122112221223122412251226122712281229123012311232123312341235123612371238123912401241124212431244124512461247124812491250125112521253125412551256125712581259126012611262126312641265126612671268126912701271127212731274127512761277127812791280128112821283128412851286128712881289129012911292129312941295129612971298129913001301130213031304130513061307130813091310131113121313131413151316131713181319132013211322132313241325132613271328132913301331133213331334133513361337133813391340134113421343134413451346134713481349135013511352135313541355135613571358135913601361136213631364136513661367136813691370137113721373137413751376137713781379138013811382138313841385138613871388138913901391139213931394139513961397139813991400140114021403140414051406140714081409141014111412141314141415141614171418141914201421142214231424142514261427142814291430143114321433143414351436143714381439144014411442144314441445144614471448144914501451145214531454145514561457145814591460146114621463146414651466146714681469147014711472147314741475147614771478147914801481148214831484148514861487148814891490149114921493149414951496149714981499150015011502150315041505150615071508150915101511151215131514151515161517151815191520152115221523152415251526152715281529153015311532153315341535153615371538153915401541154215431544154515461547154815491550155115521553155415551556155715581559156015611562156315641565156615671568156915701571157215731574157515761577157815791580158115821583158415851586158715881589159015911592159315941595159615971598159916001601160216031604160516061607160816091610161116121613161416151616161716181619162016211622162316241625162616271628162916301631163216331634163516361637163816391640164116421643164416451646164716481649165016511652165316541655165616571658165916601661166216631664166516661667166816691670167116721673167416751676167716781679168016811682168316841685168616871688168916901691169216931694169516961697169816991700170117021703170417051706170717081709171017111712171317141715171617171718171917201721172217231724172517261727172817291730173117321733173417351736173717381739174017411742174317441745174617471748174917501751175217531754175517561757175817591760176117621763176417651766176717681769177017711772177317741775177617771778177917801781178217831784178517861787178817891790179117921793179417951796179717981799180018011802180318041805180618071808180918101811181218131814181518161817181818191820182118221823182418251826182718281829183018311832183318341835183618371838183918401841184218431844184518461847184818491850185118521853185418551856185718581859186018611862186318641865186618671868186918701871187218731874187518761877187818791880188118821883188418851886188718881889189018911892189318941895189618971898189919001901190219031904190519061907190819091910191119121913191419151916191719181919192019211922192319241925192619271928192919301931193219331934193519361937193819391940194119421943194419451946194719481949195019511952195319541955195619571958195919601961196219631964196519661967196819691970197119721973197419751976197719781979198019811982198319841985198619871988198919901991199219931994199519961997199819992000200120022003200420052006200720082009201020112012201320142015201620172018201920202021202220232024202520262027202820292030203120322033203420352036203720382039204020412042204320442045204620472048204920502051205220532054205520562057205820592060206120622063206420652066206720682069207020712072207320742075207620772078207920802081208220832084208520862087208820892090209120922093209420952096209720982099210021012102210321042105210621072108210921102111211221132114211521162117211821192120212121222123212421252126212721282129213021312132213321342135213621372138213921402141214221432144214521462147214821492150215121522153215421552156215721582159216021612162216321642165216621672168216921702171217221732174217521762177217821792180218121822183218421852186218721882189219021912192219321942195219621972198219922002201220222032204220522062207220822092210221122122213221422152216221722182219222022212222222322242225222622272228222922302231223222332234223522362237223822392240224122422243224422452246224722482249225022512252225322542255225622572258225922602261226222632264226522662267226822692270227122722273227422752276227722782279228022812282228322842285228622872288228922902291229222932294229522962297229822992300230123022303230423052306230723082309231023112312231323142315231623172318231923202321232223232324232523262327232823292330233123322333233423352336233723382339234023412342234323442345234623472348234923502351235223532354235523562357235823592360236123622363236423652366236723682369237023712372237323742375237623772378237923802381238223832384238523862387238823892390239123922393239423952396239723982399240024012402240324042405240624072408240924102411241224132414241524162417241824192420242124222423242424252426242724282429243024312432243324342435243624372438243924402441244224432444244524462447244824492450245124522453245424552456245724582459246024612462246324642465246624672468246924702471247224732474247524762477247824792480248124822483248424852486248724882489249024912492249324942495249624972498249925002501250225032504250525062507250825092510251125122513251425152516251725182519252025212522252325242525252625272528252925302531253225332534253525362537253825392540254125422543254425452546254725482549255025512552255325542555255625572558255925602561256225632564256525662567256825692570257125722573257425752576257725782579258025812582258325842585258625872588258925902591259225932594259525962597259825992600260126022603260426052606260726082609261026112612261326142615261626172618261926202621262226232624262526262627262826292630263126322633263426352636263726382639264026412642264326442645264626472648264926502651265226532654265526562657265826592660266126622663266426652666266726682669267026712672267326742675267626772678267926802681268226832684268526862687268826892690269126922693269426952696269726982699270027012702270327042705270627072708270927102711271227132714271527162717271827192720272127222723272427252726272727282729273027312732273327342735273627372738273927402741274227432744274527462747274827492750275127522753275427552756275727582759276027612762276327642765276627672768276927702771277227732774277527762777277827792780278127822783278427852786278727882789279027912792279327942795279627972798279928002801280228032804280528062807280828092810281128122813281428152816281728182819282028212822282328242825282628272828282928302831283228332834283528362837283828392840284128422843284428452846284728482849285028512852285328542855285628572858285928602861286228632864286528662867286828692870287128722873287428752876287728782879288028812882288328842885288628872888288928902891289228932894289528962897289828992900290129022903290429052906290729082909291029112912291329142915291629172918291929202921292229232924292529262927292829292930293129322933293429352936293729382939294029412942294329442945294629472948294929502951295229532954295529562957295829592960296129622963296429652966296729682969297029712972297329742975297629772978297929802981298229832984298529862987298829892990299129922993299429952996299729982999300030013002300330043005
  1. /* SuperH Ethernet device driver
  2. *
  3. * Copyright (C) 2014 Renesas Electronics Corporation
  4. * Copyright (C) 2006-2012 Nobuhiro Iwamatsu
  5. * Copyright (C) 2008-2014 Renesas Solutions Corp.
  6. * Copyright (C) 2013-2014 Cogent Embedded, Inc.
  7. * Copyright (C) 2014 Codethink Limited
  8. *
  9. * This program is free software; you can redistribute it and/or modify it
  10. * under the terms and conditions of the GNU General Public License,
  11. * version 2, as published by the Free Software Foundation.
  12. *
  13. * This program is distributed in the hope it will be useful, but WITHOUT
  14. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  15. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  16. * more details.
  17. *
  18. * The full GNU General Public License is included in this distribution in
  19. * the file called "COPYING".
  20. */
  21. #include <linux/module.h>
  22. #include <linux/kernel.h>
  23. #include <linux/spinlock.h>
  24. #include <linux/interrupt.h>
  25. #include <linux/dma-mapping.h>
  26. #include <linux/etherdevice.h>
  27. #include <linux/delay.h>
  28. #include <linux/platform_device.h>
  29. #include <linux/mdio-bitbang.h>
  30. #include <linux/netdevice.h>
  31. #include <linux/of.h>
  32. #include <linux/of_device.h>
  33. #include <linux/of_irq.h>
  34. #include <linux/of_net.h>
  35. #include <linux/phy.h>
  36. #include <linux/cache.h>
  37. #include <linux/io.h>
  38. #include <linux/pm_runtime.h>
  39. #include <linux/slab.h>
  40. #include <linux/ethtool.h>
  41. #include <linux/if_vlan.h>
  42. #include <linux/clk.h>
  43. #include <linux/sh_eth.h>
  44. #include <linux/of_mdio.h>
  45. #include "sh_eth.h"
  46. #define SH_ETH_DEF_MSG_ENABLE \
  47. (NETIF_MSG_LINK | \
  48. NETIF_MSG_TIMER | \
  49. NETIF_MSG_RX_ERR| \
  50. NETIF_MSG_TX_ERR)
  51. static const u16 sh_eth_offset_gigabit[SH_ETH_MAX_REGISTER_OFFSET] = {
  52. [EDSR] = 0x0000,
  53. [EDMR] = 0x0400,
  54. [EDTRR] = 0x0408,
  55. [EDRRR] = 0x0410,
  56. [EESR] = 0x0428,
  57. [EESIPR] = 0x0430,
  58. [TDLAR] = 0x0010,
  59. [TDFAR] = 0x0014,
  60. [TDFXR] = 0x0018,
  61. [TDFFR] = 0x001c,
  62. [RDLAR] = 0x0030,
  63. [RDFAR] = 0x0034,
  64. [RDFXR] = 0x0038,
  65. [RDFFR] = 0x003c,
  66. [TRSCER] = 0x0438,
  67. [RMFCR] = 0x0440,
  68. [TFTR] = 0x0448,
  69. [FDR] = 0x0450,
  70. [RMCR] = 0x0458,
  71. [RPADIR] = 0x0460,
  72. [FCFTR] = 0x0468,
  73. [CSMR] = 0x04E4,
  74. [ECMR] = 0x0500,
  75. [ECSR] = 0x0510,
  76. [ECSIPR] = 0x0518,
  77. [PIR] = 0x0520,
  78. [PSR] = 0x0528,
  79. [PIPR] = 0x052c,
  80. [RFLR] = 0x0508,
  81. [APR] = 0x0554,
  82. [MPR] = 0x0558,
  83. [PFTCR] = 0x055c,
  84. [PFRCR] = 0x0560,
  85. [TPAUSER] = 0x0564,
  86. [GECMR] = 0x05b0,
  87. [BCULR] = 0x05b4,
  88. [MAHR] = 0x05c0,
  89. [MALR] = 0x05c8,
  90. [TROCR] = 0x0700,
  91. [CDCR] = 0x0708,
  92. [LCCR] = 0x0710,
  93. [CEFCR] = 0x0740,
  94. [FRECR] = 0x0748,
  95. [TSFRCR] = 0x0750,
  96. [TLFRCR] = 0x0758,
  97. [RFCR] = 0x0760,
  98. [CERCR] = 0x0768,
  99. [CEECR] = 0x0770,
  100. [MAFCR] = 0x0778,
  101. [RMII_MII] = 0x0790,
  102. [ARSTR] = 0x0000,
  103. [TSU_CTRST] = 0x0004,
  104. [TSU_FWEN0] = 0x0010,
  105. [TSU_FWEN1] = 0x0014,
  106. [TSU_FCM] = 0x0018,
  107. [TSU_BSYSL0] = 0x0020,
  108. [TSU_BSYSL1] = 0x0024,
  109. [TSU_PRISL0] = 0x0028,
  110. [TSU_PRISL1] = 0x002c,
  111. [TSU_FWSL0] = 0x0030,
  112. [TSU_FWSL1] = 0x0034,
  113. [TSU_FWSLC] = 0x0038,
  114. [TSU_QTAG0] = 0x0040,
  115. [TSU_QTAG1] = 0x0044,
  116. [TSU_FWSR] = 0x0050,
  117. [TSU_FWINMK] = 0x0054,
  118. [TSU_ADQT0] = 0x0048,
  119. [TSU_ADQT1] = 0x004c,
  120. [TSU_VTAG0] = 0x0058,
  121. [TSU_VTAG1] = 0x005c,
  122. [TSU_ADSBSY] = 0x0060,
  123. [TSU_TEN] = 0x0064,
  124. [TSU_POST1] = 0x0070,
  125. [TSU_POST2] = 0x0074,
  126. [TSU_POST3] = 0x0078,
  127. [TSU_POST4] = 0x007c,
  128. [TSU_ADRH0] = 0x0100,
  129. [TSU_ADRL0] = 0x0104,
  130. [TSU_ADRH31] = 0x01f8,
  131. [TSU_ADRL31] = 0x01fc,
  132. [TXNLCR0] = 0x0080,
  133. [TXALCR0] = 0x0084,
  134. [RXNLCR0] = 0x0088,
  135. [RXALCR0] = 0x008c,
  136. [FWNLCR0] = 0x0090,
  137. [FWALCR0] = 0x0094,
  138. [TXNLCR1] = 0x00a0,
  139. [TXALCR1] = 0x00a0,
  140. [RXNLCR1] = 0x00a8,
  141. [RXALCR1] = 0x00ac,
  142. [FWNLCR1] = 0x00b0,
  143. [FWALCR1] = 0x00b4,
  144. };
  145. static const u16 sh_eth_offset_fast_rz[SH_ETH_MAX_REGISTER_OFFSET] = {
  146. [EDSR] = 0x0000,
  147. [EDMR] = 0x0400,
  148. [EDTRR] = 0x0408,
  149. [EDRRR] = 0x0410,
  150. [EESR] = 0x0428,
  151. [EESIPR] = 0x0430,
  152. [TDLAR] = 0x0010,
  153. [TDFAR] = 0x0014,
  154. [TDFXR] = 0x0018,
  155. [TDFFR] = 0x001c,
  156. [RDLAR] = 0x0030,
  157. [RDFAR] = 0x0034,
  158. [RDFXR] = 0x0038,
  159. [RDFFR] = 0x003c,
  160. [TRSCER] = 0x0438,
  161. [RMFCR] = 0x0440,
  162. [TFTR] = 0x0448,
  163. [FDR] = 0x0450,
  164. [RMCR] = 0x0458,
  165. [RPADIR] = 0x0460,
  166. [FCFTR] = 0x0468,
  167. [CSMR] = 0x04E4,
  168. [ECMR] = 0x0500,
  169. [RFLR] = 0x0508,
  170. [ECSR] = 0x0510,
  171. [ECSIPR] = 0x0518,
  172. [PIR] = 0x0520,
  173. [APR] = 0x0554,
  174. [MPR] = 0x0558,
  175. [PFTCR] = 0x055c,
  176. [PFRCR] = 0x0560,
  177. [TPAUSER] = 0x0564,
  178. [MAHR] = 0x05c0,
  179. [MALR] = 0x05c8,
  180. [CEFCR] = 0x0740,
  181. [FRECR] = 0x0748,
  182. [TSFRCR] = 0x0750,
  183. [TLFRCR] = 0x0758,
  184. [RFCR] = 0x0760,
  185. [MAFCR] = 0x0778,
  186. [ARSTR] = 0x0000,
  187. [TSU_CTRST] = 0x0004,
  188. [TSU_VTAG0] = 0x0058,
  189. [TSU_ADSBSY] = 0x0060,
  190. [TSU_TEN] = 0x0064,
  191. [TSU_ADRH0] = 0x0100,
  192. [TSU_ADRL0] = 0x0104,
  193. [TSU_ADRH31] = 0x01f8,
  194. [TSU_ADRL31] = 0x01fc,
  195. [TXNLCR0] = 0x0080,
  196. [TXALCR0] = 0x0084,
  197. [RXNLCR0] = 0x0088,
  198. [RXALCR0] = 0x008C,
  199. };
  200. static const u16 sh_eth_offset_fast_rcar[SH_ETH_MAX_REGISTER_OFFSET] = {
  201. [ECMR] = 0x0300,
  202. [RFLR] = 0x0308,
  203. [ECSR] = 0x0310,
  204. [ECSIPR] = 0x0318,
  205. [PIR] = 0x0320,
  206. [PSR] = 0x0328,
  207. [RDMLR] = 0x0340,
  208. [IPGR] = 0x0350,
  209. [APR] = 0x0354,
  210. [MPR] = 0x0358,
  211. [RFCF] = 0x0360,
  212. [TPAUSER] = 0x0364,
  213. [TPAUSECR] = 0x0368,
  214. [MAHR] = 0x03c0,
  215. [MALR] = 0x03c8,
  216. [TROCR] = 0x03d0,
  217. [CDCR] = 0x03d4,
  218. [LCCR] = 0x03d8,
  219. [CNDCR] = 0x03dc,
  220. [CEFCR] = 0x03e4,
  221. [FRECR] = 0x03e8,
  222. [TSFRCR] = 0x03ec,
  223. [TLFRCR] = 0x03f0,
  224. [RFCR] = 0x03f4,
  225. [MAFCR] = 0x03f8,
  226. [EDMR] = 0x0200,
  227. [EDTRR] = 0x0208,
  228. [EDRRR] = 0x0210,
  229. [TDLAR] = 0x0218,
  230. [RDLAR] = 0x0220,
  231. [EESR] = 0x0228,
  232. [EESIPR] = 0x0230,
  233. [TRSCER] = 0x0238,
  234. [RMFCR] = 0x0240,
  235. [TFTR] = 0x0248,
  236. [FDR] = 0x0250,
  237. [RMCR] = 0x0258,
  238. [TFUCR] = 0x0264,
  239. [RFOCR] = 0x0268,
  240. [RMIIMODE] = 0x026c,
  241. [FCFTR] = 0x0270,
  242. [TRIMD] = 0x027c,
  243. };
  244. static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = {
  245. [ECMR] = 0x0100,
  246. [RFLR] = 0x0108,
  247. [ECSR] = 0x0110,
  248. [ECSIPR] = 0x0118,
  249. [PIR] = 0x0120,
  250. [PSR] = 0x0128,
  251. [RDMLR] = 0x0140,
  252. [IPGR] = 0x0150,
  253. [APR] = 0x0154,
  254. [MPR] = 0x0158,
  255. [TPAUSER] = 0x0164,
  256. [RFCF] = 0x0160,
  257. [TPAUSECR] = 0x0168,
  258. [BCFRR] = 0x016c,
  259. [MAHR] = 0x01c0,
  260. [MALR] = 0x01c8,
  261. [TROCR] = 0x01d0,
  262. [CDCR] = 0x01d4,
  263. [LCCR] = 0x01d8,
  264. [CNDCR] = 0x01dc,
  265. [CEFCR] = 0x01e4,
  266. [FRECR] = 0x01e8,
  267. [TSFRCR] = 0x01ec,
  268. [TLFRCR] = 0x01f0,
  269. [RFCR] = 0x01f4,
  270. [MAFCR] = 0x01f8,
  271. [RTRATE] = 0x01fc,
  272. [EDMR] = 0x0000,
  273. [EDTRR] = 0x0008,
  274. [EDRRR] = 0x0010,
  275. [TDLAR] = 0x0018,
  276. [RDLAR] = 0x0020,
  277. [EESR] = 0x0028,
  278. [EESIPR] = 0x0030,
  279. [TRSCER] = 0x0038,
  280. [RMFCR] = 0x0040,
  281. [TFTR] = 0x0048,
  282. [FDR] = 0x0050,
  283. [RMCR] = 0x0058,
  284. [TFUCR] = 0x0064,
  285. [RFOCR] = 0x0068,
  286. [FCFTR] = 0x0070,
  287. [RPADIR] = 0x0078,
  288. [TRIMD] = 0x007c,
  289. [RBWAR] = 0x00c8,
  290. [RDFAR] = 0x00cc,
  291. [TBRAR] = 0x00d4,
  292. [TDFAR] = 0x00d8,
  293. };
  294. static const u16 sh_eth_offset_fast_sh3_sh2[SH_ETH_MAX_REGISTER_OFFSET] = {
  295. [EDMR] = 0x0000,
  296. [EDTRR] = 0x0004,
  297. [EDRRR] = 0x0008,
  298. [TDLAR] = 0x000c,
  299. [RDLAR] = 0x0010,
  300. [EESR] = 0x0014,
  301. [EESIPR] = 0x0018,
  302. [TRSCER] = 0x001c,
  303. [RMFCR] = 0x0020,
  304. [TFTR] = 0x0024,
  305. [FDR] = 0x0028,
  306. [RMCR] = 0x002c,
  307. [EDOCR] = 0x0030,
  308. [FCFTR] = 0x0034,
  309. [RPADIR] = 0x0038,
  310. [TRIMD] = 0x003c,
  311. [RBWAR] = 0x0040,
  312. [RDFAR] = 0x0044,
  313. [TBRAR] = 0x004c,
  314. [TDFAR] = 0x0050,
  315. [ECMR] = 0x0160,
  316. [ECSR] = 0x0164,
  317. [ECSIPR] = 0x0168,
  318. [PIR] = 0x016c,
  319. [MAHR] = 0x0170,
  320. [MALR] = 0x0174,
  321. [RFLR] = 0x0178,
  322. [PSR] = 0x017c,
  323. [TROCR] = 0x0180,
  324. [CDCR] = 0x0184,
  325. [LCCR] = 0x0188,
  326. [CNDCR] = 0x018c,
  327. [CEFCR] = 0x0194,
  328. [FRECR] = 0x0198,
  329. [TSFRCR] = 0x019c,
  330. [TLFRCR] = 0x01a0,
  331. [RFCR] = 0x01a4,
  332. [MAFCR] = 0x01a8,
  333. [IPGR] = 0x01b4,
  334. [APR] = 0x01b8,
  335. [MPR] = 0x01bc,
  336. [TPAUSER] = 0x01c4,
  337. [BCFR] = 0x01cc,
  338. [ARSTR] = 0x0000,
  339. [TSU_CTRST] = 0x0004,
  340. [TSU_FWEN0] = 0x0010,
  341. [TSU_FWEN1] = 0x0014,
  342. [TSU_FCM] = 0x0018,
  343. [TSU_BSYSL0] = 0x0020,
  344. [TSU_BSYSL1] = 0x0024,
  345. [TSU_PRISL0] = 0x0028,
  346. [TSU_PRISL1] = 0x002c,
  347. [TSU_FWSL0] = 0x0030,
  348. [TSU_FWSL1] = 0x0034,
  349. [TSU_FWSLC] = 0x0038,
  350. [TSU_QTAGM0] = 0x0040,
  351. [TSU_QTAGM1] = 0x0044,
  352. [TSU_ADQT0] = 0x0048,
  353. [TSU_ADQT1] = 0x004c,
  354. [TSU_FWSR] = 0x0050,
  355. [TSU_FWINMK] = 0x0054,
  356. [TSU_ADSBSY] = 0x0060,
  357. [TSU_TEN] = 0x0064,
  358. [TSU_POST1] = 0x0070,
  359. [TSU_POST2] = 0x0074,
  360. [TSU_POST3] = 0x0078,
  361. [TSU_POST4] = 0x007c,
  362. [TXNLCR0] = 0x0080,
  363. [TXALCR0] = 0x0084,
  364. [RXNLCR0] = 0x0088,
  365. [RXALCR0] = 0x008c,
  366. [FWNLCR0] = 0x0090,
  367. [FWALCR0] = 0x0094,
  368. [TXNLCR1] = 0x00a0,
  369. [TXALCR1] = 0x00a0,
  370. [RXNLCR1] = 0x00a8,
  371. [RXALCR1] = 0x00ac,
  372. [FWNLCR1] = 0x00b0,
  373. [FWALCR1] = 0x00b4,
  374. [TSU_ADRH0] = 0x0100,
  375. [TSU_ADRL0] = 0x0104,
  376. [TSU_ADRL31] = 0x01fc,
  377. };
  378. static bool sh_eth_is_gether(struct sh_eth_private *mdp)
  379. {
  380. return mdp->reg_offset == sh_eth_offset_gigabit;
  381. }
  382. static bool sh_eth_is_rz_fast_ether(struct sh_eth_private *mdp)
  383. {
  384. return mdp->reg_offset == sh_eth_offset_fast_rz;
  385. }
  386. static void sh_eth_select_mii(struct net_device *ndev)
  387. {
  388. u32 value = 0x0;
  389. struct sh_eth_private *mdp = netdev_priv(ndev);
  390. switch (mdp->phy_interface) {
  391. case PHY_INTERFACE_MODE_GMII:
  392. value = 0x2;
  393. break;
  394. case PHY_INTERFACE_MODE_MII:
  395. value = 0x1;
  396. break;
  397. case PHY_INTERFACE_MODE_RMII:
  398. value = 0x0;
  399. break;
  400. default:
  401. netdev_warn(ndev,
  402. "PHY interface mode was not setup. Set to MII.\n");
  403. value = 0x1;
  404. break;
  405. }
  406. sh_eth_write(ndev, value, RMII_MII);
  407. }
  408. static void sh_eth_set_duplex(struct net_device *ndev)
  409. {
  410. struct sh_eth_private *mdp = netdev_priv(ndev);
  411. if (mdp->duplex) /* Full */
  412. sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_DM, ECMR);
  413. else /* Half */
  414. sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_DM, ECMR);
  415. }
  416. /* There is CPU dependent code */
  417. static void sh_eth_set_rate_r8a777x(struct net_device *ndev)
  418. {
  419. struct sh_eth_private *mdp = netdev_priv(ndev);
  420. switch (mdp->speed) {
  421. case 10: /* 10BASE */
  422. sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_ELB, ECMR);
  423. break;
  424. case 100:/* 100BASE */
  425. sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_ELB, ECMR);
  426. break;
  427. default:
  428. break;
  429. }
  430. }
  431. /* R8A7778/9 */
  432. static struct sh_eth_cpu_data r8a777x_data = {
  433. .set_duplex = sh_eth_set_duplex,
  434. .set_rate = sh_eth_set_rate_r8a777x,
  435. .register_type = SH_ETH_REG_FAST_RCAR,
  436. .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
  437. .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
  438. .eesipr_value = 0x01ff009f,
  439. .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
  440. .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
  441. EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
  442. EESR_ECI,
  443. .fdr_value = 0x00000f0f,
  444. .apr = 1,
  445. .mpr = 1,
  446. .tpauser = 1,
  447. .hw_swap = 1,
  448. };
  449. /* R8A7790/1 */
  450. static struct sh_eth_cpu_data r8a779x_data = {
  451. .set_duplex = sh_eth_set_duplex,
  452. .set_rate = sh_eth_set_rate_r8a777x,
  453. .register_type = SH_ETH_REG_FAST_RCAR,
  454. .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
  455. .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
  456. .eesipr_value = 0x01ff009f,
  457. .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
  458. .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
  459. EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
  460. EESR_ECI,
  461. .fdr_value = 0x00000f0f,
  462. .apr = 1,
  463. .mpr = 1,
  464. .tpauser = 1,
  465. .hw_swap = 1,
  466. .rmiimode = 1,
  467. .shift_rd0 = 1,
  468. };
  469. static void sh_eth_set_rate_sh7724(struct net_device *ndev)
  470. {
  471. struct sh_eth_private *mdp = netdev_priv(ndev);
  472. switch (mdp->speed) {
  473. case 10: /* 10BASE */
  474. sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_RTM, ECMR);
  475. break;
  476. case 100:/* 100BASE */
  477. sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_RTM, ECMR);
  478. break;
  479. default:
  480. break;
  481. }
  482. }
  483. /* SH7724 */
  484. static struct sh_eth_cpu_data sh7724_data = {
  485. .set_duplex = sh_eth_set_duplex,
  486. .set_rate = sh_eth_set_rate_sh7724,
  487. .register_type = SH_ETH_REG_FAST_SH4,
  488. .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
  489. .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
  490. .eesipr_value = 0x01ff009f,
  491. .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
  492. .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
  493. EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
  494. EESR_ECI,
  495. .trscer_err_mask = DESC_I_RINT8,
  496. .apr = 1,
  497. .mpr = 1,
  498. .tpauser = 1,
  499. .hw_swap = 1,
  500. .rpadir = 1,
  501. .rpadir_value = 0x00020000, /* NET_IP_ALIGN assumed to be 2 */
  502. };
  503. static void sh_eth_set_rate_sh7757(struct net_device *ndev)
  504. {
  505. struct sh_eth_private *mdp = netdev_priv(ndev);
  506. switch (mdp->speed) {
  507. case 10: /* 10BASE */
  508. sh_eth_write(ndev, 0, RTRATE);
  509. break;
  510. case 100:/* 100BASE */
  511. sh_eth_write(ndev, 1, RTRATE);
  512. break;
  513. default:
  514. break;
  515. }
  516. }
  517. /* SH7757 */
  518. static struct sh_eth_cpu_data sh7757_data = {
  519. .set_duplex = sh_eth_set_duplex,
  520. .set_rate = sh_eth_set_rate_sh7757,
  521. .register_type = SH_ETH_REG_FAST_SH4,
  522. .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
  523. .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
  524. .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
  525. EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
  526. EESR_ECI,
  527. .irq_flags = IRQF_SHARED,
  528. .apr = 1,
  529. .mpr = 1,
  530. .tpauser = 1,
  531. .hw_swap = 1,
  532. .no_ade = 1,
  533. .rpadir = 1,
  534. .rpadir_value = 2 << 16,
  535. };
  536. #define SH_GIGA_ETH_BASE 0xfee00000UL
  537. #define GIGA_MALR(port) (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c8)
  538. #define GIGA_MAHR(port) (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c0)
  539. static void sh_eth_chip_reset_giga(struct net_device *ndev)
  540. {
  541. int i;
  542. u32 mahr[2], malr[2];
  543. /* save MAHR and MALR */
  544. for (i = 0; i < 2; i++) {
  545. malr[i] = ioread32((void *)GIGA_MALR(i));
  546. mahr[i] = ioread32((void *)GIGA_MAHR(i));
  547. }
  548. /* reset device */
  549. iowrite32(ARSTR_ARSTR, (void *)(SH_GIGA_ETH_BASE + 0x1800));
  550. mdelay(1);
  551. /* restore MAHR and MALR */
  552. for (i = 0; i < 2; i++) {
  553. iowrite32(malr[i], (void *)GIGA_MALR(i));
  554. iowrite32(mahr[i], (void *)GIGA_MAHR(i));
  555. }
  556. }
  557. static void sh_eth_set_rate_giga(struct net_device *ndev)
  558. {
  559. struct sh_eth_private *mdp = netdev_priv(ndev);
  560. switch (mdp->speed) {
  561. case 10: /* 10BASE */
  562. sh_eth_write(ndev, 0x00000000, GECMR);
  563. break;
  564. case 100:/* 100BASE */
  565. sh_eth_write(ndev, 0x00000010, GECMR);
  566. break;
  567. case 1000: /* 1000BASE */
  568. sh_eth_write(ndev, 0x00000020, GECMR);
  569. break;
  570. default:
  571. break;
  572. }
  573. }
  574. /* SH7757(GETHERC) */
  575. static struct sh_eth_cpu_data sh7757_data_giga = {
  576. .chip_reset = sh_eth_chip_reset_giga,
  577. .set_duplex = sh_eth_set_duplex,
  578. .set_rate = sh_eth_set_rate_giga,
  579. .register_type = SH_ETH_REG_GIGABIT,
  580. .ecsr_value = ECSR_ICD | ECSR_MPD,
  581. .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
  582. .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
  583. .tx_check = EESR_TC1 | EESR_FTC,
  584. .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
  585. EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
  586. EESR_TDE | EESR_ECI,
  587. .fdr_value = 0x0000072f,
  588. .irq_flags = IRQF_SHARED,
  589. .apr = 1,
  590. .mpr = 1,
  591. .tpauser = 1,
  592. .bculr = 1,
  593. .hw_swap = 1,
  594. .rpadir = 1,
  595. .rpadir_value = 2 << 16,
  596. .no_trimd = 1,
  597. .no_ade = 1,
  598. .tsu = 1,
  599. };
  600. static void sh_eth_chip_reset(struct net_device *ndev)
  601. {
  602. struct sh_eth_private *mdp = netdev_priv(ndev);
  603. /* reset device */
  604. sh_eth_tsu_write(mdp, ARSTR_ARSTR, ARSTR);
  605. mdelay(1);
  606. }
  607. static void sh_eth_set_rate_gether(struct net_device *ndev)
  608. {
  609. struct sh_eth_private *mdp = netdev_priv(ndev);
  610. switch (mdp->speed) {
  611. case 10: /* 10BASE */
  612. sh_eth_write(ndev, GECMR_10, GECMR);
  613. break;
  614. case 100:/* 100BASE */
  615. sh_eth_write(ndev, GECMR_100, GECMR);
  616. break;
  617. case 1000: /* 1000BASE */
  618. sh_eth_write(ndev, GECMR_1000, GECMR);
  619. break;
  620. default:
  621. break;
  622. }
  623. }
  624. /* SH7734 */
  625. static struct sh_eth_cpu_data sh7734_data = {
  626. .chip_reset = sh_eth_chip_reset,
  627. .set_duplex = sh_eth_set_duplex,
  628. .set_rate = sh_eth_set_rate_gether,
  629. .register_type = SH_ETH_REG_GIGABIT,
  630. .ecsr_value = ECSR_ICD | ECSR_MPD,
  631. .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
  632. .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
  633. .tx_check = EESR_TC1 | EESR_FTC,
  634. .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
  635. EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
  636. EESR_TDE | EESR_ECI,
  637. .apr = 1,
  638. .mpr = 1,
  639. .tpauser = 1,
  640. .bculr = 1,
  641. .hw_swap = 1,
  642. .no_trimd = 1,
  643. .no_ade = 1,
  644. .tsu = 1,
  645. .hw_crc = 1,
  646. .select_mii = 1,
  647. };
  648. /* SH7763 */
  649. static struct sh_eth_cpu_data sh7763_data = {
  650. .chip_reset = sh_eth_chip_reset,
  651. .set_duplex = sh_eth_set_duplex,
  652. .set_rate = sh_eth_set_rate_gether,
  653. .register_type = SH_ETH_REG_GIGABIT,
  654. .ecsr_value = ECSR_ICD | ECSR_MPD,
  655. .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
  656. .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
  657. .tx_check = EESR_TC1 | EESR_FTC,
  658. .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
  659. EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
  660. EESR_ECI,
  661. .apr = 1,
  662. .mpr = 1,
  663. .tpauser = 1,
  664. .bculr = 1,
  665. .hw_swap = 1,
  666. .no_trimd = 1,
  667. .no_ade = 1,
  668. .tsu = 1,
  669. .irq_flags = IRQF_SHARED,
  670. };
  671. static void sh_eth_chip_reset_r8a7740(struct net_device *ndev)
  672. {
  673. struct sh_eth_private *mdp = netdev_priv(ndev);
  674. /* reset device */
  675. sh_eth_tsu_write(mdp, ARSTR_ARSTR, ARSTR);
  676. mdelay(1);
  677. sh_eth_select_mii(ndev);
  678. }
  679. /* R8A7740 */
  680. static struct sh_eth_cpu_data r8a7740_data = {
  681. .chip_reset = sh_eth_chip_reset_r8a7740,
  682. .set_duplex = sh_eth_set_duplex,
  683. .set_rate = sh_eth_set_rate_gether,
  684. .register_type = SH_ETH_REG_GIGABIT,
  685. .ecsr_value = ECSR_ICD | ECSR_MPD,
  686. .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
  687. .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
  688. .tx_check = EESR_TC1 | EESR_FTC,
  689. .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
  690. EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
  691. EESR_TDE | EESR_ECI,
  692. .fdr_value = 0x0000070f,
  693. .apr = 1,
  694. .mpr = 1,
  695. .tpauser = 1,
  696. .bculr = 1,
  697. .hw_swap = 1,
  698. .rpadir = 1,
  699. .rpadir_value = 2 << 16,
  700. .no_trimd = 1,
  701. .no_ade = 1,
  702. .tsu = 1,
  703. .select_mii = 1,
  704. .shift_rd0 = 1,
  705. };
  706. /* R7S72100 */
  707. static struct sh_eth_cpu_data r7s72100_data = {
  708. .chip_reset = sh_eth_chip_reset,
  709. .set_duplex = sh_eth_set_duplex,
  710. .register_type = SH_ETH_REG_FAST_RZ,
  711. .ecsr_value = ECSR_ICD,
  712. .ecsipr_value = ECSIPR_ICDIP,
  713. .eesipr_value = 0xff7f009f,
  714. .tx_check = EESR_TC1 | EESR_FTC,
  715. .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
  716. EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
  717. EESR_TDE | EESR_ECI,
  718. .fdr_value = 0x0000070f,
  719. .no_psr = 1,
  720. .apr = 1,
  721. .mpr = 1,
  722. .tpauser = 1,
  723. .hw_swap = 1,
  724. .rpadir = 1,
  725. .rpadir_value = 2 << 16,
  726. .no_trimd = 1,
  727. .no_ade = 1,
  728. .hw_crc = 1,
  729. .tsu = 1,
  730. .shift_rd0 = 1,
  731. };
  732. static struct sh_eth_cpu_data sh7619_data = {
  733. .register_type = SH_ETH_REG_FAST_SH3_SH2,
  734. .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
  735. .apr = 1,
  736. .mpr = 1,
  737. .tpauser = 1,
  738. .hw_swap = 1,
  739. };
  740. static struct sh_eth_cpu_data sh771x_data = {
  741. .register_type = SH_ETH_REG_FAST_SH3_SH2,
  742. .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
  743. .tsu = 1,
  744. };
  745. static void sh_eth_set_default_cpu_data(struct sh_eth_cpu_data *cd)
  746. {
  747. if (!cd->ecsr_value)
  748. cd->ecsr_value = DEFAULT_ECSR_INIT;
  749. if (!cd->ecsipr_value)
  750. cd->ecsipr_value = DEFAULT_ECSIPR_INIT;
  751. if (!cd->fcftr_value)
  752. cd->fcftr_value = DEFAULT_FIFO_F_D_RFF |
  753. DEFAULT_FIFO_F_D_RFD;
  754. if (!cd->fdr_value)
  755. cd->fdr_value = DEFAULT_FDR_INIT;
  756. if (!cd->tx_check)
  757. cd->tx_check = DEFAULT_TX_CHECK;
  758. if (!cd->eesr_err_check)
  759. cd->eesr_err_check = DEFAULT_EESR_ERR_CHECK;
  760. if (!cd->trscer_err_mask)
  761. cd->trscer_err_mask = DEFAULT_TRSCER_ERR_MASK;
  762. }
  763. static int sh_eth_check_reset(struct net_device *ndev)
  764. {
  765. int ret = 0;
  766. int cnt = 100;
  767. while (cnt > 0) {
  768. if (!(sh_eth_read(ndev, EDMR) & 0x3))
  769. break;
  770. mdelay(1);
  771. cnt--;
  772. }
  773. if (cnt <= 0) {
  774. netdev_err(ndev, "Device reset failed\n");
  775. ret = -ETIMEDOUT;
  776. }
  777. return ret;
  778. }
  779. static int sh_eth_reset(struct net_device *ndev)
  780. {
  781. struct sh_eth_private *mdp = netdev_priv(ndev);
  782. int ret = 0;
  783. if (sh_eth_is_gether(mdp) || sh_eth_is_rz_fast_ether(mdp)) {
  784. sh_eth_write(ndev, EDSR_ENALL, EDSR);
  785. sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_GETHER,
  786. EDMR);
  787. ret = sh_eth_check_reset(ndev);
  788. if (ret)
  789. return ret;
  790. /* Table Init */
  791. sh_eth_write(ndev, 0x0, TDLAR);
  792. sh_eth_write(ndev, 0x0, TDFAR);
  793. sh_eth_write(ndev, 0x0, TDFXR);
  794. sh_eth_write(ndev, 0x0, TDFFR);
  795. sh_eth_write(ndev, 0x0, RDLAR);
  796. sh_eth_write(ndev, 0x0, RDFAR);
  797. sh_eth_write(ndev, 0x0, RDFXR);
  798. sh_eth_write(ndev, 0x0, RDFFR);
  799. /* Reset HW CRC register */
  800. if (mdp->cd->hw_crc)
  801. sh_eth_write(ndev, 0x0, CSMR);
  802. /* Select MII mode */
  803. if (mdp->cd->select_mii)
  804. sh_eth_select_mii(ndev);
  805. } else {
  806. sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_ETHER,
  807. EDMR);
  808. mdelay(3);
  809. sh_eth_write(ndev, sh_eth_read(ndev, EDMR) & ~EDMR_SRST_ETHER,
  810. EDMR);
  811. }
  812. return ret;
  813. }
  814. static void sh_eth_set_receive_align(struct sk_buff *skb)
  815. {
  816. uintptr_t reserve = (uintptr_t)skb->data & (SH_ETH_RX_ALIGN - 1);
  817. if (reserve)
  818. skb_reserve(skb, SH_ETH_RX_ALIGN - reserve);
  819. }
  820. /* CPU <-> EDMAC endian convert */
  821. static inline __u32 cpu_to_edmac(struct sh_eth_private *mdp, u32 x)
  822. {
  823. switch (mdp->edmac_endian) {
  824. case EDMAC_LITTLE_ENDIAN:
  825. return cpu_to_le32(x);
  826. case EDMAC_BIG_ENDIAN:
  827. return cpu_to_be32(x);
  828. }
  829. return x;
  830. }
  831. static inline __u32 edmac_to_cpu(struct sh_eth_private *mdp, u32 x)
  832. {
  833. switch (mdp->edmac_endian) {
  834. case EDMAC_LITTLE_ENDIAN:
  835. return le32_to_cpu(x);
  836. case EDMAC_BIG_ENDIAN:
  837. return be32_to_cpu(x);
  838. }
  839. return x;
  840. }
  841. /* Program the hardware MAC address from dev->dev_addr. */
  842. static void update_mac_address(struct net_device *ndev)
  843. {
  844. sh_eth_write(ndev,
  845. (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) |
  846. (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR);
  847. sh_eth_write(ndev,
  848. (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR);
  849. }
  850. /* Get MAC address from SuperH MAC address register
  851. *
  852. * SuperH's Ethernet device doesn't have 'ROM' to MAC address.
  853. * This driver get MAC address that use by bootloader(U-boot or sh-ipl+g).
  854. * When you want use this device, you must set MAC address in bootloader.
  855. *
  856. */
  857. static void read_mac_address(struct net_device *ndev, unsigned char *mac)
  858. {
  859. if (mac[0] || mac[1] || mac[2] || mac[3] || mac[4] || mac[5]) {
  860. memcpy(ndev->dev_addr, mac, ETH_ALEN);
  861. } else {
  862. ndev->dev_addr[0] = (sh_eth_read(ndev, MAHR) >> 24);
  863. ndev->dev_addr[1] = (sh_eth_read(ndev, MAHR) >> 16) & 0xFF;
  864. ndev->dev_addr[2] = (sh_eth_read(ndev, MAHR) >> 8) & 0xFF;
  865. ndev->dev_addr[3] = (sh_eth_read(ndev, MAHR) & 0xFF);
  866. ndev->dev_addr[4] = (sh_eth_read(ndev, MALR) >> 8) & 0xFF;
  867. ndev->dev_addr[5] = (sh_eth_read(ndev, MALR) & 0xFF);
  868. }
  869. }
  870. static u32 sh_eth_get_edtrr_trns(struct sh_eth_private *mdp)
  871. {
  872. if (sh_eth_is_gether(mdp) || sh_eth_is_rz_fast_ether(mdp))
  873. return EDTRR_TRNS_GETHER;
  874. else
  875. return EDTRR_TRNS_ETHER;
  876. }
  877. struct bb_info {
  878. void (*set_gate)(void *addr);
  879. struct mdiobb_ctrl ctrl;
  880. void *addr;
  881. u32 mmd_msk;/* MMD */
  882. u32 mdo_msk;
  883. u32 mdi_msk;
  884. u32 mdc_msk;
  885. };
  886. /* PHY bit set */
  887. static void bb_set(void *addr, u32 msk)
  888. {
  889. iowrite32(ioread32(addr) | msk, addr);
  890. }
  891. /* PHY bit clear */
  892. static void bb_clr(void *addr, u32 msk)
  893. {
  894. iowrite32((ioread32(addr) & ~msk), addr);
  895. }
  896. /* PHY bit read */
  897. static int bb_read(void *addr, u32 msk)
  898. {
  899. return (ioread32(addr) & msk) != 0;
  900. }
  901. /* Data I/O pin control */
  902. static void sh_mmd_ctrl(struct mdiobb_ctrl *ctrl, int bit)
  903. {
  904. struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
  905. if (bitbang->set_gate)
  906. bitbang->set_gate(bitbang->addr);
  907. if (bit)
  908. bb_set(bitbang->addr, bitbang->mmd_msk);
  909. else
  910. bb_clr(bitbang->addr, bitbang->mmd_msk);
  911. }
  912. /* Set bit data*/
  913. static void sh_set_mdio(struct mdiobb_ctrl *ctrl, int bit)
  914. {
  915. struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
  916. if (bitbang->set_gate)
  917. bitbang->set_gate(bitbang->addr);
  918. if (bit)
  919. bb_set(bitbang->addr, bitbang->mdo_msk);
  920. else
  921. bb_clr(bitbang->addr, bitbang->mdo_msk);
  922. }
  923. /* Get bit data*/
  924. static int sh_get_mdio(struct mdiobb_ctrl *ctrl)
  925. {
  926. struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
  927. if (bitbang->set_gate)
  928. bitbang->set_gate(bitbang->addr);
  929. return bb_read(bitbang->addr, bitbang->mdi_msk);
  930. }
  931. /* MDC pin control */
  932. static void sh_mdc_ctrl(struct mdiobb_ctrl *ctrl, int bit)
  933. {
  934. struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
  935. if (bitbang->set_gate)
  936. bitbang->set_gate(bitbang->addr);
  937. if (bit)
  938. bb_set(bitbang->addr, bitbang->mdc_msk);
  939. else
  940. bb_clr(bitbang->addr, bitbang->mdc_msk);
  941. }
  942. /* mdio bus control struct */
  943. static struct mdiobb_ops bb_ops = {
  944. .owner = THIS_MODULE,
  945. .set_mdc = sh_mdc_ctrl,
  946. .set_mdio_dir = sh_mmd_ctrl,
  947. .set_mdio_data = sh_set_mdio,
  948. .get_mdio_data = sh_get_mdio,
  949. };
  950. /* free skb and descriptor buffer */
  951. static void sh_eth_ring_free(struct net_device *ndev)
  952. {
  953. struct sh_eth_private *mdp = netdev_priv(ndev);
  954. int i;
  955. /* Free Rx skb ringbuffer */
  956. if (mdp->rx_skbuff) {
  957. for (i = 0; i < mdp->num_rx_ring; i++)
  958. dev_kfree_skb(mdp->rx_skbuff[i]);
  959. }
  960. kfree(mdp->rx_skbuff);
  961. mdp->rx_skbuff = NULL;
  962. /* Free Tx skb ringbuffer */
  963. if (mdp->tx_skbuff) {
  964. for (i = 0; i < mdp->num_tx_ring; i++)
  965. dev_kfree_skb(mdp->tx_skbuff[i]);
  966. }
  967. kfree(mdp->tx_skbuff);
  968. mdp->tx_skbuff = NULL;
  969. }
  970. /* format skb and descriptor buffer */
  971. static void sh_eth_ring_format(struct net_device *ndev)
  972. {
  973. struct sh_eth_private *mdp = netdev_priv(ndev);
  974. int i;
  975. struct sk_buff *skb;
  976. struct sh_eth_rxdesc *rxdesc = NULL;
  977. struct sh_eth_txdesc *txdesc = NULL;
  978. int rx_ringsize = sizeof(*rxdesc) * mdp->num_rx_ring;
  979. int tx_ringsize = sizeof(*txdesc) * mdp->num_tx_ring;
  980. int skbuff_size = mdp->rx_buf_sz + SH_ETH_RX_ALIGN - 1;
  981. mdp->cur_rx = 0;
  982. mdp->cur_tx = 0;
  983. mdp->dirty_rx = 0;
  984. mdp->dirty_tx = 0;
  985. memset(mdp->rx_ring, 0, rx_ringsize);
  986. /* build Rx ring buffer */
  987. for (i = 0; i < mdp->num_rx_ring; i++) {
  988. /* skb */
  989. mdp->rx_skbuff[i] = NULL;
  990. skb = netdev_alloc_skb(ndev, skbuff_size);
  991. mdp->rx_skbuff[i] = skb;
  992. if (skb == NULL)
  993. break;
  994. sh_eth_set_receive_align(skb);
  995. /* RX descriptor */
  996. rxdesc = &mdp->rx_ring[i];
  997. /* The size of the buffer is a multiple of 16 bytes. */
  998. rxdesc->buffer_length = ALIGN(mdp->rx_buf_sz, 16);
  999. dma_map_single(&ndev->dev, skb->data, rxdesc->buffer_length,
  1000. DMA_FROM_DEVICE);
  1001. rxdesc->addr = virt_to_phys(skb->data);
  1002. rxdesc->status = cpu_to_edmac(mdp, RD_RACT | RD_RFP);
  1003. /* Rx descriptor address set */
  1004. if (i == 0) {
  1005. sh_eth_write(ndev, mdp->rx_desc_dma, RDLAR);
  1006. if (sh_eth_is_gether(mdp) ||
  1007. sh_eth_is_rz_fast_ether(mdp))
  1008. sh_eth_write(ndev, mdp->rx_desc_dma, RDFAR);
  1009. }
  1010. }
  1011. mdp->dirty_rx = (u32) (i - mdp->num_rx_ring);
  1012. /* Mark the last entry as wrapping the ring. */
  1013. rxdesc->status |= cpu_to_edmac(mdp, RD_RDEL);
  1014. memset(mdp->tx_ring, 0, tx_ringsize);
  1015. /* build Tx ring buffer */
  1016. for (i = 0; i < mdp->num_tx_ring; i++) {
  1017. mdp->tx_skbuff[i] = NULL;
  1018. txdesc = &mdp->tx_ring[i];
  1019. txdesc->status = cpu_to_edmac(mdp, TD_TFP);
  1020. txdesc->buffer_length = 0;
  1021. if (i == 0) {
  1022. /* Tx descriptor address set */
  1023. sh_eth_write(ndev, mdp->tx_desc_dma, TDLAR);
  1024. if (sh_eth_is_gether(mdp) ||
  1025. sh_eth_is_rz_fast_ether(mdp))
  1026. sh_eth_write(ndev, mdp->tx_desc_dma, TDFAR);
  1027. }
  1028. }
  1029. txdesc->status |= cpu_to_edmac(mdp, TD_TDLE);
  1030. }
  1031. /* Get skb and descriptor buffer */
  1032. static int sh_eth_ring_init(struct net_device *ndev)
  1033. {
  1034. struct sh_eth_private *mdp = netdev_priv(ndev);
  1035. int rx_ringsize, tx_ringsize, ret = 0;
  1036. /* +26 gets the maximum ethernet encapsulation, +7 & ~7 because the
  1037. * card needs room to do 8 byte alignment, +2 so we can reserve
  1038. * the first 2 bytes, and +16 gets room for the status word from the
  1039. * card.
  1040. */
  1041. mdp->rx_buf_sz = (ndev->mtu <= 1492 ? PKT_BUF_SZ :
  1042. (((ndev->mtu + 26 + 7) & ~7) + 2 + 16));
  1043. if (mdp->cd->rpadir)
  1044. mdp->rx_buf_sz += NET_IP_ALIGN;
  1045. /* Allocate RX and TX skb rings */
  1046. mdp->rx_skbuff = kmalloc_array(mdp->num_rx_ring,
  1047. sizeof(*mdp->rx_skbuff), GFP_KERNEL);
  1048. if (!mdp->rx_skbuff) {
  1049. ret = -ENOMEM;
  1050. return ret;
  1051. }
  1052. mdp->tx_skbuff = kmalloc_array(mdp->num_tx_ring,
  1053. sizeof(*mdp->tx_skbuff), GFP_KERNEL);
  1054. if (!mdp->tx_skbuff) {
  1055. ret = -ENOMEM;
  1056. goto skb_ring_free;
  1057. }
  1058. /* Allocate all Rx descriptors. */
  1059. rx_ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring;
  1060. mdp->rx_ring = dma_alloc_coherent(NULL, rx_ringsize, &mdp->rx_desc_dma,
  1061. GFP_KERNEL);
  1062. if (!mdp->rx_ring) {
  1063. ret = -ENOMEM;
  1064. goto desc_ring_free;
  1065. }
  1066. mdp->dirty_rx = 0;
  1067. /* Allocate all Tx descriptors. */
  1068. tx_ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring;
  1069. mdp->tx_ring = dma_alloc_coherent(NULL, tx_ringsize, &mdp->tx_desc_dma,
  1070. GFP_KERNEL);
  1071. if (!mdp->tx_ring) {
  1072. ret = -ENOMEM;
  1073. goto desc_ring_free;
  1074. }
  1075. return ret;
  1076. desc_ring_free:
  1077. /* free DMA buffer */
  1078. dma_free_coherent(NULL, rx_ringsize, mdp->rx_ring, mdp->rx_desc_dma);
  1079. skb_ring_free:
  1080. /* Free Rx and Tx skb ring buffer */
  1081. sh_eth_ring_free(ndev);
  1082. mdp->tx_ring = NULL;
  1083. mdp->rx_ring = NULL;
  1084. return ret;
  1085. }
  1086. static void sh_eth_free_dma_buffer(struct sh_eth_private *mdp)
  1087. {
  1088. int ringsize;
  1089. if (mdp->rx_ring) {
  1090. ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring;
  1091. dma_free_coherent(NULL, ringsize, mdp->rx_ring,
  1092. mdp->rx_desc_dma);
  1093. mdp->rx_ring = NULL;
  1094. }
  1095. if (mdp->tx_ring) {
  1096. ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring;
  1097. dma_free_coherent(NULL, ringsize, mdp->tx_ring,
  1098. mdp->tx_desc_dma);
  1099. mdp->tx_ring = NULL;
  1100. }
  1101. }
  1102. static int sh_eth_dev_init(struct net_device *ndev, bool start)
  1103. {
  1104. int ret = 0;
  1105. struct sh_eth_private *mdp = netdev_priv(ndev);
  1106. u32 val;
  1107. /* Soft Reset */
  1108. ret = sh_eth_reset(ndev);
  1109. if (ret)
  1110. return ret;
  1111. if (mdp->cd->rmiimode)
  1112. sh_eth_write(ndev, 0x1, RMIIMODE);
  1113. /* Descriptor format */
  1114. sh_eth_ring_format(ndev);
  1115. if (mdp->cd->rpadir)
  1116. sh_eth_write(ndev, mdp->cd->rpadir_value, RPADIR);
  1117. /* all sh_eth int mask */
  1118. sh_eth_write(ndev, 0, EESIPR);
  1119. #if defined(__LITTLE_ENDIAN)
  1120. if (mdp->cd->hw_swap)
  1121. sh_eth_write(ndev, EDMR_EL, EDMR);
  1122. else
  1123. #endif
  1124. sh_eth_write(ndev, 0, EDMR);
  1125. /* FIFO size set */
  1126. sh_eth_write(ndev, mdp->cd->fdr_value, FDR);
  1127. sh_eth_write(ndev, 0, TFTR);
  1128. /* Frame recv control (enable multiple-packets per rx irq) */
  1129. sh_eth_write(ndev, RMCR_RNC, RMCR);
  1130. sh_eth_write(ndev, mdp->cd->trscer_err_mask, TRSCER);
  1131. if (mdp->cd->bculr)
  1132. sh_eth_write(ndev, 0x800, BCULR); /* Burst sycle set */
  1133. sh_eth_write(ndev, mdp->cd->fcftr_value, FCFTR);
  1134. if (!mdp->cd->no_trimd)
  1135. sh_eth_write(ndev, 0, TRIMD);
  1136. /* Recv frame limit set register */
  1137. sh_eth_write(ndev, ndev->mtu + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN,
  1138. RFLR);
  1139. sh_eth_write(ndev, sh_eth_read(ndev, EESR), EESR);
  1140. if (start)
  1141. sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
  1142. /* PAUSE Prohibition */
  1143. val = (sh_eth_read(ndev, ECMR) & ECMR_DM) |
  1144. ECMR_ZPF | (mdp->duplex ? ECMR_DM : 0) | ECMR_TE | ECMR_RE;
  1145. sh_eth_write(ndev, val, ECMR);
  1146. if (mdp->cd->set_rate)
  1147. mdp->cd->set_rate(ndev);
  1148. /* E-MAC Status Register clear */
  1149. sh_eth_write(ndev, mdp->cd->ecsr_value, ECSR);
  1150. /* E-MAC Interrupt Enable register */
  1151. if (start)
  1152. sh_eth_write(ndev, mdp->cd->ecsipr_value, ECSIPR);
  1153. /* Set MAC address */
  1154. update_mac_address(ndev);
  1155. /* mask reset */
  1156. if (mdp->cd->apr)
  1157. sh_eth_write(ndev, APR_AP, APR);
  1158. if (mdp->cd->mpr)
  1159. sh_eth_write(ndev, MPR_MP, MPR);
  1160. if (mdp->cd->tpauser)
  1161. sh_eth_write(ndev, TPAUSER_UNLIMITED, TPAUSER);
  1162. if (start) {
  1163. /* Setting the Rx mode will start the Rx process. */
  1164. sh_eth_write(ndev, EDRRR_R, EDRRR);
  1165. netif_start_queue(ndev);
  1166. }
  1167. return ret;
  1168. }
  1169. /* free Tx skb function */
  1170. static int sh_eth_txfree(struct net_device *ndev)
  1171. {
  1172. struct sh_eth_private *mdp = netdev_priv(ndev);
  1173. struct sh_eth_txdesc *txdesc;
  1174. int free_num = 0;
  1175. int entry = 0;
  1176. for (; mdp->cur_tx - mdp->dirty_tx > 0; mdp->dirty_tx++) {
  1177. entry = mdp->dirty_tx % mdp->num_tx_ring;
  1178. txdesc = &mdp->tx_ring[entry];
  1179. if (txdesc->status & cpu_to_edmac(mdp, TD_TACT))
  1180. break;
  1181. /* Free the original skb. */
  1182. if (mdp->tx_skbuff[entry]) {
  1183. dma_unmap_single(&ndev->dev, txdesc->addr,
  1184. txdesc->buffer_length, DMA_TO_DEVICE);
  1185. dev_kfree_skb_irq(mdp->tx_skbuff[entry]);
  1186. mdp->tx_skbuff[entry] = NULL;
  1187. free_num++;
  1188. }
  1189. txdesc->status = cpu_to_edmac(mdp, TD_TFP);
  1190. if (entry >= mdp->num_tx_ring - 1)
  1191. txdesc->status |= cpu_to_edmac(mdp, TD_TDLE);
  1192. ndev->stats.tx_packets++;
  1193. ndev->stats.tx_bytes += txdesc->buffer_length;
  1194. }
  1195. return free_num;
  1196. }
  1197. /* Packet receive function */
  1198. static int sh_eth_rx(struct net_device *ndev, u32 intr_status, int *quota)
  1199. {
  1200. struct sh_eth_private *mdp = netdev_priv(ndev);
  1201. struct sh_eth_rxdesc *rxdesc;
  1202. int entry = mdp->cur_rx % mdp->num_rx_ring;
  1203. int boguscnt = (mdp->dirty_rx + mdp->num_rx_ring) - mdp->cur_rx;
  1204. int limit;
  1205. struct sk_buff *skb;
  1206. u16 pkt_len = 0;
  1207. u32 desc_status;
  1208. int skbuff_size = mdp->rx_buf_sz + SH_ETH_RX_ALIGN - 1;
  1209. boguscnt = min(boguscnt, *quota);
  1210. limit = boguscnt;
  1211. rxdesc = &mdp->rx_ring[entry];
  1212. while (!(rxdesc->status & cpu_to_edmac(mdp, RD_RACT))) {
  1213. desc_status = edmac_to_cpu(mdp, rxdesc->status);
  1214. pkt_len = rxdesc->frame_length;
  1215. if (--boguscnt < 0)
  1216. break;
  1217. if (!(desc_status & RDFEND))
  1218. ndev->stats.rx_length_errors++;
  1219. /* In case of almost all GETHER/ETHERs, the Receive Frame State
  1220. * (RFS) bits in the Receive Descriptor 0 are from bit 9 to
  1221. * bit 0. However, in case of the R8A7740, R8A779x, and
  1222. * R7S72100 the RFS bits are from bit 25 to bit 16. So, the
  1223. * driver needs right shifting by 16.
  1224. */
  1225. if (mdp->cd->shift_rd0)
  1226. desc_status >>= 16;
  1227. if (desc_status & (RD_RFS1 | RD_RFS2 | RD_RFS3 | RD_RFS4 |
  1228. RD_RFS5 | RD_RFS6 | RD_RFS10)) {
  1229. ndev->stats.rx_errors++;
  1230. if (desc_status & RD_RFS1)
  1231. ndev->stats.rx_crc_errors++;
  1232. if (desc_status & RD_RFS2)
  1233. ndev->stats.rx_frame_errors++;
  1234. if (desc_status & RD_RFS3)
  1235. ndev->stats.rx_length_errors++;
  1236. if (desc_status & RD_RFS4)
  1237. ndev->stats.rx_length_errors++;
  1238. if (desc_status & RD_RFS6)
  1239. ndev->stats.rx_missed_errors++;
  1240. if (desc_status & RD_RFS10)
  1241. ndev->stats.rx_over_errors++;
  1242. } else {
  1243. if (!mdp->cd->hw_swap)
  1244. sh_eth_soft_swap(
  1245. phys_to_virt(ALIGN(rxdesc->addr, 4)),
  1246. pkt_len + 2);
  1247. skb = mdp->rx_skbuff[entry];
  1248. mdp->rx_skbuff[entry] = NULL;
  1249. if (mdp->cd->rpadir)
  1250. skb_reserve(skb, NET_IP_ALIGN);
  1251. dma_sync_single_for_cpu(&ndev->dev, rxdesc->addr,
  1252. ALIGN(mdp->rx_buf_sz, 16),
  1253. DMA_FROM_DEVICE);
  1254. skb_put(skb, pkt_len);
  1255. skb->protocol = eth_type_trans(skb, ndev);
  1256. netif_receive_skb(skb);
  1257. ndev->stats.rx_packets++;
  1258. ndev->stats.rx_bytes += pkt_len;
  1259. }
  1260. entry = (++mdp->cur_rx) % mdp->num_rx_ring;
  1261. rxdesc = &mdp->rx_ring[entry];
  1262. }
  1263. /* Refill the Rx ring buffers. */
  1264. for (; mdp->cur_rx - mdp->dirty_rx > 0; mdp->dirty_rx++) {
  1265. entry = mdp->dirty_rx % mdp->num_rx_ring;
  1266. rxdesc = &mdp->rx_ring[entry];
  1267. /* The size of the buffer is 16 byte boundary. */
  1268. rxdesc->buffer_length = ALIGN(mdp->rx_buf_sz, 16);
  1269. if (mdp->rx_skbuff[entry] == NULL) {
  1270. skb = netdev_alloc_skb(ndev, skbuff_size);
  1271. mdp->rx_skbuff[entry] = skb;
  1272. if (skb == NULL)
  1273. break; /* Better luck next round. */
  1274. sh_eth_set_receive_align(skb);
  1275. dma_map_single(&ndev->dev, skb->data,
  1276. rxdesc->buffer_length, DMA_FROM_DEVICE);
  1277. skb_checksum_none_assert(skb);
  1278. rxdesc->addr = virt_to_phys(skb->data);
  1279. }
  1280. if (entry >= mdp->num_rx_ring - 1)
  1281. rxdesc->status |=
  1282. cpu_to_edmac(mdp, RD_RACT | RD_RFP | RD_RDEL);
  1283. else
  1284. rxdesc->status |=
  1285. cpu_to_edmac(mdp, RD_RACT | RD_RFP);
  1286. }
  1287. /* Restart Rx engine if stopped. */
  1288. /* If we don't need to check status, don't. -KDU */
  1289. if (!(sh_eth_read(ndev, EDRRR) & EDRRR_R)) {
  1290. /* fix the values for the next receiving if RDE is set */
  1291. if (intr_status & EESR_RDE) {
  1292. u32 count = (sh_eth_read(ndev, RDFAR) -
  1293. sh_eth_read(ndev, RDLAR)) >> 4;
  1294. mdp->cur_rx = count;
  1295. mdp->dirty_rx = count;
  1296. }
  1297. sh_eth_write(ndev, EDRRR_R, EDRRR);
  1298. }
  1299. *quota -= limit - boguscnt - 1;
  1300. return *quota <= 0;
  1301. }
  1302. static void sh_eth_rcv_snd_disable(struct net_device *ndev)
  1303. {
  1304. /* disable tx and rx */
  1305. sh_eth_write(ndev, sh_eth_read(ndev, ECMR) &
  1306. ~(ECMR_RE | ECMR_TE), ECMR);
  1307. }
  1308. static void sh_eth_rcv_snd_enable(struct net_device *ndev)
  1309. {
  1310. /* enable tx and rx */
  1311. sh_eth_write(ndev, sh_eth_read(ndev, ECMR) |
  1312. (ECMR_RE | ECMR_TE), ECMR);
  1313. }
  1314. /* error control function */
  1315. static void sh_eth_error(struct net_device *ndev, u32 intr_status)
  1316. {
  1317. struct sh_eth_private *mdp = netdev_priv(ndev);
  1318. u32 felic_stat;
  1319. u32 link_stat;
  1320. u32 mask;
  1321. if (intr_status & EESR_ECI) {
  1322. felic_stat = sh_eth_read(ndev, ECSR);
  1323. sh_eth_write(ndev, felic_stat, ECSR); /* clear int */
  1324. if (felic_stat & ECSR_ICD)
  1325. ndev->stats.tx_carrier_errors++;
  1326. if (felic_stat & ECSR_LCHNG) {
  1327. /* Link Changed */
  1328. if (mdp->cd->no_psr || mdp->no_ether_link) {
  1329. goto ignore_link;
  1330. } else {
  1331. link_stat = (sh_eth_read(ndev, PSR));
  1332. if (mdp->ether_link_active_low)
  1333. link_stat = ~link_stat;
  1334. }
  1335. if (!(link_stat & PHY_ST_LINK)) {
  1336. sh_eth_rcv_snd_disable(ndev);
  1337. } else {
  1338. /* Link Up */
  1339. sh_eth_write(ndev, sh_eth_read(ndev, EESIPR) &
  1340. ~DMAC_M_ECI, EESIPR);
  1341. /* clear int */
  1342. sh_eth_write(ndev, sh_eth_read(ndev, ECSR),
  1343. ECSR);
  1344. sh_eth_write(ndev, sh_eth_read(ndev, EESIPR) |
  1345. DMAC_M_ECI, EESIPR);
  1346. /* enable tx and rx */
  1347. sh_eth_rcv_snd_enable(ndev);
  1348. }
  1349. }
  1350. }
  1351. ignore_link:
  1352. if (intr_status & EESR_TWB) {
  1353. /* Unused write back interrupt */
  1354. if (intr_status & EESR_TABT) { /* Transmit Abort int */
  1355. ndev->stats.tx_aborted_errors++;
  1356. netif_err(mdp, tx_err, ndev, "Transmit Abort\n");
  1357. }
  1358. }
  1359. if (intr_status & EESR_RABT) {
  1360. /* Receive Abort int */
  1361. if (intr_status & EESR_RFRMER) {
  1362. /* Receive Frame Overflow int */
  1363. ndev->stats.rx_frame_errors++;
  1364. netif_err(mdp, rx_err, ndev, "Receive Abort\n");
  1365. }
  1366. }
  1367. if (intr_status & EESR_TDE) {
  1368. /* Transmit Descriptor Empty int */
  1369. ndev->stats.tx_fifo_errors++;
  1370. netif_err(mdp, tx_err, ndev, "Transmit Descriptor Empty\n");
  1371. }
  1372. if (intr_status & EESR_TFE) {
  1373. /* FIFO under flow */
  1374. ndev->stats.tx_fifo_errors++;
  1375. netif_err(mdp, tx_err, ndev, "Transmit FIFO Under flow\n");
  1376. }
  1377. if (intr_status & EESR_RDE) {
  1378. /* Receive Descriptor Empty int */
  1379. ndev->stats.rx_over_errors++;
  1380. netif_err(mdp, rx_err, ndev, "Receive Descriptor Empty\n");
  1381. }
  1382. if (intr_status & EESR_RFE) {
  1383. /* Receive FIFO Overflow int */
  1384. ndev->stats.rx_fifo_errors++;
  1385. netif_err(mdp, rx_err, ndev, "Receive FIFO Overflow\n");
  1386. }
  1387. if (!mdp->cd->no_ade && (intr_status & EESR_ADE)) {
  1388. /* Address Error */
  1389. ndev->stats.tx_fifo_errors++;
  1390. netif_err(mdp, tx_err, ndev, "Address Error\n");
  1391. }
  1392. mask = EESR_TWB | EESR_TABT | EESR_ADE | EESR_TDE | EESR_TFE;
  1393. if (mdp->cd->no_ade)
  1394. mask &= ~EESR_ADE;
  1395. if (intr_status & mask) {
  1396. /* Tx error */
  1397. u32 edtrr = sh_eth_read(ndev, EDTRR);
  1398. /* dmesg */
  1399. netdev_err(ndev, "TX error. status=%8.8x cur_tx=%8.8x dirty_tx=%8.8x state=%8.8x EDTRR=%8.8x.\n",
  1400. intr_status, mdp->cur_tx, mdp->dirty_tx,
  1401. (u32)ndev->state, edtrr);
  1402. /* dirty buffer free */
  1403. sh_eth_txfree(ndev);
  1404. /* SH7712 BUG */
  1405. if (edtrr ^ sh_eth_get_edtrr_trns(mdp)) {
  1406. /* tx dma start */
  1407. sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR);
  1408. }
  1409. /* wakeup */
  1410. netif_wake_queue(ndev);
  1411. }
  1412. }
  1413. static irqreturn_t sh_eth_interrupt(int irq, void *netdev)
  1414. {
  1415. struct net_device *ndev = netdev;
  1416. struct sh_eth_private *mdp = netdev_priv(ndev);
  1417. struct sh_eth_cpu_data *cd = mdp->cd;
  1418. irqreturn_t ret = IRQ_NONE;
  1419. u32 intr_status, intr_enable;
  1420. spin_lock(&mdp->lock);
  1421. /* Get interrupt status */
  1422. intr_status = sh_eth_read(ndev, EESR);
  1423. /* Mask it with the interrupt mask, forcing ECI interrupt to be always
  1424. * enabled since it's the one that comes thru regardless of the mask,
  1425. * and we need to fully handle it in sh_eth_error() in order to quench
  1426. * it as it doesn't get cleared by just writing 1 to the ECI bit...
  1427. */
  1428. intr_enable = sh_eth_read(ndev, EESIPR);
  1429. intr_status &= intr_enable | DMAC_M_ECI;
  1430. if (intr_status & (EESR_RX_CHECK | cd->tx_check | cd->eesr_err_check))
  1431. ret = IRQ_HANDLED;
  1432. else
  1433. goto other_irq;
  1434. if (intr_status & EESR_RX_CHECK) {
  1435. if (napi_schedule_prep(&mdp->napi)) {
  1436. /* Mask Rx interrupts */
  1437. sh_eth_write(ndev, intr_enable & ~EESR_RX_CHECK,
  1438. EESIPR);
  1439. __napi_schedule(&mdp->napi);
  1440. } else {
  1441. netdev_warn(ndev,
  1442. "ignoring interrupt, status 0x%08x, mask 0x%08x.\n",
  1443. intr_status, intr_enable);
  1444. }
  1445. }
  1446. /* Tx Check */
  1447. if (intr_status & cd->tx_check) {
  1448. /* Clear Tx interrupts */
  1449. sh_eth_write(ndev, intr_status & cd->tx_check, EESR);
  1450. sh_eth_txfree(ndev);
  1451. netif_wake_queue(ndev);
  1452. }
  1453. if (intr_status & cd->eesr_err_check) {
  1454. /* Clear error interrupts */
  1455. sh_eth_write(ndev, intr_status & cd->eesr_err_check, EESR);
  1456. sh_eth_error(ndev, intr_status);
  1457. }
  1458. other_irq:
  1459. spin_unlock(&mdp->lock);
  1460. return ret;
  1461. }
  1462. static int sh_eth_poll(struct napi_struct *napi, int budget)
  1463. {
  1464. struct sh_eth_private *mdp = container_of(napi, struct sh_eth_private,
  1465. napi);
  1466. struct net_device *ndev = napi->dev;
  1467. int quota = budget;
  1468. u32 intr_status;
  1469. for (;;) {
  1470. intr_status = sh_eth_read(ndev, EESR);
  1471. if (!(intr_status & EESR_RX_CHECK))
  1472. break;
  1473. /* Clear Rx interrupts */
  1474. sh_eth_write(ndev, intr_status & EESR_RX_CHECK, EESR);
  1475. if (sh_eth_rx(ndev, intr_status, &quota))
  1476. goto out;
  1477. }
  1478. napi_complete(napi);
  1479. /* Reenable Rx interrupts */
  1480. sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
  1481. out:
  1482. return budget - quota;
  1483. }
  1484. /* PHY state control function */
  1485. static void sh_eth_adjust_link(struct net_device *ndev)
  1486. {
  1487. struct sh_eth_private *mdp = netdev_priv(ndev);
  1488. struct phy_device *phydev = mdp->phydev;
  1489. int new_state = 0;
  1490. if (phydev->link) {
  1491. if (phydev->duplex != mdp->duplex) {
  1492. new_state = 1;
  1493. mdp->duplex = phydev->duplex;
  1494. if (mdp->cd->set_duplex)
  1495. mdp->cd->set_duplex(ndev);
  1496. }
  1497. if (phydev->speed != mdp->speed) {
  1498. new_state = 1;
  1499. mdp->speed = phydev->speed;
  1500. if (mdp->cd->set_rate)
  1501. mdp->cd->set_rate(ndev);
  1502. }
  1503. if (!mdp->link) {
  1504. sh_eth_write(ndev,
  1505. sh_eth_read(ndev, ECMR) & ~ECMR_TXF,
  1506. ECMR);
  1507. new_state = 1;
  1508. mdp->link = phydev->link;
  1509. if (mdp->cd->no_psr || mdp->no_ether_link)
  1510. sh_eth_rcv_snd_enable(ndev);
  1511. }
  1512. } else if (mdp->link) {
  1513. new_state = 1;
  1514. mdp->link = 0;
  1515. mdp->speed = 0;
  1516. mdp->duplex = -1;
  1517. if (mdp->cd->no_psr || mdp->no_ether_link)
  1518. sh_eth_rcv_snd_disable(ndev);
  1519. }
  1520. if (new_state && netif_msg_link(mdp))
  1521. phy_print_status(phydev);
  1522. }
  1523. /* PHY init function */
  1524. static int sh_eth_phy_init(struct net_device *ndev)
  1525. {
  1526. struct device_node *np = ndev->dev.parent->of_node;
  1527. struct sh_eth_private *mdp = netdev_priv(ndev);
  1528. struct phy_device *phydev = NULL;
  1529. mdp->link = 0;
  1530. mdp->speed = 0;
  1531. mdp->duplex = -1;
  1532. /* Try connect to PHY */
  1533. if (np) {
  1534. struct device_node *pn;
  1535. pn = of_parse_phandle(np, "phy-handle", 0);
  1536. phydev = of_phy_connect(ndev, pn,
  1537. sh_eth_adjust_link, 0,
  1538. mdp->phy_interface);
  1539. if (!phydev)
  1540. phydev = ERR_PTR(-ENOENT);
  1541. } else {
  1542. char phy_id[MII_BUS_ID_SIZE + 3];
  1543. snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT,
  1544. mdp->mii_bus->id, mdp->phy_id);
  1545. phydev = phy_connect(ndev, phy_id, sh_eth_adjust_link,
  1546. mdp->phy_interface);
  1547. }
  1548. if (IS_ERR(phydev)) {
  1549. netdev_err(ndev, "failed to connect PHY\n");
  1550. return PTR_ERR(phydev);
  1551. }
  1552. netdev_info(ndev, "attached PHY %d (IRQ %d) to driver %s\n",
  1553. phydev->addr, phydev->irq, phydev->drv->name);
  1554. mdp->phydev = phydev;
  1555. return 0;
  1556. }
  1557. /* PHY control start function */
  1558. static int sh_eth_phy_start(struct net_device *ndev)
  1559. {
  1560. struct sh_eth_private *mdp = netdev_priv(ndev);
  1561. int ret;
  1562. ret = sh_eth_phy_init(ndev);
  1563. if (ret)
  1564. return ret;
  1565. phy_start(mdp->phydev);
  1566. return 0;
  1567. }
  1568. static int sh_eth_get_settings(struct net_device *ndev,
  1569. struct ethtool_cmd *ecmd)
  1570. {
  1571. struct sh_eth_private *mdp = netdev_priv(ndev);
  1572. unsigned long flags;
  1573. int ret;
  1574. spin_lock_irqsave(&mdp->lock, flags);
  1575. ret = phy_ethtool_gset(mdp->phydev, ecmd);
  1576. spin_unlock_irqrestore(&mdp->lock, flags);
  1577. return ret;
  1578. }
  1579. static int sh_eth_set_settings(struct net_device *ndev,
  1580. struct ethtool_cmd *ecmd)
  1581. {
  1582. struct sh_eth_private *mdp = netdev_priv(ndev);
  1583. unsigned long flags;
  1584. int ret;
  1585. spin_lock_irqsave(&mdp->lock, flags);
  1586. /* disable tx and rx */
  1587. sh_eth_rcv_snd_disable(ndev);
  1588. ret = phy_ethtool_sset(mdp->phydev, ecmd);
  1589. if (ret)
  1590. goto error_exit;
  1591. if (ecmd->duplex == DUPLEX_FULL)
  1592. mdp->duplex = 1;
  1593. else
  1594. mdp->duplex = 0;
  1595. if (mdp->cd->set_duplex)
  1596. mdp->cd->set_duplex(ndev);
  1597. error_exit:
  1598. mdelay(1);
  1599. /* enable tx and rx */
  1600. sh_eth_rcv_snd_enable(ndev);
  1601. spin_unlock_irqrestore(&mdp->lock, flags);
  1602. return ret;
  1603. }
  1604. static int sh_eth_nway_reset(struct net_device *ndev)
  1605. {
  1606. struct sh_eth_private *mdp = netdev_priv(ndev);
  1607. unsigned long flags;
  1608. int ret;
  1609. spin_lock_irqsave(&mdp->lock, flags);
  1610. ret = phy_start_aneg(mdp->phydev);
  1611. spin_unlock_irqrestore(&mdp->lock, flags);
  1612. return ret;
  1613. }
  1614. static u32 sh_eth_get_msglevel(struct net_device *ndev)
  1615. {
  1616. struct sh_eth_private *mdp = netdev_priv(ndev);
  1617. return mdp->msg_enable;
  1618. }
  1619. static void sh_eth_set_msglevel(struct net_device *ndev, u32 value)
  1620. {
  1621. struct sh_eth_private *mdp = netdev_priv(ndev);
  1622. mdp->msg_enable = value;
  1623. }
  1624. static const char sh_eth_gstrings_stats[][ETH_GSTRING_LEN] = {
  1625. "rx_current", "tx_current",
  1626. "rx_dirty", "tx_dirty",
  1627. };
  1628. #define SH_ETH_STATS_LEN ARRAY_SIZE(sh_eth_gstrings_stats)
  1629. static int sh_eth_get_sset_count(struct net_device *netdev, int sset)
  1630. {
  1631. switch (sset) {
  1632. case ETH_SS_STATS:
  1633. return SH_ETH_STATS_LEN;
  1634. default:
  1635. return -EOPNOTSUPP;
  1636. }
  1637. }
  1638. static void sh_eth_get_ethtool_stats(struct net_device *ndev,
  1639. struct ethtool_stats *stats, u64 *data)
  1640. {
  1641. struct sh_eth_private *mdp = netdev_priv(ndev);
  1642. int i = 0;
  1643. /* device-specific stats */
  1644. data[i++] = mdp->cur_rx;
  1645. data[i++] = mdp->cur_tx;
  1646. data[i++] = mdp->dirty_rx;
  1647. data[i++] = mdp->dirty_tx;
  1648. }
  1649. static void sh_eth_get_strings(struct net_device *ndev, u32 stringset, u8 *data)
  1650. {
  1651. switch (stringset) {
  1652. case ETH_SS_STATS:
  1653. memcpy(data, *sh_eth_gstrings_stats,
  1654. sizeof(sh_eth_gstrings_stats));
  1655. break;
  1656. }
  1657. }
  1658. static void sh_eth_get_ringparam(struct net_device *ndev,
  1659. struct ethtool_ringparam *ring)
  1660. {
  1661. struct sh_eth_private *mdp = netdev_priv(ndev);
  1662. ring->rx_max_pending = RX_RING_MAX;
  1663. ring->tx_max_pending = TX_RING_MAX;
  1664. ring->rx_pending = mdp->num_rx_ring;
  1665. ring->tx_pending = mdp->num_tx_ring;
  1666. }
  1667. static int sh_eth_set_ringparam(struct net_device *ndev,
  1668. struct ethtool_ringparam *ring)
  1669. {
  1670. struct sh_eth_private *mdp = netdev_priv(ndev);
  1671. int ret;
  1672. if (ring->tx_pending > TX_RING_MAX ||
  1673. ring->rx_pending > RX_RING_MAX ||
  1674. ring->tx_pending < TX_RING_MIN ||
  1675. ring->rx_pending < RX_RING_MIN)
  1676. return -EINVAL;
  1677. if (ring->rx_mini_pending || ring->rx_jumbo_pending)
  1678. return -EINVAL;
  1679. if (netif_running(ndev)) {
  1680. netif_tx_disable(ndev);
  1681. /* Disable interrupts by clearing the interrupt mask. */
  1682. sh_eth_write(ndev, 0x0000, EESIPR);
  1683. /* Stop the chip's Tx and Rx processes. */
  1684. sh_eth_write(ndev, 0, EDTRR);
  1685. sh_eth_write(ndev, 0, EDRRR);
  1686. synchronize_irq(ndev->irq);
  1687. }
  1688. /* Free all the skbuffs in the Rx queue. */
  1689. sh_eth_ring_free(ndev);
  1690. /* Free DMA buffer */
  1691. sh_eth_free_dma_buffer(mdp);
  1692. /* Set new parameters */
  1693. mdp->num_rx_ring = ring->rx_pending;
  1694. mdp->num_tx_ring = ring->tx_pending;
  1695. ret = sh_eth_ring_init(ndev);
  1696. if (ret < 0) {
  1697. netdev_err(ndev, "%s: sh_eth_ring_init failed.\n", __func__);
  1698. return ret;
  1699. }
  1700. ret = sh_eth_dev_init(ndev, false);
  1701. if (ret < 0) {
  1702. netdev_err(ndev, "%s: sh_eth_dev_init failed.\n", __func__);
  1703. return ret;
  1704. }
  1705. if (netif_running(ndev)) {
  1706. sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
  1707. /* Setting the Rx mode will start the Rx process. */
  1708. sh_eth_write(ndev, EDRRR_R, EDRRR);
  1709. netif_wake_queue(ndev);
  1710. }
  1711. return 0;
  1712. }
  1713. static const struct ethtool_ops sh_eth_ethtool_ops = {
  1714. .get_settings = sh_eth_get_settings,
  1715. .set_settings = sh_eth_set_settings,
  1716. .nway_reset = sh_eth_nway_reset,
  1717. .get_msglevel = sh_eth_get_msglevel,
  1718. .set_msglevel = sh_eth_set_msglevel,
  1719. .get_link = ethtool_op_get_link,
  1720. .get_strings = sh_eth_get_strings,
  1721. .get_ethtool_stats = sh_eth_get_ethtool_stats,
  1722. .get_sset_count = sh_eth_get_sset_count,
  1723. .get_ringparam = sh_eth_get_ringparam,
  1724. .set_ringparam = sh_eth_set_ringparam,
  1725. };
  1726. /* network device open function */
  1727. static int sh_eth_open(struct net_device *ndev)
  1728. {
  1729. int ret = 0;
  1730. struct sh_eth_private *mdp = netdev_priv(ndev);
  1731. pm_runtime_get_sync(&mdp->pdev->dev);
  1732. napi_enable(&mdp->napi);
  1733. ret = request_irq(ndev->irq, sh_eth_interrupt,
  1734. mdp->cd->irq_flags, ndev->name, ndev);
  1735. if (ret) {
  1736. netdev_err(ndev, "Can not assign IRQ number\n");
  1737. goto out_napi_off;
  1738. }
  1739. /* Descriptor set */
  1740. ret = sh_eth_ring_init(ndev);
  1741. if (ret)
  1742. goto out_free_irq;
  1743. /* device init */
  1744. ret = sh_eth_dev_init(ndev, true);
  1745. if (ret)
  1746. goto out_free_irq;
  1747. /* PHY control start*/
  1748. ret = sh_eth_phy_start(ndev);
  1749. if (ret)
  1750. goto out_free_irq;
  1751. mdp->is_opened = 1;
  1752. return ret;
  1753. out_free_irq:
  1754. free_irq(ndev->irq, ndev);
  1755. out_napi_off:
  1756. napi_disable(&mdp->napi);
  1757. pm_runtime_put_sync(&mdp->pdev->dev);
  1758. return ret;
  1759. }
  1760. /* Timeout function */
  1761. static void sh_eth_tx_timeout(struct net_device *ndev)
  1762. {
  1763. struct sh_eth_private *mdp = netdev_priv(ndev);
  1764. struct sh_eth_rxdesc *rxdesc;
  1765. int i;
  1766. netif_stop_queue(ndev);
  1767. netif_err(mdp, timer, ndev,
  1768. "transmit timed out, status %8.8x, resetting...\n",
  1769. sh_eth_read(ndev, EESR));
  1770. /* tx_errors count up */
  1771. ndev->stats.tx_errors++;
  1772. /* Free all the skbuffs in the Rx queue. */
  1773. for (i = 0; i < mdp->num_rx_ring; i++) {
  1774. rxdesc = &mdp->rx_ring[i];
  1775. rxdesc->status = 0;
  1776. rxdesc->addr = 0xBADF00D0;
  1777. dev_kfree_skb(mdp->rx_skbuff[i]);
  1778. mdp->rx_skbuff[i] = NULL;
  1779. }
  1780. for (i = 0; i < mdp->num_tx_ring; i++) {
  1781. dev_kfree_skb(mdp->tx_skbuff[i]);
  1782. mdp->tx_skbuff[i] = NULL;
  1783. }
  1784. /* device init */
  1785. sh_eth_dev_init(ndev, true);
  1786. }
  1787. /* Packet transmit function */
  1788. static int sh_eth_start_xmit(struct sk_buff *skb, struct net_device *ndev)
  1789. {
  1790. struct sh_eth_private *mdp = netdev_priv(ndev);
  1791. struct sh_eth_txdesc *txdesc;
  1792. u32 entry;
  1793. unsigned long flags;
  1794. spin_lock_irqsave(&mdp->lock, flags);
  1795. if ((mdp->cur_tx - mdp->dirty_tx) >= (mdp->num_tx_ring - 4)) {
  1796. if (!sh_eth_txfree(ndev)) {
  1797. netif_warn(mdp, tx_queued, ndev, "TxFD exhausted.\n");
  1798. netif_stop_queue(ndev);
  1799. spin_unlock_irqrestore(&mdp->lock, flags);
  1800. return NETDEV_TX_BUSY;
  1801. }
  1802. }
  1803. spin_unlock_irqrestore(&mdp->lock, flags);
  1804. entry = mdp->cur_tx % mdp->num_tx_ring;
  1805. mdp->tx_skbuff[entry] = skb;
  1806. txdesc = &mdp->tx_ring[entry];
  1807. /* soft swap. */
  1808. if (!mdp->cd->hw_swap)
  1809. sh_eth_soft_swap(phys_to_virt(ALIGN(txdesc->addr, 4)),
  1810. skb->len + 2);
  1811. txdesc->addr = dma_map_single(&ndev->dev, skb->data, skb->len,
  1812. DMA_TO_DEVICE);
  1813. if (skb->len < ETH_ZLEN)
  1814. txdesc->buffer_length = ETH_ZLEN;
  1815. else
  1816. txdesc->buffer_length = skb->len;
  1817. if (entry >= mdp->num_tx_ring - 1)
  1818. txdesc->status |= cpu_to_edmac(mdp, TD_TACT | TD_TDLE);
  1819. else
  1820. txdesc->status |= cpu_to_edmac(mdp, TD_TACT);
  1821. mdp->cur_tx++;
  1822. if (!(sh_eth_read(ndev, EDTRR) & sh_eth_get_edtrr_trns(mdp)))
  1823. sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR);
  1824. return NETDEV_TX_OK;
  1825. }
  1826. static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev)
  1827. {
  1828. struct sh_eth_private *mdp = netdev_priv(ndev);
  1829. if (sh_eth_is_rz_fast_ether(mdp))
  1830. return &ndev->stats;
  1831. if (!mdp->is_opened)
  1832. return &ndev->stats;
  1833. ndev->stats.tx_dropped += sh_eth_read(ndev, TROCR);
  1834. sh_eth_write(ndev, 0, TROCR); /* (write clear) */
  1835. ndev->stats.collisions += sh_eth_read(ndev, CDCR);
  1836. sh_eth_write(ndev, 0, CDCR); /* (write clear) */
  1837. ndev->stats.tx_carrier_errors += sh_eth_read(ndev, LCCR);
  1838. sh_eth_write(ndev, 0, LCCR); /* (write clear) */
  1839. if (sh_eth_is_gether(mdp)) {
  1840. ndev->stats.tx_carrier_errors += sh_eth_read(ndev, CERCR);
  1841. sh_eth_write(ndev, 0, CERCR); /* (write clear) */
  1842. ndev->stats.tx_carrier_errors += sh_eth_read(ndev, CEECR);
  1843. sh_eth_write(ndev, 0, CEECR); /* (write clear) */
  1844. } else {
  1845. ndev->stats.tx_carrier_errors += sh_eth_read(ndev, CNDCR);
  1846. sh_eth_write(ndev, 0, CNDCR); /* (write clear) */
  1847. }
  1848. return &ndev->stats;
  1849. }
  1850. /* device close function */
  1851. static int sh_eth_close(struct net_device *ndev)
  1852. {
  1853. struct sh_eth_private *mdp = netdev_priv(ndev);
  1854. netif_stop_queue(ndev);
  1855. /* Disable interrupts by clearing the interrupt mask. */
  1856. sh_eth_write(ndev, 0x0000, EESIPR);
  1857. /* Stop the chip's Tx and Rx processes. */
  1858. sh_eth_write(ndev, 0, EDTRR);
  1859. sh_eth_write(ndev, 0, EDRRR);
  1860. sh_eth_get_stats(ndev);
  1861. /* PHY Disconnect */
  1862. if (mdp->phydev) {
  1863. phy_stop(mdp->phydev);
  1864. phy_disconnect(mdp->phydev);
  1865. }
  1866. free_irq(ndev->irq, ndev);
  1867. napi_disable(&mdp->napi);
  1868. /* Free all the skbuffs in the Rx queue. */
  1869. sh_eth_ring_free(ndev);
  1870. /* free DMA buffer */
  1871. sh_eth_free_dma_buffer(mdp);
  1872. pm_runtime_put_sync(&mdp->pdev->dev);
  1873. mdp->is_opened = 0;
  1874. return 0;
  1875. }
  1876. /* ioctl to device function */
  1877. static int sh_eth_do_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd)
  1878. {
  1879. struct sh_eth_private *mdp = netdev_priv(ndev);
  1880. struct phy_device *phydev = mdp->phydev;
  1881. if (!netif_running(ndev))
  1882. return -EINVAL;
  1883. if (!phydev)
  1884. return -ENODEV;
  1885. return phy_mii_ioctl(phydev, rq, cmd);
  1886. }
  1887. /* For TSU_POSTn. Please refer to the manual about this (strange) bitfields */
  1888. static void *sh_eth_tsu_get_post_reg_offset(struct sh_eth_private *mdp,
  1889. int entry)
  1890. {
  1891. return sh_eth_tsu_get_offset(mdp, TSU_POST1) + (entry / 8 * 4);
  1892. }
  1893. static u32 sh_eth_tsu_get_post_mask(int entry)
  1894. {
  1895. return 0x0f << (28 - ((entry % 8) * 4));
  1896. }
  1897. static u32 sh_eth_tsu_get_post_bit(struct sh_eth_private *mdp, int entry)
  1898. {
  1899. return (0x08 >> (mdp->port << 1)) << (28 - ((entry % 8) * 4));
  1900. }
  1901. static void sh_eth_tsu_enable_cam_entry_post(struct net_device *ndev,
  1902. int entry)
  1903. {
  1904. struct sh_eth_private *mdp = netdev_priv(ndev);
  1905. u32 tmp;
  1906. void *reg_offset;
  1907. reg_offset = sh_eth_tsu_get_post_reg_offset(mdp, entry);
  1908. tmp = ioread32(reg_offset);
  1909. iowrite32(tmp | sh_eth_tsu_get_post_bit(mdp, entry), reg_offset);
  1910. }
  1911. static bool sh_eth_tsu_disable_cam_entry_post(struct net_device *ndev,
  1912. int entry)
  1913. {
  1914. struct sh_eth_private *mdp = netdev_priv(ndev);
  1915. u32 post_mask, ref_mask, tmp;
  1916. void *reg_offset;
  1917. reg_offset = sh_eth_tsu_get_post_reg_offset(mdp, entry);
  1918. post_mask = sh_eth_tsu_get_post_mask(entry);
  1919. ref_mask = sh_eth_tsu_get_post_bit(mdp, entry) & ~post_mask;
  1920. tmp = ioread32(reg_offset);
  1921. iowrite32(tmp & ~post_mask, reg_offset);
  1922. /* If other port enables, the function returns "true" */
  1923. return tmp & ref_mask;
  1924. }
  1925. static int sh_eth_tsu_busy(struct net_device *ndev)
  1926. {
  1927. int timeout = SH_ETH_TSU_TIMEOUT_MS * 100;
  1928. struct sh_eth_private *mdp = netdev_priv(ndev);
  1929. while ((sh_eth_tsu_read(mdp, TSU_ADSBSY) & TSU_ADSBSY_0)) {
  1930. udelay(10);
  1931. timeout--;
  1932. if (timeout <= 0) {
  1933. netdev_err(ndev, "%s: timeout\n", __func__);
  1934. return -ETIMEDOUT;
  1935. }
  1936. }
  1937. return 0;
  1938. }
  1939. static int sh_eth_tsu_write_entry(struct net_device *ndev, void *reg,
  1940. const u8 *addr)
  1941. {
  1942. u32 val;
  1943. val = addr[0] << 24 | addr[1] << 16 | addr[2] << 8 | addr[3];
  1944. iowrite32(val, reg);
  1945. if (sh_eth_tsu_busy(ndev) < 0)
  1946. return -EBUSY;
  1947. val = addr[4] << 8 | addr[5];
  1948. iowrite32(val, reg + 4);
  1949. if (sh_eth_tsu_busy(ndev) < 0)
  1950. return -EBUSY;
  1951. return 0;
  1952. }
  1953. static void sh_eth_tsu_read_entry(void *reg, u8 *addr)
  1954. {
  1955. u32 val;
  1956. val = ioread32(reg);
  1957. addr[0] = (val >> 24) & 0xff;
  1958. addr[1] = (val >> 16) & 0xff;
  1959. addr[2] = (val >> 8) & 0xff;
  1960. addr[3] = val & 0xff;
  1961. val = ioread32(reg + 4);
  1962. addr[4] = (val >> 8) & 0xff;
  1963. addr[5] = val & 0xff;
  1964. }
  1965. static int sh_eth_tsu_find_entry(struct net_device *ndev, const u8 *addr)
  1966. {
  1967. struct sh_eth_private *mdp = netdev_priv(ndev);
  1968. void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
  1969. int i;
  1970. u8 c_addr[ETH_ALEN];
  1971. for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) {
  1972. sh_eth_tsu_read_entry(reg_offset, c_addr);
  1973. if (ether_addr_equal(addr, c_addr))
  1974. return i;
  1975. }
  1976. return -ENOENT;
  1977. }
  1978. static int sh_eth_tsu_find_empty(struct net_device *ndev)
  1979. {
  1980. u8 blank[ETH_ALEN];
  1981. int entry;
  1982. memset(blank, 0, sizeof(blank));
  1983. entry = sh_eth_tsu_find_entry(ndev, blank);
  1984. return (entry < 0) ? -ENOMEM : entry;
  1985. }
  1986. static int sh_eth_tsu_disable_cam_entry_table(struct net_device *ndev,
  1987. int entry)
  1988. {
  1989. struct sh_eth_private *mdp = netdev_priv(ndev);
  1990. void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
  1991. int ret;
  1992. u8 blank[ETH_ALEN];
  1993. sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) &
  1994. ~(1 << (31 - entry)), TSU_TEN);
  1995. memset(blank, 0, sizeof(blank));
  1996. ret = sh_eth_tsu_write_entry(ndev, reg_offset + entry * 8, blank);
  1997. if (ret < 0)
  1998. return ret;
  1999. return 0;
  2000. }
  2001. static int sh_eth_tsu_add_entry(struct net_device *ndev, const u8 *addr)
  2002. {
  2003. struct sh_eth_private *mdp = netdev_priv(ndev);
  2004. void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
  2005. int i, ret;
  2006. if (!mdp->cd->tsu)
  2007. return 0;
  2008. i = sh_eth_tsu_find_entry(ndev, addr);
  2009. if (i < 0) {
  2010. /* No entry found, create one */
  2011. i = sh_eth_tsu_find_empty(ndev);
  2012. if (i < 0)
  2013. return -ENOMEM;
  2014. ret = sh_eth_tsu_write_entry(ndev, reg_offset + i * 8, addr);
  2015. if (ret < 0)
  2016. return ret;
  2017. /* Enable the entry */
  2018. sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) |
  2019. (1 << (31 - i)), TSU_TEN);
  2020. }
  2021. /* Entry found or created, enable POST */
  2022. sh_eth_tsu_enable_cam_entry_post(ndev, i);
  2023. return 0;
  2024. }
  2025. static int sh_eth_tsu_del_entry(struct net_device *ndev, const u8 *addr)
  2026. {
  2027. struct sh_eth_private *mdp = netdev_priv(ndev);
  2028. int i, ret;
  2029. if (!mdp->cd->tsu)
  2030. return 0;
  2031. i = sh_eth_tsu_find_entry(ndev, addr);
  2032. if (i) {
  2033. /* Entry found */
  2034. if (sh_eth_tsu_disable_cam_entry_post(ndev, i))
  2035. goto done;
  2036. /* Disable the entry if both ports was disabled */
  2037. ret = sh_eth_tsu_disable_cam_entry_table(ndev, i);
  2038. if (ret < 0)
  2039. return ret;
  2040. }
  2041. done:
  2042. return 0;
  2043. }
  2044. static int sh_eth_tsu_purge_all(struct net_device *ndev)
  2045. {
  2046. struct sh_eth_private *mdp = netdev_priv(ndev);
  2047. int i, ret;
  2048. if (unlikely(!mdp->cd->tsu))
  2049. return 0;
  2050. for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++) {
  2051. if (sh_eth_tsu_disable_cam_entry_post(ndev, i))
  2052. continue;
  2053. /* Disable the entry if both ports was disabled */
  2054. ret = sh_eth_tsu_disable_cam_entry_table(ndev, i);
  2055. if (ret < 0)
  2056. return ret;
  2057. }
  2058. return 0;
  2059. }
  2060. static void sh_eth_tsu_purge_mcast(struct net_device *ndev)
  2061. {
  2062. struct sh_eth_private *mdp = netdev_priv(ndev);
  2063. u8 addr[ETH_ALEN];
  2064. void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
  2065. int i;
  2066. if (unlikely(!mdp->cd->tsu))
  2067. return;
  2068. for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) {
  2069. sh_eth_tsu_read_entry(reg_offset, addr);
  2070. if (is_multicast_ether_addr(addr))
  2071. sh_eth_tsu_del_entry(ndev, addr);
  2072. }
  2073. }
  2074. /* Multicast reception directions set */
  2075. static void sh_eth_set_multicast_list(struct net_device *ndev)
  2076. {
  2077. struct sh_eth_private *mdp = netdev_priv(ndev);
  2078. u32 ecmr_bits;
  2079. int mcast_all = 0;
  2080. unsigned long flags;
  2081. spin_lock_irqsave(&mdp->lock, flags);
  2082. /* Initial condition is MCT = 1, PRM = 0.
  2083. * Depending on ndev->flags, set PRM or clear MCT
  2084. */
  2085. ecmr_bits = (sh_eth_read(ndev, ECMR) & ~ECMR_PRM) | ECMR_MCT;
  2086. if (!(ndev->flags & IFF_MULTICAST)) {
  2087. sh_eth_tsu_purge_mcast(ndev);
  2088. mcast_all = 1;
  2089. }
  2090. if (ndev->flags & IFF_ALLMULTI) {
  2091. sh_eth_tsu_purge_mcast(ndev);
  2092. ecmr_bits &= ~ECMR_MCT;
  2093. mcast_all = 1;
  2094. }
  2095. if (ndev->flags & IFF_PROMISC) {
  2096. sh_eth_tsu_purge_all(ndev);
  2097. ecmr_bits = (ecmr_bits & ~ECMR_MCT) | ECMR_PRM;
  2098. } else if (mdp->cd->tsu) {
  2099. struct netdev_hw_addr *ha;
  2100. netdev_for_each_mc_addr(ha, ndev) {
  2101. if (mcast_all && is_multicast_ether_addr(ha->addr))
  2102. continue;
  2103. if (sh_eth_tsu_add_entry(ndev, ha->addr) < 0) {
  2104. if (!mcast_all) {
  2105. sh_eth_tsu_purge_mcast(ndev);
  2106. ecmr_bits &= ~ECMR_MCT;
  2107. mcast_all = 1;
  2108. }
  2109. }
  2110. }
  2111. } else {
  2112. /* Normal, unicast/broadcast-only mode. */
  2113. ecmr_bits = (ecmr_bits & ~ECMR_PRM) | ECMR_MCT;
  2114. }
  2115. /* update the ethernet mode */
  2116. sh_eth_write(ndev, ecmr_bits, ECMR);
  2117. spin_unlock_irqrestore(&mdp->lock, flags);
  2118. }
  2119. static int sh_eth_get_vtag_index(struct sh_eth_private *mdp)
  2120. {
  2121. if (!mdp->port)
  2122. return TSU_VTAG0;
  2123. else
  2124. return TSU_VTAG1;
  2125. }
  2126. static int sh_eth_vlan_rx_add_vid(struct net_device *ndev,
  2127. __be16 proto, u16 vid)
  2128. {
  2129. struct sh_eth_private *mdp = netdev_priv(ndev);
  2130. int vtag_reg_index = sh_eth_get_vtag_index(mdp);
  2131. if (unlikely(!mdp->cd->tsu))
  2132. return -EPERM;
  2133. /* No filtering if vid = 0 */
  2134. if (!vid)
  2135. return 0;
  2136. mdp->vlan_num_ids++;
  2137. /* The controller has one VLAN tag HW filter. So, if the filter is
  2138. * already enabled, the driver disables it and the filte
  2139. */
  2140. if (mdp->vlan_num_ids > 1) {
  2141. /* disable VLAN filter */
  2142. sh_eth_tsu_write(mdp, 0, vtag_reg_index);
  2143. return 0;
  2144. }
  2145. sh_eth_tsu_write(mdp, TSU_VTAG_ENABLE | (vid & TSU_VTAG_VID_MASK),
  2146. vtag_reg_index);
  2147. return 0;
  2148. }
  2149. static int sh_eth_vlan_rx_kill_vid(struct net_device *ndev,
  2150. __be16 proto, u16 vid)
  2151. {
  2152. struct sh_eth_private *mdp = netdev_priv(ndev);
  2153. int vtag_reg_index = sh_eth_get_vtag_index(mdp);
  2154. if (unlikely(!mdp->cd->tsu))
  2155. return -EPERM;
  2156. /* No filtering if vid = 0 */
  2157. if (!vid)
  2158. return 0;
  2159. mdp->vlan_num_ids--;
  2160. sh_eth_tsu_write(mdp, 0, vtag_reg_index);
  2161. return 0;
  2162. }
  2163. /* SuperH's TSU register init function */
  2164. static void sh_eth_tsu_init(struct sh_eth_private *mdp)
  2165. {
  2166. if (sh_eth_is_rz_fast_ether(mdp)) {
  2167. sh_eth_tsu_write(mdp, 0, TSU_TEN); /* Disable all CAM entry */
  2168. return;
  2169. }
  2170. sh_eth_tsu_write(mdp, 0, TSU_FWEN0); /* Disable forward(0->1) */
  2171. sh_eth_tsu_write(mdp, 0, TSU_FWEN1); /* Disable forward(1->0) */
  2172. sh_eth_tsu_write(mdp, 0, TSU_FCM); /* forward fifo 3k-3k */
  2173. sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL0);
  2174. sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL1);
  2175. sh_eth_tsu_write(mdp, 0, TSU_PRISL0);
  2176. sh_eth_tsu_write(mdp, 0, TSU_PRISL1);
  2177. sh_eth_tsu_write(mdp, 0, TSU_FWSL0);
  2178. sh_eth_tsu_write(mdp, 0, TSU_FWSL1);
  2179. sh_eth_tsu_write(mdp, TSU_FWSLC_POSTENU | TSU_FWSLC_POSTENL, TSU_FWSLC);
  2180. if (sh_eth_is_gether(mdp)) {
  2181. sh_eth_tsu_write(mdp, 0, TSU_QTAG0); /* Disable QTAG(0->1) */
  2182. sh_eth_tsu_write(mdp, 0, TSU_QTAG1); /* Disable QTAG(1->0) */
  2183. } else {
  2184. sh_eth_tsu_write(mdp, 0, TSU_QTAGM0); /* Disable QTAG(0->1) */
  2185. sh_eth_tsu_write(mdp, 0, TSU_QTAGM1); /* Disable QTAG(1->0) */
  2186. }
  2187. sh_eth_tsu_write(mdp, 0, TSU_FWSR); /* all interrupt status clear */
  2188. sh_eth_tsu_write(mdp, 0, TSU_FWINMK); /* Disable all interrupt */
  2189. sh_eth_tsu_write(mdp, 0, TSU_TEN); /* Disable all CAM entry */
  2190. sh_eth_tsu_write(mdp, 0, TSU_POST1); /* Disable CAM entry [ 0- 7] */
  2191. sh_eth_tsu_write(mdp, 0, TSU_POST2); /* Disable CAM entry [ 8-15] */
  2192. sh_eth_tsu_write(mdp, 0, TSU_POST3); /* Disable CAM entry [16-23] */
  2193. sh_eth_tsu_write(mdp, 0, TSU_POST4); /* Disable CAM entry [24-31] */
  2194. }
  2195. /* MDIO bus release function */
  2196. static int sh_mdio_release(struct sh_eth_private *mdp)
  2197. {
  2198. /* unregister mdio bus */
  2199. mdiobus_unregister(mdp->mii_bus);
  2200. /* free bitbang info */
  2201. free_mdio_bitbang(mdp->mii_bus);
  2202. return 0;
  2203. }
  2204. /* MDIO bus init function */
  2205. static int sh_mdio_init(struct sh_eth_private *mdp,
  2206. struct sh_eth_plat_data *pd)
  2207. {
  2208. int ret, i;
  2209. struct bb_info *bitbang;
  2210. struct platform_device *pdev = mdp->pdev;
  2211. struct device *dev = &mdp->pdev->dev;
  2212. /* create bit control struct for PHY */
  2213. bitbang = devm_kzalloc(dev, sizeof(struct bb_info), GFP_KERNEL);
  2214. if (!bitbang)
  2215. return -ENOMEM;
  2216. /* bitbang init */
  2217. bitbang->addr = mdp->addr + mdp->reg_offset[PIR];
  2218. bitbang->set_gate = pd->set_mdio_gate;
  2219. bitbang->mdi_msk = PIR_MDI;
  2220. bitbang->mdo_msk = PIR_MDO;
  2221. bitbang->mmd_msk = PIR_MMD;
  2222. bitbang->mdc_msk = PIR_MDC;
  2223. bitbang->ctrl.ops = &bb_ops;
  2224. /* MII controller setting */
  2225. mdp->mii_bus = alloc_mdio_bitbang(&bitbang->ctrl);
  2226. if (!mdp->mii_bus)
  2227. return -ENOMEM;
  2228. /* Hook up MII support for ethtool */
  2229. mdp->mii_bus->name = "sh_mii";
  2230. mdp->mii_bus->parent = dev;
  2231. snprintf(mdp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
  2232. pdev->name, pdev->id);
  2233. /* PHY IRQ */
  2234. mdp->mii_bus->irq = devm_kmalloc_array(dev, PHY_MAX_ADDR, sizeof(int),
  2235. GFP_KERNEL);
  2236. if (!mdp->mii_bus->irq) {
  2237. ret = -ENOMEM;
  2238. goto out_free_bus;
  2239. }
  2240. /* register MDIO bus */
  2241. if (dev->of_node) {
  2242. ret = of_mdiobus_register(mdp->mii_bus, dev->of_node);
  2243. } else {
  2244. for (i = 0; i < PHY_MAX_ADDR; i++)
  2245. mdp->mii_bus->irq[i] = PHY_POLL;
  2246. if (pd->phy_irq > 0)
  2247. mdp->mii_bus->irq[pd->phy] = pd->phy_irq;
  2248. ret = mdiobus_register(mdp->mii_bus);
  2249. }
  2250. if (ret)
  2251. goto out_free_bus;
  2252. return 0;
  2253. out_free_bus:
  2254. free_mdio_bitbang(mdp->mii_bus);
  2255. return ret;
  2256. }
  2257. static const u16 *sh_eth_get_register_offset(int register_type)
  2258. {
  2259. const u16 *reg_offset = NULL;
  2260. switch (register_type) {
  2261. case SH_ETH_REG_GIGABIT:
  2262. reg_offset = sh_eth_offset_gigabit;
  2263. break;
  2264. case SH_ETH_REG_FAST_RZ:
  2265. reg_offset = sh_eth_offset_fast_rz;
  2266. break;
  2267. case SH_ETH_REG_FAST_RCAR:
  2268. reg_offset = sh_eth_offset_fast_rcar;
  2269. break;
  2270. case SH_ETH_REG_FAST_SH4:
  2271. reg_offset = sh_eth_offset_fast_sh4;
  2272. break;
  2273. case SH_ETH_REG_FAST_SH3_SH2:
  2274. reg_offset = sh_eth_offset_fast_sh3_sh2;
  2275. break;
  2276. default:
  2277. break;
  2278. }
  2279. return reg_offset;
  2280. }
  2281. static const struct net_device_ops sh_eth_netdev_ops = {
  2282. .ndo_open = sh_eth_open,
  2283. .ndo_stop = sh_eth_close,
  2284. .ndo_start_xmit = sh_eth_start_xmit,
  2285. .ndo_get_stats = sh_eth_get_stats,
  2286. .ndo_tx_timeout = sh_eth_tx_timeout,
  2287. .ndo_do_ioctl = sh_eth_do_ioctl,
  2288. .ndo_validate_addr = eth_validate_addr,
  2289. .ndo_set_mac_address = eth_mac_addr,
  2290. .ndo_change_mtu = eth_change_mtu,
  2291. };
  2292. static const struct net_device_ops sh_eth_netdev_ops_tsu = {
  2293. .ndo_open = sh_eth_open,
  2294. .ndo_stop = sh_eth_close,
  2295. .ndo_start_xmit = sh_eth_start_xmit,
  2296. .ndo_get_stats = sh_eth_get_stats,
  2297. .ndo_set_rx_mode = sh_eth_set_multicast_list,
  2298. .ndo_vlan_rx_add_vid = sh_eth_vlan_rx_add_vid,
  2299. .ndo_vlan_rx_kill_vid = sh_eth_vlan_rx_kill_vid,
  2300. .ndo_tx_timeout = sh_eth_tx_timeout,
  2301. .ndo_do_ioctl = sh_eth_do_ioctl,
  2302. .ndo_validate_addr = eth_validate_addr,
  2303. .ndo_set_mac_address = eth_mac_addr,
  2304. .ndo_change_mtu = eth_change_mtu,
  2305. };
  2306. #ifdef CONFIG_OF
  2307. static struct sh_eth_plat_data *sh_eth_parse_dt(struct device *dev)
  2308. {
  2309. struct device_node *np = dev->of_node;
  2310. struct sh_eth_plat_data *pdata;
  2311. const char *mac_addr;
  2312. pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
  2313. if (!pdata)
  2314. return NULL;
  2315. pdata->phy_interface = of_get_phy_mode(np);
  2316. mac_addr = of_get_mac_address(np);
  2317. if (mac_addr)
  2318. memcpy(pdata->mac_addr, mac_addr, ETH_ALEN);
  2319. pdata->no_ether_link =
  2320. of_property_read_bool(np, "renesas,no-ether-link");
  2321. pdata->ether_link_active_low =
  2322. of_property_read_bool(np, "renesas,ether-link-active-low");
  2323. return pdata;
  2324. }
  2325. static const struct of_device_id sh_eth_match_table[] = {
  2326. { .compatible = "renesas,gether-r8a7740", .data = &r8a7740_data },
  2327. { .compatible = "renesas,ether-r8a7778", .data = &r8a777x_data },
  2328. { .compatible = "renesas,ether-r8a7779", .data = &r8a777x_data },
  2329. { .compatible = "renesas,ether-r8a7790", .data = &r8a779x_data },
  2330. { .compatible = "renesas,ether-r8a7791", .data = &r8a779x_data },
  2331. { .compatible = "renesas,ether-r8a7793", .data = &r8a779x_data },
  2332. { .compatible = "renesas,ether-r8a7794", .data = &r8a779x_data },
  2333. { .compatible = "renesas,ether-r7s72100", .data = &r7s72100_data },
  2334. { }
  2335. };
  2336. MODULE_DEVICE_TABLE(of, sh_eth_match_table);
  2337. #else
  2338. static inline struct sh_eth_plat_data *sh_eth_parse_dt(struct device *dev)
  2339. {
  2340. return NULL;
  2341. }
  2342. #endif
  2343. static int sh_eth_drv_probe(struct platform_device *pdev)
  2344. {
  2345. int ret, devno = 0;
  2346. struct resource *res;
  2347. struct net_device *ndev = NULL;
  2348. struct sh_eth_private *mdp = NULL;
  2349. struct sh_eth_plat_data *pd = dev_get_platdata(&pdev->dev);
  2350. const struct platform_device_id *id = platform_get_device_id(pdev);
  2351. /* get base addr */
  2352. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  2353. ndev = alloc_etherdev(sizeof(struct sh_eth_private));
  2354. if (!ndev)
  2355. return -ENOMEM;
  2356. pm_runtime_enable(&pdev->dev);
  2357. pm_runtime_get_sync(&pdev->dev);
  2358. devno = pdev->id;
  2359. if (devno < 0)
  2360. devno = 0;
  2361. ndev->dma = -1;
  2362. ret = platform_get_irq(pdev, 0);
  2363. if (ret < 0) {
  2364. ret = -ENODEV;
  2365. goto out_release;
  2366. }
  2367. ndev->irq = ret;
  2368. SET_NETDEV_DEV(ndev, &pdev->dev);
  2369. mdp = netdev_priv(ndev);
  2370. mdp->num_tx_ring = TX_RING_SIZE;
  2371. mdp->num_rx_ring = RX_RING_SIZE;
  2372. mdp->addr = devm_ioremap_resource(&pdev->dev, res);
  2373. if (IS_ERR(mdp->addr)) {
  2374. ret = PTR_ERR(mdp->addr);
  2375. goto out_release;
  2376. }
  2377. ndev->base_addr = res->start;
  2378. spin_lock_init(&mdp->lock);
  2379. mdp->pdev = pdev;
  2380. if (pdev->dev.of_node)
  2381. pd = sh_eth_parse_dt(&pdev->dev);
  2382. if (!pd) {
  2383. dev_err(&pdev->dev, "no platform data\n");
  2384. ret = -EINVAL;
  2385. goto out_release;
  2386. }
  2387. /* get PHY ID */
  2388. mdp->phy_id = pd->phy;
  2389. mdp->phy_interface = pd->phy_interface;
  2390. /* EDMAC endian */
  2391. mdp->edmac_endian = pd->edmac_endian;
  2392. mdp->no_ether_link = pd->no_ether_link;
  2393. mdp->ether_link_active_low = pd->ether_link_active_low;
  2394. /* set cpu data */
  2395. if (id) {
  2396. mdp->cd = (struct sh_eth_cpu_data *)id->driver_data;
  2397. } else {
  2398. const struct of_device_id *match;
  2399. match = of_match_device(of_match_ptr(sh_eth_match_table),
  2400. &pdev->dev);
  2401. mdp->cd = (struct sh_eth_cpu_data *)match->data;
  2402. }
  2403. mdp->reg_offset = sh_eth_get_register_offset(mdp->cd->register_type);
  2404. if (!mdp->reg_offset) {
  2405. dev_err(&pdev->dev, "Unknown register type (%d)\n",
  2406. mdp->cd->register_type);
  2407. ret = -EINVAL;
  2408. goto out_release;
  2409. }
  2410. sh_eth_set_default_cpu_data(mdp->cd);
  2411. /* set function */
  2412. if (mdp->cd->tsu)
  2413. ndev->netdev_ops = &sh_eth_netdev_ops_tsu;
  2414. else
  2415. ndev->netdev_ops = &sh_eth_netdev_ops;
  2416. ndev->ethtool_ops = &sh_eth_ethtool_ops;
  2417. ndev->watchdog_timeo = TX_TIMEOUT;
  2418. /* debug message level */
  2419. mdp->msg_enable = SH_ETH_DEF_MSG_ENABLE;
  2420. /* read and set MAC address */
  2421. read_mac_address(ndev, pd->mac_addr);
  2422. if (!is_valid_ether_addr(ndev->dev_addr)) {
  2423. dev_warn(&pdev->dev,
  2424. "no valid MAC address supplied, using a random one.\n");
  2425. eth_hw_addr_random(ndev);
  2426. }
  2427. /* ioremap the TSU registers */
  2428. if (mdp->cd->tsu) {
  2429. struct resource *rtsu;
  2430. rtsu = platform_get_resource(pdev, IORESOURCE_MEM, 1);
  2431. mdp->tsu_addr = devm_ioremap_resource(&pdev->dev, rtsu);
  2432. if (IS_ERR(mdp->tsu_addr)) {
  2433. ret = PTR_ERR(mdp->tsu_addr);
  2434. goto out_release;
  2435. }
  2436. mdp->port = devno % 2;
  2437. ndev->features = NETIF_F_HW_VLAN_CTAG_FILTER;
  2438. }
  2439. /* initialize first or needed device */
  2440. if (!devno || pd->needs_init) {
  2441. if (mdp->cd->chip_reset)
  2442. mdp->cd->chip_reset(ndev);
  2443. if (mdp->cd->tsu) {
  2444. /* TSU init (Init only)*/
  2445. sh_eth_tsu_init(mdp);
  2446. }
  2447. }
  2448. if (mdp->cd->rmiimode)
  2449. sh_eth_write(ndev, 0x1, RMIIMODE);
  2450. /* MDIO bus init */
  2451. ret = sh_mdio_init(mdp, pd);
  2452. if (ret) {
  2453. dev_err(&ndev->dev, "failed to initialise MDIO\n");
  2454. goto out_release;
  2455. }
  2456. netif_napi_add(ndev, &mdp->napi, sh_eth_poll, 64);
  2457. /* network device register */
  2458. ret = register_netdev(ndev);
  2459. if (ret)
  2460. goto out_napi_del;
  2461. /* print device information */
  2462. netdev_info(ndev, "Base address at 0x%x, %pM, IRQ %d.\n",
  2463. (u32)ndev->base_addr, ndev->dev_addr, ndev->irq);
  2464. pm_runtime_put(&pdev->dev);
  2465. platform_set_drvdata(pdev, ndev);
  2466. return ret;
  2467. out_napi_del:
  2468. netif_napi_del(&mdp->napi);
  2469. sh_mdio_release(mdp);
  2470. out_release:
  2471. /* net_dev free */
  2472. if (ndev)
  2473. free_netdev(ndev);
  2474. pm_runtime_put(&pdev->dev);
  2475. pm_runtime_disable(&pdev->dev);
  2476. return ret;
  2477. }
  2478. static int sh_eth_drv_remove(struct platform_device *pdev)
  2479. {
  2480. struct net_device *ndev = platform_get_drvdata(pdev);
  2481. struct sh_eth_private *mdp = netdev_priv(ndev);
  2482. unregister_netdev(ndev);
  2483. netif_napi_del(&mdp->napi);
  2484. sh_mdio_release(mdp);
  2485. pm_runtime_disable(&pdev->dev);
  2486. free_netdev(ndev);
  2487. return 0;
  2488. }
  2489. #ifdef CONFIG_PM
  2490. static int sh_eth_runtime_nop(struct device *dev)
  2491. {
  2492. /* Runtime PM callback shared between ->runtime_suspend()
  2493. * and ->runtime_resume(). Simply returns success.
  2494. *
  2495. * This driver re-initializes all registers after
  2496. * pm_runtime_get_sync() anyway so there is no need
  2497. * to save and restore registers here.
  2498. */
  2499. return 0;
  2500. }
  2501. static const struct dev_pm_ops sh_eth_dev_pm_ops = {
  2502. .runtime_suspend = sh_eth_runtime_nop,
  2503. .runtime_resume = sh_eth_runtime_nop,
  2504. };
  2505. #define SH_ETH_PM_OPS (&sh_eth_dev_pm_ops)
  2506. #else
  2507. #define SH_ETH_PM_OPS NULL
  2508. #endif
  2509. static struct platform_device_id sh_eth_id_table[] = {
  2510. { "sh7619-ether", (kernel_ulong_t)&sh7619_data },
  2511. { "sh771x-ether", (kernel_ulong_t)&sh771x_data },
  2512. { "sh7724-ether", (kernel_ulong_t)&sh7724_data },
  2513. { "sh7734-gether", (kernel_ulong_t)&sh7734_data },
  2514. { "sh7757-ether", (kernel_ulong_t)&sh7757_data },
  2515. { "sh7757-gether", (kernel_ulong_t)&sh7757_data_giga },
  2516. { "sh7763-gether", (kernel_ulong_t)&sh7763_data },
  2517. { "r7s72100-ether", (kernel_ulong_t)&r7s72100_data },
  2518. { "r8a7740-gether", (kernel_ulong_t)&r8a7740_data },
  2519. { "r8a777x-ether", (kernel_ulong_t)&r8a777x_data },
  2520. { "r8a7790-ether", (kernel_ulong_t)&r8a779x_data },
  2521. { "r8a7791-ether", (kernel_ulong_t)&r8a779x_data },
  2522. { "r8a7793-ether", (kernel_ulong_t)&r8a779x_data },
  2523. { "r8a7794-ether", (kernel_ulong_t)&r8a779x_data },
  2524. { }
  2525. };
  2526. MODULE_DEVICE_TABLE(platform, sh_eth_id_table);
  2527. static struct platform_driver sh_eth_driver = {
  2528. .probe = sh_eth_drv_probe,
  2529. .remove = sh_eth_drv_remove,
  2530. .id_table = sh_eth_id_table,
  2531. .driver = {
  2532. .name = CARDNAME,
  2533. .pm = SH_ETH_PM_OPS,
  2534. .of_match_table = of_match_ptr(sh_eth_match_table),
  2535. },
  2536. };
  2537. module_platform_driver(sh_eth_driver);
  2538. MODULE_AUTHOR("Nobuhiro Iwamatsu, Yoshihiro Shimoda");
  2539. MODULE_DESCRIPTION("Renesas SuperH Ethernet driver");
  2540. MODULE_LICENSE("GPL v2");