intel_pmc_ipc.c 18 KB

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  1. /*
  2. * intel_pmc_ipc.c: Driver for the Intel PMC IPC mechanism
  3. *
  4. * (C) Copyright 2014-2015 Intel Corporation
  5. *
  6. * This driver is based on Intel SCU IPC driver(intel_scu_opc.c) by
  7. * Sreedhara DS <sreedhara.ds@intel.com>
  8. *
  9. * This program is free software; you can redistribute it and/or
  10. * modify it under the terms of the GNU General Public License
  11. * as published by the Free Software Foundation; version 2
  12. * of the License.
  13. *
  14. * PMC running in ARC processor communicates with other entity running in IA
  15. * core through IPC mechanism which in turn messaging between IA core ad PMC.
  16. */
  17. #include <linux/module.h>
  18. #include <linux/delay.h>
  19. #include <linux/errno.h>
  20. #include <linux/init.h>
  21. #include <linux/device.h>
  22. #include <linux/pm.h>
  23. #include <linux/pci.h>
  24. #include <linux/platform_device.h>
  25. #include <linux/interrupt.h>
  26. #include <linux/pm_qos.h>
  27. #include <linux/kernel.h>
  28. #include <linux/bitops.h>
  29. #include <linux/sched.h>
  30. #include <linux/atomic.h>
  31. #include <linux/notifier.h>
  32. #include <linux/suspend.h>
  33. #include <linux/acpi.h>
  34. #include <asm/intel_pmc_ipc.h>
  35. #include <linux/platform_data/itco_wdt.h>
  36. /*
  37. * IPC registers
  38. * The IA write to IPC_CMD command register triggers an interrupt to the ARC,
  39. * The ARC handles the interrupt and services it, writing optional data to
  40. * the IPC1 registers, updates the IPC_STS response register with the status.
  41. */
  42. #define IPC_CMD 0x0
  43. #define IPC_CMD_MSI 0x100
  44. #define IPC_CMD_SIZE 16
  45. #define IPC_CMD_SUBCMD 12
  46. #define IPC_STATUS 0x04
  47. #define IPC_STATUS_IRQ 0x4
  48. #define IPC_STATUS_ERR 0x2
  49. #define IPC_STATUS_BUSY 0x1
  50. #define IPC_SPTR 0x08
  51. #define IPC_DPTR 0x0C
  52. #define IPC_WRITE_BUFFER 0x80
  53. #define IPC_READ_BUFFER 0x90
  54. /*
  55. * 16-byte buffer for sending data associated with IPC command.
  56. */
  57. #define IPC_DATA_BUFFER_SIZE 16
  58. #define IPC_LOOP_CNT 3000000
  59. #define IPC_MAX_SEC 3
  60. #define IPC_TRIGGER_MODE_IRQ true
  61. /* exported resources from IFWI */
  62. #define PLAT_RESOURCE_IPC_INDEX 0
  63. #define PLAT_RESOURCE_IPC_SIZE 0x1000
  64. #define PLAT_RESOURCE_GCR_SIZE 0x1000
  65. #define PLAT_RESOURCE_PUNIT_DATA_INDEX 1
  66. #define PLAT_RESOURCE_PUNIT_INTER_INDEX 2
  67. #define PLAT_RESOURCE_ACPI_IO_INDEX 0
  68. /*
  69. * BIOS does not create an ACPI device for each PMC function,
  70. * but exports multiple resources from one ACPI device(IPC) for
  71. * multiple functions. This driver is responsible to create a
  72. * platform device and to export resources for those functions.
  73. */
  74. #define TCO_DEVICE_NAME "iTCO_wdt"
  75. #define SMI_EN_OFFSET 0x30
  76. #define SMI_EN_SIZE 4
  77. #define TCO_BASE_OFFSET 0x60
  78. #define TCO_REGS_SIZE 16
  79. #define PUNIT_DEVICE_NAME "intel_punit_ipc"
  80. static const int iTCO_version = 3;
  81. static struct intel_pmc_ipc_dev {
  82. struct device *dev;
  83. void __iomem *ipc_base;
  84. bool irq_mode;
  85. int irq;
  86. int cmd;
  87. struct completion cmd_complete;
  88. /* The following PMC BARs share the same ACPI device with the IPC */
  89. resource_size_t acpi_io_base;
  90. int acpi_io_size;
  91. struct platform_device *tco_dev;
  92. /* gcr */
  93. resource_size_t gcr_base;
  94. int gcr_size;
  95. /* punit */
  96. resource_size_t punit_base;
  97. int punit_size;
  98. resource_size_t punit_base2;
  99. int punit_size2;
  100. struct platform_device *punit_dev;
  101. } ipcdev;
  102. static char *ipc_err_sources[] = {
  103. [IPC_ERR_NONE] =
  104. "no error",
  105. [IPC_ERR_CMD_NOT_SUPPORTED] =
  106. "command not supported",
  107. [IPC_ERR_CMD_NOT_SERVICED] =
  108. "command not serviced",
  109. [IPC_ERR_UNABLE_TO_SERVICE] =
  110. "unable to service",
  111. [IPC_ERR_CMD_INVALID] =
  112. "command invalid",
  113. [IPC_ERR_CMD_FAILED] =
  114. "command failed",
  115. [IPC_ERR_EMSECURITY] =
  116. "Invalid Battery",
  117. [IPC_ERR_UNSIGNEDKERNEL] =
  118. "Unsigned kernel",
  119. };
  120. /* Prevent concurrent calls to the PMC */
  121. static DEFINE_MUTEX(ipclock);
  122. static inline void ipc_send_command(u32 cmd)
  123. {
  124. ipcdev.cmd = cmd;
  125. if (ipcdev.irq_mode) {
  126. reinit_completion(&ipcdev.cmd_complete);
  127. cmd |= IPC_CMD_MSI;
  128. }
  129. writel(cmd, ipcdev.ipc_base + IPC_CMD);
  130. }
  131. static inline u32 ipc_read_status(void)
  132. {
  133. return readl(ipcdev.ipc_base + IPC_STATUS);
  134. }
  135. static inline void ipc_data_writel(u32 data, u32 offset)
  136. {
  137. writel(data, ipcdev.ipc_base + IPC_WRITE_BUFFER + offset);
  138. }
  139. static inline u8 ipc_data_readb(u32 offset)
  140. {
  141. return readb(ipcdev.ipc_base + IPC_READ_BUFFER + offset);
  142. }
  143. static inline u32 ipc_data_readl(u32 offset)
  144. {
  145. return readl(ipcdev.ipc_base + IPC_READ_BUFFER + offset);
  146. }
  147. static int intel_pmc_ipc_check_status(void)
  148. {
  149. int status;
  150. int ret = 0;
  151. if (ipcdev.irq_mode) {
  152. if (0 == wait_for_completion_timeout(
  153. &ipcdev.cmd_complete, IPC_MAX_SEC * HZ))
  154. ret = -ETIMEDOUT;
  155. } else {
  156. int loop_count = IPC_LOOP_CNT;
  157. while ((ipc_read_status() & IPC_STATUS_BUSY) && --loop_count)
  158. udelay(1);
  159. if (loop_count == 0)
  160. ret = -ETIMEDOUT;
  161. }
  162. status = ipc_read_status();
  163. if (ret == -ETIMEDOUT) {
  164. dev_err(ipcdev.dev,
  165. "IPC timed out, TS=0x%x, CMD=0x%x\n",
  166. status, ipcdev.cmd);
  167. return ret;
  168. }
  169. if (status & IPC_STATUS_ERR) {
  170. int i;
  171. ret = -EIO;
  172. i = (status >> IPC_CMD_SIZE) & 0xFF;
  173. if (i < ARRAY_SIZE(ipc_err_sources))
  174. dev_err(ipcdev.dev,
  175. "IPC failed: %s, STS=0x%x, CMD=0x%x\n",
  176. ipc_err_sources[i], status, ipcdev.cmd);
  177. else
  178. dev_err(ipcdev.dev,
  179. "IPC failed: unknown, STS=0x%x, CMD=0x%x\n",
  180. status, ipcdev.cmd);
  181. if ((i == IPC_ERR_UNSIGNEDKERNEL) || (i == IPC_ERR_EMSECURITY))
  182. ret = -EACCES;
  183. }
  184. return ret;
  185. }
  186. /**
  187. * intel_pmc_ipc_simple_command() - Simple IPC command
  188. * @cmd: IPC command code.
  189. * @sub: IPC command sub type.
  190. *
  191. * Send a simple IPC command to PMC when don't need to specify
  192. * input/output data and source/dest pointers.
  193. *
  194. * Return: an IPC error code or 0 on success.
  195. */
  196. int intel_pmc_ipc_simple_command(int cmd, int sub)
  197. {
  198. int ret;
  199. mutex_lock(&ipclock);
  200. if (ipcdev.dev == NULL) {
  201. mutex_unlock(&ipclock);
  202. return -ENODEV;
  203. }
  204. ipc_send_command(sub << IPC_CMD_SUBCMD | cmd);
  205. ret = intel_pmc_ipc_check_status();
  206. mutex_unlock(&ipclock);
  207. return ret;
  208. }
  209. EXPORT_SYMBOL_GPL(intel_pmc_ipc_simple_command);
  210. /**
  211. * intel_pmc_ipc_raw_cmd() - IPC command with data and pointers
  212. * @cmd: IPC command code.
  213. * @sub: IPC command sub type.
  214. * @in: input data of this IPC command.
  215. * @inlen: input data length in bytes.
  216. * @out: output data of this IPC command.
  217. * @outlen: output data length in dwords.
  218. * @sptr: data writing to SPTR register.
  219. * @dptr: data writing to DPTR register.
  220. *
  221. * Send an IPC command to PMC with input/output data and source/dest pointers.
  222. *
  223. * Return: an IPC error code or 0 on success.
  224. */
  225. int intel_pmc_ipc_raw_cmd(u32 cmd, u32 sub, u8 *in, u32 inlen, u32 *out,
  226. u32 outlen, u32 dptr, u32 sptr)
  227. {
  228. u32 wbuf[4] = { 0 };
  229. int ret;
  230. int i;
  231. if (inlen > IPC_DATA_BUFFER_SIZE || outlen > IPC_DATA_BUFFER_SIZE / 4)
  232. return -EINVAL;
  233. mutex_lock(&ipclock);
  234. if (ipcdev.dev == NULL) {
  235. mutex_unlock(&ipclock);
  236. return -ENODEV;
  237. }
  238. memcpy(wbuf, in, inlen);
  239. writel(dptr, ipcdev.ipc_base + IPC_DPTR);
  240. writel(sptr, ipcdev.ipc_base + IPC_SPTR);
  241. /* The input data register is 32bit register and inlen is in Byte */
  242. for (i = 0; i < ((inlen + 3) / 4); i++)
  243. ipc_data_writel(wbuf[i], 4 * i);
  244. ipc_send_command((inlen << IPC_CMD_SIZE) |
  245. (sub << IPC_CMD_SUBCMD) | cmd);
  246. ret = intel_pmc_ipc_check_status();
  247. if (!ret) {
  248. /* out is read from 32bit register and outlen is in 32bit */
  249. for (i = 0; i < outlen; i++)
  250. *out++ = ipc_data_readl(4 * i);
  251. }
  252. mutex_unlock(&ipclock);
  253. return ret;
  254. }
  255. EXPORT_SYMBOL_GPL(intel_pmc_ipc_raw_cmd);
  256. /**
  257. * intel_pmc_ipc_command() - IPC command with input/output data
  258. * @cmd: IPC command code.
  259. * @sub: IPC command sub type.
  260. * @in: input data of this IPC command.
  261. * @inlen: input data length in bytes.
  262. * @out: output data of this IPC command.
  263. * @outlen: output data length in dwords.
  264. *
  265. * Send an IPC command to PMC with input/output data.
  266. *
  267. * Return: an IPC error code or 0 on success.
  268. */
  269. int intel_pmc_ipc_command(u32 cmd, u32 sub, u8 *in, u32 inlen,
  270. u32 *out, u32 outlen)
  271. {
  272. return intel_pmc_ipc_raw_cmd(cmd, sub, in, inlen, out, outlen, 0, 0);
  273. }
  274. EXPORT_SYMBOL_GPL(intel_pmc_ipc_command);
  275. static irqreturn_t ioc(int irq, void *dev_id)
  276. {
  277. int status;
  278. if (ipcdev.irq_mode) {
  279. status = ipc_read_status();
  280. writel(status | IPC_STATUS_IRQ, ipcdev.ipc_base + IPC_STATUS);
  281. }
  282. complete(&ipcdev.cmd_complete);
  283. return IRQ_HANDLED;
  284. }
  285. static int ipc_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
  286. {
  287. resource_size_t pci_resource;
  288. int ret;
  289. int len;
  290. ipcdev.dev = &pci_dev_get(pdev)->dev;
  291. ipcdev.irq_mode = IPC_TRIGGER_MODE_IRQ;
  292. ret = pci_enable_device(pdev);
  293. if (ret)
  294. return ret;
  295. ret = pci_request_regions(pdev, "intel_pmc_ipc");
  296. if (ret)
  297. return ret;
  298. pci_resource = pci_resource_start(pdev, 0);
  299. len = pci_resource_len(pdev, 0);
  300. if (!pci_resource || !len) {
  301. dev_err(&pdev->dev, "Failed to get resource\n");
  302. return -ENOMEM;
  303. }
  304. init_completion(&ipcdev.cmd_complete);
  305. if (request_irq(pdev->irq, ioc, 0, "intel_pmc_ipc", &ipcdev)) {
  306. dev_err(&pdev->dev, "Failed to request irq\n");
  307. return -EBUSY;
  308. }
  309. ipcdev.ipc_base = ioremap_nocache(pci_resource, len);
  310. if (!ipcdev.ipc_base) {
  311. dev_err(&pdev->dev, "Failed to ioremap ipc base\n");
  312. free_irq(pdev->irq, &ipcdev);
  313. ret = -ENOMEM;
  314. }
  315. return ret;
  316. }
  317. static void ipc_pci_remove(struct pci_dev *pdev)
  318. {
  319. free_irq(pdev->irq, &ipcdev);
  320. pci_release_regions(pdev);
  321. pci_dev_put(pdev);
  322. iounmap(ipcdev.ipc_base);
  323. ipcdev.dev = NULL;
  324. }
  325. static const struct pci_device_id ipc_pci_ids[] = {
  326. {PCI_VDEVICE(INTEL, 0x0a94), 0},
  327. {PCI_VDEVICE(INTEL, 0x1a94), 0},
  328. { 0,}
  329. };
  330. MODULE_DEVICE_TABLE(pci, ipc_pci_ids);
  331. static struct pci_driver ipc_pci_driver = {
  332. .name = "intel_pmc_ipc",
  333. .id_table = ipc_pci_ids,
  334. .probe = ipc_pci_probe,
  335. .remove = ipc_pci_remove,
  336. };
  337. static ssize_t intel_pmc_ipc_simple_cmd_store(struct device *dev,
  338. struct device_attribute *attr,
  339. const char *buf, size_t count)
  340. {
  341. int subcmd;
  342. int cmd;
  343. int ret;
  344. ret = sscanf(buf, "%d %d", &cmd, &subcmd);
  345. if (ret != 2) {
  346. dev_err(dev, "Error args\n");
  347. return -EINVAL;
  348. }
  349. ret = intel_pmc_ipc_simple_command(cmd, subcmd);
  350. if (ret) {
  351. dev_err(dev, "command %d error with %d\n", cmd, ret);
  352. return ret;
  353. }
  354. return (ssize_t)count;
  355. }
  356. static ssize_t intel_pmc_ipc_northpeak_store(struct device *dev,
  357. struct device_attribute *attr,
  358. const char *buf, size_t count)
  359. {
  360. unsigned long val;
  361. int subcmd;
  362. int ret;
  363. if (kstrtoul(buf, 0, &val))
  364. return -EINVAL;
  365. if (val)
  366. subcmd = 1;
  367. else
  368. subcmd = 0;
  369. ret = intel_pmc_ipc_simple_command(PMC_IPC_NORTHPEAK_CTRL, subcmd);
  370. if (ret) {
  371. dev_err(dev, "command north %d error with %d\n", subcmd, ret);
  372. return ret;
  373. }
  374. return (ssize_t)count;
  375. }
  376. static DEVICE_ATTR(simplecmd, S_IWUSR,
  377. NULL, intel_pmc_ipc_simple_cmd_store);
  378. static DEVICE_ATTR(northpeak, S_IWUSR,
  379. NULL, intel_pmc_ipc_northpeak_store);
  380. static struct attribute *intel_ipc_attrs[] = {
  381. &dev_attr_northpeak.attr,
  382. &dev_attr_simplecmd.attr,
  383. NULL
  384. };
  385. static const struct attribute_group intel_ipc_group = {
  386. .attrs = intel_ipc_attrs,
  387. };
  388. #define PUNIT_RESOURCE_INTER 1
  389. static struct resource punit_res[] = {
  390. /* Punit */
  391. {
  392. .flags = IORESOURCE_MEM,
  393. },
  394. {
  395. .flags = IORESOURCE_MEM,
  396. },
  397. };
  398. #define TCO_RESOURCE_ACPI_IO 0
  399. #define TCO_RESOURCE_SMI_EN_IO 1
  400. #define TCO_RESOURCE_GCR_MEM 2
  401. static struct resource tco_res[] = {
  402. /* ACPI - TCO */
  403. {
  404. .flags = IORESOURCE_IO,
  405. },
  406. /* ACPI - SMI */
  407. {
  408. .flags = IORESOURCE_IO,
  409. },
  410. /* GCS */
  411. {
  412. .flags = IORESOURCE_MEM,
  413. },
  414. };
  415. static struct itco_wdt_platform_data tco_info = {
  416. .name = "Apollo Lake SoC",
  417. .version = 3,
  418. };
  419. static int ipc_create_punit_device(void)
  420. {
  421. struct platform_device *pdev;
  422. struct resource *res;
  423. int ret;
  424. pdev = platform_device_alloc(PUNIT_DEVICE_NAME, -1);
  425. if (!pdev) {
  426. dev_err(ipcdev.dev, "Failed to alloc punit platform device\n");
  427. return -ENOMEM;
  428. }
  429. pdev->dev.parent = ipcdev.dev;
  430. res = punit_res;
  431. res->start = ipcdev.punit_base;
  432. res->end = res->start + ipcdev.punit_size - 1;
  433. res = punit_res + PUNIT_RESOURCE_INTER;
  434. res->start = ipcdev.punit_base2;
  435. res->end = res->start + ipcdev.punit_size2 - 1;
  436. ret = platform_device_add_resources(pdev, punit_res,
  437. ARRAY_SIZE(punit_res));
  438. if (ret) {
  439. dev_err(ipcdev.dev, "Failed to add platform punit resources\n");
  440. goto err;
  441. }
  442. ret = platform_device_add(pdev);
  443. if (ret) {
  444. dev_err(ipcdev.dev, "Failed to add punit platform device\n");
  445. goto err;
  446. }
  447. ipcdev.punit_dev = pdev;
  448. return 0;
  449. err:
  450. platform_device_put(pdev);
  451. return ret;
  452. }
  453. static int ipc_create_tco_device(void)
  454. {
  455. struct platform_device *pdev;
  456. struct resource *res;
  457. int ret;
  458. pdev = platform_device_alloc(TCO_DEVICE_NAME, -1);
  459. if (!pdev) {
  460. dev_err(ipcdev.dev, "Failed to alloc tco platform device\n");
  461. return -ENOMEM;
  462. }
  463. pdev->dev.parent = ipcdev.dev;
  464. res = tco_res + TCO_RESOURCE_ACPI_IO;
  465. res->start = ipcdev.acpi_io_base + TCO_BASE_OFFSET;
  466. res->end = res->start + TCO_REGS_SIZE - 1;
  467. res = tco_res + TCO_RESOURCE_SMI_EN_IO;
  468. res->start = ipcdev.acpi_io_base + SMI_EN_OFFSET;
  469. res->end = res->start + SMI_EN_SIZE - 1;
  470. res = tco_res + TCO_RESOURCE_GCR_MEM;
  471. res->start = ipcdev.gcr_base;
  472. res->end = res->start + ipcdev.gcr_size - 1;
  473. ret = platform_device_add_resources(pdev, tco_res, ARRAY_SIZE(tco_res));
  474. if (ret) {
  475. dev_err(ipcdev.dev, "Failed to add tco platform resources\n");
  476. goto err;
  477. }
  478. ret = platform_device_add_data(pdev, &tco_info, sizeof(tco_info));
  479. if (ret) {
  480. dev_err(ipcdev.dev, "Failed to add tco platform data\n");
  481. goto err;
  482. }
  483. ret = platform_device_add(pdev);
  484. if (ret) {
  485. dev_err(ipcdev.dev, "Failed to add tco platform device\n");
  486. goto err;
  487. }
  488. ipcdev.tco_dev = pdev;
  489. return 0;
  490. err:
  491. platform_device_put(pdev);
  492. return ret;
  493. }
  494. static int ipc_create_pmc_devices(void)
  495. {
  496. int ret;
  497. ret = ipc_create_tco_device();
  498. if (ret) {
  499. dev_err(ipcdev.dev, "Failed to add tco platform device\n");
  500. return ret;
  501. }
  502. ret = ipc_create_punit_device();
  503. if (ret) {
  504. dev_err(ipcdev.dev, "Failed to add punit platform device\n");
  505. platform_device_unregister(ipcdev.tco_dev);
  506. }
  507. return ret;
  508. }
  509. static int ipc_plat_get_res(struct platform_device *pdev)
  510. {
  511. struct resource *res;
  512. void __iomem *addr;
  513. int size;
  514. res = platform_get_resource(pdev, IORESOURCE_IO,
  515. PLAT_RESOURCE_ACPI_IO_INDEX);
  516. if (!res) {
  517. dev_err(&pdev->dev, "Failed to get io resource\n");
  518. return -ENXIO;
  519. }
  520. size = resource_size(res);
  521. ipcdev.acpi_io_base = res->start;
  522. ipcdev.acpi_io_size = size;
  523. dev_info(&pdev->dev, "io res: %llx %x\n",
  524. (long long)res->start, (int)resource_size(res));
  525. res = platform_get_resource(pdev, IORESOURCE_MEM,
  526. PLAT_RESOURCE_PUNIT_DATA_INDEX);
  527. if (!res) {
  528. dev_err(&pdev->dev, "Failed to get punit resource\n");
  529. return -ENXIO;
  530. }
  531. size = resource_size(res);
  532. ipcdev.punit_base = res->start;
  533. ipcdev.punit_size = size;
  534. dev_info(&pdev->dev, "punit data res: %llx %x\n",
  535. (long long)res->start, (int)resource_size(res));
  536. res = platform_get_resource(pdev, IORESOURCE_MEM,
  537. PLAT_RESOURCE_PUNIT_INTER_INDEX);
  538. if (!res) {
  539. dev_err(&pdev->dev, "Failed to get punit inter resource\n");
  540. return -ENXIO;
  541. }
  542. size = resource_size(res);
  543. ipcdev.punit_base2 = res->start;
  544. ipcdev.punit_size2 = size;
  545. dev_info(&pdev->dev, "punit interface res: %llx %x\n",
  546. (long long)res->start, (int)resource_size(res));
  547. res = platform_get_resource(pdev, IORESOURCE_MEM,
  548. PLAT_RESOURCE_IPC_INDEX);
  549. if (!res) {
  550. dev_err(&pdev->dev, "Failed to get ipc resource\n");
  551. return -ENXIO;
  552. }
  553. size = PLAT_RESOURCE_IPC_SIZE;
  554. if (!request_mem_region(res->start, size, pdev->name)) {
  555. dev_err(&pdev->dev, "Failed to request ipc resource\n");
  556. return -EBUSY;
  557. }
  558. addr = ioremap_nocache(res->start, size);
  559. if (!addr) {
  560. dev_err(&pdev->dev, "I/O memory remapping failed\n");
  561. release_mem_region(res->start, size);
  562. return -ENOMEM;
  563. }
  564. ipcdev.ipc_base = addr;
  565. ipcdev.gcr_base = res->start + size;
  566. ipcdev.gcr_size = PLAT_RESOURCE_GCR_SIZE;
  567. dev_info(&pdev->dev, "ipc res: %llx %x\n",
  568. (long long)res->start, (int)resource_size(res));
  569. return 0;
  570. }
  571. #ifdef CONFIG_ACPI
  572. static const struct acpi_device_id ipc_acpi_ids[] = {
  573. { "INT34D2", 0},
  574. { }
  575. };
  576. MODULE_DEVICE_TABLE(acpi, ipc_acpi_ids);
  577. #endif
  578. static int ipc_plat_probe(struct platform_device *pdev)
  579. {
  580. struct resource *res;
  581. int ret;
  582. ipcdev.dev = &pdev->dev;
  583. ipcdev.irq_mode = IPC_TRIGGER_MODE_IRQ;
  584. init_completion(&ipcdev.cmd_complete);
  585. ipcdev.irq = platform_get_irq(pdev, 0);
  586. if (ipcdev.irq < 0) {
  587. dev_err(&pdev->dev, "Failed to get irq\n");
  588. return -EINVAL;
  589. }
  590. ret = ipc_plat_get_res(pdev);
  591. if (ret) {
  592. dev_err(&pdev->dev, "Failed to request resource\n");
  593. return ret;
  594. }
  595. ret = ipc_create_pmc_devices();
  596. if (ret) {
  597. dev_err(&pdev->dev, "Failed to create pmc devices\n");
  598. goto err_device;
  599. }
  600. if (request_irq(ipcdev.irq, ioc, 0, "intel_pmc_ipc", &ipcdev)) {
  601. dev_err(&pdev->dev, "Failed to request irq\n");
  602. ret = -EBUSY;
  603. goto err_irq;
  604. }
  605. ret = sysfs_create_group(&pdev->dev.kobj, &intel_ipc_group);
  606. if (ret) {
  607. dev_err(&pdev->dev, "Failed to create sysfs group %d\n",
  608. ret);
  609. goto err_sys;
  610. }
  611. return 0;
  612. err_sys:
  613. free_irq(ipcdev.irq, &ipcdev);
  614. err_irq:
  615. platform_device_unregister(ipcdev.tco_dev);
  616. platform_device_unregister(ipcdev.punit_dev);
  617. err_device:
  618. iounmap(ipcdev.ipc_base);
  619. res = platform_get_resource(pdev, IORESOURCE_MEM,
  620. PLAT_RESOURCE_IPC_INDEX);
  621. if (res)
  622. release_mem_region(res->start, PLAT_RESOURCE_IPC_SIZE);
  623. return ret;
  624. }
  625. static int ipc_plat_remove(struct platform_device *pdev)
  626. {
  627. struct resource *res;
  628. sysfs_remove_group(&pdev->dev.kobj, &intel_ipc_group);
  629. free_irq(ipcdev.irq, &ipcdev);
  630. platform_device_unregister(ipcdev.tco_dev);
  631. platform_device_unregister(ipcdev.punit_dev);
  632. iounmap(ipcdev.ipc_base);
  633. res = platform_get_resource(pdev, IORESOURCE_MEM,
  634. PLAT_RESOURCE_IPC_INDEX);
  635. if (res)
  636. release_mem_region(res->start, PLAT_RESOURCE_IPC_SIZE);
  637. ipcdev.dev = NULL;
  638. return 0;
  639. }
  640. static struct platform_driver ipc_plat_driver = {
  641. .remove = ipc_plat_remove,
  642. .probe = ipc_plat_probe,
  643. .driver = {
  644. .name = "pmc-ipc-plat",
  645. .acpi_match_table = ACPI_PTR(ipc_acpi_ids),
  646. },
  647. };
  648. static int __init intel_pmc_ipc_init(void)
  649. {
  650. int ret;
  651. ret = platform_driver_register(&ipc_plat_driver);
  652. if (ret) {
  653. pr_err("Failed to register PMC ipc platform driver\n");
  654. return ret;
  655. }
  656. ret = pci_register_driver(&ipc_pci_driver);
  657. if (ret) {
  658. pr_err("Failed to register PMC ipc pci driver\n");
  659. platform_driver_unregister(&ipc_plat_driver);
  660. return ret;
  661. }
  662. return ret;
  663. }
  664. static void __exit intel_pmc_ipc_exit(void)
  665. {
  666. pci_unregister_driver(&ipc_pci_driver);
  667. platform_driver_unregister(&ipc_plat_driver);
  668. }
  669. MODULE_AUTHOR("Zha Qipeng <qipeng.zha@intel.com>");
  670. MODULE_DESCRIPTION("Intel PMC IPC driver");
  671. MODULE_LICENSE("GPL");
  672. /* Some modules are dependent on this, so init earlier */
  673. fs_initcall(intel_pmc_ipc_init);
  674. module_exit(intel_pmc_ipc_exit);