smsc911x.c 70 KB

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  1. /***************************************************************************
  2. *
  3. * Copyright (C) 2004-2008 SMSC
  4. * Copyright (C) 2005-2008 ARM
  5. *
  6. * This program is free software; you can redistribute it and/or
  7. * modify it under the terms of the GNU General Public License
  8. * as published by the Free Software Foundation; either version 2
  9. * of the License, or (at your option) any later version.
  10. *
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. * GNU General Public License for more details.
  15. *
  16. * You should have received a copy of the GNU General Public License
  17. * along with this program; if not, see <http://www.gnu.org/licenses/>.
  18. *
  19. ***************************************************************************
  20. * Rewritten, heavily based on smsc911x simple driver by SMSC.
  21. * Partly uses io macros from smc91x.c by Nicolas Pitre
  22. *
  23. * Supported devices:
  24. * LAN9115, LAN9116, LAN9117, LAN9118
  25. * LAN9215, LAN9216, LAN9217, LAN9218
  26. * LAN9210, LAN9211
  27. * LAN9220, LAN9221
  28. * LAN89218
  29. *
  30. */
  31. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  32. #include <linux/crc32.h>
  33. #include <linux/clk.h>
  34. #include <linux/delay.h>
  35. #include <linux/errno.h>
  36. #include <linux/etherdevice.h>
  37. #include <linux/ethtool.h>
  38. #include <linux/init.h>
  39. #include <linux/interrupt.h>
  40. #include <linux/ioport.h>
  41. #include <linux/kernel.h>
  42. #include <linux/module.h>
  43. #include <linux/netdevice.h>
  44. #include <linux/platform_device.h>
  45. #include <linux/regulator/consumer.h>
  46. #include <linux/sched.h>
  47. #include <linux/timer.h>
  48. #include <linux/bug.h>
  49. #include <linux/bitops.h>
  50. #include <linux/irq.h>
  51. #include <linux/io.h>
  52. #include <linux/swab.h>
  53. #include <linux/phy.h>
  54. #include <linux/smsc911x.h>
  55. #include <linux/device.h>
  56. #include <linux/of.h>
  57. #include <linux/of_device.h>
  58. #include <linux/of_gpio.h>
  59. #include <linux/of_net.h>
  60. #include <linux/acpi.h>
  61. #include <linux/pm_runtime.h>
  62. #include <linux/property.h>
  63. #include "smsc911x.h"
  64. #define SMSC_CHIPNAME "smsc911x"
  65. #define SMSC_MDIONAME "smsc911x-mdio"
  66. #define SMSC_DRV_VERSION "2008-10-21"
  67. MODULE_LICENSE("GPL");
  68. MODULE_VERSION(SMSC_DRV_VERSION);
  69. MODULE_ALIAS("platform:smsc911x");
  70. #if USE_DEBUG > 0
  71. static int debug = 16;
  72. #else
  73. static int debug = 3;
  74. #endif
  75. module_param(debug, int, 0);
  76. MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
  77. struct smsc911x_data;
  78. struct smsc911x_ops {
  79. u32 (*reg_read)(struct smsc911x_data *pdata, u32 reg);
  80. void (*reg_write)(struct smsc911x_data *pdata, u32 reg, u32 val);
  81. void (*rx_readfifo)(struct smsc911x_data *pdata,
  82. unsigned int *buf, unsigned int wordcount);
  83. void (*tx_writefifo)(struct smsc911x_data *pdata,
  84. unsigned int *buf, unsigned int wordcount);
  85. };
  86. #define SMSC911X_NUM_SUPPLIES 2
  87. struct smsc911x_data {
  88. void __iomem *ioaddr;
  89. unsigned int idrev;
  90. /* used to decide which workarounds apply */
  91. unsigned int generation;
  92. /* device configuration (copied from platform_data during probe) */
  93. struct smsc911x_platform_config config;
  94. /* This needs to be acquired before calling any of below:
  95. * smsc911x_mac_read(), smsc911x_mac_write()
  96. */
  97. spinlock_t mac_lock;
  98. /* spinlock to ensure register accesses are serialised */
  99. spinlock_t dev_lock;
  100. struct phy_device *phy_dev;
  101. struct mii_bus *mii_bus;
  102. int phy_irq[PHY_MAX_ADDR];
  103. unsigned int using_extphy;
  104. int last_duplex;
  105. int last_carrier;
  106. u32 msg_enable;
  107. unsigned int gpio_setting;
  108. unsigned int gpio_orig_setting;
  109. struct net_device *dev;
  110. struct napi_struct napi;
  111. unsigned int software_irq_signal;
  112. #ifdef USE_PHY_WORK_AROUND
  113. #define MIN_PACKET_SIZE (64)
  114. char loopback_tx_pkt[MIN_PACKET_SIZE];
  115. char loopback_rx_pkt[MIN_PACKET_SIZE];
  116. unsigned int resetcount;
  117. #endif
  118. /* Members for Multicast filter workaround */
  119. unsigned int multicast_update_pending;
  120. unsigned int set_bits_mask;
  121. unsigned int clear_bits_mask;
  122. unsigned int hashhi;
  123. unsigned int hashlo;
  124. /* register access functions */
  125. const struct smsc911x_ops *ops;
  126. /* regulators */
  127. struct regulator_bulk_data supplies[SMSC911X_NUM_SUPPLIES];
  128. /* clock */
  129. struct clk *clk;
  130. };
  131. /* Easy access to information */
  132. #define __smsc_shift(pdata, reg) ((reg) << ((pdata)->config.shift))
  133. static inline u32 __smsc911x_reg_read(struct smsc911x_data *pdata, u32 reg)
  134. {
  135. if (pdata->config.flags & SMSC911X_USE_32BIT)
  136. return readl(pdata->ioaddr + reg);
  137. if (pdata->config.flags & SMSC911X_USE_16BIT)
  138. return ((readw(pdata->ioaddr + reg) & 0xFFFF) |
  139. ((readw(pdata->ioaddr + reg + 2) & 0xFFFF) << 16));
  140. BUG();
  141. return 0;
  142. }
  143. static inline u32
  144. __smsc911x_reg_read_shift(struct smsc911x_data *pdata, u32 reg)
  145. {
  146. if (pdata->config.flags & SMSC911X_USE_32BIT)
  147. return readl(pdata->ioaddr + __smsc_shift(pdata, reg));
  148. if (pdata->config.flags & SMSC911X_USE_16BIT)
  149. return (readw(pdata->ioaddr +
  150. __smsc_shift(pdata, reg)) & 0xFFFF) |
  151. ((readw(pdata->ioaddr +
  152. __smsc_shift(pdata, reg + 2)) & 0xFFFF) << 16);
  153. BUG();
  154. return 0;
  155. }
  156. static inline u32 smsc911x_reg_read(struct smsc911x_data *pdata, u32 reg)
  157. {
  158. u32 data;
  159. unsigned long flags;
  160. spin_lock_irqsave(&pdata->dev_lock, flags);
  161. data = pdata->ops->reg_read(pdata, reg);
  162. spin_unlock_irqrestore(&pdata->dev_lock, flags);
  163. return data;
  164. }
  165. static inline void __smsc911x_reg_write(struct smsc911x_data *pdata, u32 reg,
  166. u32 val)
  167. {
  168. if (pdata->config.flags & SMSC911X_USE_32BIT) {
  169. writel(val, pdata->ioaddr + reg);
  170. return;
  171. }
  172. if (pdata->config.flags & SMSC911X_USE_16BIT) {
  173. writew(val & 0xFFFF, pdata->ioaddr + reg);
  174. writew((val >> 16) & 0xFFFF, pdata->ioaddr + reg + 2);
  175. return;
  176. }
  177. BUG();
  178. }
  179. static inline void
  180. __smsc911x_reg_write_shift(struct smsc911x_data *pdata, u32 reg, u32 val)
  181. {
  182. if (pdata->config.flags & SMSC911X_USE_32BIT) {
  183. writel(val, pdata->ioaddr + __smsc_shift(pdata, reg));
  184. return;
  185. }
  186. if (pdata->config.flags & SMSC911X_USE_16BIT) {
  187. writew(val & 0xFFFF,
  188. pdata->ioaddr + __smsc_shift(pdata, reg));
  189. writew((val >> 16) & 0xFFFF,
  190. pdata->ioaddr + __smsc_shift(pdata, reg + 2));
  191. return;
  192. }
  193. BUG();
  194. }
  195. static inline void smsc911x_reg_write(struct smsc911x_data *pdata, u32 reg,
  196. u32 val)
  197. {
  198. unsigned long flags;
  199. spin_lock_irqsave(&pdata->dev_lock, flags);
  200. pdata->ops->reg_write(pdata, reg, val);
  201. spin_unlock_irqrestore(&pdata->dev_lock, flags);
  202. }
  203. /* Writes a packet to the TX_DATA_FIFO */
  204. static inline void
  205. smsc911x_tx_writefifo(struct smsc911x_data *pdata, unsigned int *buf,
  206. unsigned int wordcount)
  207. {
  208. unsigned long flags;
  209. spin_lock_irqsave(&pdata->dev_lock, flags);
  210. if (pdata->config.flags & SMSC911X_SWAP_FIFO) {
  211. while (wordcount--)
  212. __smsc911x_reg_write(pdata, TX_DATA_FIFO,
  213. swab32(*buf++));
  214. goto out;
  215. }
  216. if (pdata->config.flags & SMSC911X_USE_32BIT) {
  217. iowrite32_rep(pdata->ioaddr + TX_DATA_FIFO, buf, wordcount);
  218. goto out;
  219. }
  220. if (pdata->config.flags & SMSC911X_USE_16BIT) {
  221. while (wordcount--)
  222. __smsc911x_reg_write(pdata, TX_DATA_FIFO, *buf++);
  223. goto out;
  224. }
  225. BUG();
  226. out:
  227. spin_unlock_irqrestore(&pdata->dev_lock, flags);
  228. }
  229. /* Writes a packet to the TX_DATA_FIFO - shifted version */
  230. static inline void
  231. smsc911x_tx_writefifo_shift(struct smsc911x_data *pdata, unsigned int *buf,
  232. unsigned int wordcount)
  233. {
  234. unsigned long flags;
  235. spin_lock_irqsave(&pdata->dev_lock, flags);
  236. if (pdata->config.flags & SMSC911X_SWAP_FIFO) {
  237. while (wordcount--)
  238. __smsc911x_reg_write_shift(pdata, TX_DATA_FIFO,
  239. swab32(*buf++));
  240. goto out;
  241. }
  242. if (pdata->config.flags & SMSC911X_USE_32BIT) {
  243. iowrite32_rep(pdata->ioaddr + __smsc_shift(pdata,
  244. TX_DATA_FIFO), buf, wordcount);
  245. goto out;
  246. }
  247. if (pdata->config.flags & SMSC911X_USE_16BIT) {
  248. while (wordcount--)
  249. __smsc911x_reg_write_shift(pdata,
  250. TX_DATA_FIFO, *buf++);
  251. goto out;
  252. }
  253. BUG();
  254. out:
  255. spin_unlock_irqrestore(&pdata->dev_lock, flags);
  256. }
  257. /* Reads a packet out of the RX_DATA_FIFO */
  258. static inline void
  259. smsc911x_rx_readfifo(struct smsc911x_data *pdata, unsigned int *buf,
  260. unsigned int wordcount)
  261. {
  262. unsigned long flags;
  263. spin_lock_irqsave(&pdata->dev_lock, flags);
  264. if (pdata->config.flags & SMSC911X_SWAP_FIFO) {
  265. while (wordcount--)
  266. *buf++ = swab32(__smsc911x_reg_read(pdata,
  267. RX_DATA_FIFO));
  268. goto out;
  269. }
  270. if (pdata->config.flags & SMSC911X_USE_32BIT) {
  271. ioread32_rep(pdata->ioaddr + RX_DATA_FIFO, buf, wordcount);
  272. goto out;
  273. }
  274. if (pdata->config.flags & SMSC911X_USE_16BIT) {
  275. while (wordcount--)
  276. *buf++ = __smsc911x_reg_read(pdata, RX_DATA_FIFO);
  277. goto out;
  278. }
  279. BUG();
  280. out:
  281. spin_unlock_irqrestore(&pdata->dev_lock, flags);
  282. }
  283. /* Reads a packet out of the RX_DATA_FIFO - shifted version */
  284. static inline void
  285. smsc911x_rx_readfifo_shift(struct smsc911x_data *pdata, unsigned int *buf,
  286. unsigned int wordcount)
  287. {
  288. unsigned long flags;
  289. spin_lock_irqsave(&pdata->dev_lock, flags);
  290. if (pdata->config.flags & SMSC911X_SWAP_FIFO) {
  291. while (wordcount--)
  292. *buf++ = swab32(__smsc911x_reg_read_shift(pdata,
  293. RX_DATA_FIFO));
  294. goto out;
  295. }
  296. if (pdata->config.flags & SMSC911X_USE_32BIT) {
  297. ioread32_rep(pdata->ioaddr + __smsc_shift(pdata,
  298. RX_DATA_FIFO), buf, wordcount);
  299. goto out;
  300. }
  301. if (pdata->config.flags & SMSC911X_USE_16BIT) {
  302. while (wordcount--)
  303. *buf++ = __smsc911x_reg_read_shift(pdata,
  304. RX_DATA_FIFO);
  305. goto out;
  306. }
  307. BUG();
  308. out:
  309. spin_unlock_irqrestore(&pdata->dev_lock, flags);
  310. }
  311. /*
  312. * enable regulator and clock resources.
  313. */
  314. static int smsc911x_enable_resources(struct platform_device *pdev)
  315. {
  316. struct net_device *ndev = platform_get_drvdata(pdev);
  317. struct smsc911x_data *pdata = netdev_priv(ndev);
  318. int ret = 0;
  319. ret = regulator_bulk_enable(ARRAY_SIZE(pdata->supplies),
  320. pdata->supplies);
  321. if (ret)
  322. netdev_err(ndev, "failed to enable regulators %d\n",
  323. ret);
  324. if (!IS_ERR(pdata->clk)) {
  325. ret = clk_prepare_enable(pdata->clk);
  326. if (ret < 0)
  327. netdev_err(ndev, "failed to enable clock %d\n", ret);
  328. }
  329. return ret;
  330. }
  331. /*
  332. * disable resources, currently just regulators.
  333. */
  334. static int smsc911x_disable_resources(struct platform_device *pdev)
  335. {
  336. struct net_device *ndev = platform_get_drvdata(pdev);
  337. struct smsc911x_data *pdata = netdev_priv(ndev);
  338. int ret = 0;
  339. ret = regulator_bulk_disable(ARRAY_SIZE(pdata->supplies),
  340. pdata->supplies);
  341. if (!IS_ERR(pdata->clk))
  342. clk_disable_unprepare(pdata->clk);
  343. return ret;
  344. }
  345. /*
  346. * Request resources, currently just regulators.
  347. *
  348. * The SMSC911x has two power pins: vddvario and vdd33a, in designs where
  349. * these are not always-on we need to request regulators to be turned on
  350. * before we can try to access the device registers.
  351. */
  352. static int smsc911x_request_resources(struct platform_device *pdev)
  353. {
  354. struct net_device *ndev = platform_get_drvdata(pdev);
  355. struct smsc911x_data *pdata = netdev_priv(ndev);
  356. int ret = 0;
  357. /* Request regulators */
  358. pdata->supplies[0].supply = "vdd33a";
  359. pdata->supplies[1].supply = "vddvario";
  360. ret = regulator_bulk_get(&pdev->dev,
  361. ARRAY_SIZE(pdata->supplies),
  362. pdata->supplies);
  363. if (ret)
  364. netdev_err(ndev, "couldn't get regulators %d\n",
  365. ret);
  366. /* Request clock */
  367. pdata->clk = clk_get(&pdev->dev, NULL);
  368. if (IS_ERR(pdata->clk))
  369. dev_dbg(&pdev->dev, "couldn't get clock %li\n",
  370. PTR_ERR(pdata->clk));
  371. return ret;
  372. }
  373. /*
  374. * Free resources, currently just regulators.
  375. *
  376. */
  377. static void smsc911x_free_resources(struct platform_device *pdev)
  378. {
  379. struct net_device *ndev = platform_get_drvdata(pdev);
  380. struct smsc911x_data *pdata = netdev_priv(ndev);
  381. /* Free regulators */
  382. regulator_bulk_free(ARRAY_SIZE(pdata->supplies),
  383. pdata->supplies);
  384. /* Free clock */
  385. if (!IS_ERR(pdata->clk)) {
  386. clk_put(pdata->clk);
  387. pdata->clk = NULL;
  388. }
  389. }
  390. /* waits for MAC not busy, with timeout. Only called by smsc911x_mac_read
  391. * and smsc911x_mac_write, so assumes mac_lock is held */
  392. static int smsc911x_mac_complete(struct smsc911x_data *pdata)
  393. {
  394. int i;
  395. u32 val;
  396. SMSC_ASSERT_MAC_LOCK(pdata);
  397. for (i = 0; i < 40; i++) {
  398. val = smsc911x_reg_read(pdata, MAC_CSR_CMD);
  399. if (!(val & MAC_CSR_CMD_CSR_BUSY_))
  400. return 0;
  401. }
  402. SMSC_WARN(pdata, hw, "Timed out waiting for MAC not BUSY. "
  403. "MAC_CSR_CMD: 0x%08X", val);
  404. return -EIO;
  405. }
  406. /* Fetches a MAC register value. Assumes mac_lock is acquired */
  407. static u32 smsc911x_mac_read(struct smsc911x_data *pdata, unsigned int offset)
  408. {
  409. unsigned int temp;
  410. SMSC_ASSERT_MAC_LOCK(pdata);
  411. temp = smsc911x_reg_read(pdata, MAC_CSR_CMD);
  412. if (unlikely(temp & MAC_CSR_CMD_CSR_BUSY_)) {
  413. SMSC_WARN(pdata, hw, "MAC busy at entry");
  414. return 0xFFFFFFFF;
  415. }
  416. /* Send the MAC cmd */
  417. smsc911x_reg_write(pdata, MAC_CSR_CMD, ((offset & 0xFF) |
  418. MAC_CSR_CMD_CSR_BUSY_ | MAC_CSR_CMD_R_NOT_W_));
  419. /* Workaround for hardware read-after-write restriction */
  420. temp = smsc911x_reg_read(pdata, BYTE_TEST);
  421. /* Wait for the read to complete */
  422. if (likely(smsc911x_mac_complete(pdata) == 0))
  423. return smsc911x_reg_read(pdata, MAC_CSR_DATA);
  424. SMSC_WARN(pdata, hw, "MAC busy after read");
  425. return 0xFFFFFFFF;
  426. }
  427. /* Set a mac register, mac_lock must be acquired before calling */
  428. static void smsc911x_mac_write(struct smsc911x_data *pdata,
  429. unsigned int offset, u32 val)
  430. {
  431. unsigned int temp;
  432. SMSC_ASSERT_MAC_LOCK(pdata);
  433. temp = smsc911x_reg_read(pdata, MAC_CSR_CMD);
  434. if (unlikely(temp & MAC_CSR_CMD_CSR_BUSY_)) {
  435. SMSC_WARN(pdata, hw,
  436. "smsc911x_mac_write failed, MAC busy at entry");
  437. return;
  438. }
  439. /* Send data to write */
  440. smsc911x_reg_write(pdata, MAC_CSR_DATA, val);
  441. /* Write the actual data */
  442. smsc911x_reg_write(pdata, MAC_CSR_CMD, ((offset & 0xFF) |
  443. MAC_CSR_CMD_CSR_BUSY_));
  444. /* Workaround for hardware read-after-write restriction */
  445. temp = smsc911x_reg_read(pdata, BYTE_TEST);
  446. /* Wait for the write to complete */
  447. if (likely(smsc911x_mac_complete(pdata) == 0))
  448. return;
  449. SMSC_WARN(pdata, hw, "smsc911x_mac_write failed, MAC busy after write");
  450. }
  451. /* Get a phy register */
  452. static int smsc911x_mii_read(struct mii_bus *bus, int phyaddr, int regidx)
  453. {
  454. struct smsc911x_data *pdata = (struct smsc911x_data *)bus->priv;
  455. unsigned long flags;
  456. unsigned int addr;
  457. int i, reg;
  458. spin_lock_irqsave(&pdata->mac_lock, flags);
  459. /* Confirm MII not busy */
  460. if (unlikely(smsc911x_mac_read(pdata, MII_ACC) & MII_ACC_MII_BUSY_)) {
  461. SMSC_WARN(pdata, hw, "MII is busy in smsc911x_mii_read???");
  462. reg = -EIO;
  463. goto out;
  464. }
  465. /* Set the address, index & direction (read from PHY) */
  466. addr = ((phyaddr & 0x1F) << 11) | ((regidx & 0x1F) << 6);
  467. smsc911x_mac_write(pdata, MII_ACC, addr);
  468. /* Wait for read to complete w/ timeout */
  469. for (i = 0; i < 100; i++)
  470. if (!(smsc911x_mac_read(pdata, MII_ACC) & MII_ACC_MII_BUSY_)) {
  471. reg = smsc911x_mac_read(pdata, MII_DATA);
  472. goto out;
  473. }
  474. SMSC_WARN(pdata, hw, "Timed out waiting for MII read to finish");
  475. reg = -EIO;
  476. out:
  477. spin_unlock_irqrestore(&pdata->mac_lock, flags);
  478. return reg;
  479. }
  480. /* Set a phy register */
  481. static int smsc911x_mii_write(struct mii_bus *bus, int phyaddr, int regidx,
  482. u16 val)
  483. {
  484. struct smsc911x_data *pdata = (struct smsc911x_data *)bus->priv;
  485. unsigned long flags;
  486. unsigned int addr;
  487. int i, reg;
  488. spin_lock_irqsave(&pdata->mac_lock, flags);
  489. /* Confirm MII not busy */
  490. if (unlikely(smsc911x_mac_read(pdata, MII_ACC) & MII_ACC_MII_BUSY_)) {
  491. SMSC_WARN(pdata, hw, "MII is busy in smsc911x_mii_write???");
  492. reg = -EIO;
  493. goto out;
  494. }
  495. /* Put the data to write in the MAC */
  496. smsc911x_mac_write(pdata, MII_DATA, val);
  497. /* Set the address, index & direction (write to PHY) */
  498. addr = ((phyaddr & 0x1F) << 11) | ((regidx & 0x1F) << 6) |
  499. MII_ACC_MII_WRITE_;
  500. smsc911x_mac_write(pdata, MII_ACC, addr);
  501. /* Wait for write to complete w/ timeout */
  502. for (i = 0; i < 100; i++)
  503. if (!(smsc911x_mac_read(pdata, MII_ACC) & MII_ACC_MII_BUSY_)) {
  504. reg = 0;
  505. goto out;
  506. }
  507. SMSC_WARN(pdata, hw, "Timed out waiting for MII write to finish");
  508. reg = -EIO;
  509. out:
  510. spin_unlock_irqrestore(&pdata->mac_lock, flags);
  511. return reg;
  512. }
  513. /* Switch to external phy. Assumes tx and rx are stopped. */
  514. static void smsc911x_phy_enable_external(struct smsc911x_data *pdata)
  515. {
  516. unsigned int hwcfg = smsc911x_reg_read(pdata, HW_CFG);
  517. /* Disable phy clocks to the MAC */
  518. hwcfg &= (~HW_CFG_PHY_CLK_SEL_);
  519. hwcfg |= HW_CFG_PHY_CLK_SEL_CLK_DIS_;
  520. smsc911x_reg_write(pdata, HW_CFG, hwcfg);
  521. udelay(10); /* Enough time for clocks to stop */
  522. /* Switch to external phy */
  523. hwcfg |= HW_CFG_EXT_PHY_EN_;
  524. smsc911x_reg_write(pdata, HW_CFG, hwcfg);
  525. /* Enable phy clocks to the MAC */
  526. hwcfg &= (~HW_CFG_PHY_CLK_SEL_);
  527. hwcfg |= HW_CFG_PHY_CLK_SEL_EXT_PHY_;
  528. smsc911x_reg_write(pdata, HW_CFG, hwcfg);
  529. udelay(10); /* Enough time for clocks to restart */
  530. hwcfg |= HW_CFG_SMI_SEL_;
  531. smsc911x_reg_write(pdata, HW_CFG, hwcfg);
  532. }
  533. /* Autodetects and enables external phy if present on supported chips.
  534. * autodetection can be overridden by specifying SMSC911X_FORCE_INTERNAL_PHY
  535. * or SMSC911X_FORCE_EXTERNAL_PHY in the platform_data flags. */
  536. static void smsc911x_phy_initialise_external(struct smsc911x_data *pdata)
  537. {
  538. unsigned int hwcfg = smsc911x_reg_read(pdata, HW_CFG);
  539. if (pdata->config.flags & SMSC911X_FORCE_INTERNAL_PHY) {
  540. SMSC_TRACE(pdata, hw, "Forcing internal PHY");
  541. pdata->using_extphy = 0;
  542. } else if (pdata->config.flags & SMSC911X_FORCE_EXTERNAL_PHY) {
  543. SMSC_TRACE(pdata, hw, "Forcing external PHY");
  544. smsc911x_phy_enable_external(pdata);
  545. pdata->using_extphy = 1;
  546. } else if (hwcfg & HW_CFG_EXT_PHY_DET_) {
  547. SMSC_TRACE(pdata, hw,
  548. "HW_CFG EXT_PHY_DET set, using external PHY");
  549. smsc911x_phy_enable_external(pdata);
  550. pdata->using_extphy = 1;
  551. } else {
  552. SMSC_TRACE(pdata, hw,
  553. "HW_CFG EXT_PHY_DET clear, using internal PHY");
  554. pdata->using_extphy = 0;
  555. }
  556. }
  557. /* Fetches a tx status out of the status fifo */
  558. static unsigned int smsc911x_tx_get_txstatus(struct smsc911x_data *pdata)
  559. {
  560. unsigned int result =
  561. smsc911x_reg_read(pdata, TX_FIFO_INF) & TX_FIFO_INF_TSUSED_;
  562. if (result != 0)
  563. result = smsc911x_reg_read(pdata, TX_STATUS_FIFO);
  564. return result;
  565. }
  566. /* Fetches the next rx status */
  567. static unsigned int smsc911x_rx_get_rxstatus(struct smsc911x_data *pdata)
  568. {
  569. unsigned int result =
  570. smsc911x_reg_read(pdata, RX_FIFO_INF) & RX_FIFO_INF_RXSUSED_;
  571. if (result != 0)
  572. result = smsc911x_reg_read(pdata, RX_STATUS_FIFO);
  573. return result;
  574. }
  575. #ifdef USE_PHY_WORK_AROUND
  576. static int smsc911x_phy_check_loopbackpkt(struct smsc911x_data *pdata)
  577. {
  578. unsigned int tries;
  579. u32 wrsz;
  580. u32 rdsz;
  581. ulong bufp;
  582. for (tries = 0; tries < 10; tries++) {
  583. unsigned int txcmd_a;
  584. unsigned int txcmd_b;
  585. unsigned int status;
  586. unsigned int pktlength;
  587. unsigned int i;
  588. /* Zero-out rx packet memory */
  589. memset(pdata->loopback_rx_pkt, 0, MIN_PACKET_SIZE);
  590. /* Write tx packet to 118 */
  591. txcmd_a = (u32)((ulong)pdata->loopback_tx_pkt & 0x03) << 16;
  592. txcmd_a |= TX_CMD_A_FIRST_SEG_ | TX_CMD_A_LAST_SEG_;
  593. txcmd_a |= MIN_PACKET_SIZE;
  594. txcmd_b = MIN_PACKET_SIZE << 16 | MIN_PACKET_SIZE;
  595. smsc911x_reg_write(pdata, TX_DATA_FIFO, txcmd_a);
  596. smsc911x_reg_write(pdata, TX_DATA_FIFO, txcmd_b);
  597. bufp = (ulong)pdata->loopback_tx_pkt & (~0x3);
  598. wrsz = MIN_PACKET_SIZE + 3;
  599. wrsz += (u32)((ulong)pdata->loopback_tx_pkt & 0x3);
  600. wrsz >>= 2;
  601. pdata->ops->tx_writefifo(pdata, (unsigned int *)bufp, wrsz);
  602. /* Wait till transmit is done */
  603. i = 60;
  604. do {
  605. udelay(5);
  606. status = smsc911x_tx_get_txstatus(pdata);
  607. } while ((i--) && (!status));
  608. if (!status) {
  609. SMSC_WARN(pdata, hw,
  610. "Failed to transmit during loopback test");
  611. continue;
  612. }
  613. if (status & TX_STS_ES_) {
  614. SMSC_WARN(pdata, hw,
  615. "Transmit encountered errors during loopback test");
  616. continue;
  617. }
  618. /* Wait till receive is done */
  619. i = 60;
  620. do {
  621. udelay(5);
  622. status = smsc911x_rx_get_rxstatus(pdata);
  623. } while ((i--) && (!status));
  624. if (!status) {
  625. SMSC_WARN(pdata, hw,
  626. "Failed to receive during loopback test");
  627. continue;
  628. }
  629. if (status & RX_STS_ES_) {
  630. SMSC_WARN(pdata, hw,
  631. "Receive encountered errors during loopback test");
  632. continue;
  633. }
  634. pktlength = ((status & 0x3FFF0000UL) >> 16);
  635. bufp = (ulong)pdata->loopback_rx_pkt;
  636. rdsz = pktlength + 3;
  637. rdsz += (u32)((ulong)pdata->loopback_rx_pkt & 0x3);
  638. rdsz >>= 2;
  639. pdata->ops->rx_readfifo(pdata, (unsigned int *)bufp, rdsz);
  640. if (pktlength != (MIN_PACKET_SIZE + 4)) {
  641. SMSC_WARN(pdata, hw, "Unexpected packet size "
  642. "during loop back test, size=%d, will retry",
  643. pktlength);
  644. } else {
  645. unsigned int j;
  646. int mismatch = 0;
  647. for (j = 0; j < MIN_PACKET_SIZE; j++) {
  648. if (pdata->loopback_tx_pkt[j]
  649. != pdata->loopback_rx_pkt[j]) {
  650. mismatch = 1;
  651. break;
  652. }
  653. }
  654. if (!mismatch) {
  655. SMSC_TRACE(pdata, hw, "Successfully verified "
  656. "loopback packet");
  657. return 0;
  658. } else {
  659. SMSC_WARN(pdata, hw, "Data mismatch "
  660. "during loop back test, will retry");
  661. }
  662. }
  663. }
  664. return -EIO;
  665. }
  666. static int smsc911x_phy_reset(struct smsc911x_data *pdata)
  667. {
  668. struct phy_device *phy_dev = pdata->phy_dev;
  669. unsigned int temp;
  670. unsigned int i = 100000;
  671. BUG_ON(!phy_dev);
  672. BUG_ON(!phy_dev->bus);
  673. SMSC_TRACE(pdata, hw, "Performing PHY BCR Reset");
  674. smsc911x_mii_write(phy_dev->bus, phy_dev->addr, MII_BMCR, BMCR_RESET);
  675. do {
  676. msleep(1);
  677. temp = smsc911x_mii_read(phy_dev->bus, phy_dev->addr,
  678. MII_BMCR);
  679. } while ((i--) && (temp & BMCR_RESET));
  680. if (temp & BMCR_RESET) {
  681. SMSC_WARN(pdata, hw, "PHY reset failed to complete");
  682. return -EIO;
  683. }
  684. /* Extra delay required because the phy may not be completed with
  685. * its reset when BMCR_RESET is cleared. Specs say 256 uS is
  686. * enough delay but using 1ms here to be safe */
  687. msleep(1);
  688. return 0;
  689. }
  690. static int smsc911x_phy_loopbacktest(struct net_device *dev)
  691. {
  692. struct smsc911x_data *pdata = netdev_priv(dev);
  693. struct phy_device *phy_dev = pdata->phy_dev;
  694. int result = -EIO;
  695. unsigned int i, val;
  696. unsigned long flags;
  697. /* Initialise tx packet using broadcast destination address */
  698. eth_broadcast_addr(pdata->loopback_tx_pkt);
  699. /* Use incrementing source address */
  700. for (i = 6; i < 12; i++)
  701. pdata->loopback_tx_pkt[i] = (char)i;
  702. /* Set length type field */
  703. pdata->loopback_tx_pkt[12] = 0x00;
  704. pdata->loopback_tx_pkt[13] = 0x00;
  705. for (i = 14; i < MIN_PACKET_SIZE; i++)
  706. pdata->loopback_tx_pkt[i] = (char)i;
  707. val = smsc911x_reg_read(pdata, HW_CFG);
  708. val &= HW_CFG_TX_FIF_SZ_;
  709. val |= HW_CFG_SF_;
  710. smsc911x_reg_write(pdata, HW_CFG, val);
  711. smsc911x_reg_write(pdata, TX_CFG, TX_CFG_TX_ON_);
  712. smsc911x_reg_write(pdata, RX_CFG,
  713. (u32)((ulong)pdata->loopback_rx_pkt & 0x03) << 8);
  714. for (i = 0; i < 10; i++) {
  715. /* Set PHY to 10/FD, no ANEG, and loopback mode */
  716. smsc911x_mii_write(phy_dev->bus, phy_dev->addr, MII_BMCR,
  717. BMCR_LOOPBACK | BMCR_FULLDPLX);
  718. /* Enable MAC tx/rx, FD */
  719. spin_lock_irqsave(&pdata->mac_lock, flags);
  720. smsc911x_mac_write(pdata, MAC_CR, MAC_CR_FDPX_
  721. | MAC_CR_TXEN_ | MAC_CR_RXEN_);
  722. spin_unlock_irqrestore(&pdata->mac_lock, flags);
  723. if (smsc911x_phy_check_loopbackpkt(pdata) == 0) {
  724. result = 0;
  725. break;
  726. }
  727. pdata->resetcount++;
  728. /* Disable MAC rx */
  729. spin_lock_irqsave(&pdata->mac_lock, flags);
  730. smsc911x_mac_write(pdata, MAC_CR, 0);
  731. spin_unlock_irqrestore(&pdata->mac_lock, flags);
  732. smsc911x_phy_reset(pdata);
  733. }
  734. /* Disable MAC */
  735. spin_lock_irqsave(&pdata->mac_lock, flags);
  736. smsc911x_mac_write(pdata, MAC_CR, 0);
  737. spin_unlock_irqrestore(&pdata->mac_lock, flags);
  738. /* Cancel PHY loopback mode */
  739. smsc911x_mii_write(phy_dev->bus, phy_dev->addr, MII_BMCR, 0);
  740. smsc911x_reg_write(pdata, TX_CFG, 0);
  741. smsc911x_reg_write(pdata, RX_CFG, 0);
  742. return result;
  743. }
  744. #endif /* USE_PHY_WORK_AROUND */
  745. static void smsc911x_phy_update_flowcontrol(struct smsc911x_data *pdata)
  746. {
  747. struct phy_device *phy_dev = pdata->phy_dev;
  748. u32 afc = smsc911x_reg_read(pdata, AFC_CFG);
  749. u32 flow;
  750. unsigned long flags;
  751. if (phy_dev->duplex == DUPLEX_FULL) {
  752. u16 lcladv = phy_read(phy_dev, MII_ADVERTISE);
  753. u16 rmtadv = phy_read(phy_dev, MII_LPA);
  754. u8 cap = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
  755. if (cap & FLOW_CTRL_RX)
  756. flow = 0xFFFF0002;
  757. else
  758. flow = 0;
  759. if (cap & FLOW_CTRL_TX)
  760. afc |= 0xF;
  761. else
  762. afc &= ~0xF;
  763. SMSC_TRACE(pdata, hw, "rx pause %s, tx pause %s",
  764. (cap & FLOW_CTRL_RX ? "enabled" : "disabled"),
  765. (cap & FLOW_CTRL_TX ? "enabled" : "disabled"));
  766. } else {
  767. SMSC_TRACE(pdata, hw, "half duplex");
  768. flow = 0;
  769. afc |= 0xF;
  770. }
  771. spin_lock_irqsave(&pdata->mac_lock, flags);
  772. smsc911x_mac_write(pdata, FLOW, flow);
  773. spin_unlock_irqrestore(&pdata->mac_lock, flags);
  774. smsc911x_reg_write(pdata, AFC_CFG, afc);
  775. }
  776. /* Update link mode if anything has changed. Called periodically when the
  777. * PHY is in polling mode, even if nothing has changed. */
  778. static void smsc911x_phy_adjust_link(struct net_device *dev)
  779. {
  780. struct smsc911x_data *pdata = netdev_priv(dev);
  781. struct phy_device *phy_dev = pdata->phy_dev;
  782. unsigned long flags;
  783. int carrier;
  784. if (phy_dev->duplex != pdata->last_duplex) {
  785. unsigned int mac_cr;
  786. SMSC_TRACE(pdata, hw, "duplex state has changed");
  787. spin_lock_irqsave(&pdata->mac_lock, flags);
  788. mac_cr = smsc911x_mac_read(pdata, MAC_CR);
  789. if (phy_dev->duplex) {
  790. SMSC_TRACE(pdata, hw,
  791. "configuring for full duplex mode");
  792. mac_cr |= MAC_CR_FDPX_;
  793. } else {
  794. SMSC_TRACE(pdata, hw,
  795. "configuring for half duplex mode");
  796. mac_cr &= ~MAC_CR_FDPX_;
  797. }
  798. smsc911x_mac_write(pdata, MAC_CR, mac_cr);
  799. spin_unlock_irqrestore(&pdata->mac_lock, flags);
  800. smsc911x_phy_update_flowcontrol(pdata);
  801. pdata->last_duplex = phy_dev->duplex;
  802. }
  803. carrier = netif_carrier_ok(dev);
  804. if (carrier != pdata->last_carrier) {
  805. SMSC_TRACE(pdata, hw, "carrier state has changed");
  806. if (carrier) {
  807. SMSC_TRACE(pdata, hw, "configuring for carrier OK");
  808. if ((pdata->gpio_orig_setting & GPIO_CFG_LED1_EN_) &&
  809. (!pdata->using_extphy)) {
  810. /* Restore original GPIO configuration */
  811. pdata->gpio_setting = pdata->gpio_orig_setting;
  812. smsc911x_reg_write(pdata, GPIO_CFG,
  813. pdata->gpio_setting);
  814. }
  815. } else {
  816. SMSC_TRACE(pdata, hw, "configuring for no carrier");
  817. /* Check global setting that LED1
  818. * usage is 10/100 indicator */
  819. pdata->gpio_setting = smsc911x_reg_read(pdata,
  820. GPIO_CFG);
  821. if ((pdata->gpio_setting & GPIO_CFG_LED1_EN_) &&
  822. (!pdata->using_extphy)) {
  823. /* Force 10/100 LED off, after saving
  824. * original GPIO configuration */
  825. pdata->gpio_orig_setting = pdata->gpio_setting;
  826. pdata->gpio_setting &= ~GPIO_CFG_LED1_EN_;
  827. pdata->gpio_setting |= (GPIO_CFG_GPIOBUF0_
  828. | GPIO_CFG_GPIODIR0_
  829. | GPIO_CFG_GPIOD0_);
  830. smsc911x_reg_write(pdata, GPIO_CFG,
  831. pdata->gpio_setting);
  832. }
  833. }
  834. pdata->last_carrier = carrier;
  835. }
  836. }
  837. static int smsc911x_mii_probe(struct net_device *dev)
  838. {
  839. struct smsc911x_data *pdata = netdev_priv(dev);
  840. struct phy_device *phydev = NULL;
  841. int ret;
  842. /* find the first phy */
  843. phydev = phy_find_first(pdata->mii_bus);
  844. if (!phydev) {
  845. netdev_err(dev, "no PHY found\n");
  846. return -ENODEV;
  847. }
  848. SMSC_TRACE(pdata, probe, "PHY: addr %d, phy_id 0x%08X",
  849. phydev->addr, phydev->phy_id);
  850. ret = phy_connect_direct(dev, phydev, &smsc911x_phy_adjust_link,
  851. pdata->config.phy_interface);
  852. if (ret) {
  853. netdev_err(dev, "Could not attach to PHY\n");
  854. return ret;
  855. }
  856. netdev_info(dev,
  857. "attached PHY driver [%s] (mii_bus:phy_addr=%s, irq=%d)\n",
  858. phydev->drv->name, dev_name(&phydev->dev), phydev->irq);
  859. /* mask with MAC supported features */
  860. phydev->supported &= (PHY_BASIC_FEATURES | SUPPORTED_Pause |
  861. SUPPORTED_Asym_Pause);
  862. phydev->advertising = phydev->supported;
  863. pdata->phy_dev = phydev;
  864. pdata->last_duplex = -1;
  865. pdata->last_carrier = -1;
  866. #ifdef USE_PHY_WORK_AROUND
  867. if (smsc911x_phy_loopbacktest(dev) < 0) {
  868. SMSC_WARN(pdata, hw, "Failed Loop Back Test");
  869. return -ENODEV;
  870. }
  871. SMSC_TRACE(pdata, hw, "Passed Loop Back Test");
  872. #endif /* USE_PHY_WORK_AROUND */
  873. SMSC_TRACE(pdata, hw, "phy initialised successfully");
  874. return 0;
  875. }
  876. static int smsc911x_mii_init(struct platform_device *pdev,
  877. struct net_device *dev)
  878. {
  879. struct smsc911x_data *pdata = netdev_priv(dev);
  880. int err = -ENXIO, i;
  881. pdata->mii_bus = mdiobus_alloc();
  882. if (!pdata->mii_bus) {
  883. err = -ENOMEM;
  884. goto err_out_1;
  885. }
  886. pdata->mii_bus->name = SMSC_MDIONAME;
  887. snprintf(pdata->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
  888. pdev->name, pdev->id);
  889. pdata->mii_bus->priv = pdata;
  890. pdata->mii_bus->read = smsc911x_mii_read;
  891. pdata->mii_bus->write = smsc911x_mii_write;
  892. pdata->mii_bus->irq = pdata->phy_irq;
  893. for (i = 0; i < PHY_MAX_ADDR; ++i)
  894. pdata->mii_bus->irq[i] = PHY_POLL;
  895. pdata->mii_bus->parent = &pdev->dev;
  896. switch (pdata->idrev & 0xFFFF0000) {
  897. case 0x01170000:
  898. case 0x01150000:
  899. case 0x117A0000:
  900. case 0x115A0000:
  901. /* External PHY supported, try to autodetect */
  902. smsc911x_phy_initialise_external(pdata);
  903. break;
  904. default:
  905. SMSC_TRACE(pdata, hw, "External PHY is not supported, "
  906. "using internal PHY");
  907. pdata->using_extphy = 0;
  908. break;
  909. }
  910. if (!pdata->using_extphy) {
  911. /* Mask all PHYs except ID 1 (internal) */
  912. pdata->mii_bus->phy_mask = ~(1 << 1);
  913. }
  914. if (mdiobus_register(pdata->mii_bus)) {
  915. SMSC_WARN(pdata, probe, "Error registering mii bus");
  916. goto err_out_free_bus_2;
  917. }
  918. if (smsc911x_mii_probe(dev) < 0) {
  919. SMSC_WARN(pdata, probe, "Error registering mii bus");
  920. goto err_out_unregister_bus_3;
  921. }
  922. return 0;
  923. err_out_unregister_bus_3:
  924. mdiobus_unregister(pdata->mii_bus);
  925. err_out_free_bus_2:
  926. mdiobus_free(pdata->mii_bus);
  927. err_out_1:
  928. return err;
  929. }
  930. /* Gets the number of tx statuses in the fifo */
  931. static unsigned int smsc911x_tx_get_txstatcount(struct smsc911x_data *pdata)
  932. {
  933. return (smsc911x_reg_read(pdata, TX_FIFO_INF)
  934. & TX_FIFO_INF_TSUSED_) >> 16;
  935. }
  936. /* Reads tx statuses and increments counters where necessary */
  937. static void smsc911x_tx_update_txcounters(struct net_device *dev)
  938. {
  939. struct smsc911x_data *pdata = netdev_priv(dev);
  940. unsigned int tx_stat;
  941. while ((tx_stat = smsc911x_tx_get_txstatus(pdata)) != 0) {
  942. if (unlikely(tx_stat & 0x80000000)) {
  943. /* In this driver the packet tag is used as the packet
  944. * length. Since a packet length can never reach the
  945. * size of 0x8000, this bit is reserved. It is worth
  946. * noting that the "reserved bit" in the warning above
  947. * does not reference a hardware defined reserved bit
  948. * but rather a driver defined one.
  949. */
  950. SMSC_WARN(pdata, hw, "Packet tag reserved bit is high");
  951. } else {
  952. if (unlikely(tx_stat & TX_STS_ES_)) {
  953. dev->stats.tx_errors++;
  954. } else {
  955. dev->stats.tx_packets++;
  956. dev->stats.tx_bytes += (tx_stat >> 16);
  957. }
  958. if (unlikely(tx_stat & TX_STS_EXCESS_COL_)) {
  959. dev->stats.collisions += 16;
  960. dev->stats.tx_aborted_errors += 1;
  961. } else {
  962. dev->stats.collisions +=
  963. ((tx_stat >> 3) & 0xF);
  964. }
  965. if (unlikely(tx_stat & TX_STS_LOST_CARRIER_))
  966. dev->stats.tx_carrier_errors += 1;
  967. if (unlikely(tx_stat & TX_STS_LATE_COL_)) {
  968. dev->stats.collisions++;
  969. dev->stats.tx_aborted_errors++;
  970. }
  971. }
  972. }
  973. }
  974. /* Increments the Rx error counters */
  975. static void
  976. smsc911x_rx_counterrors(struct net_device *dev, unsigned int rxstat)
  977. {
  978. int crc_err = 0;
  979. if (unlikely(rxstat & RX_STS_ES_)) {
  980. dev->stats.rx_errors++;
  981. if (unlikely(rxstat & RX_STS_CRC_ERR_)) {
  982. dev->stats.rx_crc_errors++;
  983. crc_err = 1;
  984. }
  985. }
  986. if (likely(!crc_err)) {
  987. if (unlikely((rxstat & RX_STS_FRAME_TYPE_) &&
  988. (rxstat & RX_STS_LENGTH_ERR_)))
  989. dev->stats.rx_length_errors++;
  990. if (rxstat & RX_STS_MCAST_)
  991. dev->stats.multicast++;
  992. }
  993. }
  994. /* Quickly dumps bad packets */
  995. static void
  996. smsc911x_rx_fastforward(struct smsc911x_data *pdata, unsigned int pktwords)
  997. {
  998. if (likely(pktwords >= 4)) {
  999. unsigned int timeout = 500;
  1000. unsigned int val;
  1001. smsc911x_reg_write(pdata, RX_DP_CTRL, RX_DP_CTRL_RX_FFWD_);
  1002. do {
  1003. udelay(1);
  1004. val = smsc911x_reg_read(pdata, RX_DP_CTRL);
  1005. } while ((val & RX_DP_CTRL_RX_FFWD_) && --timeout);
  1006. if (unlikely(timeout == 0))
  1007. SMSC_WARN(pdata, hw, "Timed out waiting for "
  1008. "RX FFWD to finish, RX_DP_CTRL: 0x%08X", val);
  1009. } else {
  1010. unsigned int temp;
  1011. while (pktwords--)
  1012. temp = smsc911x_reg_read(pdata, RX_DATA_FIFO);
  1013. }
  1014. }
  1015. /* NAPI poll function */
  1016. static int smsc911x_poll(struct napi_struct *napi, int budget)
  1017. {
  1018. struct smsc911x_data *pdata =
  1019. container_of(napi, struct smsc911x_data, napi);
  1020. struct net_device *dev = pdata->dev;
  1021. int npackets = 0;
  1022. while (npackets < budget) {
  1023. unsigned int pktlength;
  1024. unsigned int pktwords;
  1025. struct sk_buff *skb;
  1026. unsigned int rxstat = smsc911x_rx_get_rxstatus(pdata);
  1027. if (!rxstat) {
  1028. unsigned int temp;
  1029. /* We processed all packets available. Tell NAPI it can
  1030. * stop polling then re-enable rx interrupts */
  1031. smsc911x_reg_write(pdata, INT_STS, INT_STS_RSFL_);
  1032. napi_complete(napi);
  1033. temp = smsc911x_reg_read(pdata, INT_EN);
  1034. temp |= INT_EN_RSFL_EN_;
  1035. smsc911x_reg_write(pdata, INT_EN, temp);
  1036. break;
  1037. }
  1038. /* Count packet for NAPI scheduling, even if it has an error.
  1039. * Error packets still require cycles to discard */
  1040. npackets++;
  1041. pktlength = ((rxstat & 0x3FFF0000) >> 16);
  1042. pktwords = (pktlength + NET_IP_ALIGN + 3) >> 2;
  1043. smsc911x_rx_counterrors(dev, rxstat);
  1044. if (unlikely(rxstat & RX_STS_ES_)) {
  1045. SMSC_WARN(pdata, rx_err,
  1046. "Discarding packet with error bit set");
  1047. /* Packet has an error, discard it and continue with
  1048. * the next */
  1049. smsc911x_rx_fastforward(pdata, pktwords);
  1050. dev->stats.rx_dropped++;
  1051. continue;
  1052. }
  1053. skb = netdev_alloc_skb(dev, pktwords << 2);
  1054. if (unlikely(!skb)) {
  1055. SMSC_WARN(pdata, rx_err,
  1056. "Unable to allocate skb for rx packet");
  1057. /* Drop the packet and stop this polling iteration */
  1058. smsc911x_rx_fastforward(pdata, pktwords);
  1059. dev->stats.rx_dropped++;
  1060. break;
  1061. }
  1062. pdata->ops->rx_readfifo(pdata,
  1063. (unsigned int *)skb->data, pktwords);
  1064. /* Align IP on 16B boundary */
  1065. skb_reserve(skb, NET_IP_ALIGN);
  1066. skb_put(skb, pktlength - 4);
  1067. skb->protocol = eth_type_trans(skb, dev);
  1068. skb_checksum_none_assert(skb);
  1069. netif_receive_skb(skb);
  1070. /* Update counters */
  1071. dev->stats.rx_packets++;
  1072. dev->stats.rx_bytes += (pktlength - 4);
  1073. }
  1074. /* Return total received packets */
  1075. return npackets;
  1076. }
  1077. /* Returns hash bit number for given MAC address
  1078. * Example:
  1079. * 01 00 5E 00 00 01 -> returns bit number 31 */
  1080. static unsigned int smsc911x_hash(char addr[ETH_ALEN])
  1081. {
  1082. return (ether_crc(ETH_ALEN, addr) >> 26) & 0x3f;
  1083. }
  1084. static void smsc911x_rx_multicast_update(struct smsc911x_data *pdata)
  1085. {
  1086. /* Performs the multicast & mac_cr update. This is called when
  1087. * safe on the current hardware, and with the mac_lock held */
  1088. unsigned int mac_cr;
  1089. SMSC_ASSERT_MAC_LOCK(pdata);
  1090. mac_cr = smsc911x_mac_read(pdata, MAC_CR);
  1091. mac_cr |= pdata->set_bits_mask;
  1092. mac_cr &= ~(pdata->clear_bits_mask);
  1093. smsc911x_mac_write(pdata, MAC_CR, mac_cr);
  1094. smsc911x_mac_write(pdata, HASHH, pdata->hashhi);
  1095. smsc911x_mac_write(pdata, HASHL, pdata->hashlo);
  1096. SMSC_TRACE(pdata, hw, "maccr 0x%08X, HASHH 0x%08X, HASHL 0x%08X",
  1097. mac_cr, pdata->hashhi, pdata->hashlo);
  1098. }
  1099. static void smsc911x_rx_multicast_update_workaround(struct smsc911x_data *pdata)
  1100. {
  1101. unsigned int mac_cr;
  1102. /* This function is only called for older LAN911x devices
  1103. * (revA or revB), where MAC_CR, HASHH and HASHL should not
  1104. * be modified during Rx - newer devices immediately update the
  1105. * registers.
  1106. *
  1107. * This is called from interrupt context */
  1108. spin_lock(&pdata->mac_lock);
  1109. /* Check Rx has stopped */
  1110. if (smsc911x_mac_read(pdata, MAC_CR) & MAC_CR_RXEN_)
  1111. SMSC_WARN(pdata, drv, "Rx not stopped");
  1112. /* Perform the update - safe to do now Rx has stopped */
  1113. smsc911x_rx_multicast_update(pdata);
  1114. /* Re-enable Rx */
  1115. mac_cr = smsc911x_mac_read(pdata, MAC_CR);
  1116. mac_cr |= MAC_CR_RXEN_;
  1117. smsc911x_mac_write(pdata, MAC_CR, mac_cr);
  1118. pdata->multicast_update_pending = 0;
  1119. spin_unlock(&pdata->mac_lock);
  1120. }
  1121. static int smsc911x_phy_general_power_up(struct smsc911x_data *pdata)
  1122. {
  1123. int rc = 0;
  1124. if (!pdata->phy_dev)
  1125. return rc;
  1126. /* If the internal PHY is in General Power-Down mode, all, except the
  1127. * management interface, is powered-down and stays in that condition as
  1128. * long as Phy register bit 0.11 is HIGH.
  1129. *
  1130. * In that case, clear the bit 0.11, so the PHY powers up and we can
  1131. * access to the phy registers.
  1132. */
  1133. rc = phy_read(pdata->phy_dev, MII_BMCR);
  1134. if (rc < 0) {
  1135. SMSC_WARN(pdata, drv, "Failed reading PHY control reg");
  1136. return rc;
  1137. }
  1138. /* If the PHY general power-down bit is not set is not necessary to
  1139. * disable the general power down-mode.
  1140. */
  1141. if (rc & BMCR_PDOWN) {
  1142. rc = phy_write(pdata->phy_dev, MII_BMCR, rc & ~BMCR_PDOWN);
  1143. if (rc < 0) {
  1144. SMSC_WARN(pdata, drv, "Failed writing PHY control reg");
  1145. return rc;
  1146. }
  1147. usleep_range(1000, 1500);
  1148. }
  1149. return 0;
  1150. }
  1151. static int smsc911x_phy_disable_energy_detect(struct smsc911x_data *pdata)
  1152. {
  1153. int rc = 0;
  1154. if (!pdata->phy_dev)
  1155. return rc;
  1156. rc = phy_read(pdata->phy_dev, MII_LAN83C185_CTRL_STATUS);
  1157. if (rc < 0) {
  1158. SMSC_WARN(pdata, drv, "Failed reading PHY control reg");
  1159. return rc;
  1160. }
  1161. /* Only disable if energy detect mode is already enabled */
  1162. if (rc & MII_LAN83C185_EDPWRDOWN) {
  1163. /* Disable energy detect mode for this SMSC Transceivers */
  1164. rc = phy_write(pdata->phy_dev, MII_LAN83C185_CTRL_STATUS,
  1165. rc & (~MII_LAN83C185_EDPWRDOWN));
  1166. if (rc < 0) {
  1167. SMSC_WARN(pdata, drv, "Failed writing PHY control reg");
  1168. return rc;
  1169. }
  1170. /* Allow PHY to wakeup */
  1171. mdelay(2);
  1172. }
  1173. return 0;
  1174. }
  1175. static int smsc911x_phy_enable_energy_detect(struct smsc911x_data *pdata)
  1176. {
  1177. int rc = 0;
  1178. if (!pdata->phy_dev)
  1179. return rc;
  1180. rc = phy_read(pdata->phy_dev, MII_LAN83C185_CTRL_STATUS);
  1181. if (rc < 0) {
  1182. SMSC_WARN(pdata, drv, "Failed reading PHY control reg");
  1183. return rc;
  1184. }
  1185. /* Only enable if energy detect mode is already disabled */
  1186. if (!(rc & MII_LAN83C185_EDPWRDOWN)) {
  1187. /* Enable energy detect mode for this SMSC Transceivers */
  1188. rc = phy_write(pdata->phy_dev, MII_LAN83C185_CTRL_STATUS,
  1189. rc | MII_LAN83C185_EDPWRDOWN);
  1190. if (rc < 0) {
  1191. SMSC_WARN(pdata, drv, "Failed writing PHY control reg");
  1192. return rc;
  1193. }
  1194. }
  1195. return 0;
  1196. }
  1197. static int smsc911x_soft_reset(struct smsc911x_data *pdata)
  1198. {
  1199. unsigned int timeout;
  1200. unsigned int temp;
  1201. int ret;
  1202. /*
  1203. * Make sure to power-up the PHY chip before doing a reset, otherwise
  1204. * the reset fails.
  1205. */
  1206. ret = smsc911x_phy_general_power_up(pdata);
  1207. if (ret) {
  1208. SMSC_WARN(pdata, drv, "Failed to power-up the PHY chip");
  1209. return ret;
  1210. }
  1211. /*
  1212. * LAN9210/LAN9211/LAN9220/LAN9221 chips have an internal PHY that
  1213. * are initialized in a Energy Detect Power-Down mode that prevents
  1214. * the MAC chip to be software reseted. So we have to wakeup the PHY
  1215. * before.
  1216. */
  1217. if (pdata->generation == 4) {
  1218. ret = smsc911x_phy_disable_energy_detect(pdata);
  1219. if (ret) {
  1220. SMSC_WARN(pdata, drv, "Failed to wakeup the PHY chip");
  1221. return ret;
  1222. }
  1223. }
  1224. /* Reset the LAN911x */
  1225. smsc911x_reg_write(pdata, HW_CFG, HW_CFG_SRST_);
  1226. timeout = 10;
  1227. do {
  1228. udelay(10);
  1229. temp = smsc911x_reg_read(pdata, HW_CFG);
  1230. } while ((--timeout) && (temp & HW_CFG_SRST_));
  1231. if (unlikely(temp & HW_CFG_SRST_)) {
  1232. SMSC_WARN(pdata, drv, "Failed to complete reset");
  1233. return -EIO;
  1234. }
  1235. if (pdata->generation == 4) {
  1236. ret = smsc911x_phy_enable_energy_detect(pdata);
  1237. if (ret) {
  1238. SMSC_WARN(pdata, drv, "Failed to wakeup the PHY chip");
  1239. return ret;
  1240. }
  1241. }
  1242. return 0;
  1243. }
  1244. /* Sets the device MAC address to dev_addr, called with mac_lock held */
  1245. static void
  1246. smsc911x_set_hw_mac_address(struct smsc911x_data *pdata, u8 dev_addr[6])
  1247. {
  1248. u32 mac_high16 = (dev_addr[5] << 8) | dev_addr[4];
  1249. u32 mac_low32 = (dev_addr[3] << 24) | (dev_addr[2] << 16) |
  1250. (dev_addr[1] << 8) | dev_addr[0];
  1251. SMSC_ASSERT_MAC_LOCK(pdata);
  1252. smsc911x_mac_write(pdata, ADDRH, mac_high16);
  1253. smsc911x_mac_write(pdata, ADDRL, mac_low32);
  1254. }
  1255. static void smsc911x_disable_irq_chip(struct net_device *dev)
  1256. {
  1257. struct smsc911x_data *pdata = netdev_priv(dev);
  1258. smsc911x_reg_write(pdata, INT_EN, 0);
  1259. smsc911x_reg_write(pdata, INT_STS, 0xFFFFFFFF);
  1260. }
  1261. static int smsc911x_open(struct net_device *dev)
  1262. {
  1263. struct smsc911x_data *pdata = netdev_priv(dev);
  1264. unsigned int timeout;
  1265. unsigned int temp;
  1266. unsigned int intcfg;
  1267. /* if the phy is not yet registered, retry later*/
  1268. if (!pdata->phy_dev) {
  1269. SMSC_WARN(pdata, hw, "phy_dev is NULL");
  1270. return -EAGAIN;
  1271. }
  1272. /* Reset the LAN911x */
  1273. if (smsc911x_soft_reset(pdata)) {
  1274. SMSC_WARN(pdata, hw, "soft reset failed");
  1275. return -EIO;
  1276. }
  1277. smsc911x_reg_write(pdata, HW_CFG, 0x00050000);
  1278. smsc911x_reg_write(pdata, AFC_CFG, 0x006E3740);
  1279. /* Increase the legal frame size of VLAN tagged frames to 1522 bytes */
  1280. spin_lock_irq(&pdata->mac_lock);
  1281. smsc911x_mac_write(pdata, VLAN1, ETH_P_8021Q);
  1282. spin_unlock_irq(&pdata->mac_lock);
  1283. /* Make sure EEPROM has finished loading before setting GPIO_CFG */
  1284. timeout = 50;
  1285. while ((smsc911x_reg_read(pdata, E2P_CMD) & E2P_CMD_EPC_BUSY_) &&
  1286. --timeout) {
  1287. udelay(10);
  1288. }
  1289. if (unlikely(timeout == 0))
  1290. SMSC_WARN(pdata, ifup,
  1291. "Timed out waiting for EEPROM busy bit to clear");
  1292. smsc911x_reg_write(pdata, GPIO_CFG, 0x70070000);
  1293. /* The soft reset above cleared the device's MAC address,
  1294. * restore it from local copy (set in probe) */
  1295. spin_lock_irq(&pdata->mac_lock);
  1296. smsc911x_set_hw_mac_address(pdata, dev->dev_addr);
  1297. spin_unlock_irq(&pdata->mac_lock);
  1298. /* Initialise irqs, but leave all sources disabled */
  1299. smsc911x_disable_irq_chip(dev);
  1300. /* Set interrupt deassertion to 100uS */
  1301. intcfg = ((10 << 24) | INT_CFG_IRQ_EN_);
  1302. if (pdata->config.irq_polarity) {
  1303. SMSC_TRACE(pdata, ifup, "irq polarity: active high");
  1304. intcfg |= INT_CFG_IRQ_POL_;
  1305. } else {
  1306. SMSC_TRACE(pdata, ifup, "irq polarity: active low");
  1307. }
  1308. if (pdata->config.irq_type) {
  1309. SMSC_TRACE(pdata, ifup, "irq type: push-pull");
  1310. intcfg |= INT_CFG_IRQ_TYPE_;
  1311. } else {
  1312. SMSC_TRACE(pdata, ifup, "irq type: open drain");
  1313. }
  1314. smsc911x_reg_write(pdata, INT_CFG, intcfg);
  1315. SMSC_TRACE(pdata, ifup, "Testing irq handler using IRQ %d", dev->irq);
  1316. pdata->software_irq_signal = 0;
  1317. smp_wmb();
  1318. temp = smsc911x_reg_read(pdata, INT_EN);
  1319. temp |= INT_EN_SW_INT_EN_;
  1320. smsc911x_reg_write(pdata, INT_EN, temp);
  1321. timeout = 1000;
  1322. while (timeout--) {
  1323. if (pdata->software_irq_signal)
  1324. break;
  1325. msleep(1);
  1326. }
  1327. if (!pdata->software_irq_signal) {
  1328. netdev_warn(dev, "ISR failed signaling test (IRQ %d)\n",
  1329. dev->irq);
  1330. return -ENODEV;
  1331. }
  1332. SMSC_TRACE(pdata, ifup, "IRQ handler passed test using IRQ %d",
  1333. dev->irq);
  1334. netdev_info(dev, "SMSC911x/921x identified at %#08lx, IRQ: %d\n",
  1335. (unsigned long)pdata->ioaddr, dev->irq);
  1336. /* Reset the last known duplex and carrier */
  1337. pdata->last_duplex = -1;
  1338. pdata->last_carrier = -1;
  1339. /* Bring the PHY up */
  1340. phy_start(pdata->phy_dev);
  1341. temp = smsc911x_reg_read(pdata, HW_CFG);
  1342. /* Preserve TX FIFO size and external PHY configuration */
  1343. temp &= (HW_CFG_TX_FIF_SZ_|0x00000FFF);
  1344. temp |= HW_CFG_SF_;
  1345. smsc911x_reg_write(pdata, HW_CFG, temp);
  1346. temp = smsc911x_reg_read(pdata, FIFO_INT);
  1347. temp |= FIFO_INT_TX_AVAIL_LEVEL_;
  1348. temp &= ~(FIFO_INT_RX_STS_LEVEL_);
  1349. smsc911x_reg_write(pdata, FIFO_INT, temp);
  1350. /* set RX Data offset to 2 bytes for alignment */
  1351. smsc911x_reg_write(pdata, RX_CFG, (NET_IP_ALIGN << 8));
  1352. /* enable NAPI polling before enabling RX interrupts */
  1353. napi_enable(&pdata->napi);
  1354. temp = smsc911x_reg_read(pdata, INT_EN);
  1355. temp |= (INT_EN_TDFA_EN_ | INT_EN_RSFL_EN_ | INT_EN_RXSTOP_INT_EN_);
  1356. smsc911x_reg_write(pdata, INT_EN, temp);
  1357. spin_lock_irq(&pdata->mac_lock);
  1358. temp = smsc911x_mac_read(pdata, MAC_CR);
  1359. temp |= (MAC_CR_TXEN_ | MAC_CR_RXEN_ | MAC_CR_HBDIS_);
  1360. smsc911x_mac_write(pdata, MAC_CR, temp);
  1361. spin_unlock_irq(&pdata->mac_lock);
  1362. smsc911x_reg_write(pdata, TX_CFG, TX_CFG_TX_ON_);
  1363. netif_start_queue(dev);
  1364. return 0;
  1365. }
  1366. /* Entry point for stopping the interface */
  1367. static int smsc911x_stop(struct net_device *dev)
  1368. {
  1369. struct smsc911x_data *pdata = netdev_priv(dev);
  1370. unsigned int temp;
  1371. /* Disable all device interrupts */
  1372. temp = smsc911x_reg_read(pdata, INT_CFG);
  1373. temp &= ~INT_CFG_IRQ_EN_;
  1374. smsc911x_reg_write(pdata, INT_CFG, temp);
  1375. /* Stop Tx and Rx polling */
  1376. netif_stop_queue(dev);
  1377. napi_disable(&pdata->napi);
  1378. /* At this point all Rx and Tx activity is stopped */
  1379. dev->stats.rx_dropped += smsc911x_reg_read(pdata, RX_DROP);
  1380. smsc911x_tx_update_txcounters(dev);
  1381. /* Bring the PHY down */
  1382. if (pdata->phy_dev)
  1383. phy_stop(pdata->phy_dev);
  1384. SMSC_TRACE(pdata, ifdown, "Interface stopped");
  1385. return 0;
  1386. }
  1387. /* Entry point for transmitting a packet */
  1388. static int smsc911x_hard_start_xmit(struct sk_buff *skb, struct net_device *dev)
  1389. {
  1390. struct smsc911x_data *pdata = netdev_priv(dev);
  1391. unsigned int freespace;
  1392. unsigned int tx_cmd_a;
  1393. unsigned int tx_cmd_b;
  1394. unsigned int temp;
  1395. u32 wrsz;
  1396. ulong bufp;
  1397. freespace = smsc911x_reg_read(pdata, TX_FIFO_INF) & TX_FIFO_INF_TDFREE_;
  1398. if (unlikely(freespace < TX_FIFO_LOW_THRESHOLD))
  1399. SMSC_WARN(pdata, tx_err,
  1400. "Tx data fifo low, space available: %d", freespace);
  1401. /* Word alignment adjustment */
  1402. tx_cmd_a = (u32)((ulong)skb->data & 0x03) << 16;
  1403. tx_cmd_a |= TX_CMD_A_FIRST_SEG_ | TX_CMD_A_LAST_SEG_;
  1404. tx_cmd_a |= (unsigned int)skb->len;
  1405. tx_cmd_b = ((unsigned int)skb->len) << 16;
  1406. tx_cmd_b |= (unsigned int)skb->len;
  1407. smsc911x_reg_write(pdata, TX_DATA_FIFO, tx_cmd_a);
  1408. smsc911x_reg_write(pdata, TX_DATA_FIFO, tx_cmd_b);
  1409. bufp = (ulong)skb->data & (~0x3);
  1410. wrsz = (u32)skb->len + 3;
  1411. wrsz += (u32)((ulong)skb->data & 0x3);
  1412. wrsz >>= 2;
  1413. pdata->ops->tx_writefifo(pdata, (unsigned int *)bufp, wrsz);
  1414. freespace -= (skb->len + 32);
  1415. skb_tx_timestamp(skb);
  1416. dev_consume_skb_any(skb);
  1417. if (unlikely(smsc911x_tx_get_txstatcount(pdata) >= 30))
  1418. smsc911x_tx_update_txcounters(dev);
  1419. if (freespace < TX_FIFO_LOW_THRESHOLD) {
  1420. netif_stop_queue(dev);
  1421. temp = smsc911x_reg_read(pdata, FIFO_INT);
  1422. temp &= 0x00FFFFFF;
  1423. temp |= 0x32000000;
  1424. smsc911x_reg_write(pdata, FIFO_INT, temp);
  1425. }
  1426. return NETDEV_TX_OK;
  1427. }
  1428. /* Entry point for getting status counters */
  1429. static struct net_device_stats *smsc911x_get_stats(struct net_device *dev)
  1430. {
  1431. struct smsc911x_data *pdata = netdev_priv(dev);
  1432. smsc911x_tx_update_txcounters(dev);
  1433. dev->stats.rx_dropped += smsc911x_reg_read(pdata, RX_DROP);
  1434. return &dev->stats;
  1435. }
  1436. /* Entry point for setting addressing modes */
  1437. static void smsc911x_set_multicast_list(struct net_device *dev)
  1438. {
  1439. struct smsc911x_data *pdata = netdev_priv(dev);
  1440. unsigned long flags;
  1441. if (dev->flags & IFF_PROMISC) {
  1442. /* Enabling promiscuous mode */
  1443. pdata->set_bits_mask = MAC_CR_PRMS_;
  1444. pdata->clear_bits_mask = (MAC_CR_MCPAS_ | MAC_CR_HPFILT_);
  1445. pdata->hashhi = 0;
  1446. pdata->hashlo = 0;
  1447. } else if (dev->flags & IFF_ALLMULTI) {
  1448. /* Enabling all multicast mode */
  1449. pdata->set_bits_mask = MAC_CR_MCPAS_;
  1450. pdata->clear_bits_mask = (MAC_CR_PRMS_ | MAC_CR_HPFILT_);
  1451. pdata->hashhi = 0;
  1452. pdata->hashlo = 0;
  1453. } else if (!netdev_mc_empty(dev)) {
  1454. /* Enabling specific multicast addresses */
  1455. unsigned int hash_high = 0;
  1456. unsigned int hash_low = 0;
  1457. struct netdev_hw_addr *ha;
  1458. pdata->set_bits_mask = MAC_CR_HPFILT_;
  1459. pdata->clear_bits_mask = (MAC_CR_PRMS_ | MAC_CR_MCPAS_);
  1460. netdev_for_each_mc_addr(ha, dev) {
  1461. unsigned int bitnum = smsc911x_hash(ha->addr);
  1462. unsigned int mask = 0x01 << (bitnum & 0x1F);
  1463. if (bitnum & 0x20)
  1464. hash_high |= mask;
  1465. else
  1466. hash_low |= mask;
  1467. }
  1468. pdata->hashhi = hash_high;
  1469. pdata->hashlo = hash_low;
  1470. } else {
  1471. /* Enabling local MAC address only */
  1472. pdata->set_bits_mask = 0;
  1473. pdata->clear_bits_mask =
  1474. (MAC_CR_PRMS_ | MAC_CR_MCPAS_ | MAC_CR_HPFILT_);
  1475. pdata->hashhi = 0;
  1476. pdata->hashlo = 0;
  1477. }
  1478. spin_lock_irqsave(&pdata->mac_lock, flags);
  1479. if (pdata->generation <= 1) {
  1480. /* Older hardware revision - cannot change these flags while
  1481. * receiving data */
  1482. if (!pdata->multicast_update_pending) {
  1483. unsigned int temp;
  1484. SMSC_TRACE(pdata, hw, "scheduling mcast update");
  1485. pdata->multicast_update_pending = 1;
  1486. /* Request the hardware to stop, then perform the
  1487. * update when we get an RX_STOP interrupt */
  1488. temp = smsc911x_mac_read(pdata, MAC_CR);
  1489. temp &= ~(MAC_CR_RXEN_);
  1490. smsc911x_mac_write(pdata, MAC_CR, temp);
  1491. } else {
  1492. /* There is another update pending, this should now
  1493. * use the newer values */
  1494. }
  1495. } else {
  1496. /* Newer hardware revision - can write immediately */
  1497. smsc911x_rx_multicast_update(pdata);
  1498. }
  1499. spin_unlock_irqrestore(&pdata->mac_lock, flags);
  1500. }
  1501. static irqreturn_t smsc911x_irqhandler(int irq, void *dev_id)
  1502. {
  1503. struct net_device *dev = dev_id;
  1504. struct smsc911x_data *pdata = netdev_priv(dev);
  1505. u32 intsts = smsc911x_reg_read(pdata, INT_STS);
  1506. u32 inten = smsc911x_reg_read(pdata, INT_EN);
  1507. int serviced = IRQ_NONE;
  1508. u32 temp;
  1509. if (unlikely(intsts & inten & INT_STS_SW_INT_)) {
  1510. temp = smsc911x_reg_read(pdata, INT_EN);
  1511. temp &= (~INT_EN_SW_INT_EN_);
  1512. smsc911x_reg_write(pdata, INT_EN, temp);
  1513. smsc911x_reg_write(pdata, INT_STS, INT_STS_SW_INT_);
  1514. pdata->software_irq_signal = 1;
  1515. smp_wmb();
  1516. serviced = IRQ_HANDLED;
  1517. }
  1518. if (unlikely(intsts & inten & INT_STS_RXSTOP_INT_)) {
  1519. /* Called when there is a multicast update scheduled and
  1520. * it is now safe to complete the update */
  1521. SMSC_TRACE(pdata, intr, "RX Stop interrupt");
  1522. smsc911x_reg_write(pdata, INT_STS, INT_STS_RXSTOP_INT_);
  1523. if (pdata->multicast_update_pending)
  1524. smsc911x_rx_multicast_update_workaround(pdata);
  1525. serviced = IRQ_HANDLED;
  1526. }
  1527. if (intsts & inten & INT_STS_TDFA_) {
  1528. temp = smsc911x_reg_read(pdata, FIFO_INT);
  1529. temp |= FIFO_INT_TX_AVAIL_LEVEL_;
  1530. smsc911x_reg_write(pdata, FIFO_INT, temp);
  1531. smsc911x_reg_write(pdata, INT_STS, INT_STS_TDFA_);
  1532. netif_wake_queue(dev);
  1533. serviced = IRQ_HANDLED;
  1534. }
  1535. if (unlikely(intsts & inten & INT_STS_RXE_)) {
  1536. SMSC_TRACE(pdata, intr, "RX Error interrupt");
  1537. smsc911x_reg_write(pdata, INT_STS, INT_STS_RXE_);
  1538. serviced = IRQ_HANDLED;
  1539. }
  1540. if (likely(intsts & inten & INT_STS_RSFL_)) {
  1541. if (likely(napi_schedule_prep(&pdata->napi))) {
  1542. /* Disable Rx interrupts */
  1543. temp = smsc911x_reg_read(pdata, INT_EN);
  1544. temp &= (~INT_EN_RSFL_EN_);
  1545. smsc911x_reg_write(pdata, INT_EN, temp);
  1546. /* Schedule a NAPI poll */
  1547. __napi_schedule(&pdata->napi);
  1548. } else {
  1549. SMSC_WARN(pdata, rx_err, "napi_schedule_prep failed");
  1550. }
  1551. serviced = IRQ_HANDLED;
  1552. }
  1553. return serviced;
  1554. }
  1555. #ifdef CONFIG_NET_POLL_CONTROLLER
  1556. static void smsc911x_poll_controller(struct net_device *dev)
  1557. {
  1558. disable_irq(dev->irq);
  1559. smsc911x_irqhandler(0, dev);
  1560. enable_irq(dev->irq);
  1561. }
  1562. #endif /* CONFIG_NET_POLL_CONTROLLER */
  1563. static int smsc911x_set_mac_address(struct net_device *dev, void *p)
  1564. {
  1565. struct smsc911x_data *pdata = netdev_priv(dev);
  1566. struct sockaddr *addr = p;
  1567. /* On older hardware revisions we cannot change the mac address
  1568. * registers while receiving data. Newer devices can safely change
  1569. * this at any time. */
  1570. if (pdata->generation <= 1 && netif_running(dev))
  1571. return -EBUSY;
  1572. if (!is_valid_ether_addr(addr->sa_data))
  1573. return -EADDRNOTAVAIL;
  1574. memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
  1575. spin_lock_irq(&pdata->mac_lock);
  1576. smsc911x_set_hw_mac_address(pdata, dev->dev_addr);
  1577. spin_unlock_irq(&pdata->mac_lock);
  1578. netdev_info(dev, "MAC Address: %pM\n", dev->dev_addr);
  1579. return 0;
  1580. }
  1581. /* Standard ioctls for mii-tool */
  1582. static int smsc911x_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
  1583. {
  1584. struct smsc911x_data *pdata = netdev_priv(dev);
  1585. if (!netif_running(dev) || !pdata->phy_dev)
  1586. return -EINVAL;
  1587. return phy_mii_ioctl(pdata->phy_dev, ifr, cmd);
  1588. }
  1589. static int
  1590. smsc911x_ethtool_getsettings(struct net_device *dev, struct ethtool_cmd *cmd)
  1591. {
  1592. struct smsc911x_data *pdata = netdev_priv(dev);
  1593. cmd->maxtxpkt = 1;
  1594. cmd->maxrxpkt = 1;
  1595. return phy_ethtool_gset(pdata->phy_dev, cmd);
  1596. }
  1597. static int
  1598. smsc911x_ethtool_setsettings(struct net_device *dev, struct ethtool_cmd *cmd)
  1599. {
  1600. struct smsc911x_data *pdata = netdev_priv(dev);
  1601. return phy_ethtool_sset(pdata->phy_dev, cmd);
  1602. }
  1603. static void smsc911x_ethtool_getdrvinfo(struct net_device *dev,
  1604. struct ethtool_drvinfo *info)
  1605. {
  1606. strlcpy(info->driver, SMSC_CHIPNAME, sizeof(info->driver));
  1607. strlcpy(info->version, SMSC_DRV_VERSION, sizeof(info->version));
  1608. strlcpy(info->bus_info, dev_name(dev->dev.parent),
  1609. sizeof(info->bus_info));
  1610. }
  1611. static int smsc911x_ethtool_nwayreset(struct net_device *dev)
  1612. {
  1613. struct smsc911x_data *pdata = netdev_priv(dev);
  1614. return phy_start_aneg(pdata->phy_dev);
  1615. }
  1616. static u32 smsc911x_ethtool_getmsglevel(struct net_device *dev)
  1617. {
  1618. struct smsc911x_data *pdata = netdev_priv(dev);
  1619. return pdata->msg_enable;
  1620. }
  1621. static void smsc911x_ethtool_setmsglevel(struct net_device *dev, u32 level)
  1622. {
  1623. struct smsc911x_data *pdata = netdev_priv(dev);
  1624. pdata->msg_enable = level;
  1625. }
  1626. static int smsc911x_ethtool_getregslen(struct net_device *dev)
  1627. {
  1628. return (((E2P_DATA - ID_REV) / 4 + 1) + (WUCSR - MAC_CR) + 1 + 32) *
  1629. sizeof(u32);
  1630. }
  1631. static void
  1632. smsc911x_ethtool_getregs(struct net_device *dev, struct ethtool_regs *regs,
  1633. void *buf)
  1634. {
  1635. struct smsc911x_data *pdata = netdev_priv(dev);
  1636. struct phy_device *phy_dev = pdata->phy_dev;
  1637. unsigned long flags;
  1638. unsigned int i;
  1639. unsigned int j = 0;
  1640. u32 *data = buf;
  1641. regs->version = pdata->idrev;
  1642. for (i = ID_REV; i <= E2P_DATA; i += (sizeof(u32)))
  1643. data[j++] = smsc911x_reg_read(pdata, i);
  1644. for (i = MAC_CR; i <= WUCSR; i++) {
  1645. spin_lock_irqsave(&pdata->mac_lock, flags);
  1646. data[j++] = smsc911x_mac_read(pdata, i);
  1647. spin_unlock_irqrestore(&pdata->mac_lock, flags);
  1648. }
  1649. for (i = 0; i <= 31; i++)
  1650. data[j++] = smsc911x_mii_read(phy_dev->bus, phy_dev->addr, i);
  1651. }
  1652. static void smsc911x_eeprom_enable_access(struct smsc911x_data *pdata)
  1653. {
  1654. unsigned int temp = smsc911x_reg_read(pdata, GPIO_CFG);
  1655. temp &= ~GPIO_CFG_EEPR_EN_;
  1656. smsc911x_reg_write(pdata, GPIO_CFG, temp);
  1657. msleep(1);
  1658. }
  1659. static int smsc911x_eeprom_send_cmd(struct smsc911x_data *pdata, u32 op)
  1660. {
  1661. int timeout = 100;
  1662. u32 e2cmd;
  1663. SMSC_TRACE(pdata, drv, "op 0x%08x", op);
  1664. if (smsc911x_reg_read(pdata, E2P_CMD) & E2P_CMD_EPC_BUSY_) {
  1665. SMSC_WARN(pdata, drv, "Busy at start");
  1666. return -EBUSY;
  1667. }
  1668. e2cmd = op | E2P_CMD_EPC_BUSY_;
  1669. smsc911x_reg_write(pdata, E2P_CMD, e2cmd);
  1670. do {
  1671. msleep(1);
  1672. e2cmd = smsc911x_reg_read(pdata, E2P_CMD);
  1673. } while ((e2cmd & E2P_CMD_EPC_BUSY_) && (--timeout));
  1674. if (!timeout) {
  1675. SMSC_TRACE(pdata, drv, "TIMED OUT");
  1676. return -EAGAIN;
  1677. }
  1678. if (e2cmd & E2P_CMD_EPC_TIMEOUT_) {
  1679. SMSC_TRACE(pdata, drv, "Error occurred during eeprom operation");
  1680. return -EINVAL;
  1681. }
  1682. return 0;
  1683. }
  1684. static int smsc911x_eeprom_read_location(struct smsc911x_data *pdata,
  1685. u8 address, u8 *data)
  1686. {
  1687. u32 op = E2P_CMD_EPC_CMD_READ_ | address;
  1688. int ret;
  1689. SMSC_TRACE(pdata, drv, "address 0x%x", address);
  1690. ret = smsc911x_eeprom_send_cmd(pdata, op);
  1691. if (!ret)
  1692. data[address] = smsc911x_reg_read(pdata, E2P_DATA);
  1693. return ret;
  1694. }
  1695. static int smsc911x_eeprom_write_location(struct smsc911x_data *pdata,
  1696. u8 address, u8 data)
  1697. {
  1698. u32 op = E2P_CMD_EPC_CMD_ERASE_ | address;
  1699. u32 temp;
  1700. int ret;
  1701. SMSC_TRACE(pdata, drv, "address 0x%x, data 0x%x", address, data);
  1702. ret = smsc911x_eeprom_send_cmd(pdata, op);
  1703. if (!ret) {
  1704. op = E2P_CMD_EPC_CMD_WRITE_ | address;
  1705. smsc911x_reg_write(pdata, E2P_DATA, (u32)data);
  1706. /* Workaround for hardware read-after-write restriction */
  1707. temp = smsc911x_reg_read(pdata, BYTE_TEST);
  1708. ret = smsc911x_eeprom_send_cmd(pdata, op);
  1709. }
  1710. return ret;
  1711. }
  1712. static int smsc911x_ethtool_get_eeprom_len(struct net_device *dev)
  1713. {
  1714. return SMSC911X_EEPROM_SIZE;
  1715. }
  1716. static int smsc911x_ethtool_get_eeprom(struct net_device *dev,
  1717. struct ethtool_eeprom *eeprom, u8 *data)
  1718. {
  1719. struct smsc911x_data *pdata = netdev_priv(dev);
  1720. u8 eeprom_data[SMSC911X_EEPROM_SIZE];
  1721. int len;
  1722. int i;
  1723. smsc911x_eeprom_enable_access(pdata);
  1724. len = min(eeprom->len, SMSC911X_EEPROM_SIZE);
  1725. for (i = 0; i < len; i++) {
  1726. int ret = smsc911x_eeprom_read_location(pdata, i, eeprom_data);
  1727. if (ret < 0) {
  1728. eeprom->len = 0;
  1729. return ret;
  1730. }
  1731. }
  1732. memcpy(data, &eeprom_data[eeprom->offset], len);
  1733. eeprom->len = len;
  1734. return 0;
  1735. }
  1736. static int smsc911x_ethtool_set_eeprom(struct net_device *dev,
  1737. struct ethtool_eeprom *eeprom, u8 *data)
  1738. {
  1739. int ret;
  1740. struct smsc911x_data *pdata = netdev_priv(dev);
  1741. smsc911x_eeprom_enable_access(pdata);
  1742. smsc911x_eeprom_send_cmd(pdata, E2P_CMD_EPC_CMD_EWEN_);
  1743. ret = smsc911x_eeprom_write_location(pdata, eeprom->offset, *data);
  1744. smsc911x_eeprom_send_cmd(pdata, E2P_CMD_EPC_CMD_EWDS_);
  1745. /* Single byte write, according to man page */
  1746. eeprom->len = 1;
  1747. return ret;
  1748. }
  1749. static const struct ethtool_ops smsc911x_ethtool_ops = {
  1750. .get_settings = smsc911x_ethtool_getsettings,
  1751. .set_settings = smsc911x_ethtool_setsettings,
  1752. .get_link = ethtool_op_get_link,
  1753. .get_drvinfo = smsc911x_ethtool_getdrvinfo,
  1754. .nway_reset = smsc911x_ethtool_nwayreset,
  1755. .get_msglevel = smsc911x_ethtool_getmsglevel,
  1756. .set_msglevel = smsc911x_ethtool_setmsglevel,
  1757. .get_regs_len = smsc911x_ethtool_getregslen,
  1758. .get_regs = smsc911x_ethtool_getregs,
  1759. .get_eeprom_len = smsc911x_ethtool_get_eeprom_len,
  1760. .get_eeprom = smsc911x_ethtool_get_eeprom,
  1761. .set_eeprom = smsc911x_ethtool_set_eeprom,
  1762. .get_ts_info = ethtool_op_get_ts_info,
  1763. };
  1764. static const struct net_device_ops smsc911x_netdev_ops = {
  1765. .ndo_open = smsc911x_open,
  1766. .ndo_stop = smsc911x_stop,
  1767. .ndo_start_xmit = smsc911x_hard_start_xmit,
  1768. .ndo_get_stats = smsc911x_get_stats,
  1769. .ndo_set_rx_mode = smsc911x_set_multicast_list,
  1770. .ndo_do_ioctl = smsc911x_do_ioctl,
  1771. .ndo_change_mtu = eth_change_mtu,
  1772. .ndo_validate_addr = eth_validate_addr,
  1773. .ndo_set_mac_address = smsc911x_set_mac_address,
  1774. #ifdef CONFIG_NET_POLL_CONTROLLER
  1775. .ndo_poll_controller = smsc911x_poll_controller,
  1776. #endif
  1777. };
  1778. /* copies the current mac address from hardware to dev->dev_addr */
  1779. static void smsc911x_read_mac_address(struct net_device *dev)
  1780. {
  1781. struct smsc911x_data *pdata = netdev_priv(dev);
  1782. u32 mac_high16 = smsc911x_mac_read(pdata, ADDRH);
  1783. u32 mac_low32 = smsc911x_mac_read(pdata, ADDRL);
  1784. dev->dev_addr[0] = (u8)(mac_low32);
  1785. dev->dev_addr[1] = (u8)(mac_low32 >> 8);
  1786. dev->dev_addr[2] = (u8)(mac_low32 >> 16);
  1787. dev->dev_addr[3] = (u8)(mac_low32 >> 24);
  1788. dev->dev_addr[4] = (u8)(mac_high16);
  1789. dev->dev_addr[5] = (u8)(mac_high16 >> 8);
  1790. }
  1791. /* Initializing private device structures, only called from probe */
  1792. static int smsc911x_init(struct net_device *dev)
  1793. {
  1794. struct smsc911x_data *pdata = netdev_priv(dev);
  1795. unsigned int byte_test, mask;
  1796. unsigned int to = 100;
  1797. SMSC_TRACE(pdata, probe, "Driver Parameters:");
  1798. SMSC_TRACE(pdata, probe, "LAN base: 0x%08lX",
  1799. (unsigned long)pdata->ioaddr);
  1800. SMSC_TRACE(pdata, probe, "IRQ: %d", dev->irq);
  1801. SMSC_TRACE(pdata, probe, "PHY will be autodetected.");
  1802. spin_lock_init(&pdata->dev_lock);
  1803. spin_lock_init(&pdata->mac_lock);
  1804. if (pdata->ioaddr == NULL) {
  1805. SMSC_WARN(pdata, probe, "pdata->ioaddr: 0x00000000");
  1806. return -ENODEV;
  1807. }
  1808. /*
  1809. * poll the READY bit in PMT_CTRL. Any other access to the device is
  1810. * forbidden while this bit isn't set. Try for 100ms
  1811. *
  1812. * Note that this test is done before the WORD_SWAP register is
  1813. * programmed. So in some configurations the READY bit is at 16 before
  1814. * WORD_SWAP is written to. This issue is worked around by waiting
  1815. * until either bit 0 or bit 16 gets set in PMT_CTRL.
  1816. *
  1817. * SMSC has confirmed that checking bit 16 (marked as reserved in
  1818. * the datasheet) is fine since these bits "will either never be set
  1819. * or can only go high after READY does (so also indicate the device
  1820. * is ready)".
  1821. */
  1822. mask = PMT_CTRL_READY_ | swahw32(PMT_CTRL_READY_);
  1823. while (!(smsc911x_reg_read(pdata, PMT_CTRL) & mask) && --to)
  1824. udelay(1000);
  1825. if (to == 0) {
  1826. netdev_err(dev, "Device not READY in 100ms aborting\n");
  1827. return -ENODEV;
  1828. }
  1829. /* Check byte ordering */
  1830. byte_test = smsc911x_reg_read(pdata, BYTE_TEST);
  1831. SMSC_TRACE(pdata, probe, "BYTE_TEST: 0x%08X", byte_test);
  1832. if (byte_test == 0x43218765) {
  1833. SMSC_TRACE(pdata, probe, "BYTE_TEST looks swapped, "
  1834. "applying WORD_SWAP");
  1835. smsc911x_reg_write(pdata, WORD_SWAP, 0xffffffff);
  1836. /* 1 dummy read of BYTE_TEST is needed after a write to
  1837. * WORD_SWAP before its contents are valid */
  1838. byte_test = smsc911x_reg_read(pdata, BYTE_TEST);
  1839. byte_test = smsc911x_reg_read(pdata, BYTE_TEST);
  1840. }
  1841. if (byte_test != 0x87654321) {
  1842. SMSC_WARN(pdata, drv, "BYTE_TEST: 0x%08X", byte_test);
  1843. if (((byte_test >> 16) & 0xFFFF) == (byte_test & 0xFFFF)) {
  1844. SMSC_WARN(pdata, probe,
  1845. "top 16 bits equal to bottom 16 bits");
  1846. SMSC_TRACE(pdata, probe,
  1847. "This may mean the chip is set "
  1848. "for 32 bit while the bus is reading 16 bit");
  1849. }
  1850. return -ENODEV;
  1851. }
  1852. /* Default generation to zero (all workarounds apply) */
  1853. pdata->generation = 0;
  1854. pdata->idrev = smsc911x_reg_read(pdata, ID_REV);
  1855. switch (pdata->idrev & 0xFFFF0000) {
  1856. case 0x01180000:
  1857. case 0x01170000:
  1858. case 0x01160000:
  1859. case 0x01150000:
  1860. case 0x218A0000:
  1861. /* LAN911[5678] family */
  1862. pdata->generation = pdata->idrev & 0x0000FFFF;
  1863. break;
  1864. case 0x118A0000:
  1865. case 0x117A0000:
  1866. case 0x116A0000:
  1867. case 0x115A0000:
  1868. /* LAN921[5678] family */
  1869. pdata->generation = 3;
  1870. break;
  1871. case 0x92100000:
  1872. case 0x92110000:
  1873. case 0x92200000:
  1874. case 0x92210000:
  1875. /* LAN9210/LAN9211/LAN9220/LAN9221 */
  1876. pdata->generation = 4;
  1877. break;
  1878. default:
  1879. SMSC_WARN(pdata, probe, "LAN911x not identified, idrev: 0x%08X",
  1880. pdata->idrev);
  1881. return -ENODEV;
  1882. }
  1883. SMSC_TRACE(pdata, probe,
  1884. "LAN911x identified, idrev: 0x%08X, generation: %d",
  1885. pdata->idrev, pdata->generation);
  1886. if (pdata->generation == 0)
  1887. SMSC_WARN(pdata, probe,
  1888. "This driver is not intended for this chip revision");
  1889. /* workaround for platforms without an eeprom, where the mac address
  1890. * is stored elsewhere and set by the bootloader. This saves the
  1891. * mac address before resetting the device */
  1892. if (pdata->config.flags & SMSC911X_SAVE_MAC_ADDRESS) {
  1893. spin_lock_irq(&pdata->mac_lock);
  1894. smsc911x_read_mac_address(dev);
  1895. spin_unlock_irq(&pdata->mac_lock);
  1896. }
  1897. /* Reset the LAN911x */
  1898. if (smsc911x_soft_reset(pdata))
  1899. return -ENODEV;
  1900. dev->flags |= IFF_MULTICAST;
  1901. netif_napi_add(dev, &pdata->napi, smsc911x_poll, SMSC_NAPI_WEIGHT);
  1902. dev->netdev_ops = &smsc911x_netdev_ops;
  1903. dev->ethtool_ops = &smsc911x_ethtool_ops;
  1904. return 0;
  1905. }
  1906. static int smsc911x_drv_remove(struct platform_device *pdev)
  1907. {
  1908. struct net_device *dev;
  1909. struct smsc911x_data *pdata;
  1910. struct resource *res;
  1911. dev = platform_get_drvdata(pdev);
  1912. BUG_ON(!dev);
  1913. pdata = netdev_priv(dev);
  1914. BUG_ON(!pdata);
  1915. BUG_ON(!pdata->ioaddr);
  1916. BUG_ON(!pdata->phy_dev);
  1917. SMSC_TRACE(pdata, ifdown, "Stopping driver");
  1918. phy_disconnect(pdata->phy_dev);
  1919. pdata->phy_dev = NULL;
  1920. mdiobus_unregister(pdata->mii_bus);
  1921. mdiobus_free(pdata->mii_bus);
  1922. unregister_netdev(dev);
  1923. free_irq(dev->irq, dev);
  1924. res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
  1925. "smsc911x-memory");
  1926. if (!res)
  1927. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  1928. release_mem_region(res->start, resource_size(res));
  1929. iounmap(pdata->ioaddr);
  1930. (void)smsc911x_disable_resources(pdev);
  1931. smsc911x_free_resources(pdev);
  1932. free_netdev(dev);
  1933. pm_runtime_put(&pdev->dev);
  1934. pm_runtime_disable(&pdev->dev);
  1935. return 0;
  1936. }
  1937. /* standard register acces */
  1938. static const struct smsc911x_ops standard_smsc911x_ops = {
  1939. .reg_read = __smsc911x_reg_read,
  1940. .reg_write = __smsc911x_reg_write,
  1941. .rx_readfifo = smsc911x_rx_readfifo,
  1942. .tx_writefifo = smsc911x_tx_writefifo,
  1943. };
  1944. /* shifted register access */
  1945. static const struct smsc911x_ops shifted_smsc911x_ops = {
  1946. .reg_read = __smsc911x_reg_read_shift,
  1947. .reg_write = __smsc911x_reg_write_shift,
  1948. .rx_readfifo = smsc911x_rx_readfifo_shift,
  1949. .tx_writefifo = smsc911x_tx_writefifo_shift,
  1950. };
  1951. static int smsc911x_probe_config(struct smsc911x_platform_config *config,
  1952. struct device *dev)
  1953. {
  1954. int phy_interface;
  1955. u32 width = 0;
  1956. int err;
  1957. phy_interface = device_get_phy_mode(dev);
  1958. if (phy_interface < 0)
  1959. phy_interface = PHY_INTERFACE_MODE_NA;
  1960. config->phy_interface = phy_interface;
  1961. device_get_mac_address(dev, config->mac, ETH_ALEN);
  1962. err = device_property_read_u32(dev, "reg-io-width", &width);
  1963. if (err == -ENXIO)
  1964. return err;
  1965. if (!err && width == 4)
  1966. config->flags |= SMSC911X_USE_32BIT;
  1967. else
  1968. config->flags |= SMSC911X_USE_16BIT;
  1969. device_property_read_u32(dev, "reg-shift", &config->shift);
  1970. if (device_property_present(dev, "smsc,irq-active-high"))
  1971. config->irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_HIGH;
  1972. if (device_property_present(dev, "smsc,irq-push-pull"))
  1973. config->irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL;
  1974. if (device_property_present(dev, "smsc,force-internal-phy"))
  1975. config->flags |= SMSC911X_FORCE_INTERNAL_PHY;
  1976. if (device_property_present(dev, "smsc,force-external-phy"))
  1977. config->flags |= SMSC911X_FORCE_EXTERNAL_PHY;
  1978. if (device_property_present(dev, "smsc,save-mac-address"))
  1979. config->flags |= SMSC911X_SAVE_MAC_ADDRESS;
  1980. return 0;
  1981. }
  1982. static int smsc911x_drv_probe(struct platform_device *pdev)
  1983. {
  1984. struct net_device *dev;
  1985. struct smsc911x_data *pdata;
  1986. struct smsc911x_platform_config *config = dev_get_platdata(&pdev->dev);
  1987. struct resource *res;
  1988. unsigned int intcfg = 0;
  1989. int res_size, irq, irq_flags;
  1990. int retval;
  1991. res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
  1992. "smsc911x-memory");
  1993. if (!res)
  1994. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  1995. if (!res) {
  1996. pr_warn("Could not allocate resource\n");
  1997. retval = -ENODEV;
  1998. goto out_0;
  1999. }
  2000. res_size = resource_size(res);
  2001. irq = platform_get_irq(pdev, 0);
  2002. if (irq == -EPROBE_DEFER) {
  2003. retval = -EPROBE_DEFER;
  2004. goto out_0;
  2005. } else if (irq <= 0) {
  2006. pr_warn("Could not allocate irq resource\n");
  2007. retval = -ENODEV;
  2008. goto out_0;
  2009. }
  2010. if (!request_mem_region(res->start, res_size, SMSC_CHIPNAME)) {
  2011. retval = -EBUSY;
  2012. goto out_0;
  2013. }
  2014. dev = alloc_etherdev(sizeof(struct smsc911x_data));
  2015. if (!dev) {
  2016. retval = -ENOMEM;
  2017. goto out_release_io_1;
  2018. }
  2019. SET_NETDEV_DEV(dev, &pdev->dev);
  2020. pdata = netdev_priv(dev);
  2021. dev->irq = irq;
  2022. irq_flags = irq_get_trigger_type(irq);
  2023. pdata->ioaddr = ioremap_nocache(res->start, res_size);
  2024. pdata->dev = dev;
  2025. pdata->msg_enable = ((1 << debug) - 1);
  2026. platform_set_drvdata(pdev, dev);
  2027. retval = smsc911x_request_resources(pdev);
  2028. if (retval)
  2029. goto out_request_resources_fail;
  2030. retval = smsc911x_enable_resources(pdev);
  2031. if (retval)
  2032. goto out_enable_resources_fail;
  2033. if (pdata->ioaddr == NULL) {
  2034. SMSC_WARN(pdata, probe, "Error smsc911x base address invalid");
  2035. retval = -ENOMEM;
  2036. goto out_disable_resources;
  2037. }
  2038. retval = smsc911x_probe_config(&pdata->config, &pdev->dev);
  2039. if (retval && config) {
  2040. /* copy config parameters across to pdata */
  2041. memcpy(&pdata->config, config, sizeof(pdata->config));
  2042. retval = 0;
  2043. }
  2044. if (retval) {
  2045. SMSC_WARN(pdata, probe, "Error smsc911x config not found");
  2046. goto out_disable_resources;
  2047. }
  2048. /* assume standard, non-shifted, access to HW registers */
  2049. pdata->ops = &standard_smsc911x_ops;
  2050. /* apply the right access if shifting is needed */
  2051. if (pdata->config.shift)
  2052. pdata->ops = &shifted_smsc911x_ops;
  2053. pm_runtime_enable(&pdev->dev);
  2054. pm_runtime_get_sync(&pdev->dev);
  2055. retval = smsc911x_init(dev);
  2056. if (retval < 0)
  2057. goto out_disable_resources;
  2058. /* configure irq polarity and type before connecting isr */
  2059. if (pdata->config.irq_polarity == SMSC911X_IRQ_POLARITY_ACTIVE_HIGH)
  2060. intcfg |= INT_CFG_IRQ_POL_;
  2061. if (pdata->config.irq_type == SMSC911X_IRQ_TYPE_PUSH_PULL)
  2062. intcfg |= INT_CFG_IRQ_TYPE_;
  2063. smsc911x_reg_write(pdata, INT_CFG, intcfg);
  2064. /* Ensure interrupts are globally disabled before connecting ISR */
  2065. smsc911x_disable_irq_chip(dev);
  2066. retval = request_irq(dev->irq, smsc911x_irqhandler,
  2067. irq_flags | IRQF_SHARED, dev->name, dev);
  2068. if (retval) {
  2069. SMSC_WARN(pdata, probe,
  2070. "Unable to claim requested irq: %d", dev->irq);
  2071. goto out_disable_resources;
  2072. }
  2073. netif_carrier_off(dev);
  2074. retval = register_netdev(dev);
  2075. if (retval) {
  2076. SMSC_WARN(pdata, probe, "Error %i registering device", retval);
  2077. goto out_free_irq;
  2078. } else {
  2079. SMSC_TRACE(pdata, probe,
  2080. "Network interface: \"%s\"", dev->name);
  2081. }
  2082. retval = smsc911x_mii_init(pdev, dev);
  2083. if (retval) {
  2084. SMSC_WARN(pdata, probe, "Error %i initialising mii", retval);
  2085. goto out_unregister_netdev_5;
  2086. }
  2087. spin_lock_irq(&pdata->mac_lock);
  2088. /* Check if mac address has been specified when bringing interface up */
  2089. if (is_valid_ether_addr(dev->dev_addr)) {
  2090. smsc911x_set_hw_mac_address(pdata, dev->dev_addr);
  2091. SMSC_TRACE(pdata, probe,
  2092. "MAC Address is specified by configuration");
  2093. } else if (is_valid_ether_addr(pdata->config.mac)) {
  2094. memcpy(dev->dev_addr, pdata->config.mac, ETH_ALEN);
  2095. SMSC_TRACE(pdata, probe,
  2096. "MAC Address specified by platform data");
  2097. } else {
  2098. /* Try reading mac address from device. if EEPROM is present
  2099. * it will already have been set */
  2100. smsc_get_mac(dev);
  2101. if (is_valid_ether_addr(dev->dev_addr)) {
  2102. /* eeprom values are valid so use them */
  2103. SMSC_TRACE(pdata, probe,
  2104. "Mac Address is read from LAN911x EEPROM");
  2105. } else {
  2106. /* eeprom values are invalid, generate random MAC */
  2107. eth_hw_addr_random(dev);
  2108. smsc911x_set_hw_mac_address(pdata, dev->dev_addr);
  2109. SMSC_TRACE(pdata, probe,
  2110. "MAC Address is set to eth_random_addr");
  2111. }
  2112. }
  2113. spin_unlock_irq(&pdata->mac_lock);
  2114. netdev_info(dev, "MAC Address: %pM\n", dev->dev_addr);
  2115. return 0;
  2116. out_unregister_netdev_5:
  2117. unregister_netdev(dev);
  2118. out_free_irq:
  2119. free_irq(dev->irq, dev);
  2120. out_disable_resources:
  2121. pm_runtime_put(&pdev->dev);
  2122. pm_runtime_disable(&pdev->dev);
  2123. (void)smsc911x_disable_resources(pdev);
  2124. out_enable_resources_fail:
  2125. smsc911x_free_resources(pdev);
  2126. out_request_resources_fail:
  2127. iounmap(pdata->ioaddr);
  2128. free_netdev(dev);
  2129. out_release_io_1:
  2130. release_mem_region(res->start, resource_size(res));
  2131. out_0:
  2132. return retval;
  2133. }
  2134. #ifdef CONFIG_PM
  2135. /* This implementation assumes the devices remains powered on its VDDVARIO
  2136. * pins during suspend. */
  2137. /* TODO: implement freeze/thaw callbacks for hibernation.*/
  2138. static int smsc911x_suspend(struct device *dev)
  2139. {
  2140. struct net_device *ndev = dev_get_drvdata(dev);
  2141. struct smsc911x_data *pdata = netdev_priv(ndev);
  2142. /* enable wake on LAN, energy detection and the external PME
  2143. * signal. */
  2144. smsc911x_reg_write(pdata, PMT_CTRL,
  2145. PMT_CTRL_PM_MODE_D1_ | PMT_CTRL_WOL_EN_ |
  2146. PMT_CTRL_ED_EN_ | PMT_CTRL_PME_EN_);
  2147. return 0;
  2148. }
  2149. static int smsc911x_resume(struct device *dev)
  2150. {
  2151. struct net_device *ndev = dev_get_drvdata(dev);
  2152. struct smsc911x_data *pdata = netdev_priv(ndev);
  2153. unsigned int to = 100;
  2154. /* Note 3.11 from the datasheet:
  2155. * "When the LAN9220 is in a power saving state, a write of any
  2156. * data to the BYTE_TEST register will wake-up the device."
  2157. */
  2158. smsc911x_reg_write(pdata, BYTE_TEST, 0);
  2159. /* poll the READY bit in PMT_CTRL. Any other access to the device is
  2160. * forbidden while this bit isn't set. Try for 100ms and return -EIO
  2161. * if it failed. */
  2162. while (!(smsc911x_reg_read(pdata, PMT_CTRL) & PMT_CTRL_READY_) && --to)
  2163. udelay(1000);
  2164. return (to == 0) ? -EIO : 0;
  2165. }
  2166. static const struct dev_pm_ops smsc911x_pm_ops = {
  2167. .suspend = smsc911x_suspend,
  2168. .resume = smsc911x_resume,
  2169. };
  2170. #define SMSC911X_PM_OPS (&smsc911x_pm_ops)
  2171. #else
  2172. #define SMSC911X_PM_OPS NULL
  2173. #endif
  2174. #ifdef CONFIG_OF
  2175. static const struct of_device_id smsc911x_dt_ids[] = {
  2176. { .compatible = "smsc,lan9115", },
  2177. { /* sentinel */ }
  2178. };
  2179. MODULE_DEVICE_TABLE(of, smsc911x_dt_ids);
  2180. #endif
  2181. static const struct acpi_device_id smsc911x_acpi_match[] = {
  2182. { "ARMH9118", 0 },
  2183. { }
  2184. };
  2185. MODULE_DEVICE_TABLE(acpi, smsc911x_acpi_match);
  2186. static struct platform_driver smsc911x_driver = {
  2187. .probe = smsc911x_drv_probe,
  2188. .remove = smsc911x_drv_remove,
  2189. .driver = {
  2190. .name = SMSC_CHIPNAME,
  2191. .pm = SMSC911X_PM_OPS,
  2192. .of_match_table = of_match_ptr(smsc911x_dt_ids),
  2193. .acpi_match_table = ACPI_PTR(smsc911x_acpi_match),
  2194. },
  2195. };
  2196. /* Entry point for loading the module */
  2197. static int __init smsc911x_init_module(void)
  2198. {
  2199. SMSC_INITIALIZE();
  2200. return platform_driver_register(&smsc911x_driver);
  2201. }
  2202. /* entry point for unloading the module */
  2203. static void __exit smsc911x_cleanup_module(void)
  2204. {
  2205. platform_driver_unregister(&smsc911x_driver);
  2206. }
  2207. module_init(smsc911x_init_module);
  2208. module_exit(smsc911x_cleanup_module);