irq-mtk-sysirq.c 4.3 KB

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  1. /*
  2. * Copyright (c) 2014 MediaTek Inc.
  3. * Author: Joe.C <yingjoe.chen@mediatek.com>
  4. *
  5. * This program is free software; you can redistribute it and/or modify
  6. * it under the terms of the GNU General Public License version 2 as
  7. * published by the Free Software Foundation.
  8. *
  9. * This program is distributed in the hope that it will be useful,
  10. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  12. * GNU General Public License for more details.
  13. */
  14. #include <linux/irq.h>
  15. #include <linux/irqchip.h>
  16. #include <linux/irqdomain.h>
  17. #include <linux/of.h>
  18. #include <linux/of_irq.h>
  19. #include <linux/of_address.h>
  20. #include <linux/io.h>
  21. #include <linux/slab.h>
  22. #include <linux/spinlock.h>
  23. struct mtk_sysirq_chip_data {
  24. spinlock_t lock;
  25. void __iomem *intpol_base;
  26. };
  27. static int mtk_sysirq_set_type(struct irq_data *data, unsigned int type)
  28. {
  29. irq_hw_number_t hwirq = data->hwirq;
  30. struct mtk_sysirq_chip_data *chip_data = data->chip_data;
  31. u32 offset, reg_index, value;
  32. unsigned long flags;
  33. int ret;
  34. offset = hwirq & 0x1f;
  35. reg_index = hwirq >> 5;
  36. spin_lock_irqsave(&chip_data->lock, flags);
  37. value = readl_relaxed(chip_data->intpol_base + reg_index * 4);
  38. if (type == IRQ_TYPE_LEVEL_LOW || type == IRQ_TYPE_EDGE_FALLING) {
  39. if (type == IRQ_TYPE_LEVEL_LOW)
  40. type = IRQ_TYPE_LEVEL_HIGH;
  41. else
  42. type = IRQ_TYPE_EDGE_RISING;
  43. value |= (1 << offset);
  44. } else {
  45. value &= ~(1 << offset);
  46. }
  47. writel(value, chip_data->intpol_base + reg_index * 4);
  48. data = data->parent_data;
  49. ret = data->chip->irq_set_type(data, type);
  50. spin_unlock_irqrestore(&chip_data->lock, flags);
  51. return ret;
  52. }
  53. static struct irq_chip mtk_sysirq_chip = {
  54. .name = "MT_SYSIRQ",
  55. .irq_mask = irq_chip_mask_parent,
  56. .irq_unmask = irq_chip_unmask_parent,
  57. .irq_eoi = irq_chip_eoi_parent,
  58. .irq_set_type = mtk_sysirq_set_type,
  59. .irq_retrigger = irq_chip_retrigger_hierarchy,
  60. .irq_set_affinity = irq_chip_set_affinity_parent,
  61. };
  62. static int mtk_sysirq_domain_xlate(struct irq_domain *d,
  63. struct device_node *controller,
  64. const u32 *intspec, unsigned int intsize,
  65. unsigned long *out_hwirq,
  66. unsigned int *out_type)
  67. {
  68. if (intsize != 3)
  69. return -EINVAL;
  70. /* sysirq doesn't support PPI */
  71. if (intspec[0])
  72. return -EINVAL;
  73. *out_hwirq = intspec[1];
  74. *out_type = intspec[2] & IRQ_TYPE_SENSE_MASK;
  75. return 0;
  76. }
  77. static int mtk_sysirq_domain_alloc(struct irq_domain *domain, unsigned int virq,
  78. unsigned int nr_irqs, void *arg)
  79. {
  80. int i;
  81. irq_hw_number_t hwirq;
  82. struct of_phandle_args *irq_data = arg;
  83. struct of_phandle_args gic_data = *irq_data;
  84. if (irq_data->args_count != 3)
  85. return -EINVAL;
  86. /* sysirq doesn't support PPI */
  87. if (irq_data->args[0])
  88. return -EINVAL;
  89. hwirq = irq_data->args[1];
  90. for (i = 0; i < nr_irqs; i++)
  91. irq_domain_set_hwirq_and_chip(domain, virq + i, hwirq + i,
  92. &mtk_sysirq_chip,
  93. domain->host_data);
  94. gic_data.np = domain->parent->of_node;
  95. return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, &gic_data);
  96. }
  97. static const struct irq_domain_ops sysirq_domain_ops = {
  98. .xlate = mtk_sysirq_domain_xlate,
  99. .alloc = mtk_sysirq_domain_alloc,
  100. .free = irq_domain_free_irqs_common,
  101. };
  102. static int __init mtk_sysirq_of_init(struct device_node *node,
  103. struct device_node *parent)
  104. {
  105. struct irq_domain *domain, *domain_parent;
  106. struct mtk_sysirq_chip_data *chip_data;
  107. int ret, size, intpol_num;
  108. struct resource res;
  109. domain_parent = irq_find_host(parent);
  110. if (!domain_parent) {
  111. pr_err("mtk_sysirq: interrupt-parent not found\n");
  112. return -EINVAL;
  113. }
  114. ret = of_address_to_resource(node, 0, &res);
  115. if (ret)
  116. return ret;
  117. chip_data = kzalloc(sizeof(*chip_data), GFP_KERNEL);
  118. if (!chip_data)
  119. return -ENOMEM;
  120. size = resource_size(&res);
  121. intpol_num = size * 8;
  122. chip_data->intpol_base = ioremap(res.start, size);
  123. if (!chip_data->intpol_base) {
  124. pr_err("mtk_sysirq: unable to map sysirq register\n");
  125. ret = -ENXIO;
  126. goto out_free;
  127. }
  128. domain = irq_domain_add_hierarchy(domain_parent, 0, intpol_num, node,
  129. &sysirq_domain_ops, chip_data);
  130. if (!domain) {
  131. ret = -ENOMEM;
  132. goto out_unmap;
  133. }
  134. spin_lock_init(&chip_data->lock);
  135. return 0;
  136. out_unmap:
  137. iounmap(chip_data->intpol_base);
  138. out_free:
  139. kfree(chip_data);
  140. return ret;
  141. }
  142. IRQCHIP_DECLARE(mtk_sysirq, "mediatek,mt6577-sysirq", mtk_sysirq_of_init);