berlin2-adc.c 10 KB

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  1. /*
  2. * Marvell Berlin2 ADC driver
  3. *
  4. * Copyright (C) 2015 Marvell Technology Group Ltd.
  5. *
  6. * Antoine Tenart <antoine.tenart@free-electrons.com>
  7. *
  8. * This file is licensed under the terms of the GNU General Public
  9. * License version 2. This program is licensed "as is" without any
  10. * warranty of any kind, whether express or implied.
  11. */
  12. #include <linux/iio/iio.h>
  13. #include <linux/iio/driver.h>
  14. #include <linux/iio/machine.h>
  15. #include <linux/interrupt.h>
  16. #include <linux/kernel.h>
  17. #include <linux/module.h>
  18. #include <linux/platform_device.h>
  19. #include <linux/slab.h>
  20. #include <linux/mfd/syscon.h>
  21. #include <linux/regmap.h>
  22. #include <linux/sched.h>
  23. #include <linux/wait.h>
  24. #define BERLIN2_SM_CTRL 0x14
  25. #define BERLIN2_SM_CTRL_SM_SOC_INT BIT(1)
  26. #define BERLIN2_SM_CTRL_SOC_SM_INT BIT(2)
  27. #define BERLIN2_SM_CTRL_ADC_SEL(x) ((x) << 5) /* 0-15 */
  28. #define BERLIN2_SM_CTRL_ADC_SEL_MASK (0xf << 5)
  29. #define BERLIN2_SM_CTRL_ADC_POWER BIT(9)
  30. #define BERLIN2_SM_CTRL_ADC_CLKSEL_DIV2 (0x0 << 10)
  31. #define BERLIN2_SM_CTRL_ADC_CLKSEL_DIV3 (0x1 << 10)
  32. #define BERLIN2_SM_CTRL_ADC_CLKSEL_DIV4 (0x2 << 10)
  33. #define BERLIN2_SM_CTRL_ADC_CLKSEL_DIV8 (0x3 << 10)
  34. #define BERLIN2_SM_CTRL_ADC_CLKSEL_MASK (0x3 << 10)
  35. #define BERLIN2_SM_CTRL_ADC_START BIT(12)
  36. #define BERLIN2_SM_CTRL_ADC_RESET BIT(13)
  37. #define BERLIN2_SM_CTRL_ADC_BANDGAP_RDY BIT(14)
  38. #define BERLIN2_SM_CTRL_ADC_CONT_SINGLE (0x0 << 15)
  39. #define BERLIN2_SM_CTRL_ADC_CONT_CONTINUOUS (0x1 << 15)
  40. #define BERLIN2_SM_CTRL_ADC_BUFFER_EN BIT(16)
  41. #define BERLIN2_SM_CTRL_ADC_VREF_EXT (0x0 << 17)
  42. #define BERLIN2_SM_CTRL_ADC_VREF_INT (0x1 << 17)
  43. #define BERLIN2_SM_CTRL_ADC_ROTATE BIT(19)
  44. #define BERLIN2_SM_CTRL_TSEN_EN BIT(20)
  45. #define BERLIN2_SM_CTRL_TSEN_CLK_SEL_125 (0x0 << 21) /* 1.25 MHz */
  46. #define BERLIN2_SM_CTRL_TSEN_CLK_SEL_250 (0x1 << 21) /* 2.5 MHz */
  47. #define BERLIN2_SM_CTRL_TSEN_MODE_0_125 (0x0 << 22) /* 0-125 C */
  48. #define BERLIN2_SM_CTRL_TSEN_MODE_10_50 (0x1 << 22) /* 10-50 C */
  49. #define BERLIN2_SM_CTRL_TSEN_RESET BIT(29)
  50. #define BERLIN2_SM_ADC_DATA 0x20
  51. #define BERLIN2_SM_ADC_MASK 0x3ff
  52. #define BERLIN2_SM_ADC_STATUS 0x1c
  53. #define BERLIN2_SM_ADC_STATUS_DATA_RDY(x) BIT(x) /* 0-15 */
  54. #define BERLIN2_SM_ADC_STATUS_DATA_RDY_MASK GENMASK(15, 0)
  55. #define BERLIN2_SM_ADC_STATUS_INT_EN(x) (BIT(x) << 16) /* 0-15 */
  56. #define BERLIN2_SM_ADC_STATUS_INT_EN_MASK GENMASK(31, 16)
  57. #define BERLIN2_SM_TSEN_STATUS 0x24
  58. #define BERLIN2_SM_TSEN_STATUS_DATA_RDY BIT(0)
  59. #define BERLIN2_SM_TSEN_STATUS_INT_EN BIT(1)
  60. #define BERLIN2_SM_TSEN_DATA 0x28
  61. #define BERLIN2_SM_TSEN_MASK GENMASK(9, 0)
  62. #define BERLIN2_SM_TSEN_CTRL 0x74
  63. #define BERLIN2_SM_TSEN_CTRL_START BIT(8)
  64. #define BERLIN2_SM_TSEN_CTRL_SETTLING_4 (0x0 << 21) /* 4 us */
  65. #define BERLIN2_SM_TSEN_CTRL_SETTLING_12 (0x1 << 21) /* 12 us */
  66. #define BERLIN2_SM_TSEN_CTRL_SETTLING_MASK (0x1 << 21)
  67. #define BERLIN2_SM_TSEN_CTRL_TRIM(x) ((x) << 22)
  68. #define BERLIN2_SM_TSEN_CTRL_TRIM_MASK (0xf << 22)
  69. struct berlin2_adc_priv {
  70. struct regmap *regmap;
  71. struct mutex lock;
  72. wait_queue_head_t wq;
  73. bool data_available;
  74. int data;
  75. };
  76. #define BERLIN2_ADC_CHANNEL(n, t) \
  77. { \
  78. .channel = n, \
  79. .datasheet_name = "channel"#n, \
  80. .type = t, \
  81. .indexed = 1, \
  82. .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
  83. }
  84. static const struct iio_chan_spec berlin2_adc_channels[] = {
  85. BERLIN2_ADC_CHANNEL(0, IIO_VOLTAGE), /* external input */
  86. BERLIN2_ADC_CHANNEL(1, IIO_VOLTAGE), /* external input */
  87. BERLIN2_ADC_CHANNEL(2, IIO_VOLTAGE), /* external input */
  88. BERLIN2_ADC_CHANNEL(3, IIO_VOLTAGE), /* external input */
  89. BERLIN2_ADC_CHANNEL(4, IIO_VOLTAGE), /* reserved */
  90. BERLIN2_ADC_CHANNEL(5, IIO_VOLTAGE), /* reserved */
  91. { /* temperature sensor */
  92. .channel = 6,
  93. .datasheet_name = "channel6",
  94. .type = IIO_TEMP,
  95. .indexed = 0,
  96. .info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED),
  97. },
  98. BERLIN2_ADC_CHANNEL(7, IIO_VOLTAGE), /* reserved */
  99. IIO_CHAN_SOFT_TIMESTAMP(8), /* timestamp */
  100. };
  101. static int berlin2_adc_read(struct iio_dev *indio_dev, int channel)
  102. {
  103. struct berlin2_adc_priv *priv = iio_priv(indio_dev);
  104. int data, ret;
  105. mutex_lock(&priv->lock);
  106. /* Configure the ADC */
  107. regmap_update_bits(priv->regmap, BERLIN2_SM_CTRL,
  108. BERLIN2_SM_CTRL_ADC_RESET | BERLIN2_SM_CTRL_ADC_SEL_MASK
  109. | BERLIN2_SM_CTRL_ADC_START,
  110. BERLIN2_SM_CTRL_ADC_SEL(channel) | BERLIN2_SM_CTRL_ADC_START);
  111. ret = wait_event_interruptible_timeout(priv->wq, priv->data_available,
  112. msecs_to_jiffies(1000));
  113. /* Disable the interrupts */
  114. regmap_update_bits(priv->regmap, BERLIN2_SM_ADC_STATUS,
  115. BERLIN2_SM_ADC_STATUS_INT_EN(channel), 0);
  116. if (ret == 0)
  117. ret = -ETIMEDOUT;
  118. if (ret < 0) {
  119. mutex_unlock(&priv->lock);
  120. return ret;
  121. }
  122. regmap_update_bits(priv->regmap, BERLIN2_SM_CTRL,
  123. BERLIN2_SM_CTRL_ADC_START, 0);
  124. data = priv->data;
  125. priv->data_available = false;
  126. mutex_unlock(&priv->lock);
  127. return data;
  128. }
  129. static int berlin2_adc_tsen_read(struct iio_dev *indio_dev)
  130. {
  131. struct berlin2_adc_priv *priv = iio_priv(indio_dev);
  132. int data, ret;
  133. mutex_lock(&priv->lock);
  134. /* Configure the ADC */
  135. regmap_update_bits(priv->regmap, BERLIN2_SM_CTRL,
  136. BERLIN2_SM_CTRL_TSEN_RESET | BERLIN2_SM_CTRL_ADC_ROTATE,
  137. BERLIN2_SM_CTRL_ADC_ROTATE);
  138. /* Configure the temperature sensor */
  139. regmap_update_bits(priv->regmap, BERLIN2_SM_TSEN_CTRL,
  140. BERLIN2_SM_TSEN_CTRL_TRIM_MASK | BERLIN2_SM_TSEN_CTRL_SETTLING_MASK
  141. | BERLIN2_SM_TSEN_CTRL_START,
  142. BERLIN2_SM_TSEN_CTRL_TRIM(3) | BERLIN2_SM_TSEN_CTRL_SETTLING_12
  143. | BERLIN2_SM_TSEN_CTRL_START);
  144. ret = wait_event_interruptible_timeout(priv->wq, priv->data_available,
  145. msecs_to_jiffies(1000));
  146. /* Disable interrupts */
  147. regmap_update_bits(priv->regmap, BERLIN2_SM_TSEN_STATUS,
  148. BERLIN2_SM_TSEN_STATUS_INT_EN, 0);
  149. if (ret == 0)
  150. ret = -ETIMEDOUT;
  151. if (ret < 0) {
  152. mutex_unlock(&priv->lock);
  153. return ret;
  154. }
  155. regmap_update_bits(priv->regmap, BERLIN2_SM_TSEN_CTRL,
  156. BERLIN2_SM_TSEN_CTRL_START, 0);
  157. data = priv->data;
  158. priv->data_available = false;
  159. mutex_unlock(&priv->lock);
  160. return data;
  161. }
  162. static int berlin2_adc_read_raw(struct iio_dev *indio_dev,
  163. struct iio_chan_spec const *chan, int *val, int *val2,
  164. long mask)
  165. {
  166. struct berlin2_adc_priv *priv = iio_priv(indio_dev);
  167. int temp;
  168. switch (mask) {
  169. case IIO_CHAN_INFO_RAW:
  170. if (chan->type != IIO_VOLTAGE)
  171. return -EINVAL;
  172. /* Enable the interrupts */
  173. regmap_write(priv->regmap, BERLIN2_SM_ADC_STATUS,
  174. BERLIN2_SM_ADC_STATUS_INT_EN(chan->channel));
  175. *val = berlin2_adc_read(indio_dev, chan->channel);
  176. if (*val < 0)
  177. return *val;
  178. return IIO_VAL_INT;
  179. case IIO_CHAN_INFO_PROCESSED:
  180. if (chan->type != IIO_TEMP)
  181. return -EINVAL;
  182. /* Enable interrupts */
  183. regmap_write(priv->regmap, BERLIN2_SM_TSEN_STATUS,
  184. BERLIN2_SM_TSEN_STATUS_INT_EN);
  185. temp = berlin2_adc_tsen_read(indio_dev);
  186. if (temp < 0)
  187. return temp;
  188. if (temp > 2047)
  189. temp -= 4096;
  190. /* Convert to milli Celsius */
  191. *val = ((temp * 100000) / 264 - 270000);
  192. return IIO_VAL_INT;
  193. default:
  194. break;
  195. }
  196. return -EINVAL;
  197. }
  198. static irqreturn_t berlin2_adc_irq(int irq, void *private)
  199. {
  200. struct berlin2_adc_priv *priv = iio_priv(private);
  201. unsigned val;
  202. regmap_read(priv->regmap, BERLIN2_SM_ADC_STATUS, &val);
  203. if (val & BERLIN2_SM_ADC_STATUS_DATA_RDY_MASK) {
  204. regmap_read(priv->regmap, BERLIN2_SM_ADC_DATA, &priv->data);
  205. priv->data &= BERLIN2_SM_ADC_MASK;
  206. val &= ~BERLIN2_SM_ADC_STATUS_DATA_RDY_MASK;
  207. regmap_write(priv->regmap, BERLIN2_SM_ADC_STATUS, val);
  208. priv->data_available = true;
  209. wake_up_interruptible(&priv->wq);
  210. }
  211. return IRQ_HANDLED;
  212. }
  213. static irqreturn_t berlin2_adc_tsen_irq(int irq, void *private)
  214. {
  215. struct berlin2_adc_priv *priv = iio_priv(private);
  216. unsigned val;
  217. regmap_read(priv->regmap, BERLIN2_SM_TSEN_STATUS, &val);
  218. if (val & BERLIN2_SM_TSEN_STATUS_DATA_RDY) {
  219. regmap_read(priv->regmap, BERLIN2_SM_TSEN_DATA, &priv->data);
  220. priv->data &= BERLIN2_SM_TSEN_MASK;
  221. val &= ~BERLIN2_SM_TSEN_STATUS_DATA_RDY;
  222. regmap_write(priv->regmap, BERLIN2_SM_TSEN_STATUS, val);
  223. priv->data_available = true;
  224. wake_up_interruptible(&priv->wq);
  225. }
  226. return IRQ_HANDLED;
  227. }
  228. static const struct iio_info berlin2_adc_info = {
  229. .driver_module = THIS_MODULE,
  230. .read_raw = berlin2_adc_read_raw,
  231. };
  232. static int berlin2_adc_probe(struct platform_device *pdev)
  233. {
  234. struct iio_dev *indio_dev;
  235. struct berlin2_adc_priv *priv;
  236. struct device_node *parent_np = of_get_parent(pdev->dev.of_node);
  237. int irq, tsen_irq;
  238. int ret;
  239. indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*priv));
  240. if (!indio_dev)
  241. return -ENOMEM;
  242. priv = iio_priv(indio_dev);
  243. platform_set_drvdata(pdev, indio_dev);
  244. priv->regmap = syscon_node_to_regmap(parent_np);
  245. of_node_put(parent_np);
  246. if (IS_ERR(priv->regmap))
  247. return PTR_ERR(priv->regmap);
  248. irq = platform_get_irq_byname(pdev, "adc");
  249. if (irq < 0)
  250. return irq;
  251. tsen_irq = platform_get_irq_byname(pdev, "tsen");
  252. if (tsen_irq < 0)
  253. return tsen_irq;
  254. ret = devm_request_irq(&pdev->dev, irq, berlin2_adc_irq, 0,
  255. pdev->dev.driver->name, indio_dev);
  256. if (ret)
  257. return ret;
  258. ret = devm_request_irq(&pdev->dev, tsen_irq, berlin2_adc_tsen_irq,
  259. 0, pdev->dev.driver->name, indio_dev);
  260. if (ret)
  261. return ret;
  262. init_waitqueue_head(&priv->wq);
  263. mutex_init(&priv->lock);
  264. indio_dev->dev.parent = &pdev->dev;
  265. indio_dev->name = dev_name(&pdev->dev);
  266. indio_dev->modes = INDIO_DIRECT_MODE;
  267. indio_dev->info = &berlin2_adc_info;
  268. indio_dev->channels = berlin2_adc_channels;
  269. indio_dev->num_channels = ARRAY_SIZE(berlin2_adc_channels);
  270. /* Power up the ADC */
  271. regmap_update_bits(priv->regmap, BERLIN2_SM_CTRL,
  272. BERLIN2_SM_CTRL_ADC_POWER, BERLIN2_SM_CTRL_ADC_POWER);
  273. ret = iio_device_register(indio_dev);
  274. if (ret) {
  275. /* Power down the ADC */
  276. regmap_update_bits(priv->regmap, BERLIN2_SM_CTRL,
  277. BERLIN2_SM_CTRL_ADC_POWER, 0);
  278. return ret;
  279. }
  280. return 0;
  281. }
  282. static int berlin2_adc_remove(struct platform_device *pdev)
  283. {
  284. struct iio_dev *indio_dev = platform_get_drvdata(pdev);
  285. struct berlin2_adc_priv *priv = iio_priv(indio_dev);
  286. iio_device_unregister(indio_dev);
  287. /* Power down the ADC */
  288. regmap_update_bits(priv->regmap, BERLIN2_SM_CTRL,
  289. BERLIN2_SM_CTRL_ADC_POWER, 0);
  290. return 0;
  291. }
  292. static const struct of_device_id berlin2_adc_match[] = {
  293. { .compatible = "marvell,berlin2-adc", },
  294. { },
  295. };
  296. MODULE_DEVICE_TABLE(of, berlin2_adc_match);
  297. static struct platform_driver berlin2_adc_driver = {
  298. .driver = {
  299. .name = "berlin2-adc",
  300. .of_match_table = berlin2_adc_match,
  301. },
  302. .probe = berlin2_adc_probe,
  303. .remove = berlin2_adc_remove,
  304. };
  305. module_platform_driver(berlin2_adc_driver);
  306. MODULE_AUTHOR("Antoine Tenart <antoine.tenart@free-electrons.com>");
  307. MODULE_DESCRIPTION("Marvell Berlin2 ADC driver");
  308. MODULE_LICENSE("GPL v2");