amdgpu_sync.c 9.1 KB

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  1. /*
  2. * Copyright 2014 Advanced Micro Devices, Inc.
  3. * All Rights Reserved.
  4. *
  5. * Permission is hereby granted, free of charge, to any person obtaining a
  6. * copy of this software and associated documentation files (the
  7. * "Software"), to deal in the Software without restriction, including
  8. * without limitation the rights to use, copy, modify, merge, publish,
  9. * distribute, sub license, and/or sell copies of the Software, and to
  10. * permit persons to whom the Software is furnished to do so, subject to
  11. * the following conditions:
  12. *
  13. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15. * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  16. * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  17. * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  18. * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19. * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20. *
  21. * The above copyright notice and this permission notice (including the
  22. * next paragraph) shall be included in all copies or substantial portions
  23. * of the Software.
  24. *
  25. */
  26. /*
  27. * Authors:
  28. * Christian König <christian.koenig@amd.com>
  29. */
  30. #include <drm/drmP.h>
  31. #include "amdgpu.h"
  32. #include "amdgpu_trace.h"
  33. struct amdgpu_sync_entry {
  34. struct hlist_node node;
  35. struct fence *fence;
  36. };
  37. /**
  38. * amdgpu_sync_create - zero init sync object
  39. *
  40. * @sync: sync object to initialize
  41. *
  42. * Just clear the sync object for now.
  43. */
  44. void amdgpu_sync_create(struct amdgpu_sync *sync)
  45. {
  46. unsigned i;
  47. for (i = 0; i < AMDGPU_NUM_SYNCS; ++i)
  48. sync->semaphores[i] = NULL;
  49. for (i = 0; i < AMDGPU_MAX_RINGS; ++i)
  50. sync->sync_to[i] = NULL;
  51. hash_init(sync->fences);
  52. sync->last_vm_update = NULL;
  53. }
  54. static bool amdgpu_sync_same_dev(struct amdgpu_device *adev, struct fence *f)
  55. {
  56. struct amdgpu_fence *a_fence = to_amdgpu_fence(f);
  57. struct amd_sched_fence *s_fence = to_amd_sched_fence(f);
  58. if (a_fence)
  59. return a_fence->ring->adev == adev;
  60. if (s_fence) {
  61. struct amdgpu_ring *ring;
  62. ring = container_of(s_fence->sched, struct amdgpu_ring, sched);
  63. return ring->adev == adev;
  64. }
  65. return false;
  66. }
  67. static bool amdgpu_sync_test_owner(struct fence *f, void *owner)
  68. {
  69. struct amdgpu_fence *a_fence = to_amdgpu_fence(f);
  70. struct amd_sched_fence *s_fence = to_amd_sched_fence(f);
  71. if (s_fence)
  72. return s_fence->owner == owner;
  73. if (a_fence)
  74. return a_fence->owner == owner;
  75. return false;
  76. }
  77. /**
  78. * amdgpu_sync_fence - remember to sync to this fence
  79. *
  80. * @sync: sync object to add fence to
  81. * @fence: fence to sync to
  82. *
  83. */
  84. int amdgpu_sync_fence(struct amdgpu_device *adev, struct amdgpu_sync *sync,
  85. struct fence *f)
  86. {
  87. struct amdgpu_sync_entry *e;
  88. struct amdgpu_fence *fence;
  89. struct amdgpu_fence *other;
  90. struct fence *tmp, *later;
  91. if (!f)
  92. return 0;
  93. if (amdgpu_sync_same_dev(adev, f) &&
  94. amdgpu_sync_test_owner(f, AMDGPU_FENCE_OWNER_VM)) {
  95. if (sync->last_vm_update) {
  96. tmp = sync->last_vm_update;
  97. BUG_ON(f->context != tmp->context);
  98. later = (f->seqno - tmp->seqno <= INT_MAX) ? f : tmp;
  99. sync->last_vm_update = fence_get(later);
  100. fence_put(tmp);
  101. } else
  102. sync->last_vm_update = fence_get(f);
  103. }
  104. fence = to_amdgpu_fence(f);
  105. if (!fence || fence->ring->adev != adev) {
  106. hash_for_each_possible(sync->fences, e, node, f->context) {
  107. struct fence *new;
  108. if (unlikely(e->fence->context != f->context))
  109. continue;
  110. new = fence_get(fence_later(e->fence, f));
  111. if (new) {
  112. fence_put(e->fence);
  113. e->fence = new;
  114. }
  115. return 0;
  116. }
  117. e = kmalloc(sizeof(struct amdgpu_sync_entry), GFP_KERNEL);
  118. if (!e)
  119. return -ENOMEM;
  120. hash_add(sync->fences, &e->node, f->context);
  121. e->fence = fence_get(f);
  122. return 0;
  123. }
  124. other = sync->sync_to[fence->ring->idx];
  125. sync->sync_to[fence->ring->idx] = amdgpu_fence_ref(
  126. amdgpu_fence_later(fence, other));
  127. amdgpu_fence_unref(&other);
  128. return 0;
  129. }
  130. static void *amdgpu_sync_get_owner(struct fence *f)
  131. {
  132. struct amdgpu_fence *a_fence = to_amdgpu_fence(f);
  133. struct amd_sched_fence *s_fence = to_amd_sched_fence(f);
  134. if (s_fence)
  135. return s_fence->owner;
  136. else if (a_fence)
  137. return a_fence->owner;
  138. return AMDGPU_FENCE_OWNER_UNDEFINED;
  139. }
  140. /**
  141. * amdgpu_sync_resv - use the semaphores to sync to a reservation object
  142. *
  143. * @sync: sync object to add fences from reservation object to
  144. * @resv: reservation object with embedded fence
  145. * @shared: true if we should only sync to the exclusive fence
  146. *
  147. * Sync to the fence using the semaphore objects
  148. */
  149. int amdgpu_sync_resv(struct amdgpu_device *adev,
  150. struct amdgpu_sync *sync,
  151. struct reservation_object *resv,
  152. void *owner)
  153. {
  154. struct reservation_object_list *flist;
  155. struct fence *f;
  156. void *fence_owner;
  157. unsigned i;
  158. int r = 0;
  159. if (resv == NULL)
  160. return -EINVAL;
  161. /* always sync to the exclusive fence */
  162. f = reservation_object_get_excl(resv);
  163. r = amdgpu_sync_fence(adev, sync, f);
  164. flist = reservation_object_get_list(resv);
  165. if (!flist || r)
  166. return r;
  167. for (i = 0; i < flist->shared_count; ++i) {
  168. f = rcu_dereference_protected(flist->shared[i],
  169. reservation_object_held(resv));
  170. if (amdgpu_sync_same_dev(adev, f)) {
  171. /* VM updates are only interesting
  172. * for other VM updates and moves.
  173. */
  174. fence_owner = amdgpu_sync_get_owner(f);
  175. if ((owner != AMDGPU_FENCE_OWNER_MOVE) &&
  176. (fence_owner != AMDGPU_FENCE_OWNER_MOVE) &&
  177. ((owner == AMDGPU_FENCE_OWNER_VM) !=
  178. (fence_owner == AMDGPU_FENCE_OWNER_VM)))
  179. continue;
  180. /* Ignore fence from the same owner as
  181. * long as it isn't undefined.
  182. */
  183. if (owner != AMDGPU_FENCE_OWNER_UNDEFINED &&
  184. fence_owner == owner)
  185. continue;
  186. }
  187. r = amdgpu_sync_fence(adev, sync, f);
  188. if (r)
  189. break;
  190. }
  191. return r;
  192. }
  193. struct fence *amdgpu_sync_get_fence(struct amdgpu_sync *sync)
  194. {
  195. struct amdgpu_sync_entry *e;
  196. struct hlist_node *tmp;
  197. struct fence *f;
  198. int i;
  199. hash_for_each_safe(sync->fences, i, tmp, e, node) {
  200. f = e->fence;
  201. hash_del(&e->node);
  202. kfree(e);
  203. if (!fence_is_signaled(f))
  204. return f;
  205. fence_put(f);
  206. }
  207. return NULL;
  208. }
  209. int amdgpu_sync_wait(struct amdgpu_sync *sync)
  210. {
  211. struct amdgpu_sync_entry *e;
  212. struct hlist_node *tmp;
  213. int i, r;
  214. hash_for_each_safe(sync->fences, i, tmp, e, node) {
  215. r = fence_wait(e->fence, false);
  216. if (r)
  217. return r;
  218. hash_del(&e->node);
  219. fence_put(e->fence);
  220. kfree(e);
  221. }
  222. if (amdgpu_enable_semaphores)
  223. return 0;
  224. for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
  225. struct amdgpu_fence *fence = sync->sync_to[i];
  226. if (!fence)
  227. continue;
  228. r = fence_wait(&fence->base, false);
  229. if (r)
  230. return r;
  231. }
  232. return 0;
  233. }
  234. /**
  235. * amdgpu_sync_rings - sync ring to all registered fences
  236. *
  237. * @sync: sync object to use
  238. * @ring: ring that needs sync
  239. *
  240. * Ensure that all registered fences are signaled before letting
  241. * the ring continue. The caller must hold the ring lock.
  242. */
  243. int amdgpu_sync_rings(struct amdgpu_sync *sync,
  244. struct amdgpu_ring *ring)
  245. {
  246. struct amdgpu_device *adev = ring->adev;
  247. unsigned count = 0;
  248. int i, r;
  249. for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
  250. struct amdgpu_fence *fence = sync->sync_to[i];
  251. struct amdgpu_semaphore *semaphore;
  252. struct amdgpu_ring *other = adev->rings[i];
  253. /* check if we really need to sync */
  254. if (!amdgpu_fence_need_sync(fence, ring))
  255. continue;
  256. /* prevent GPU deadlocks */
  257. if (!other->ready) {
  258. dev_err(adev->dev, "Syncing to a disabled ring!");
  259. return -EINVAL;
  260. }
  261. if (amdgpu_enable_scheduler || !amdgpu_enable_semaphores ||
  262. (count >= AMDGPU_NUM_SYNCS)) {
  263. /* not enough room, wait manually */
  264. r = fence_wait(&fence->base, false);
  265. if (r)
  266. return r;
  267. continue;
  268. }
  269. r = amdgpu_semaphore_create(adev, &semaphore);
  270. if (r)
  271. return r;
  272. sync->semaphores[count++] = semaphore;
  273. /* allocate enough space for sync command */
  274. r = amdgpu_ring_alloc(other, 16);
  275. if (r)
  276. return r;
  277. /* emit the signal semaphore */
  278. if (!amdgpu_semaphore_emit_signal(other, semaphore)) {
  279. /* signaling wasn't successful wait manually */
  280. amdgpu_ring_undo(other);
  281. r = fence_wait(&fence->base, false);
  282. if (r)
  283. return r;
  284. continue;
  285. }
  286. /* we assume caller has already allocated space on waiters ring */
  287. if (!amdgpu_semaphore_emit_wait(ring, semaphore)) {
  288. /* waiting wasn't successful wait manually */
  289. amdgpu_ring_undo(other);
  290. r = fence_wait(&fence->base, false);
  291. if (r)
  292. return r;
  293. continue;
  294. }
  295. amdgpu_ring_commit(other);
  296. amdgpu_fence_note_sync(fence, ring);
  297. }
  298. return 0;
  299. }
  300. /**
  301. * amdgpu_sync_free - free the sync object
  302. *
  303. * @adev: amdgpu_device pointer
  304. * @sync: sync object to use
  305. * @fence: fence to use for the free
  306. *
  307. * Free the sync object by freeing all semaphores in it.
  308. */
  309. void amdgpu_sync_free(struct amdgpu_device *adev,
  310. struct amdgpu_sync *sync,
  311. struct fence *fence)
  312. {
  313. struct amdgpu_sync_entry *e;
  314. struct hlist_node *tmp;
  315. unsigned i;
  316. hash_for_each_safe(sync->fences, i, tmp, e, node) {
  317. hash_del(&e->node);
  318. fence_put(e->fence);
  319. kfree(e);
  320. }
  321. for (i = 0; i < AMDGPU_NUM_SYNCS; ++i)
  322. amdgpu_semaphore_free(adev, &sync->semaphores[i], fence);
  323. for (i = 0; i < AMDGPU_MAX_RINGS; ++i)
  324. amdgpu_fence_unref(&sync->sync_to[i]);
  325. fence_put(sync->last_vm_update);
  326. }