clk-master.c 6.5 KB

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  1. /*
  2. * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
  3. *
  4. * This program is free software; you can redistribute it and/or modify
  5. * it under the terms of the GNU General Public License as published by
  6. * the Free Software Foundation; either version 2 of the License, or
  7. * (at your option) any later version.
  8. *
  9. */
  10. #include <linux/clk-provider.h>
  11. #include <linux/clkdev.h>
  12. #include <linux/clk/at91_pmc.h>
  13. #include <linux/of.h>
  14. #include <linux/of_address.h>
  15. #include <linux/of_irq.h>
  16. #include <linux/io.h>
  17. #include <linux/wait.h>
  18. #include <linux/sched.h>
  19. #include <linux/interrupt.h>
  20. #include <linux/irq.h>
  21. #include "pmc.h"
  22. #define MASTER_SOURCE_MAX 4
  23. #define MASTER_PRES_MASK 0x7
  24. #define MASTER_PRES_MAX MASTER_PRES_MASK
  25. #define MASTER_DIV_SHIFT 8
  26. #define MASTER_DIV_MASK 0x3
  27. struct clk_master_characteristics {
  28. struct clk_range output;
  29. u32 divisors[4];
  30. u8 have_div3_pres;
  31. };
  32. struct clk_master_layout {
  33. u32 mask;
  34. u8 pres_shift;
  35. };
  36. #define to_clk_master(hw) container_of(hw, struct clk_master, hw)
  37. struct clk_master {
  38. struct clk_hw hw;
  39. struct at91_pmc *pmc;
  40. unsigned int irq;
  41. wait_queue_head_t wait;
  42. const struct clk_master_layout *layout;
  43. const struct clk_master_characteristics *characteristics;
  44. };
  45. static irqreturn_t clk_master_irq_handler(int irq, void *dev_id)
  46. {
  47. struct clk_master *master = (struct clk_master *)dev_id;
  48. wake_up(&master->wait);
  49. disable_irq_nosync(master->irq);
  50. return IRQ_HANDLED;
  51. }
  52. static int clk_master_prepare(struct clk_hw *hw)
  53. {
  54. struct clk_master *master = to_clk_master(hw);
  55. struct at91_pmc *pmc = master->pmc;
  56. while (!(pmc_read(pmc, AT91_PMC_SR) & AT91_PMC_MCKRDY)) {
  57. enable_irq(master->irq);
  58. wait_event(master->wait,
  59. pmc_read(pmc, AT91_PMC_SR) & AT91_PMC_MCKRDY);
  60. }
  61. return 0;
  62. }
  63. static int clk_master_is_prepared(struct clk_hw *hw)
  64. {
  65. struct clk_master *master = to_clk_master(hw);
  66. return !!(pmc_read(master->pmc, AT91_PMC_SR) & AT91_PMC_MCKRDY);
  67. }
  68. static unsigned long clk_master_recalc_rate(struct clk_hw *hw,
  69. unsigned long parent_rate)
  70. {
  71. u8 pres;
  72. u8 div;
  73. unsigned long rate = parent_rate;
  74. struct clk_master *master = to_clk_master(hw);
  75. struct at91_pmc *pmc = master->pmc;
  76. const struct clk_master_layout *layout = master->layout;
  77. const struct clk_master_characteristics *characteristics =
  78. master->characteristics;
  79. u32 tmp;
  80. pmc_lock(pmc);
  81. tmp = pmc_read(pmc, AT91_PMC_MCKR) & layout->mask;
  82. pmc_unlock(pmc);
  83. pres = (tmp >> layout->pres_shift) & MASTER_PRES_MASK;
  84. div = (tmp >> MASTER_DIV_SHIFT) & MASTER_DIV_MASK;
  85. if (characteristics->have_div3_pres && pres == MASTER_PRES_MAX)
  86. rate /= 3;
  87. else
  88. rate >>= pres;
  89. rate /= characteristics->divisors[div];
  90. if (rate < characteristics->output.min)
  91. pr_warn("master clk is underclocked");
  92. else if (rate > characteristics->output.max)
  93. pr_warn("master clk is overclocked");
  94. return rate;
  95. }
  96. static u8 clk_master_get_parent(struct clk_hw *hw)
  97. {
  98. struct clk_master *master = to_clk_master(hw);
  99. struct at91_pmc *pmc = master->pmc;
  100. return pmc_read(pmc, AT91_PMC_MCKR) & AT91_PMC_CSS;
  101. }
  102. static const struct clk_ops master_ops = {
  103. .prepare = clk_master_prepare,
  104. .is_prepared = clk_master_is_prepared,
  105. .recalc_rate = clk_master_recalc_rate,
  106. .get_parent = clk_master_get_parent,
  107. };
  108. static struct clk * __init
  109. at91_clk_register_master(struct at91_pmc *pmc, unsigned int irq,
  110. const char *name, int num_parents,
  111. const char **parent_names,
  112. const struct clk_master_layout *layout,
  113. const struct clk_master_characteristics *characteristics)
  114. {
  115. int ret;
  116. struct clk_master *master;
  117. struct clk *clk = NULL;
  118. struct clk_init_data init;
  119. if (!pmc || !irq || !name || !num_parents || !parent_names)
  120. return ERR_PTR(-EINVAL);
  121. master = kzalloc(sizeof(*master), GFP_KERNEL);
  122. if (!master)
  123. return ERR_PTR(-ENOMEM);
  124. init.name = name;
  125. init.ops = &master_ops;
  126. init.parent_names = parent_names;
  127. init.num_parents = num_parents;
  128. init.flags = 0;
  129. master->hw.init = &init;
  130. master->layout = layout;
  131. master->characteristics = characteristics;
  132. master->pmc = pmc;
  133. master->irq = irq;
  134. init_waitqueue_head(&master->wait);
  135. irq_set_status_flags(master->irq, IRQ_NOAUTOEN);
  136. ret = request_irq(master->irq, clk_master_irq_handler,
  137. IRQF_TRIGGER_HIGH, "clk-master", master);
  138. if (ret) {
  139. kfree(master);
  140. return ERR_PTR(ret);
  141. }
  142. clk = clk_register(NULL, &master->hw);
  143. if (IS_ERR(clk)) {
  144. free_irq(master->irq, master);
  145. kfree(master);
  146. }
  147. return clk;
  148. }
  149. static const struct clk_master_layout at91rm9200_master_layout = {
  150. .mask = 0x31F,
  151. .pres_shift = 2,
  152. };
  153. static const struct clk_master_layout at91sam9x5_master_layout = {
  154. .mask = 0x373,
  155. .pres_shift = 4,
  156. };
  157. static struct clk_master_characteristics * __init
  158. of_at91_clk_master_get_characteristics(struct device_node *np)
  159. {
  160. struct clk_master_characteristics *characteristics;
  161. characteristics = kzalloc(sizeof(*characteristics), GFP_KERNEL);
  162. if (!characteristics)
  163. return NULL;
  164. if (of_at91_get_clk_range(np, "atmel,clk-output-range", &characteristics->output))
  165. goto out_free_characteristics;
  166. of_property_read_u32_array(np, "atmel,clk-divisors",
  167. characteristics->divisors, 4);
  168. characteristics->have_div3_pres =
  169. of_property_read_bool(np, "atmel,master-clk-have-div3-pres");
  170. return characteristics;
  171. out_free_characteristics:
  172. kfree(characteristics);
  173. return NULL;
  174. }
  175. static void __init
  176. of_at91_clk_master_setup(struct device_node *np, struct at91_pmc *pmc,
  177. const struct clk_master_layout *layout)
  178. {
  179. struct clk *clk;
  180. int num_parents;
  181. unsigned int irq;
  182. const char *parent_names[MASTER_SOURCE_MAX];
  183. const char *name = np->name;
  184. struct clk_master_characteristics *characteristics;
  185. num_parents = of_clk_get_parent_count(np);
  186. if (num_parents <= 0 || num_parents > MASTER_SOURCE_MAX)
  187. return;
  188. of_clk_parent_fill(np, parent_names, num_parents);
  189. of_property_read_string(np, "clock-output-names", &name);
  190. characteristics = of_at91_clk_master_get_characteristics(np);
  191. if (!characteristics)
  192. return;
  193. irq = irq_of_parse_and_map(np, 0);
  194. if (!irq)
  195. goto out_free_characteristics;
  196. clk = at91_clk_register_master(pmc, irq, name, num_parents,
  197. parent_names, layout,
  198. characteristics);
  199. if (IS_ERR(clk))
  200. goto out_free_characteristics;
  201. of_clk_add_provider(np, of_clk_src_simple_get, clk);
  202. return;
  203. out_free_characteristics:
  204. kfree(characteristics);
  205. }
  206. void __init of_at91rm9200_clk_master_setup(struct device_node *np,
  207. struct at91_pmc *pmc)
  208. {
  209. of_at91_clk_master_setup(np, pmc, &at91rm9200_master_layout);
  210. }
  211. void __init of_at91sam9x5_clk_master_setup(struct device_node *np,
  212. struct at91_pmc *pmc)
  213. {
  214. of_at91_clk_master_setup(np, pmc, &at91sam9x5_master_layout);
  215. }