process.c 43 KB

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  1. /*
  2. * Derived from "arch/i386/kernel/process.c"
  3. * Copyright (C) 1995 Linus Torvalds
  4. *
  5. * Updated and modified by Cort Dougan (cort@cs.nmt.edu) and
  6. * Paul Mackerras (paulus@cs.anu.edu.au)
  7. *
  8. * PowerPC version
  9. * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
  10. *
  11. * This program is free software; you can redistribute it and/or
  12. * modify it under the terms of the GNU General Public License
  13. * as published by the Free Software Foundation; either version
  14. * 2 of the License, or (at your option) any later version.
  15. */
  16. #include <linux/errno.h>
  17. #include <linux/sched.h>
  18. #include <linux/kernel.h>
  19. #include <linux/mm.h>
  20. #include <linux/smp.h>
  21. #include <linux/stddef.h>
  22. #include <linux/unistd.h>
  23. #include <linux/ptrace.h>
  24. #include <linux/slab.h>
  25. #include <linux/user.h>
  26. #include <linux/elf.h>
  27. #include <linux/prctl.h>
  28. #include <linux/init_task.h>
  29. #include <linux/export.h>
  30. #include <linux/kallsyms.h>
  31. #include <linux/mqueue.h>
  32. #include <linux/hardirq.h>
  33. #include <linux/utsname.h>
  34. #include <linux/ftrace.h>
  35. #include <linux/kernel_stat.h>
  36. #include <linux/personality.h>
  37. #include <linux/random.h>
  38. #include <linux/hw_breakpoint.h>
  39. #include <linux/uaccess.h>
  40. #include <asm/pgtable.h>
  41. #include <asm/io.h>
  42. #include <asm/processor.h>
  43. #include <asm/mmu.h>
  44. #include <asm/prom.h>
  45. #include <asm/machdep.h>
  46. #include <asm/time.h>
  47. #include <asm/runlatch.h>
  48. #include <asm/syscalls.h>
  49. #include <asm/switch_to.h>
  50. #include <asm/tm.h>
  51. #include <asm/debug.h>
  52. #ifdef CONFIG_PPC64
  53. #include <asm/firmware.h>
  54. #endif
  55. #include <asm/code-patching.h>
  56. #include <linux/kprobes.h>
  57. #include <linux/kdebug.h>
  58. /* Transactional Memory debug */
  59. #ifdef TM_DEBUG_SW
  60. #define TM_DEBUG(x...) printk(KERN_INFO x)
  61. #else
  62. #define TM_DEBUG(x...) do { } while(0)
  63. #endif
  64. extern unsigned long _get_SP(void);
  65. #ifndef CONFIG_SMP
  66. struct task_struct *last_task_used_math = NULL;
  67. struct task_struct *last_task_used_altivec = NULL;
  68. struct task_struct *last_task_used_vsx = NULL;
  69. struct task_struct *last_task_used_spe = NULL;
  70. #endif
  71. #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
  72. void giveup_fpu_maybe_transactional(struct task_struct *tsk)
  73. {
  74. /*
  75. * If we are saving the current thread's registers, and the
  76. * thread is in a transactional state, set the TIF_RESTORE_TM
  77. * bit so that we know to restore the registers before
  78. * returning to userspace.
  79. */
  80. if (tsk == current && tsk->thread.regs &&
  81. MSR_TM_ACTIVE(tsk->thread.regs->msr) &&
  82. !test_thread_flag(TIF_RESTORE_TM)) {
  83. tsk->thread.ckpt_regs.msr = tsk->thread.regs->msr;
  84. set_thread_flag(TIF_RESTORE_TM);
  85. }
  86. giveup_fpu(tsk);
  87. }
  88. void giveup_altivec_maybe_transactional(struct task_struct *tsk)
  89. {
  90. /*
  91. * If we are saving the current thread's registers, and the
  92. * thread is in a transactional state, set the TIF_RESTORE_TM
  93. * bit so that we know to restore the registers before
  94. * returning to userspace.
  95. */
  96. if (tsk == current && tsk->thread.regs &&
  97. MSR_TM_ACTIVE(tsk->thread.regs->msr) &&
  98. !test_thread_flag(TIF_RESTORE_TM)) {
  99. tsk->thread.ckpt_regs.msr = tsk->thread.regs->msr;
  100. set_thread_flag(TIF_RESTORE_TM);
  101. }
  102. giveup_altivec(tsk);
  103. }
  104. #else
  105. #define giveup_fpu_maybe_transactional(tsk) giveup_fpu(tsk)
  106. #define giveup_altivec_maybe_transactional(tsk) giveup_altivec(tsk)
  107. #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
  108. #ifdef CONFIG_PPC_FPU
  109. /*
  110. * Make sure the floating-point register state in the
  111. * the thread_struct is up to date for task tsk.
  112. */
  113. void flush_fp_to_thread(struct task_struct *tsk)
  114. {
  115. if (tsk->thread.regs) {
  116. /*
  117. * We need to disable preemption here because if we didn't,
  118. * another process could get scheduled after the regs->msr
  119. * test but before we have finished saving the FP registers
  120. * to the thread_struct. That process could take over the
  121. * FPU, and then when we get scheduled again we would store
  122. * bogus values for the remaining FP registers.
  123. */
  124. preempt_disable();
  125. if (tsk->thread.regs->msr & MSR_FP) {
  126. #ifdef CONFIG_SMP
  127. /*
  128. * This should only ever be called for current or
  129. * for a stopped child process. Since we save away
  130. * the FP register state on context switch on SMP,
  131. * there is something wrong if a stopped child appears
  132. * to still have its FP state in the CPU registers.
  133. */
  134. BUG_ON(tsk != current);
  135. #endif
  136. giveup_fpu_maybe_transactional(tsk);
  137. }
  138. preempt_enable();
  139. }
  140. }
  141. EXPORT_SYMBOL_GPL(flush_fp_to_thread);
  142. #endif /* CONFIG_PPC_FPU */
  143. void enable_kernel_fp(void)
  144. {
  145. WARN_ON(preemptible());
  146. #ifdef CONFIG_SMP
  147. if (current->thread.regs && (current->thread.regs->msr & MSR_FP))
  148. giveup_fpu_maybe_transactional(current);
  149. else
  150. giveup_fpu(NULL); /* just enables FP for kernel */
  151. #else
  152. giveup_fpu_maybe_transactional(last_task_used_math);
  153. #endif /* CONFIG_SMP */
  154. }
  155. EXPORT_SYMBOL(enable_kernel_fp);
  156. #ifdef CONFIG_ALTIVEC
  157. void enable_kernel_altivec(void)
  158. {
  159. WARN_ON(preemptible());
  160. #ifdef CONFIG_SMP
  161. if (current->thread.regs && (current->thread.regs->msr & MSR_VEC))
  162. giveup_altivec_maybe_transactional(current);
  163. else
  164. giveup_altivec_notask();
  165. #else
  166. giveup_altivec_maybe_transactional(last_task_used_altivec);
  167. #endif /* CONFIG_SMP */
  168. }
  169. EXPORT_SYMBOL(enable_kernel_altivec);
  170. /*
  171. * Make sure the VMX/Altivec register state in the
  172. * the thread_struct is up to date for task tsk.
  173. */
  174. void flush_altivec_to_thread(struct task_struct *tsk)
  175. {
  176. if (tsk->thread.regs) {
  177. preempt_disable();
  178. if (tsk->thread.regs->msr & MSR_VEC) {
  179. #ifdef CONFIG_SMP
  180. BUG_ON(tsk != current);
  181. #endif
  182. giveup_altivec_maybe_transactional(tsk);
  183. }
  184. preempt_enable();
  185. }
  186. }
  187. EXPORT_SYMBOL_GPL(flush_altivec_to_thread);
  188. #endif /* CONFIG_ALTIVEC */
  189. #ifdef CONFIG_VSX
  190. void enable_kernel_vsx(void)
  191. {
  192. WARN_ON(preemptible());
  193. #ifdef CONFIG_SMP
  194. if (current->thread.regs && (current->thread.regs->msr & MSR_VSX))
  195. giveup_vsx(current);
  196. else
  197. giveup_vsx(NULL); /* just enable vsx for kernel - force */
  198. #else
  199. giveup_vsx(last_task_used_vsx);
  200. #endif /* CONFIG_SMP */
  201. }
  202. EXPORT_SYMBOL(enable_kernel_vsx);
  203. void giveup_vsx(struct task_struct *tsk)
  204. {
  205. giveup_fpu_maybe_transactional(tsk);
  206. giveup_altivec_maybe_transactional(tsk);
  207. __giveup_vsx(tsk);
  208. }
  209. EXPORT_SYMBOL(giveup_vsx);
  210. void flush_vsx_to_thread(struct task_struct *tsk)
  211. {
  212. if (tsk->thread.regs) {
  213. preempt_disable();
  214. if (tsk->thread.regs->msr & MSR_VSX) {
  215. #ifdef CONFIG_SMP
  216. BUG_ON(tsk != current);
  217. #endif
  218. giveup_vsx(tsk);
  219. }
  220. preempt_enable();
  221. }
  222. }
  223. EXPORT_SYMBOL_GPL(flush_vsx_to_thread);
  224. #endif /* CONFIG_VSX */
  225. #ifdef CONFIG_SPE
  226. void enable_kernel_spe(void)
  227. {
  228. WARN_ON(preemptible());
  229. #ifdef CONFIG_SMP
  230. if (current->thread.regs && (current->thread.regs->msr & MSR_SPE))
  231. giveup_spe(current);
  232. else
  233. giveup_spe(NULL); /* just enable SPE for kernel - force */
  234. #else
  235. giveup_spe(last_task_used_spe);
  236. #endif /* __SMP __ */
  237. }
  238. EXPORT_SYMBOL(enable_kernel_spe);
  239. void flush_spe_to_thread(struct task_struct *tsk)
  240. {
  241. if (tsk->thread.regs) {
  242. preempt_disable();
  243. if (tsk->thread.regs->msr & MSR_SPE) {
  244. #ifdef CONFIG_SMP
  245. BUG_ON(tsk != current);
  246. #endif
  247. tsk->thread.spefscr = mfspr(SPRN_SPEFSCR);
  248. giveup_spe(tsk);
  249. }
  250. preempt_enable();
  251. }
  252. }
  253. #endif /* CONFIG_SPE */
  254. #ifndef CONFIG_SMP
  255. /*
  256. * If we are doing lazy switching of CPU state (FP, altivec or SPE),
  257. * and the current task has some state, discard it.
  258. */
  259. void discard_lazy_cpu_state(void)
  260. {
  261. preempt_disable();
  262. if (last_task_used_math == current)
  263. last_task_used_math = NULL;
  264. #ifdef CONFIG_ALTIVEC
  265. if (last_task_used_altivec == current)
  266. last_task_used_altivec = NULL;
  267. #endif /* CONFIG_ALTIVEC */
  268. #ifdef CONFIG_VSX
  269. if (last_task_used_vsx == current)
  270. last_task_used_vsx = NULL;
  271. #endif /* CONFIG_VSX */
  272. #ifdef CONFIG_SPE
  273. if (last_task_used_spe == current)
  274. last_task_used_spe = NULL;
  275. #endif
  276. preempt_enable();
  277. }
  278. #endif /* CONFIG_SMP */
  279. #ifdef CONFIG_PPC_ADV_DEBUG_REGS
  280. void do_send_trap(struct pt_regs *regs, unsigned long address,
  281. unsigned long error_code, int signal_code, int breakpt)
  282. {
  283. siginfo_t info;
  284. current->thread.trap_nr = signal_code;
  285. if (notify_die(DIE_DABR_MATCH, "dabr_match", regs, error_code,
  286. 11, SIGSEGV) == NOTIFY_STOP)
  287. return;
  288. /* Deliver the signal to userspace */
  289. info.si_signo = SIGTRAP;
  290. info.si_errno = breakpt; /* breakpoint or watchpoint id */
  291. info.si_code = signal_code;
  292. info.si_addr = (void __user *)address;
  293. force_sig_info(SIGTRAP, &info, current);
  294. }
  295. #else /* !CONFIG_PPC_ADV_DEBUG_REGS */
  296. void do_break (struct pt_regs *regs, unsigned long address,
  297. unsigned long error_code)
  298. {
  299. siginfo_t info;
  300. current->thread.trap_nr = TRAP_HWBKPT;
  301. if (notify_die(DIE_DABR_MATCH, "dabr_match", regs, error_code,
  302. 11, SIGSEGV) == NOTIFY_STOP)
  303. return;
  304. if (debugger_break_match(regs))
  305. return;
  306. /* Clear the breakpoint */
  307. hw_breakpoint_disable();
  308. /* Deliver the signal to userspace */
  309. info.si_signo = SIGTRAP;
  310. info.si_errno = 0;
  311. info.si_code = TRAP_HWBKPT;
  312. info.si_addr = (void __user *)address;
  313. force_sig_info(SIGTRAP, &info, current);
  314. }
  315. #endif /* CONFIG_PPC_ADV_DEBUG_REGS */
  316. static DEFINE_PER_CPU(struct arch_hw_breakpoint, current_brk);
  317. #ifdef CONFIG_PPC_ADV_DEBUG_REGS
  318. /*
  319. * Set the debug registers back to their default "safe" values.
  320. */
  321. static void set_debug_reg_defaults(struct thread_struct *thread)
  322. {
  323. thread->debug.iac1 = thread->debug.iac2 = 0;
  324. #if CONFIG_PPC_ADV_DEBUG_IACS > 2
  325. thread->debug.iac3 = thread->debug.iac4 = 0;
  326. #endif
  327. thread->debug.dac1 = thread->debug.dac2 = 0;
  328. #if CONFIG_PPC_ADV_DEBUG_DVCS > 0
  329. thread->debug.dvc1 = thread->debug.dvc2 = 0;
  330. #endif
  331. thread->debug.dbcr0 = 0;
  332. #ifdef CONFIG_BOOKE
  333. /*
  334. * Force User/Supervisor bits to b11 (user-only MSR[PR]=1)
  335. */
  336. thread->debug.dbcr1 = DBCR1_IAC1US | DBCR1_IAC2US |
  337. DBCR1_IAC3US | DBCR1_IAC4US;
  338. /*
  339. * Force Data Address Compare User/Supervisor bits to be User-only
  340. * (0b11 MSR[PR]=1) and set all other bits in DBCR2 register to be 0.
  341. */
  342. thread->debug.dbcr2 = DBCR2_DAC1US | DBCR2_DAC2US;
  343. #else
  344. thread->debug.dbcr1 = 0;
  345. #endif
  346. }
  347. static void prime_debug_regs(struct debug_reg *debug)
  348. {
  349. /*
  350. * We could have inherited MSR_DE from userspace, since
  351. * it doesn't get cleared on exception entry. Make sure
  352. * MSR_DE is clear before we enable any debug events.
  353. */
  354. mtmsr(mfmsr() & ~MSR_DE);
  355. mtspr(SPRN_IAC1, debug->iac1);
  356. mtspr(SPRN_IAC2, debug->iac2);
  357. #if CONFIG_PPC_ADV_DEBUG_IACS > 2
  358. mtspr(SPRN_IAC3, debug->iac3);
  359. mtspr(SPRN_IAC4, debug->iac4);
  360. #endif
  361. mtspr(SPRN_DAC1, debug->dac1);
  362. mtspr(SPRN_DAC2, debug->dac2);
  363. #if CONFIG_PPC_ADV_DEBUG_DVCS > 0
  364. mtspr(SPRN_DVC1, debug->dvc1);
  365. mtspr(SPRN_DVC2, debug->dvc2);
  366. #endif
  367. mtspr(SPRN_DBCR0, debug->dbcr0);
  368. mtspr(SPRN_DBCR1, debug->dbcr1);
  369. #ifdef CONFIG_BOOKE
  370. mtspr(SPRN_DBCR2, debug->dbcr2);
  371. #endif
  372. }
  373. /*
  374. * Unless neither the old or new thread are making use of the
  375. * debug registers, set the debug registers from the values
  376. * stored in the new thread.
  377. */
  378. void switch_booke_debug_regs(struct debug_reg *new_debug)
  379. {
  380. if ((current->thread.debug.dbcr0 & DBCR0_IDM)
  381. || (new_debug->dbcr0 & DBCR0_IDM))
  382. prime_debug_regs(new_debug);
  383. }
  384. EXPORT_SYMBOL_GPL(switch_booke_debug_regs);
  385. #else /* !CONFIG_PPC_ADV_DEBUG_REGS */
  386. #ifndef CONFIG_HAVE_HW_BREAKPOINT
  387. static void set_debug_reg_defaults(struct thread_struct *thread)
  388. {
  389. thread->hw_brk.address = 0;
  390. thread->hw_brk.type = 0;
  391. set_breakpoint(&thread->hw_brk);
  392. }
  393. #endif /* !CONFIG_HAVE_HW_BREAKPOINT */
  394. #endif /* CONFIG_PPC_ADV_DEBUG_REGS */
  395. #ifdef CONFIG_PPC_ADV_DEBUG_REGS
  396. static inline int __set_dabr(unsigned long dabr, unsigned long dabrx)
  397. {
  398. mtspr(SPRN_DAC1, dabr);
  399. #ifdef CONFIG_PPC_47x
  400. isync();
  401. #endif
  402. return 0;
  403. }
  404. #elif defined(CONFIG_PPC_BOOK3S)
  405. static inline int __set_dabr(unsigned long dabr, unsigned long dabrx)
  406. {
  407. mtspr(SPRN_DABR, dabr);
  408. if (cpu_has_feature(CPU_FTR_DABRX))
  409. mtspr(SPRN_DABRX, dabrx);
  410. return 0;
  411. }
  412. #else
  413. static inline int __set_dabr(unsigned long dabr, unsigned long dabrx)
  414. {
  415. return -EINVAL;
  416. }
  417. #endif
  418. static inline int set_dabr(struct arch_hw_breakpoint *brk)
  419. {
  420. unsigned long dabr, dabrx;
  421. dabr = brk->address | (brk->type & HW_BRK_TYPE_DABR);
  422. dabrx = ((brk->type >> 3) & 0x7);
  423. if (ppc_md.set_dabr)
  424. return ppc_md.set_dabr(dabr, dabrx);
  425. return __set_dabr(dabr, dabrx);
  426. }
  427. static inline int set_dawr(struct arch_hw_breakpoint *brk)
  428. {
  429. unsigned long dawr, dawrx, mrd;
  430. dawr = brk->address;
  431. dawrx = (brk->type & (HW_BRK_TYPE_READ | HW_BRK_TYPE_WRITE)) \
  432. << (63 - 58); //* read/write bits */
  433. dawrx |= ((brk->type & (HW_BRK_TYPE_TRANSLATE)) >> 2) \
  434. << (63 - 59); //* translate */
  435. dawrx |= (brk->type & (HW_BRK_TYPE_PRIV_ALL)) \
  436. >> 3; //* PRIM bits */
  437. /* dawr length is stored in field MDR bits 48:53. Matches range in
  438. doublewords (64 bits) baised by -1 eg. 0b000000=1DW and
  439. 0b111111=64DW.
  440. brk->len is in bytes.
  441. This aligns up to double word size, shifts and does the bias.
  442. */
  443. mrd = ((brk->len + 7) >> 3) - 1;
  444. dawrx |= (mrd & 0x3f) << (63 - 53);
  445. if (ppc_md.set_dawr)
  446. return ppc_md.set_dawr(dawr, dawrx);
  447. mtspr(SPRN_DAWR, dawr);
  448. mtspr(SPRN_DAWRX, dawrx);
  449. return 0;
  450. }
  451. void __set_breakpoint(struct arch_hw_breakpoint *brk)
  452. {
  453. memcpy(this_cpu_ptr(&current_brk), brk, sizeof(*brk));
  454. if (cpu_has_feature(CPU_FTR_DAWR))
  455. set_dawr(brk);
  456. else
  457. set_dabr(brk);
  458. }
  459. void set_breakpoint(struct arch_hw_breakpoint *brk)
  460. {
  461. preempt_disable();
  462. __set_breakpoint(brk);
  463. preempt_enable();
  464. }
  465. #ifdef CONFIG_PPC64
  466. DEFINE_PER_CPU(struct cpu_usage, cpu_usage_array);
  467. #endif
  468. static inline bool hw_brk_match(struct arch_hw_breakpoint *a,
  469. struct arch_hw_breakpoint *b)
  470. {
  471. if (a->address != b->address)
  472. return false;
  473. if (a->type != b->type)
  474. return false;
  475. if (a->len != b->len)
  476. return false;
  477. return true;
  478. }
  479. #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
  480. static void tm_reclaim_thread(struct thread_struct *thr,
  481. struct thread_info *ti, uint8_t cause)
  482. {
  483. unsigned long msr_diff = 0;
  484. /*
  485. * If FP/VSX registers have been already saved to the
  486. * thread_struct, move them to the transact_fp array.
  487. * We clear the TIF_RESTORE_TM bit since after the reclaim
  488. * the thread will no longer be transactional.
  489. */
  490. if (test_ti_thread_flag(ti, TIF_RESTORE_TM)) {
  491. msr_diff = thr->ckpt_regs.msr & ~thr->regs->msr;
  492. if (msr_diff & MSR_FP)
  493. memcpy(&thr->transact_fp, &thr->fp_state,
  494. sizeof(struct thread_fp_state));
  495. if (msr_diff & MSR_VEC)
  496. memcpy(&thr->transact_vr, &thr->vr_state,
  497. sizeof(struct thread_vr_state));
  498. clear_ti_thread_flag(ti, TIF_RESTORE_TM);
  499. msr_diff &= MSR_FP | MSR_VEC | MSR_VSX | MSR_FE0 | MSR_FE1;
  500. }
  501. tm_reclaim(thr, thr->regs->msr, cause);
  502. /* Having done the reclaim, we now have the checkpointed
  503. * FP/VSX values in the registers. These might be valid
  504. * even if we have previously called enable_kernel_fp() or
  505. * flush_fp_to_thread(), so update thr->regs->msr to
  506. * indicate their current validity.
  507. */
  508. thr->regs->msr |= msr_diff;
  509. }
  510. void tm_reclaim_current(uint8_t cause)
  511. {
  512. tm_enable();
  513. tm_reclaim_thread(&current->thread, current_thread_info(), cause);
  514. }
  515. static inline void tm_reclaim_task(struct task_struct *tsk)
  516. {
  517. /* We have to work out if we're switching from/to a task that's in the
  518. * middle of a transaction.
  519. *
  520. * In switching we need to maintain a 2nd register state as
  521. * oldtask->thread.ckpt_regs. We tm_reclaim(oldproc); this saves the
  522. * checkpointed (tbegin) state in ckpt_regs and saves the transactional
  523. * (current) FPRs into oldtask->thread.transact_fpr[].
  524. *
  525. * We also context switch (save) TFHAR/TEXASR/TFIAR in here.
  526. */
  527. struct thread_struct *thr = &tsk->thread;
  528. if (!thr->regs)
  529. return;
  530. if (!MSR_TM_ACTIVE(thr->regs->msr))
  531. goto out_and_saveregs;
  532. /* Stash the original thread MSR, as giveup_fpu et al will
  533. * modify it. We hold onto it to see whether the task used
  534. * FP & vector regs. If the TIF_RESTORE_TM flag is set,
  535. * ckpt_regs.msr is already set.
  536. */
  537. if (!test_ti_thread_flag(task_thread_info(tsk), TIF_RESTORE_TM))
  538. thr->ckpt_regs.msr = thr->regs->msr;
  539. TM_DEBUG("--- tm_reclaim on pid %d (NIP=%lx, "
  540. "ccr=%lx, msr=%lx, trap=%lx)\n",
  541. tsk->pid, thr->regs->nip,
  542. thr->regs->ccr, thr->regs->msr,
  543. thr->regs->trap);
  544. tm_reclaim_thread(thr, task_thread_info(tsk), TM_CAUSE_RESCHED);
  545. TM_DEBUG("--- tm_reclaim on pid %d complete\n",
  546. tsk->pid);
  547. out_and_saveregs:
  548. /* Always save the regs here, even if a transaction's not active.
  549. * This context-switches a thread's TM info SPRs. We do it here to
  550. * be consistent with the restore path (in recheckpoint) which
  551. * cannot happen later in _switch().
  552. */
  553. tm_save_sprs(thr);
  554. }
  555. extern void __tm_recheckpoint(struct thread_struct *thread,
  556. unsigned long orig_msr);
  557. void tm_recheckpoint(struct thread_struct *thread,
  558. unsigned long orig_msr)
  559. {
  560. unsigned long flags;
  561. /* We really can't be interrupted here as the TEXASR registers can't
  562. * change and later in the trecheckpoint code, we have a userspace R1.
  563. * So let's hard disable over this region.
  564. */
  565. local_irq_save(flags);
  566. hard_irq_disable();
  567. /* The TM SPRs are restored here, so that TEXASR.FS can be set
  568. * before the trecheckpoint and no explosion occurs.
  569. */
  570. tm_restore_sprs(thread);
  571. __tm_recheckpoint(thread, orig_msr);
  572. local_irq_restore(flags);
  573. }
  574. static inline void tm_recheckpoint_new_task(struct task_struct *new)
  575. {
  576. unsigned long msr;
  577. if (!cpu_has_feature(CPU_FTR_TM))
  578. return;
  579. /* Recheckpoint the registers of the thread we're about to switch to.
  580. *
  581. * If the task was using FP, we non-lazily reload both the original and
  582. * the speculative FP register states. This is because the kernel
  583. * doesn't see if/when a TM rollback occurs, so if we take an FP
  584. * unavoidable later, we are unable to determine which set of FP regs
  585. * need to be restored.
  586. */
  587. if (!new->thread.regs)
  588. return;
  589. if (!MSR_TM_ACTIVE(new->thread.regs->msr)){
  590. tm_restore_sprs(&new->thread);
  591. return;
  592. }
  593. msr = new->thread.ckpt_regs.msr;
  594. /* Recheckpoint to restore original checkpointed register state. */
  595. TM_DEBUG("*** tm_recheckpoint of pid %d "
  596. "(new->msr 0x%lx, new->origmsr 0x%lx)\n",
  597. new->pid, new->thread.regs->msr, msr);
  598. /* This loads the checkpointed FP/VEC state, if used */
  599. tm_recheckpoint(&new->thread, msr);
  600. /* This loads the speculative FP/VEC state, if used */
  601. if (msr & MSR_FP) {
  602. do_load_up_transact_fpu(&new->thread);
  603. new->thread.regs->msr |=
  604. (MSR_FP | new->thread.fpexc_mode);
  605. }
  606. #ifdef CONFIG_ALTIVEC
  607. if (msr & MSR_VEC) {
  608. do_load_up_transact_altivec(&new->thread);
  609. new->thread.regs->msr |= MSR_VEC;
  610. }
  611. #endif
  612. /* We may as well turn on VSX too since all the state is restored now */
  613. if (msr & MSR_VSX)
  614. new->thread.regs->msr |= MSR_VSX;
  615. TM_DEBUG("*** tm_recheckpoint of pid %d complete "
  616. "(kernel msr 0x%lx)\n",
  617. new->pid, mfmsr());
  618. }
  619. static inline void __switch_to_tm(struct task_struct *prev)
  620. {
  621. if (cpu_has_feature(CPU_FTR_TM)) {
  622. tm_enable();
  623. tm_reclaim_task(prev);
  624. }
  625. }
  626. /*
  627. * This is called if we are on the way out to userspace and the
  628. * TIF_RESTORE_TM flag is set. It checks if we need to reload
  629. * FP and/or vector state and does so if necessary.
  630. * If userspace is inside a transaction (whether active or
  631. * suspended) and FP/VMX/VSX instructions have ever been enabled
  632. * inside that transaction, then we have to keep them enabled
  633. * and keep the FP/VMX/VSX state loaded while ever the transaction
  634. * continues. The reason is that if we didn't, and subsequently
  635. * got a FP/VMX/VSX unavailable interrupt inside a transaction,
  636. * we don't know whether it's the same transaction, and thus we
  637. * don't know which of the checkpointed state and the transactional
  638. * state to use.
  639. */
  640. void restore_tm_state(struct pt_regs *regs)
  641. {
  642. unsigned long msr_diff;
  643. clear_thread_flag(TIF_RESTORE_TM);
  644. if (!MSR_TM_ACTIVE(regs->msr))
  645. return;
  646. msr_diff = current->thread.ckpt_regs.msr & ~regs->msr;
  647. msr_diff &= MSR_FP | MSR_VEC | MSR_VSX;
  648. if (msr_diff & MSR_FP) {
  649. fp_enable();
  650. load_fp_state(&current->thread.fp_state);
  651. regs->msr |= current->thread.fpexc_mode;
  652. }
  653. if (msr_diff & MSR_VEC) {
  654. vec_enable();
  655. load_vr_state(&current->thread.vr_state);
  656. }
  657. regs->msr |= msr_diff;
  658. }
  659. #else
  660. #define tm_recheckpoint_new_task(new)
  661. #define __switch_to_tm(prev)
  662. #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
  663. struct task_struct *__switch_to(struct task_struct *prev,
  664. struct task_struct *new)
  665. {
  666. struct thread_struct *new_thread, *old_thread;
  667. struct task_struct *last;
  668. #ifdef CONFIG_PPC_BOOK3S_64
  669. struct ppc64_tlb_batch *batch;
  670. #endif
  671. WARN_ON(!irqs_disabled());
  672. /* Back up the TAR and DSCR across context switches.
  673. * Note that the TAR is not available for use in the kernel. (To
  674. * provide this, the TAR should be backed up/restored on exception
  675. * entry/exit instead, and be in pt_regs. FIXME, this should be in
  676. * pt_regs anyway (for debug).)
  677. * Save the TAR and DSCR here before we do treclaim/trecheckpoint as
  678. * these will change them.
  679. */
  680. save_early_sprs(&prev->thread);
  681. __switch_to_tm(prev);
  682. #ifdef CONFIG_SMP
  683. /* avoid complexity of lazy save/restore of fpu
  684. * by just saving it every time we switch out if
  685. * this task used the fpu during the last quantum.
  686. *
  687. * If it tries to use the fpu again, it'll trap and
  688. * reload its fp regs. So we don't have to do a restore
  689. * every switch, just a save.
  690. * -- Cort
  691. */
  692. if (prev->thread.regs && (prev->thread.regs->msr & MSR_FP))
  693. giveup_fpu(prev);
  694. #ifdef CONFIG_ALTIVEC
  695. /*
  696. * If the previous thread used altivec in the last quantum
  697. * (thus changing altivec regs) then save them.
  698. * We used to check the VRSAVE register but not all apps
  699. * set it, so we don't rely on it now (and in fact we need
  700. * to save & restore VSCR even if VRSAVE == 0). -- paulus
  701. *
  702. * On SMP we always save/restore altivec regs just to avoid the
  703. * complexity of changing processors.
  704. * -- Cort
  705. */
  706. if (prev->thread.regs && (prev->thread.regs->msr & MSR_VEC))
  707. giveup_altivec(prev);
  708. #endif /* CONFIG_ALTIVEC */
  709. #ifdef CONFIG_VSX
  710. if (prev->thread.regs && (prev->thread.regs->msr & MSR_VSX))
  711. /* VMX and FPU registers are already save here */
  712. __giveup_vsx(prev);
  713. #endif /* CONFIG_VSX */
  714. #ifdef CONFIG_SPE
  715. /*
  716. * If the previous thread used spe in the last quantum
  717. * (thus changing spe regs) then save them.
  718. *
  719. * On SMP we always save/restore spe regs just to avoid the
  720. * complexity of changing processors.
  721. */
  722. if ((prev->thread.regs && (prev->thread.regs->msr & MSR_SPE)))
  723. giveup_spe(prev);
  724. #endif /* CONFIG_SPE */
  725. #else /* CONFIG_SMP */
  726. #ifdef CONFIG_ALTIVEC
  727. /* Avoid the trap. On smp this this never happens since
  728. * we don't set last_task_used_altivec -- Cort
  729. */
  730. if (new->thread.regs && last_task_used_altivec == new)
  731. new->thread.regs->msr |= MSR_VEC;
  732. #endif /* CONFIG_ALTIVEC */
  733. #ifdef CONFIG_VSX
  734. if (new->thread.regs && last_task_used_vsx == new)
  735. new->thread.regs->msr |= MSR_VSX;
  736. #endif /* CONFIG_VSX */
  737. #ifdef CONFIG_SPE
  738. /* Avoid the trap. On smp this this never happens since
  739. * we don't set last_task_used_spe
  740. */
  741. if (new->thread.regs && last_task_used_spe == new)
  742. new->thread.regs->msr |= MSR_SPE;
  743. #endif /* CONFIG_SPE */
  744. #endif /* CONFIG_SMP */
  745. #ifdef CONFIG_PPC_ADV_DEBUG_REGS
  746. switch_booke_debug_regs(&new->thread.debug);
  747. #else
  748. /*
  749. * For PPC_BOOK3S_64, we use the hw-breakpoint interfaces that would
  750. * schedule DABR
  751. */
  752. #ifndef CONFIG_HAVE_HW_BREAKPOINT
  753. if (unlikely(!hw_brk_match(this_cpu_ptr(&current_brk), &new->thread.hw_brk)))
  754. __set_breakpoint(&new->thread.hw_brk);
  755. #endif /* CONFIG_HAVE_HW_BREAKPOINT */
  756. #endif
  757. new_thread = &new->thread;
  758. old_thread = &current->thread;
  759. #ifdef CONFIG_PPC64
  760. /*
  761. * Collect processor utilization data per process
  762. */
  763. if (firmware_has_feature(FW_FEATURE_SPLPAR)) {
  764. struct cpu_usage *cu = this_cpu_ptr(&cpu_usage_array);
  765. long unsigned start_tb, current_tb;
  766. start_tb = old_thread->start_tb;
  767. cu->current_tb = current_tb = mfspr(SPRN_PURR);
  768. old_thread->accum_tb += (current_tb - start_tb);
  769. new_thread->start_tb = current_tb;
  770. }
  771. #endif /* CONFIG_PPC64 */
  772. #ifdef CONFIG_PPC_BOOK3S_64
  773. batch = this_cpu_ptr(&ppc64_tlb_batch);
  774. if (batch->active) {
  775. current_thread_info()->local_flags |= _TLF_LAZY_MMU;
  776. if (batch->index)
  777. __flush_tlb_pending(batch);
  778. batch->active = 0;
  779. }
  780. #endif /* CONFIG_PPC_BOOK3S_64 */
  781. /*
  782. * We can't take a PMU exception inside _switch() since there is a
  783. * window where the kernel stack SLB and the kernel stack are out
  784. * of sync. Hard disable here.
  785. */
  786. hard_irq_disable();
  787. tm_recheckpoint_new_task(new);
  788. last = _switch(old_thread, new_thread);
  789. #ifdef CONFIG_PPC_BOOK3S_64
  790. if (current_thread_info()->local_flags & _TLF_LAZY_MMU) {
  791. current_thread_info()->local_flags &= ~_TLF_LAZY_MMU;
  792. batch = this_cpu_ptr(&ppc64_tlb_batch);
  793. batch->active = 1;
  794. }
  795. #endif /* CONFIG_PPC_BOOK3S_64 */
  796. return last;
  797. }
  798. static int instructions_to_print = 16;
  799. static void show_instructions(struct pt_regs *regs)
  800. {
  801. int i;
  802. unsigned long pc = regs->nip - (instructions_to_print * 3 / 4 *
  803. sizeof(int));
  804. printk("Instruction dump:");
  805. for (i = 0; i < instructions_to_print; i++) {
  806. int instr;
  807. if (!(i % 8))
  808. printk("\n");
  809. #if !defined(CONFIG_BOOKE)
  810. /* If executing with the IMMU off, adjust pc rather
  811. * than print XXXXXXXX.
  812. */
  813. if (!(regs->msr & MSR_IR))
  814. pc = (unsigned long)phys_to_virt(pc);
  815. #endif
  816. if (!__kernel_text_address(pc) ||
  817. probe_kernel_address((unsigned int __user *)pc, instr)) {
  818. printk(KERN_CONT "XXXXXXXX ");
  819. } else {
  820. if (regs->nip == pc)
  821. printk(KERN_CONT "<%08x> ", instr);
  822. else
  823. printk(KERN_CONT "%08x ", instr);
  824. }
  825. pc += sizeof(int);
  826. }
  827. printk("\n");
  828. }
  829. static struct regbit {
  830. unsigned long bit;
  831. const char *name;
  832. } msr_bits[] = {
  833. #if defined(CONFIG_PPC64) && !defined(CONFIG_BOOKE)
  834. {MSR_SF, "SF"},
  835. {MSR_HV, "HV"},
  836. #endif
  837. {MSR_VEC, "VEC"},
  838. {MSR_VSX, "VSX"},
  839. #ifdef CONFIG_BOOKE
  840. {MSR_CE, "CE"},
  841. #endif
  842. {MSR_EE, "EE"},
  843. {MSR_PR, "PR"},
  844. {MSR_FP, "FP"},
  845. {MSR_ME, "ME"},
  846. #ifdef CONFIG_BOOKE
  847. {MSR_DE, "DE"},
  848. #else
  849. {MSR_SE, "SE"},
  850. {MSR_BE, "BE"},
  851. #endif
  852. {MSR_IR, "IR"},
  853. {MSR_DR, "DR"},
  854. {MSR_PMM, "PMM"},
  855. #ifndef CONFIG_BOOKE
  856. {MSR_RI, "RI"},
  857. {MSR_LE, "LE"},
  858. #endif
  859. {0, NULL}
  860. };
  861. static void printbits(unsigned long val, struct regbit *bits)
  862. {
  863. const char *sep = "";
  864. printk("<");
  865. for (; bits->bit; ++bits)
  866. if (val & bits->bit) {
  867. printk("%s%s", sep, bits->name);
  868. sep = ",";
  869. }
  870. printk(">");
  871. }
  872. #ifdef CONFIG_PPC64
  873. #define REG "%016lx"
  874. #define REGS_PER_LINE 4
  875. #define LAST_VOLATILE 13
  876. #else
  877. #define REG "%08lx"
  878. #define REGS_PER_LINE 8
  879. #define LAST_VOLATILE 12
  880. #endif
  881. void show_regs(struct pt_regs * regs)
  882. {
  883. int i, trap;
  884. show_regs_print_info(KERN_DEFAULT);
  885. printk("NIP: "REG" LR: "REG" CTR: "REG"\n",
  886. regs->nip, regs->link, regs->ctr);
  887. printk("REGS: %p TRAP: %04lx %s (%s)\n",
  888. regs, regs->trap, print_tainted(), init_utsname()->release);
  889. printk("MSR: "REG" ", regs->msr);
  890. printbits(regs->msr, msr_bits);
  891. printk(" CR: %08lx XER: %08lx\n", regs->ccr, regs->xer);
  892. trap = TRAP(regs);
  893. if ((regs->trap != 0xc00) && cpu_has_feature(CPU_FTR_CFAR))
  894. printk("CFAR: "REG" ", regs->orig_gpr3);
  895. if (trap == 0x200 || trap == 0x300 || trap == 0x600)
  896. #if defined(CONFIG_4xx) || defined(CONFIG_BOOKE)
  897. printk("DEAR: "REG" ESR: "REG" ", regs->dar, regs->dsisr);
  898. #else
  899. printk("DAR: "REG" DSISR: %08lx ", regs->dar, regs->dsisr);
  900. #endif
  901. #ifdef CONFIG_PPC64
  902. printk("SOFTE: %ld ", regs->softe);
  903. #endif
  904. #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
  905. if (MSR_TM_ACTIVE(regs->msr))
  906. printk("\nPACATMSCRATCH: %016llx ", get_paca()->tm_scratch);
  907. #endif
  908. for (i = 0; i < 32; i++) {
  909. if ((i % REGS_PER_LINE) == 0)
  910. printk("\nGPR%02d: ", i);
  911. printk(REG " ", regs->gpr[i]);
  912. if (i == LAST_VOLATILE && !FULL_REGS(regs))
  913. break;
  914. }
  915. printk("\n");
  916. #ifdef CONFIG_KALLSYMS
  917. /*
  918. * Lookup NIP late so we have the best change of getting the
  919. * above info out without failing
  920. */
  921. printk("NIP ["REG"] %pS\n", regs->nip, (void *)regs->nip);
  922. printk("LR ["REG"] %pS\n", regs->link, (void *)regs->link);
  923. #endif
  924. show_stack(current, (unsigned long *) regs->gpr[1]);
  925. if (!user_mode(regs))
  926. show_instructions(regs);
  927. }
  928. void exit_thread(void)
  929. {
  930. discard_lazy_cpu_state();
  931. }
  932. void flush_thread(void)
  933. {
  934. discard_lazy_cpu_state();
  935. #ifdef CONFIG_HAVE_HW_BREAKPOINT
  936. flush_ptrace_hw_breakpoint(current);
  937. #else /* CONFIG_HAVE_HW_BREAKPOINT */
  938. set_debug_reg_defaults(&current->thread);
  939. #endif /* CONFIG_HAVE_HW_BREAKPOINT */
  940. }
  941. void
  942. release_thread(struct task_struct *t)
  943. {
  944. }
  945. /*
  946. * this gets called so that we can store coprocessor state into memory and
  947. * copy the current task into the new thread.
  948. */
  949. int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src)
  950. {
  951. flush_fp_to_thread(src);
  952. flush_altivec_to_thread(src);
  953. flush_vsx_to_thread(src);
  954. flush_spe_to_thread(src);
  955. /*
  956. * Flush TM state out so we can copy it. __switch_to_tm() does this
  957. * flush but it removes the checkpointed state from the current CPU and
  958. * transitions the CPU out of TM mode. Hence we need to call
  959. * tm_recheckpoint_new_task() (on the same task) to restore the
  960. * checkpointed state back and the TM mode.
  961. */
  962. __switch_to_tm(src);
  963. tm_recheckpoint_new_task(src);
  964. *dst = *src;
  965. clear_task_ebb(dst);
  966. return 0;
  967. }
  968. static void setup_ksp_vsid(struct task_struct *p, unsigned long sp)
  969. {
  970. #ifdef CONFIG_PPC_STD_MMU_64
  971. unsigned long sp_vsid;
  972. unsigned long llp = mmu_psize_defs[mmu_linear_psize].sllp;
  973. if (mmu_has_feature(MMU_FTR_1T_SEGMENT))
  974. sp_vsid = get_kernel_vsid(sp, MMU_SEGSIZE_1T)
  975. << SLB_VSID_SHIFT_1T;
  976. else
  977. sp_vsid = get_kernel_vsid(sp, MMU_SEGSIZE_256M)
  978. << SLB_VSID_SHIFT;
  979. sp_vsid |= SLB_VSID_KERNEL | llp;
  980. p->thread.ksp_vsid = sp_vsid;
  981. #endif
  982. }
  983. /*
  984. * Copy a thread..
  985. */
  986. /*
  987. * Copy architecture-specific thread state
  988. */
  989. int copy_thread(unsigned long clone_flags, unsigned long usp,
  990. unsigned long kthread_arg, struct task_struct *p)
  991. {
  992. struct pt_regs *childregs, *kregs;
  993. extern void ret_from_fork(void);
  994. extern void ret_from_kernel_thread(void);
  995. void (*f)(void);
  996. unsigned long sp = (unsigned long)task_stack_page(p) + THREAD_SIZE;
  997. /* Copy registers */
  998. sp -= sizeof(struct pt_regs);
  999. childregs = (struct pt_regs *) sp;
  1000. if (unlikely(p->flags & PF_KTHREAD)) {
  1001. /* kernel thread */
  1002. struct thread_info *ti = (void *)task_stack_page(p);
  1003. memset(childregs, 0, sizeof(struct pt_regs));
  1004. childregs->gpr[1] = sp + sizeof(struct pt_regs);
  1005. /* function */
  1006. if (usp)
  1007. childregs->gpr[14] = ppc_function_entry((void *)usp);
  1008. #ifdef CONFIG_PPC64
  1009. clear_tsk_thread_flag(p, TIF_32BIT);
  1010. childregs->softe = 1;
  1011. #endif
  1012. childregs->gpr[15] = kthread_arg;
  1013. p->thread.regs = NULL; /* no user register state */
  1014. ti->flags |= _TIF_RESTOREALL;
  1015. f = ret_from_kernel_thread;
  1016. } else {
  1017. /* user thread */
  1018. struct pt_regs *regs = current_pt_regs();
  1019. CHECK_FULL_REGS(regs);
  1020. *childregs = *regs;
  1021. if (usp)
  1022. childregs->gpr[1] = usp;
  1023. p->thread.regs = childregs;
  1024. childregs->gpr[3] = 0; /* Result from fork() */
  1025. if (clone_flags & CLONE_SETTLS) {
  1026. #ifdef CONFIG_PPC64
  1027. if (!is_32bit_task())
  1028. childregs->gpr[13] = childregs->gpr[6];
  1029. else
  1030. #endif
  1031. childregs->gpr[2] = childregs->gpr[6];
  1032. }
  1033. f = ret_from_fork;
  1034. }
  1035. sp -= STACK_FRAME_OVERHEAD;
  1036. /*
  1037. * The way this works is that at some point in the future
  1038. * some task will call _switch to switch to the new task.
  1039. * That will pop off the stack frame created below and start
  1040. * the new task running at ret_from_fork. The new task will
  1041. * do some house keeping and then return from the fork or clone
  1042. * system call, using the stack frame created above.
  1043. */
  1044. ((unsigned long *)sp)[0] = 0;
  1045. sp -= sizeof(struct pt_regs);
  1046. kregs = (struct pt_regs *) sp;
  1047. sp -= STACK_FRAME_OVERHEAD;
  1048. p->thread.ksp = sp;
  1049. #ifdef CONFIG_PPC32
  1050. p->thread.ksp_limit = (unsigned long)task_stack_page(p) +
  1051. _ALIGN_UP(sizeof(struct thread_info), 16);
  1052. #endif
  1053. #ifdef CONFIG_HAVE_HW_BREAKPOINT
  1054. p->thread.ptrace_bps[0] = NULL;
  1055. #endif
  1056. p->thread.fp_save_area = NULL;
  1057. #ifdef CONFIG_ALTIVEC
  1058. p->thread.vr_save_area = NULL;
  1059. #endif
  1060. setup_ksp_vsid(p, sp);
  1061. #ifdef CONFIG_PPC64
  1062. if (cpu_has_feature(CPU_FTR_DSCR)) {
  1063. p->thread.dscr_inherit = current->thread.dscr_inherit;
  1064. p->thread.dscr = current->thread.dscr;
  1065. }
  1066. if (cpu_has_feature(CPU_FTR_HAS_PPR))
  1067. p->thread.ppr = INIT_PPR;
  1068. #endif
  1069. kregs->nip = ppc_function_entry(f);
  1070. return 0;
  1071. }
  1072. /*
  1073. * Set up a thread for executing a new program
  1074. */
  1075. void start_thread(struct pt_regs *regs, unsigned long start, unsigned long sp)
  1076. {
  1077. #ifdef CONFIG_PPC64
  1078. unsigned long load_addr = regs->gpr[2]; /* saved by ELF_PLAT_INIT */
  1079. #endif
  1080. /*
  1081. * If we exec out of a kernel thread then thread.regs will not be
  1082. * set. Do it now.
  1083. */
  1084. if (!current->thread.regs) {
  1085. struct pt_regs *regs = task_stack_page(current) + THREAD_SIZE;
  1086. current->thread.regs = regs - 1;
  1087. }
  1088. memset(regs->gpr, 0, sizeof(regs->gpr));
  1089. regs->ctr = 0;
  1090. regs->link = 0;
  1091. regs->xer = 0;
  1092. regs->ccr = 0;
  1093. regs->gpr[1] = sp;
  1094. /*
  1095. * We have just cleared all the nonvolatile GPRs, so make
  1096. * FULL_REGS(regs) return true. This is necessary to allow
  1097. * ptrace to examine the thread immediately after exec.
  1098. */
  1099. regs->trap &= ~1UL;
  1100. #ifdef CONFIG_PPC32
  1101. regs->mq = 0;
  1102. regs->nip = start;
  1103. regs->msr = MSR_USER;
  1104. #else
  1105. if (!is_32bit_task()) {
  1106. unsigned long entry;
  1107. if (is_elf2_task()) {
  1108. /* Look ma, no function descriptors! */
  1109. entry = start;
  1110. /*
  1111. * Ulrich says:
  1112. * The latest iteration of the ABI requires that when
  1113. * calling a function (at its global entry point),
  1114. * the caller must ensure r12 holds the entry point
  1115. * address (so that the function can quickly
  1116. * establish addressability).
  1117. */
  1118. regs->gpr[12] = start;
  1119. /* Make sure that's restored on entry to userspace. */
  1120. set_thread_flag(TIF_RESTOREALL);
  1121. } else {
  1122. unsigned long toc;
  1123. /* start is a relocated pointer to the function
  1124. * descriptor for the elf _start routine. The first
  1125. * entry in the function descriptor is the entry
  1126. * address of _start and the second entry is the TOC
  1127. * value we need to use.
  1128. */
  1129. __get_user(entry, (unsigned long __user *)start);
  1130. __get_user(toc, (unsigned long __user *)start+1);
  1131. /* Check whether the e_entry function descriptor entries
  1132. * need to be relocated before we can use them.
  1133. */
  1134. if (load_addr != 0) {
  1135. entry += load_addr;
  1136. toc += load_addr;
  1137. }
  1138. regs->gpr[2] = toc;
  1139. }
  1140. regs->nip = entry;
  1141. regs->msr = MSR_USER64;
  1142. } else {
  1143. regs->nip = start;
  1144. regs->gpr[2] = 0;
  1145. regs->msr = MSR_USER32;
  1146. }
  1147. #endif
  1148. discard_lazy_cpu_state();
  1149. #ifdef CONFIG_VSX
  1150. current->thread.used_vsr = 0;
  1151. #endif
  1152. memset(&current->thread.fp_state, 0, sizeof(current->thread.fp_state));
  1153. current->thread.fp_save_area = NULL;
  1154. #ifdef CONFIG_ALTIVEC
  1155. memset(&current->thread.vr_state, 0, sizeof(current->thread.vr_state));
  1156. current->thread.vr_state.vscr.u[3] = 0x00010000; /* Java mode disabled */
  1157. current->thread.vr_save_area = NULL;
  1158. current->thread.vrsave = 0;
  1159. current->thread.used_vr = 0;
  1160. #endif /* CONFIG_ALTIVEC */
  1161. #ifdef CONFIG_SPE
  1162. memset(current->thread.evr, 0, sizeof(current->thread.evr));
  1163. current->thread.acc = 0;
  1164. current->thread.spefscr = 0;
  1165. current->thread.used_spe = 0;
  1166. #endif /* CONFIG_SPE */
  1167. #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
  1168. if (cpu_has_feature(CPU_FTR_TM))
  1169. regs->msr |= MSR_TM;
  1170. current->thread.tm_tfhar = 0;
  1171. current->thread.tm_texasr = 0;
  1172. current->thread.tm_tfiar = 0;
  1173. #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
  1174. }
  1175. EXPORT_SYMBOL(start_thread);
  1176. #define PR_FP_ALL_EXCEPT (PR_FP_EXC_DIV | PR_FP_EXC_OVF | PR_FP_EXC_UND \
  1177. | PR_FP_EXC_RES | PR_FP_EXC_INV)
  1178. int set_fpexc_mode(struct task_struct *tsk, unsigned int val)
  1179. {
  1180. struct pt_regs *regs = tsk->thread.regs;
  1181. /* This is a bit hairy. If we are an SPE enabled processor
  1182. * (have embedded fp) we store the IEEE exception enable flags in
  1183. * fpexc_mode. fpexc_mode is also used for setting FP exception
  1184. * mode (asyn, precise, disabled) for 'Classic' FP. */
  1185. if (val & PR_FP_EXC_SW_ENABLE) {
  1186. #ifdef CONFIG_SPE
  1187. if (cpu_has_feature(CPU_FTR_SPE)) {
  1188. /*
  1189. * When the sticky exception bits are set
  1190. * directly by userspace, it must call prctl
  1191. * with PR_GET_FPEXC (with PR_FP_EXC_SW_ENABLE
  1192. * in the existing prctl settings) or
  1193. * PR_SET_FPEXC (with PR_FP_EXC_SW_ENABLE in
  1194. * the bits being set). <fenv.h> functions
  1195. * saving and restoring the whole
  1196. * floating-point environment need to do so
  1197. * anyway to restore the prctl settings from
  1198. * the saved environment.
  1199. */
  1200. tsk->thread.spefscr_last = mfspr(SPRN_SPEFSCR);
  1201. tsk->thread.fpexc_mode = val &
  1202. (PR_FP_EXC_SW_ENABLE | PR_FP_ALL_EXCEPT);
  1203. return 0;
  1204. } else {
  1205. return -EINVAL;
  1206. }
  1207. #else
  1208. return -EINVAL;
  1209. #endif
  1210. }
  1211. /* on a CONFIG_SPE this does not hurt us. The bits that
  1212. * __pack_fe01 use do not overlap with bits used for
  1213. * PR_FP_EXC_SW_ENABLE. Additionally, the MSR[FE0,FE1] bits
  1214. * on CONFIG_SPE implementations are reserved so writing to
  1215. * them does not change anything */
  1216. if (val > PR_FP_EXC_PRECISE)
  1217. return -EINVAL;
  1218. tsk->thread.fpexc_mode = __pack_fe01(val);
  1219. if (regs != NULL && (regs->msr & MSR_FP) != 0)
  1220. regs->msr = (regs->msr & ~(MSR_FE0|MSR_FE1))
  1221. | tsk->thread.fpexc_mode;
  1222. return 0;
  1223. }
  1224. int get_fpexc_mode(struct task_struct *tsk, unsigned long adr)
  1225. {
  1226. unsigned int val;
  1227. if (tsk->thread.fpexc_mode & PR_FP_EXC_SW_ENABLE)
  1228. #ifdef CONFIG_SPE
  1229. if (cpu_has_feature(CPU_FTR_SPE)) {
  1230. /*
  1231. * When the sticky exception bits are set
  1232. * directly by userspace, it must call prctl
  1233. * with PR_GET_FPEXC (with PR_FP_EXC_SW_ENABLE
  1234. * in the existing prctl settings) or
  1235. * PR_SET_FPEXC (with PR_FP_EXC_SW_ENABLE in
  1236. * the bits being set). <fenv.h> functions
  1237. * saving and restoring the whole
  1238. * floating-point environment need to do so
  1239. * anyway to restore the prctl settings from
  1240. * the saved environment.
  1241. */
  1242. tsk->thread.spefscr_last = mfspr(SPRN_SPEFSCR);
  1243. val = tsk->thread.fpexc_mode;
  1244. } else
  1245. return -EINVAL;
  1246. #else
  1247. return -EINVAL;
  1248. #endif
  1249. else
  1250. val = __unpack_fe01(tsk->thread.fpexc_mode);
  1251. return put_user(val, (unsigned int __user *) adr);
  1252. }
  1253. int set_endian(struct task_struct *tsk, unsigned int val)
  1254. {
  1255. struct pt_regs *regs = tsk->thread.regs;
  1256. if ((val == PR_ENDIAN_LITTLE && !cpu_has_feature(CPU_FTR_REAL_LE)) ||
  1257. (val == PR_ENDIAN_PPC_LITTLE && !cpu_has_feature(CPU_FTR_PPC_LE)))
  1258. return -EINVAL;
  1259. if (regs == NULL)
  1260. return -EINVAL;
  1261. if (val == PR_ENDIAN_BIG)
  1262. regs->msr &= ~MSR_LE;
  1263. else if (val == PR_ENDIAN_LITTLE || val == PR_ENDIAN_PPC_LITTLE)
  1264. regs->msr |= MSR_LE;
  1265. else
  1266. return -EINVAL;
  1267. return 0;
  1268. }
  1269. int get_endian(struct task_struct *tsk, unsigned long adr)
  1270. {
  1271. struct pt_regs *regs = tsk->thread.regs;
  1272. unsigned int val;
  1273. if (!cpu_has_feature(CPU_FTR_PPC_LE) &&
  1274. !cpu_has_feature(CPU_FTR_REAL_LE))
  1275. return -EINVAL;
  1276. if (regs == NULL)
  1277. return -EINVAL;
  1278. if (regs->msr & MSR_LE) {
  1279. if (cpu_has_feature(CPU_FTR_REAL_LE))
  1280. val = PR_ENDIAN_LITTLE;
  1281. else
  1282. val = PR_ENDIAN_PPC_LITTLE;
  1283. } else
  1284. val = PR_ENDIAN_BIG;
  1285. return put_user(val, (unsigned int __user *)adr);
  1286. }
  1287. int set_unalign_ctl(struct task_struct *tsk, unsigned int val)
  1288. {
  1289. tsk->thread.align_ctl = val;
  1290. return 0;
  1291. }
  1292. int get_unalign_ctl(struct task_struct *tsk, unsigned long adr)
  1293. {
  1294. return put_user(tsk->thread.align_ctl, (unsigned int __user *)adr);
  1295. }
  1296. static inline int valid_irq_stack(unsigned long sp, struct task_struct *p,
  1297. unsigned long nbytes)
  1298. {
  1299. unsigned long stack_page;
  1300. unsigned long cpu = task_cpu(p);
  1301. /*
  1302. * Avoid crashing if the stack has overflowed and corrupted
  1303. * task_cpu(p), which is in the thread_info struct.
  1304. */
  1305. if (cpu < NR_CPUS && cpu_possible(cpu)) {
  1306. stack_page = (unsigned long) hardirq_ctx[cpu];
  1307. if (sp >= stack_page + sizeof(struct thread_struct)
  1308. && sp <= stack_page + THREAD_SIZE - nbytes)
  1309. return 1;
  1310. stack_page = (unsigned long) softirq_ctx[cpu];
  1311. if (sp >= stack_page + sizeof(struct thread_struct)
  1312. && sp <= stack_page + THREAD_SIZE - nbytes)
  1313. return 1;
  1314. }
  1315. return 0;
  1316. }
  1317. int validate_sp(unsigned long sp, struct task_struct *p,
  1318. unsigned long nbytes)
  1319. {
  1320. unsigned long stack_page = (unsigned long)task_stack_page(p);
  1321. if (sp >= stack_page + sizeof(struct thread_struct)
  1322. && sp <= stack_page + THREAD_SIZE - nbytes)
  1323. return 1;
  1324. return valid_irq_stack(sp, p, nbytes);
  1325. }
  1326. EXPORT_SYMBOL(validate_sp);
  1327. unsigned long get_wchan(struct task_struct *p)
  1328. {
  1329. unsigned long ip, sp;
  1330. int count = 0;
  1331. if (!p || p == current || p->state == TASK_RUNNING)
  1332. return 0;
  1333. sp = p->thread.ksp;
  1334. if (!validate_sp(sp, p, STACK_FRAME_OVERHEAD))
  1335. return 0;
  1336. do {
  1337. sp = *(unsigned long *)sp;
  1338. if (!validate_sp(sp, p, STACK_FRAME_OVERHEAD))
  1339. return 0;
  1340. if (count > 0) {
  1341. ip = ((unsigned long *)sp)[STACK_FRAME_LR_SAVE];
  1342. if (!in_sched_functions(ip))
  1343. return ip;
  1344. }
  1345. } while (count++ < 16);
  1346. return 0;
  1347. }
  1348. static int kstack_depth_to_print = CONFIG_PRINT_STACK_DEPTH;
  1349. void show_stack(struct task_struct *tsk, unsigned long *stack)
  1350. {
  1351. unsigned long sp, ip, lr, newsp;
  1352. int count = 0;
  1353. int firstframe = 1;
  1354. #ifdef CONFIG_FUNCTION_GRAPH_TRACER
  1355. int curr_frame = current->curr_ret_stack;
  1356. extern void return_to_handler(void);
  1357. unsigned long rth = (unsigned long)return_to_handler;
  1358. #endif
  1359. sp = (unsigned long) stack;
  1360. if (tsk == NULL)
  1361. tsk = current;
  1362. if (sp == 0) {
  1363. if (tsk == current)
  1364. sp = current_stack_pointer();
  1365. else
  1366. sp = tsk->thread.ksp;
  1367. }
  1368. lr = 0;
  1369. printk("Call Trace:\n");
  1370. do {
  1371. if (!validate_sp(sp, tsk, STACK_FRAME_OVERHEAD))
  1372. return;
  1373. stack = (unsigned long *) sp;
  1374. newsp = stack[0];
  1375. ip = stack[STACK_FRAME_LR_SAVE];
  1376. if (!firstframe || ip != lr) {
  1377. printk("["REG"] ["REG"] %pS", sp, ip, (void *)ip);
  1378. #ifdef CONFIG_FUNCTION_GRAPH_TRACER
  1379. if ((ip == rth) && curr_frame >= 0) {
  1380. printk(" (%pS)",
  1381. (void *)current->ret_stack[curr_frame].ret);
  1382. curr_frame--;
  1383. }
  1384. #endif
  1385. if (firstframe)
  1386. printk(" (unreliable)");
  1387. printk("\n");
  1388. }
  1389. firstframe = 0;
  1390. /*
  1391. * See if this is an exception frame.
  1392. * We look for the "regshere" marker in the current frame.
  1393. */
  1394. if (validate_sp(sp, tsk, STACK_INT_FRAME_SIZE)
  1395. && stack[STACK_FRAME_MARKER] == STACK_FRAME_REGS_MARKER) {
  1396. struct pt_regs *regs = (struct pt_regs *)
  1397. (sp + STACK_FRAME_OVERHEAD);
  1398. lr = regs->link;
  1399. printk("--- interrupt: %lx at %pS\n LR = %pS\n",
  1400. regs->trap, (void *)regs->nip, (void *)lr);
  1401. firstframe = 1;
  1402. }
  1403. sp = newsp;
  1404. } while (count++ < kstack_depth_to_print);
  1405. }
  1406. #ifdef CONFIG_PPC64
  1407. /* Called with hard IRQs off */
  1408. void notrace __ppc64_runlatch_on(void)
  1409. {
  1410. struct thread_info *ti = current_thread_info();
  1411. unsigned long ctrl;
  1412. ctrl = mfspr(SPRN_CTRLF);
  1413. ctrl |= CTRL_RUNLATCH;
  1414. mtspr(SPRN_CTRLT, ctrl);
  1415. ti->local_flags |= _TLF_RUNLATCH;
  1416. }
  1417. /* Called with hard IRQs off */
  1418. void notrace __ppc64_runlatch_off(void)
  1419. {
  1420. struct thread_info *ti = current_thread_info();
  1421. unsigned long ctrl;
  1422. ti->local_flags &= ~_TLF_RUNLATCH;
  1423. ctrl = mfspr(SPRN_CTRLF);
  1424. ctrl &= ~CTRL_RUNLATCH;
  1425. mtspr(SPRN_CTRLT, ctrl);
  1426. }
  1427. #endif /* CONFIG_PPC64 */
  1428. unsigned long arch_align_stack(unsigned long sp)
  1429. {
  1430. if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space)
  1431. sp -= get_random_int() & ~PAGE_MASK;
  1432. return sp & ~0xf;
  1433. }
  1434. static inline unsigned long brk_rnd(void)
  1435. {
  1436. unsigned long rnd = 0;
  1437. /* 8MB for 32bit, 1GB for 64bit */
  1438. if (is_32bit_task())
  1439. rnd = (long)(get_random_int() % (1<<(23-PAGE_SHIFT)));
  1440. else
  1441. rnd = (long)(get_random_int() % (1<<(30-PAGE_SHIFT)));
  1442. return rnd << PAGE_SHIFT;
  1443. }
  1444. unsigned long arch_randomize_brk(struct mm_struct *mm)
  1445. {
  1446. unsigned long base = mm->brk;
  1447. unsigned long ret;
  1448. #ifdef CONFIG_PPC_STD_MMU_64
  1449. /*
  1450. * If we are using 1TB segments and we are allowed to randomise
  1451. * the heap, we can put it above 1TB so it is backed by a 1TB
  1452. * segment. Otherwise the heap will be in the bottom 1TB
  1453. * which always uses 256MB segments and this may result in a
  1454. * performance penalty.
  1455. */
  1456. if (!is_32bit_task() && (mmu_highuser_ssize == MMU_SEGSIZE_1T))
  1457. base = max_t(unsigned long, mm->brk, 1UL << SID_SHIFT_1T);
  1458. #endif
  1459. ret = PAGE_ALIGN(base + brk_rnd());
  1460. if (ret < mm->brk)
  1461. return mm->brk;
  1462. return ret;
  1463. }