mips.c 40 KB

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  1. /*
  2. * This file is subject to the terms and conditions of the GNU General Public
  3. * License. See the file "COPYING" in the main directory of this archive
  4. * for more details.
  5. *
  6. * KVM/MIPS: MIPS specific KVM APIs
  7. *
  8. * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved.
  9. * Authors: Sanjay Lal <sanjayl@kymasys.com>
  10. */
  11. #include <linux/errno.h>
  12. #include <linux/err.h>
  13. #include <linux/kdebug.h>
  14. #include <linux/module.h>
  15. #include <linux/vmalloc.h>
  16. #include <linux/fs.h>
  17. #include <linux/bootmem.h>
  18. #include <asm/fpu.h>
  19. #include <asm/page.h>
  20. #include <asm/cacheflush.h>
  21. #include <asm/mmu_context.h>
  22. #include <asm/pgtable.h>
  23. #include <linux/kvm_host.h>
  24. #include "interrupt.h"
  25. #include "commpage.h"
  26. #define CREATE_TRACE_POINTS
  27. #include "trace.h"
  28. #ifndef VECTORSPACING
  29. #define VECTORSPACING 0x100 /* for EI/VI mode */
  30. #endif
  31. #define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x)
  32. struct kvm_stats_debugfs_item debugfs_entries[] = {
  33. { "wait", VCPU_STAT(wait_exits), KVM_STAT_VCPU },
  34. { "cache", VCPU_STAT(cache_exits), KVM_STAT_VCPU },
  35. { "signal", VCPU_STAT(signal_exits), KVM_STAT_VCPU },
  36. { "interrupt", VCPU_STAT(int_exits), KVM_STAT_VCPU },
  37. { "cop_unsuable", VCPU_STAT(cop_unusable_exits), KVM_STAT_VCPU },
  38. { "tlbmod", VCPU_STAT(tlbmod_exits), KVM_STAT_VCPU },
  39. { "tlbmiss_ld", VCPU_STAT(tlbmiss_ld_exits), KVM_STAT_VCPU },
  40. { "tlbmiss_st", VCPU_STAT(tlbmiss_st_exits), KVM_STAT_VCPU },
  41. { "addrerr_st", VCPU_STAT(addrerr_st_exits), KVM_STAT_VCPU },
  42. { "addrerr_ld", VCPU_STAT(addrerr_ld_exits), KVM_STAT_VCPU },
  43. { "syscall", VCPU_STAT(syscall_exits), KVM_STAT_VCPU },
  44. { "resvd_inst", VCPU_STAT(resvd_inst_exits), KVM_STAT_VCPU },
  45. { "break_inst", VCPU_STAT(break_inst_exits), KVM_STAT_VCPU },
  46. { "trap_inst", VCPU_STAT(trap_inst_exits), KVM_STAT_VCPU },
  47. { "msa_fpe", VCPU_STAT(msa_fpe_exits), KVM_STAT_VCPU },
  48. { "fpe", VCPU_STAT(fpe_exits), KVM_STAT_VCPU },
  49. { "msa_disabled", VCPU_STAT(msa_disabled_exits), KVM_STAT_VCPU },
  50. { "flush_dcache", VCPU_STAT(flush_dcache_exits), KVM_STAT_VCPU },
  51. { "halt_successful_poll", VCPU_STAT(halt_successful_poll), KVM_STAT_VCPU },
  52. { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll), KVM_STAT_VCPU },
  53. { "halt_wakeup", VCPU_STAT(halt_wakeup), KVM_STAT_VCPU },
  54. {NULL}
  55. };
  56. static int kvm_mips_reset_vcpu(struct kvm_vcpu *vcpu)
  57. {
  58. int i;
  59. for_each_possible_cpu(i) {
  60. vcpu->arch.guest_kernel_asid[i] = 0;
  61. vcpu->arch.guest_user_asid[i] = 0;
  62. }
  63. return 0;
  64. }
  65. /*
  66. * XXXKYMA: We are simulatoring a processor that has the WII bit set in
  67. * Config7, so we are "runnable" if interrupts are pending
  68. */
  69. int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
  70. {
  71. return !!(vcpu->arch.pending_exceptions);
  72. }
  73. int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
  74. {
  75. return 1;
  76. }
  77. int kvm_arch_hardware_enable(void)
  78. {
  79. return 0;
  80. }
  81. int kvm_arch_hardware_setup(void)
  82. {
  83. return 0;
  84. }
  85. void kvm_arch_check_processor_compat(void *rtn)
  86. {
  87. *(int *)rtn = 0;
  88. }
  89. static void kvm_mips_init_tlbs(struct kvm *kvm)
  90. {
  91. unsigned long wired;
  92. /*
  93. * Add a wired entry to the TLB, it is used to map the commpage to
  94. * the Guest kernel
  95. */
  96. wired = read_c0_wired();
  97. write_c0_wired(wired + 1);
  98. mtc0_tlbw_hazard();
  99. kvm->arch.commpage_tlb = wired;
  100. kvm_debug("[%d] commpage TLB: %d\n", smp_processor_id(),
  101. kvm->arch.commpage_tlb);
  102. }
  103. static void kvm_mips_init_vm_percpu(void *arg)
  104. {
  105. struct kvm *kvm = (struct kvm *)arg;
  106. kvm_mips_init_tlbs(kvm);
  107. kvm_mips_callbacks->vm_init(kvm);
  108. }
  109. int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
  110. {
  111. if (atomic_inc_return(&kvm_mips_instance) == 1) {
  112. kvm_debug("%s: 1st KVM instance, setup host TLB parameters\n",
  113. __func__);
  114. on_each_cpu(kvm_mips_init_vm_percpu, kvm, 1);
  115. }
  116. return 0;
  117. }
  118. void kvm_mips_free_vcpus(struct kvm *kvm)
  119. {
  120. unsigned int i;
  121. struct kvm_vcpu *vcpu;
  122. /* Put the pages we reserved for the guest pmap */
  123. for (i = 0; i < kvm->arch.guest_pmap_npages; i++) {
  124. if (kvm->arch.guest_pmap[i] != KVM_INVALID_PAGE)
  125. kvm_mips_release_pfn_clean(kvm->arch.guest_pmap[i]);
  126. }
  127. kfree(kvm->arch.guest_pmap);
  128. kvm_for_each_vcpu(i, vcpu, kvm) {
  129. kvm_arch_vcpu_free(vcpu);
  130. }
  131. mutex_lock(&kvm->lock);
  132. for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
  133. kvm->vcpus[i] = NULL;
  134. atomic_set(&kvm->online_vcpus, 0);
  135. mutex_unlock(&kvm->lock);
  136. }
  137. static void kvm_mips_uninit_tlbs(void *arg)
  138. {
  139. /* Restore wired count */
  140. write_c0_wired(0);
  141. mtc0_tlbw_hazard();
  142. /* Clear out all the TLBs */
  143. kvm_local_flush_tlb_all();
  144. }
  145. void kvm_arch_destroy_vm(struct kvm *kvm)
  146. {
  147. kvm_mips_free_vcpus(kvm);
  148. /* If this is the last instance, restore wired count */
  149. if (atomic_dec_return(&kvm_mips_instance) == 0) {
  150. kvm_debug("%s: last KVM instance, restoring TLB parameters\n",
  151. __func__);
  152. on_each_cpu(kvm_mips_uninit_tlbs, NULL, 1);
  153. }
  154. }
  155. long kvm_arch_dev_ioctl(struct file *filp, unsigned int ioctl,
  156. unsigned long arg)
  157. {
  158. return -ENOIOCTLCMD;
  159. }
  160. int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
  161. unsigned long npages)
  162. {
  163. return 0;
  164. }
  165. int kvm_arch_prepare_memory_region(struct kvm *kvm,
  166. struct kvm_memory_slot *memslot,
  167. const struct kvm_userspace_memory_region *mem,
  168. enum kvm_mr_change change)
  169. {
  170. return 0;
  171. }
  172. void kvm_arch_commit_memory_region(struct kvm *kvm,
  173. const struct kvm_userspace_memory_region *mem,
  174. const struct kvm_memory_slot *old,
  175. const struct kvm_memory_slot *new,
  176. enum kvm_mr_change change)
  177. {
  178. unsigned long npages = 0;
  179. int i;
  180. kvm_debug("%s: kvm: %p slot: %d, GPA: %llx, size: %llx, QVA: %llx\n",
  181. __func__, kvm, mem->slot, mem->guest_phys_addr,
  182. mem->memory_size, mem->userspace_addr);
  183. /* Setup Guest PMAP table */
  184. if (!kvm->arch.guest_pmap) {
  185. if (mem->slot == 0)
  186. npages = mem->memory_size >> PAGE_SHIFT;
  187. if (npages) {
  188. kvm->arch.guest_pmap_npages = npages;
  189. kvm->arch.guest_pmap =
  190. kzalloc(npages * sizeof(unsigned long), GFP_KERNEL);
  191. if (!kvm->arch.guest_pmap) {
  192. kvm_err("Failed to allocate guest PMAP");
  193. return;
  194. }
  195. kvm_debug("Allocated space for Guest PMAP Table (%ld pages) @ %p\n",
  196. npages, kvm->arch.guest_pmap);
  197. /* Now setup the page table */
  198. for (i = 0; i < npages; i++)
  199. kvm->arch.guest_pmap[i] = KVM_INVALID_PAGE;
  200. }
  201. }
  202. }
  203. struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm, unsigned int id)
  204. {
  205. int err, size, offset;
  206. void *gebase;
  207. int i;
  208. struct kvm_vcpu *vcpu = kzalloc(sizeof(struct kvm_vcpu), GFP_KERNEL);
  209. if (!vcpu) {
  210. err = -ENOMEM;
  211. goto out;
  212. }
  213. err = kvm_vcpu_init(vcpu, kvm, id);
  214. if (err)
  215. goto out_free_cpu;
  216. kvm_debug("kvm @ %p: create cpu %d at %p\n", kvm, id, vcpu);
  217. /*
  218. * Allocate space for host mode exception handlers that handle
  219. * guest mode exits
  220. */
  221. if (cpu_has_veic || cpu_has_vint)
  222. size = 0x200 + VECTORSPACING * 64;
  223. else
  224. size = 0x4000;
  225. /* Save Linux EBASE */
  226. vcpu->arch.host_ebase = (void *)read_c0_ebase();
  227. gebase = kzalloc(ALIGN(size, PAGE_SIZE), GFP_KERNEL);
  228. if (!gebase) {
  229. err = -ENOMEM;
  230. goto out_free_cpu;
  231. }
  232. kvm_debug("Allocated %d bytes for KVM Exception Handlers @ %p\n",
  233. ALIGN(size, PAGE_SIZE), gebase);
  234. /* Save new ebase */
  235. vcpu->arch.guest_ebase = gebase;
  236. /* Copy L1 Guest Exception handler to correct offset */
  237. /* TLB Refill, EXL = 0 */
  238. memcpy(gebase, mips32_exception,
  239. mips32_exceptionEnd - mips32_exception);
  240. /* General Exception Entry point */
  241. memcpy(gebase + 0x180, mips32_exception,
  242. mips32_exceptionEnd - mips32_exception);
  243. /* For vectored interrupts poke the exception code @ all offsets 0-7 */
  244. for (i = 0; i < 8; i++) {
  245. kvm_debug("L1 Vectored handler @ %p\n",
  246. gebase + 0x200 + (i * VECTORSPACING));
  247. memcpy(gebase + 0x200 + (i * VECTORSPACING), mips32_exception,
  248. mips32_exceptionEnd - mips32_exception);
  249. }
  250. /* General handler, relocate to unmapped space for sanity's sake */
  251. offset = 0x2000;
  252. kvm_debug("Installing KVM Exception handlers @ %p, %#x bytes\n",
  253. gebase + offset,
  254. mips32_GuestExceptionEnd - mips32_GuestException);
  255. memcpy(gebase + offset, mips32_GuestException,
  256. mips32_GuestExceptionEnd - mips32_GuestException);
  257. /* Invalidate the icache for these ranges */
  258. local_flush_icache_range((unsigned long)gebase,
  259. (unsigned long)gebase + ALIGN(size, PAGE_SIZE));
  260. /*
  261. * Allocate comm page for guest kernel, a TLB will be reserved for
  262. * mapping GVA @ 0xFFFF8000 to this page
  263. */
  264. vcpu->arch.kseg0_commpage = kzalloc(PAGE_SIZE << 1, GFP_KERNEL);
  265. if (!vcpu->arch.kseg0_commpage) {
  266. err = -ENOMEM;
  267. goto out_free_gebase;
  268. }
  269. kvm_debug("Allocated COMM page @ %p\n", vcpu->arch.kseg0_commpage);
  270. kvm_mips_commpage_init(vcpu);
  271. /* Init */
  272. vcpu->arch.last_sched_cpu = -1;
  273. /* Start off the timer */
  274. kvm_mips_init_count(vcpu);
  275. return vcpu;
  276. out_free_gebase:
  277. kfree(gebase);
  278. out_free_cpu:
  279. kfree(vcpu);
  280. out:
  281. return ERR_PTR(err);
  282. }
  283. void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
  284. {
  285. hrtimer_cancel(&vcpu->arch.comparecount_timer);
  286. kvm_vcpu_uninit(vcpu);
  287. kvm_mips_dump_stats(vcpu);
  288. kfree(vcpu->arch.guest_ebase);
  289. kfree(vcpu->arch.kseg0_commpage);
  290. kfree(vcpu);
  291. }
  292. void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
  293. {
  294. kvm_arch_vcpu_free(vcpu);
  295. }
  296. int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
  297. struct kvm_guest_debug *dbg)
  298. {
  299. return -ENOIOCTLCMD;
  300. }
  301. int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *run)
  302. {
  303. int r = 0;
  304. sigset_t sigsaved;
  305. if (vcpu->sigset_active)
  306. sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
  307. if (vcpu->mmio_needed) {
  308. if (!vcpu->mmio_is_write)
  309. kvm_mips_complete_mmio_load(vcpu, run);
  310. vcpu->mmio_needed = 0;
  311. }
  312. lose_fpu(1);
  313. local_irq_disable();
  314. /* Check if we have any exceptions/interrupts pending */
  315. kvm_mips_deliver_interrupts(vcpu,
  316. kvm_read_c0_guest_cause(vcpu->arch.cop0));
  317. __kvm_guest_enter();
  318. /* Disable hardware page table walking while in guest */
  319. htw_stop();
  320. r = __kvm_mips_vcpu_run(run, vcpu);
  321. /* Re-enable HTW before enabling interrupts */
  322. htw_start();
  323. __kvm_guest_exit();
  324. local_irq_enable();
  325. if (vcpu->sigset_active)
  326. sigprocmask(SIG_SETMASK, &sigsaved, NULL);
  327. return r;
  328. }
  329. int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
  330. struct kvm_mips_interrupt *irq)
  331. {
  332. int intr = (int)irq->irq;
  333. struct kvm_vcpu *dvcpu = NULL;
  334. if (intr == 3 || intr == -3 || intr == 4 || intr == -4)
  335. kvm_debug("%s: CPU: %d, INTR: %d\n", __func__, irq->cpu,
  336. (int)intr);
  337. if (irq->cpu == -1)
  338. dvcpu = vcpu;
  339. else
  340. dvcpu = vcpu->kvm->vcpus[irq->cpu];
  341. if (intr == 2 || intr == 3 || intr == 4) {
  342. kvm_mips_callbacks->queue_io_int(dvcpu, irq);
  343. } else if (intr == -2 || intr == -3 || intr == -4) {
  344. kvm_mips_callbacks->dequeue_io_int(dvcpu, irq);
  345. } else {
  346. kvm_err("%s: invalid interrupt ioctl (%d:%d)\n", __func__,
  347. irq->cpu, irq->irq);
  348. return -EINVAL;
  349. }
  350. dvcpu->arch.wait = 0;
  351. if (waitqueue_active(&dvcpu->wq))
  352. wake_up_interruptible(&dvcpu->wq);
  353. return 0;
  354. }
  355. int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
  356. struct kvm_mp_state *mp_state)
  357. {
  358. return -ENOIOCTLCMD;
  359. }
  360. int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
  361. struct kvm_mp_state *mp_state)
  362. {
  363. return -ENOIOCTLCMD;
  364. }
  365. static u64 kvm_mips_get_one_regs[] = {
  366. KVM_REG_MIPS_R0,
  367. KVM_REG_MIPS_R1,
  368. KVM_REG_MIPS_R2,
  369. KVM_REG_MIPS_R3,
  370. KVM_REG_MIPS_R4,
  371. KVM_REG_MIPS_R5,
  372. KVM_REG_MIPS_R6,
  373. KVM_REG_MIPS_R7,
  374. KVM_REG_MIPS_R8,
  375. KVM_REG_MIPS_R9,
  376. KVM_REG_MIPS_R10,
  377. KVM_REG_MIPS_R11,
  378. KVM_REG_MIPS_R12,
  379. KVM_REG_MIPS_R13,
  380. KVM_REG_MIPS_R14,
  381. KVM_REG_MIPS_R15,
  382. KVM_REG_MIPS_R16,
  383. KVM_REG_MIPS_R17,
  384. KVM_REG_MIPS_R18,
  385. KVM_REG_MIPS_R19,
  386. KVM_REG_MIPS_R20,
  387. KVM_REG_MIPS_R21,
  388. KVM_REG_MIPS_R22,
  389. KVM_REG_MIPS_R23,
  390. KVM_REG_MIPS_R24,
  391. KVM_REG_MIPS_R25,
  392. KVM_REG_MIPS_R26,
  393. KVM_REG_MIPS_R27,
  394. KVM_REG_MIPS_R28,
  395. KVM_REG_MIPS_R29,
  396. KVM_REG_MIPS_R30,
  397. KVM_REG_MIPS_R31,
  398. KVM_REG_MIPS_HI,
  399. KVM_REG_MIPS_LO,
  400. KVM_REG_MIPS_PC,
  401. KVM_REG_MIPS_CP0_INDEX,
  402. KVM_REG_MIPS_CP0_CONTEXT,
  403. KVM_REG_MIPS_CP0_USERLOCAL,
  404. KVM_REG_MIPS_CP0_PAGEMASK,
  405. KVM_REG_MIPS_CP0_WIRED,
  406. KVM_REG_MIPS_CP0_HWRENA,
  407. KVM_REG_MIPS_CP0_BADVADDR,
  408. KVM_REG_MIPS_CP0_COUNT,
  409. KVM_REG_MIPS_CP0_ENTRYHI,
  410. KVM_REG_MIPS_CP0_COMPARE,
  411. KVM_REG_MIPS_CP0_STATUS,
  412. KVM_REG_MIPS_CP0_CAUSE,
  413. KVM_REG_MIPS_CP0_EPC,
  414. KVM_REG_MIPS_CP0_PRID,
  415. KVM_REG_MIPS_CP0_CONFIG,
  416. KVM_REG_MIPS_CP0_CONFIG1,
  417. KVM_REG_MIPS_CP0_CONFIG2,
  418. KVM_REG_MIPS_CP0_CONFIG3,
  419. KVM_REG_MIPS_CP0_CONFIG4,
  420. KVM_REG_MIPS_CP0_CONFIG5,
  421. KVM_REG_MIPS_CP0_CONFIG7,
  422. KVM_REG_MIPS_CP0_ERROREPC,
  423. KVM_REG_MIPS_COUNT_CTL,
  424. KVM_REG_MIPS_COUNT_RESUME,
  425. KVM_REG_MIPS_COUNT_HZ,
  426. };
  427. static int kvm_mips_get_reg(struct kvm_vcpu *vcpu,
  428. const struct kvm_one_reg *reg)
  429. {
  430. struct mips_coproc *cop0 = vcpu->arch.cop0;
  431. struct mips_fpu_struct *fpu = &vcpu->arch.fpu;
  432. int ret;
  433. s64 v;
  434. s64 vs[2];
  435. unsigned int idx;
  436. switch (reg->id) {
  437. /* General purpose registers */
  438. case KVM_REG_MIPS_R0 ... KVM_REG_MIPS_R31:
  439. v = (long)vcpu->arch.gprs[reg->id - KVM_REG_MIPS_R0];
  440. break;
  441. case KVM_REG_MIPS_HI:
  442. v = (long)vcpu->arch.hi;
  443. break;
  444. case KVM_REG_MIPS_LO:
  445. v = (long)vcpu->arch.lo;
  446. break;
  447. case KVM_REG_MIPS_PC:
  448. v = (long)vcpu->arch.pc;
  449. break;
  450. /* Floating point registers */
  451. case KVM_REG_MIPS_FPR_32(0) ... KVM_REG_MIPS_FPR_32(31):
  452. if (!kvm_mips_guest_has_fpu(&vcpu->arch))
  453. return -EINVAL;
  454. idx = reg->id - KVM_REG_MIPS_FPR_32(0);
  455. /* Odd singles in top of even double when FR=0 */
  456. if (kvm_read_c0_guest_status(cop0) & ST0_FR)
  457. v = get_fpr32(&fpu->fpr[idx], 0);
  458. else
  459. v = get_fpr32(&fpu->fpr[idx & ~1], idx & 1);
  460. break;
  461. case KVM_REG_MIPS_FPR_64(0) ... KVM_REG_MIPS_FPR_64(31):
  462. if (!kvm_mips_guest_has_fpu(&vcpu->arch))
  463. return -EINVAL;
  464. idx = reg->id - KVM_REG_MIPS_FPR_64(0);
  465. /* Can't access odd doubles in FR=0 mode */
  466. if (idx & 1 && !(kvm_read_c0_guest_status(cop0) & ST0_FR))
  467. return -EINVAL;
  468. v = get_fpr64(&fpu->fpr[idx], 0);
  469. break;
  470. case KVM_REG_MIPS_FCR_IR:
  471. if (!kvm_mips_guest_has_fpu(&vcpu->arch))
  472. return -EINVAL;
  473. v = boot_cpu_data.fpu_id;
  474. break;
  475. case KVM_REG_MIPS_FCR_CSR:
  476. if (!kvm_mips_guest_has_fpu(&vcpu->arch))
  477. return -EINVAL;
  478. v = fpu->fcr31;
  479. break;
  480. /* MIPS SIMD Architecture (MSA) registers */
  481. case KVM_REG_MIPS_VEC_128(0) ... KVM_REG_MIPS_VEC_128(31):
  482. if (!kvm_mips_guest_has_msa(&vcpu->arch))
  483. return -EINVAL;
  484. /* Can't access MSA registers in FR=0 mode */
  485. if (!(kvm_read_c0_guest_status(cop0) & ST0_FR))
  486. return -EINVAL;
  487. idx = reg->id - KVM_REG_MIPS_VEC_128(0);
  488. #ifdef CONFIG_CPU_LITTLE_ENDIAN
  489. /* least significant byte first */
  490. vs[0] = get_fpr64(&fpu->fpr[idx], 0);
  491. vs[1] = get_fpr64(&fpu->fpr[idx], 1);
  492. #else
  493. /* most significant byte first */
  494. vs[0] = get_fpr64(&fpu->fpr[idx], 1);
  495. vs[1] = get_fpr64(&fpu->fpr[idx], 0);
  496. #endif
  497. break;
  498. case KVM_REG_MIPS_MSA_IR:
  499. if (!kvm_mips_guest_has_msa(&vcpu->arch))
  500. return -EINVAL;
  501. v = boot_cpu_data.msa_id;
  502. break;
  503. case KVM_REG_MIPS_MSA_CSR:
  504. if (!kvm_mips_guest_has_msa(&vcpu->arch))
  505. return -EINVAL;
  506. v = fpu->msacsr;
  507. break;
  508. /* Co-processor 0 registers */
  509. case KVM_REG_MIPS_CP0_INDEX:
  510. v = (long)kvm_read_c0_guest_index(cop0);
  511. break;
  512. case KVM_REG_MIPS_CP0_CONTEXT:
  513. v = (long)kvm_read_c0_guest_context(cop0);
  514. break;
  515. case KVM_REG_MIPS_CP0_USERLOCAL:
  516. v = (long)kvm_read_c0_guest_userlocal(cop0);
  517. break;
  518. case KVM_REG_MIPS_CP0_PAGEMASK:
  519. v = (long)kvm_read_c0_guest_pagemask(cop0);
  520. break;
  521. case KVM_REG_MIPS_CP0_WIRED:
  522. v = (long)kvm_read_c0_guest_wired(cop0);
  523. break;
  524. case KVM_REG_MIPS_CP0_HWRENA:
  525. v = (long)kvm_read_c0_guest_hwrena(cop0);
  526. break;
  527. case KVM_REG_MIPS_CP0_BADVADDR:
  528. v = (long)kvm_read_c0_guest_badvaddr(cop0);
  529. break;
  530. case KVM_REG_MIPS_CP0_ENTRYHI:
  531. v = (long)kvm_read_c0_guest_entryhi(cop0);
  532. break;
  533. case KVM_REG_MIPS_CP0_COMPARE:
  534. v = (long)kvm_read_c0_guest_compare(cop0);
  535. break;
  536. case KVM_REG_MIPS_CP0_STATUS:
  537. v = (long)kvm_read_c0_guest_status(cop0);
  538. break;
  539. case KVM_REG_MIPS_CP0_CAUSE:
  540. v = (long)kvm_read_c0_guest_cause(cop0);
  541. break;
  542. case KVM_REG_MIPS_CP0_EPC:
  543. v = (long)kvm_read_c0_guest_epc(cop0);
  544. break;
  545. case KVM_REG_MIPS_CP0_PRID:
  546. v = (long)kvm_read_c0_guest_prid(cop0);
  547. break;
  548. case KVM_REG_MIPS_CP0_CONFIG:
  549. v = (long)kvm_read_c0_guest_config(cop0);
  550. break;
  551. case KVM_REG_MIPS_CP0_CONFIG1:
  552. v = (long)kvm_read_c0_guest_config1(cop0);
  553. break;
  554. case KVM_REG_MIPS_CP0_CONFIG2:
  555. v = (long)kvm_read_c0_guest_config2(cop0);
  556. break;
  557. case KVM_REG_MIPS_CP0_CONFIG3:
  558. v = (long)kvm_read_c0_guest_config3(cop0);
  559. break;
  560. case KVM_REG_MIPS_CP0_CONFIG4:
  561. v = (long)kvm_read_c0_guest_config4(cop0);
  562. break;
  563. case KVM_REG_MIPS_CP0_CONFIG5:
  564. v = (long)kvm_read_c0_guest_config5(cop0);
  565. break;
  566. case KVM_REG_MIPS_CP0_CONFIG7:
  567. v = (long)kvm_read_c0_guest_config7(cop0);
  568. break;
  569. case KVM_REG_MIPS_CP0_ERROREPC:
  570. v = (long)kvm_read_c0_guest_errorepc(cop0);
  571. break;
  572. /* registers to be handled specially */
  573. case KVM_REG_MIPS_CP0_COUNT:
  574. case KVM_REG_MIPS_COUNT_CTL:
  575. case KVM_REG_MIPS_COUNT_RESUME:
  576. case KVM_REG_MIPS_COUNT_HZ:
  577. ret = kvm_mips_callbacks->get_one_reg(vcpu, reg, &v);
  578. if (ret)
  579. return ret;
  580. break;
  581. default:
  582. return -EINVAL;
  583. }
  584. if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U64) {
  585. u64 __user *uaddr64 = (u64 __user *)(long)reg->addr;
  586. return put_user(v, uaddr64);
  587. } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U32) {
  588. u32 __user *uaddr32 = (u32 __user *)(long)reg->addr;
  589. u32 v32 = (u32)v;
  590. return put_user(v32, uaddr32);
  591. } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U128) {
  592. void __user *uaddr = (void __user *)(long)reg->addr;
  593. return copy_to_user(uaddr, vs, 16);
  594. } else {
  595. return -EINVAL;
  596. }
  597. }
  598. static int kvm_mips_set_reg(struct kvm_vcpu *vcpu,
  599. const struct kvm_one_reg *reg)
  600. {
  601. struct mips_coproc *cop0 = vcpu->arch.cop0;
  602. struct mips_fpu_struct *fpu = &vcpu->arch.fpu;
  603. s64 v;
  604. s64 vs[2];
  605. unsigned int idx;
  606. if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U64) {
  607. u64 __user *uaddr64 = (u64 __user *)(long)reg->addr;
  608. if (get_user(v, uaddr64) != 0)
  609. return -EFAULT;
  610. } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U32) {
  611. u32 __user *uaddr32 = (u32 __user *)(long)reg->addr;
  612. s32 v32;
  613. if (get_user(v32, uaddr32) != 0)
  614. return -EFAULT;
  615. v = (s64)v32;
  616. } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U128) {
  617. void __user *uaddr = (void __user *)(long)reg->addr;
  618. return copy_from_user(vs, uaddr, 16);
  619. } else {
  620. return -EINVAL;
  621. }
  622. switch (reg->id) {
  623. /* General purpose registers */
  624. case KVM_REG_MIPS_R0:
  625. /* Silently ignore requests to set $0 */
  626. break;
  627. case KVM_REG_MIPS_R1 ... KVM_REG_MIPS_R31:
  628. vcpu->arch.gprs[reg->id - KVM_REG_MIPS_R0] = v;
  629. break;
  630. case KVM_REG_MIPS_HI:
  631. vcpu->arch.hi = v;
  632. break;
  633. case KVM_REG_MIPS_LO:
  634. vcpu->arch.lo = v;
  635. break;
  636. case KVM_REG_MIPS_PC:
  637. vcpu->arch.pc = v;
  638. break;
  639. /* Floating point registers */
  640. case KVM_REG_MIPS_FPR_32(0) ... KVM_REG_MIPS_FPR_32(31):
  641. if (!kvm_mips_guest_has_fpu(&vcpu->arch))
  642. return -EINVAL;
  643. idx = reg->id - KVM_REG_MIPS_FPR_32(0);
  644. /* Odd singles in top of even double when FR=0 */
  645. if (kvm_read_c0_guest_status(cop0) & ST0_FR)
  646. set_fpr32(&fpu->fpr[idx], 0, v);
  647. else
  648. set_fpr32(&fpu->fpr[idx & ~1], idx & 1, v);
  649. break;
  650. case KVM_REG_MIPS_FPR_64(0) ... KVM_REG_MIPS_FPR_64(31):
  651. if (!kvm_mips_guest_has_fpu(&vcpu->arch))
  652. return -EINVAL;
  653. idx = reg->id - KVM_REG_MIPS_FPR_64(0);
  654. /* Can't access odd doubles in FR=0 mode */
  655. if (idx & 1 && !(kvm_read_c0_guest_status(cop0) & ST0_FR))
  656. return -EINVAL;
  657. set_fpr64(&fpu->fpr[idx], 0, v);
  658. break;
  659. case KVM_REG_MIPS_FCR_IR:
  660. if (!kvm_mips_guest_has_fpu(&vcpu->arch))
  661. return -EINVAL;
  662. /* Read-only */
  663. break;
  664. case KVM_REG_MIPS_FCR_CSR:
  665. if (!kvm_mips_guest_has_fpu(&vcpu->arch))
  666. return -EINVAL;
  667. fpu->fcr31 = v;
  668. break;
  669. /* MIPS SIMD Architecture (MSA) registers */
  670. case KVM_REG_MIPS_VEC_128(0) ... KVM_REG_MIPS_VEC_128(31):
  671. if (!kvm_mips_guest_has_msa(&vcpu->arch))
  672. return -EINVAL;
  673. idx = reg->id - KVM_REG_MIPS_VEC_128(0);
  674. #ifdef CONFIG_CPU_LITTLE_ENDIAN
  675. /* least significant byte first */
  676. set_fpr64(&fpu->fpr[idx], 0, vs[0]);
  677. set_fpr64(&fpu->fpr[idx], 1, vs[1]);
  678. #else
  679. /* most significant byte first */
  680. set_fpr64(&fpu->fpr[idx], 1, vs[0]);
  681. set_fpr64(&fpu->fpr[idx], 0, vs[1]);
  682. #endif
  683. break;
  684. case KVM_REG_MIPS_MSA_IR:
  685. if (!kvm_mips_guest_has_msa(&vcpu->arch))
  686. return -EINVAL;
  687. /* Read-only */
  688. break;
  689. case KVM_REG_MIPS_MSA_CSR:
  690. if (!kvm_mips_guest_has_msa(&vcpu->arch))
  691. return -EINVAL;
  692. fpu->msacsr = v;
  693. break;
  694. /* Co-processor 0 registers */
  695. case KVM_REG_MIPS_CP0_INDEX:
  696. kvm_write_c0_guest_index(cop0, v);
  697. break;
  698. case KVM_REG_MIPS_CP0_CONTEXT:
  699. kvm_write_c0_guest_context(cop0, v);
  700. break;
  701. case KVM_REG_MIPS_CP0_USERLOCAL:
  702. kvm_write_c0_guest_userlocal(cop0, v);
  703. break;
  704. case KVM_REG_MIPS_CP0_PAGEMASK:
  705. kvm_write_c0_guest_pagemask(cop0, v);
  706. break;
  707. case KVM_REG_MIPS_CP0_WIRED:
  708. kvm_write_c0_guest_wired(cop0, v);
  709. break;
  710. case KVM_REG_MIPS_CP0_HWRENA:
  711. kvm_write_c0_guest_hwrena(cop0, v);
  712. break;
  713. case KVM_REG_MIPS_CP0_BADVADDR:
  714. kvm_write_c0_guest_badvaddr(cop0, v);
  715. break;
  716. case KVM_REG_MIPS_CP0_ENTRYHI:
  717. kvm_write_c0_guest_entryhi(cop0, v);
  718. break;
  719. case KVM_REG_MIPS_CP0_STATUS:
  720. kvm_write_c0_guest_status(cop0, v);
  721. break;
  722. case KVM_REG_MIPS_CP0_EPC:
  723. kvm_write_c0_guest_epc(cop0, v);
  724. break;
  725. case KVM_REG_MIPS_CP0_PRID:
  726. kvm_write_c0_guest_prid(cop0, v);
  727. break;
  728. case KVM_REG_MIPS_CP0_ERROREPC:
  729. kvm_write_c0_guest_errorepc(cop0, v);
  730. break;
  731. /* registers to be handled specially */
  732. case KVM_REG_MIPS_CP0_COUNT:
  733. case KVM_REG_MIPS_CP0_COMPARE:
  734. case KVM_REG_MIPS_CP0_CAUSE:
  735. case KVM_REG_MIPS_CP0_CONFIG:
  736. case KVM_REG_MIPS_CP0_CONFIG1:
  737. case KVM_REG_MIPS_CP0_CONFIG2:
  738. case KVM_REG_MIPS_CP0_CONFIG3:
  739. case KVM_REG_MIPS_CP0_CONFIG4:
  740. case KVM_REG_MIPS_CP0_CONFIG5:
  741. case KVM_REG_MIPS_COUNT_CTL:
  742. case KVM_REG_MIPS_COUNT_RESUME:
  743. case KVM_REG_MIPS_COUNT_HZ:
  744. return kvm_mips_callbacks->set_one_reg(vcpu, reg, v);
  745. default:
  746. return -EINVAL;
  747. }
  748. return 0;
  749. }
  750. static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
  751. struct kvm_enable_cap *cap)
  752. {
  753. int r = 0;
  754. if (!kvm_vm_ioctl_check_extension(vcpu->kvm, cap->cap))
  755. return -EINVAL;
  756. if (cap->flags)
  757. return -EINVAL;
  758. if (cap->args[0])
  759. return -EINVAL;
  760. switch (cap->cap) {
  761. case KVM_CAP_MIPS_FPU:
  762. vcpu->arch.fpu_enabled = true;
  763. break;
  764. case KVM_CAP_MIPS_MSA:
  765. vcpu->arch.msa_enabled = true;
  766. break;
  767. default:
  768. r = -EINVAL;
  769. break;
  770. }
  771. return r;
  772. }
  773. long kvm_arch_vcpu_ioctl(struct file *filp, unsigned int ioctl,
  774. unsigned long arg)
  775. {
  776. struct kvm_vcpu *vcpu = filp->private_data;
  777. void __user *argp = (void __user *)arg;
  778. long r;
  779. switch (ioctl) {
  780. case KVM_SET_ONE_REG:
  781. case KVM_GET_ONE_REG: {
  782. struct kvm_one_reg reg;
  783. if (copy_from_user(&reg, argp, sizeof(reg)))
  784. return -EFAULT;
  785. if (ioctl == KVM_SET_ONE_REG)
  786. return kvm_mips_set_reg(vcpu, &reg);
  787. else
  788. return kvm_mips_get_reg(vcpu, &reg);
  789. }
  790. case KVM_GET_REG_LIST: {
  791. struct kvm_reg_list __user *user_list = argp;
  792. u64 __user *reg_dest;
  793. struct kvm_reg_list reg_list;
  794. unsigned n;
  795. if (copy_from_user(&reg_list, user_list, sizeof(reg_list)))
  796. return -EFAULT;
  797. n = reg_list.n;
  798. reg_list.n = ARRAY_SIZE(kvm_mips_get_one_regs);
  799. if (copy_to_user(user_list, &reg_list, sizeof(reg_list)))
  800. return -EFAULT;
  801. if (n < reg_list.n)
  802. return -E2BIG;
  803. reg_dest = user_list->reg;
  804. if (copy_to_user(reg_dest, kvm_mips_get_one_regs,
  805. sizeof(kvm_mips_get_one_regs)))
  806. return -EFAULT;
  807. return 0;
  808. }
  809. case KVM_NMI:
  810. /* Treat the NMI as a CPU reset */
  811. r = kvm_mips_reset_vcpu(vcpu);
  812. break;
  813. case KVM_INTERRUPT:
  814. {
  815. struct kvm_mips_interrupt irq;
  816. r = -EFAULT;
  817. if (copy_from_user(&irq, argp, sizeof(irq)))
  818. goto out;
  819. kvm_debug("[%d] %s: irq: %d\n", vcpu->vcpu_id, __func__,
  820. irq.irq);
  821. r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
  822. break;
  823. }
  824. case KVM_ENABLE_CAP: {
  825. struct kvm_enable_cap cap;
  826. r = -EFAULT;
  827. if (copy_from_user(&cap, argp, sizeof(cap)))
  828. goto out;
  829. r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap);
  830. break;
  831. }
  832. default:
  833. r = -ENOIOCTLCMD;
  834. }
  835. out:
  836. return r;
  837. }
  838. /* Get (and clear) the dirty memory log for a memory slot. */
  839. int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
  840. {
  841. struct kvm_memslots *slots;
  842. struct kvm_memory_slot *memslot;
  843. unsigned long ga, ga_end;
  844. int is_dirty = 0;
  845. int r;
  846. unsigned long n;
  847. mutex_lock(&kvm->slots_lock);
  848. r = kvm_get_dirty_log(kvm, log, &is_dirty);
  849. if (r)
  850. goto out;
  851. /* If nothing is dirty, don't bother messing with page tables. */
  852. if (is_dirty) {
  853. slots = kvm_memslots(kvm);
  854. memslot = id_to_memslot(slots, log->slot);
  855. ga = memslot->base_gfn << PAGE_SHIFT;
  856. ga_end = ga + (memslot->npages << PAGE_SHIFT);
  857. kvm_info("%s: dirty, ga: %#lx, ga_end %#lx\n", __func__, ga,
  858. ga_end);
  859. n = kvm_dirty_bitmap_bytes(memslot);
  860. memset(memslot->dirty_bitmap, 0, n);
  861. }
  862. r = 0;
  863. out:
  864. mutex_unlock(&kvm->slots_lock);
  865. return r;
  866. }
  867. long kvm_arch_vm_ioctl(struct file *filp, unsigned int ioctl, unsigned long arg)
  868. {
  869. long r;
  870. switch (ioctl) {
  871. default:
  872. r = -ENOIOCTLCMD;
  873. }
  874. return r;
  875. }
  876. int kvm_arch_init(void *opaque)
  877. {
  878. if (kvm_mips_callbacks) {
  879. kvm_err("kvm: module already exists\n");
  880. return -EEXIST;
  881. }
  882. return kvm_mips_emulation_init(&kvm_mips_callbacks);
  883. }
  884. void kvm_arch_exit(void)
  885. {
  886. kvm_mips_callbacks = NULL;
  887. }
  888. int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
  889. struct kvm_sregs *sregs)
  890. {
  891. return -ENOIOCTLCMD;
  892. }
  893. int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
  894. struct kvm_sregs *sregs)
  895. {
  896. return -ENOIOCTLCMD;
  897. }
  898. void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
  899. {
  900. }
  901. int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
  902. {
  903. return -ENOIOCTLCMD;
  904. }
  905. int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
  906. {
  907. return -ENOIOCTLCMD;
  908. }
  909. int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
  910. {
  911. return VM_FAULT_SIGBUS;
  912. }
  913. int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
  914. {
  915. int r;
  916. switch (ext) {
  917. case KVM_CAP_ONE_REG:
  918. case KVM_CAP_ENABLE_CAP:
  919. r = 1;
  920. break;
  921. case KVM_CAP_COALESCED_MMIO:
  922. r = KVM_COALESCED_MMIO_PAGE_OFFSET;
  923. break;
  924. case KVM_CAP_MIPS_FPU:
  925. r = !!cpu_has_fpu;
  926. break;
  927. case KVM_CAP_MIPS_MSA:
  928. /*
  929. * We don't support MSA vector partitioning yet:
  930. * 1) It would require explicit support which can't be tested
  931. * yet due to lack of support in current hardware.
  932. * 2) It extends the state that would need to be saved/restored
  933. * by e.g. QEMU for migration.
  934. *
  935. * When vector partitioning hardware becomes available, support
  936. * could be added by requiring a flag when enabling
  937. * KVM_CAP_MIPS_MSA capability to indicate that userland knows
  938. * to save/restore the appropriate extra state.
  939. */
  940. r = cpu_has_msa && !(boot_cpu_data.msa_id & MSA_IR_WRPF);
  941. break;
  942. default:
  943. r = 0;
  944. break;
  945. }
  946. return r;
  947. }
  948. int kvm_cpu_has_pending_timer(struct kvm_vcpu *vcpu)
  949. {
  950. return kvm_mips_pending_timer(vcpu);
  951. }
  952. int kvm_arch_vcpu_dump_regs(struct kvm_vcpu *vcpu)
  953. {
  954. int i;
  955. struct mips_coproc *cop0;
  956. if (!vcpu)
  957. return -1;
  958. kvm_debug("VCPU Register Dump:\n");
  959. kvm_debug("\tpc = 0x%08lx\n", vcpu->arch.pc);
  960. kvm_debug("\texceptions: %08lx\n", vcpu->arch.pending_exceptions);
  961. for (i = 0; i < 32; i += 4) {
  962. kvm_debug("\tgpr%02d: %08lx %08lx %08lx %08lx\n", i,
  963. vcpu->arch.gprs[i],
  964. vcpu->arch.gprs[i + 1],
  965. vcpu->arch.gprs[i + 2], vcpu->arch.gprs[i + 3]);
  966. }
  967. kvm_debug("\thi: 0x%08lx\n", vcpu->arch.hi);
  968. kvm_debug("\tlo: 0x%08lx\n", vcpu->arch.lo);
  969. cop0 = vcpu->arch.cop0;
  970. kvm_debug("\tStatus: 0x%08lx, Cause: 0x%08lx\n",
  971. kvm_read_c0_guest_status(cop0),
  972. kvm_read_c0_guest_cause(cop0));
  973. kvm_debug("\tEPC: 0x%08lx\n", kvm_read_c0_guest_epc(cop0));
  974. return 0;
  975. }
  976. int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
  977. {
  978. int i;
  979. for (i = 1; i < ARRAY_SIZE(vcpu->arch.gprs); i++)
  980. vcpu->arch.gprs[i] = regs->gpr[i];
  981. vcpu->arch.gprs[0] = 0; /* zero is special, and cannot be set. */
  982. vcpu->arch.hi = regs->hi;
  983. vcpu->arch.lo = regs->lo;
  984. vcpu->arch.pc = regs->pc;
  985. return 0;
  986. }
  987. int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
  988. {
  989. int i;
  990. for (i = 0; i < ARRAY_SIZE(vcpu->arch.gprs); i++)
  991. regs->gpr[i] = vcpu->arch.gprs[i];
  992. regs->hi = vcpu->arch.hi;
  993. regs->lo = vcpu->arch.lo;
  994. regs->pc = vcpu->arch.pc;
  995. return 0;
  996. }
  997. static void kvm_mips_comparecount_func(unsigned long data)
  998. {
  999. struct kvm_vcpu *vcpu = (struct kvm_vcpu *)data;
  1000. kvm_mips_callbacks->queue_timer_int(vcpu);
  1001. vcpu->arch.wait = 0;
  1002. if (waitqueue_active(&vcpu->wq))
  1003. wake_up_interruptible(&vcpu->wq);
  1004. }
  1005. /* low level hrtimer wake routine */
  1006. static enum hrtimer_restart kvm_mips_comparecount_wakeup(struct hrtimer *timer)
  1007. {
  1008. struct kvm_vcpu *vcpu;
  1009. vcpu = container_of(timer, struct kvm_vcpu, arch.comparecount_timer);
  1010. kvm_mips_comparecount_func((unsigned long) vcpu);
  1011. return kvm_mips_count_timeout(vcpu);
  1012. }
  1013. int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
  1014. {
  1015. kvm_mips_callbacks->vcpu_init(vcpu);
  1016. hrtimer_init(&vcpu->arch.comparecount_timer, CLOCK_MONOTONIC,
  1017. HRTIMER_MODE_REL);
  1018. vcpu->arch.comparecount_timer.function = kvm_mips_comparecount_wakeup;
  1019. return 0;
  1020. }
  1021. int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
  1022. struct kvm_translation *tr)
  1023. {
  1024. return 0;
  1025. }
  1026. /* Initial guest state */
  1027. int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
  1028. {
  1029. return kvm_mips_callbacks->vcpu_setup(vcpu);
  1030. }
  1031. static void kvm_mips_set_c0_status(void)
  1032. {
  1033. uint32_t status = read_c0_status();
  1034. if (cpu_has_dsp)
  1035. status |= (ST0_MX);
  1036. write_c0_status(status);
  1037. ehb();
  1038. }
  1039. /*
  1040. * Return value is in the form (errcode<<2 | RESUME_FLAG_HOST | RESUME_FLAG_NV)
  1041. */
  1042. int kvm_mips_handle_exit(struct kvm_run *run, struct kvm_vcpu *vcpu)
  1043. {
  1044. uint32_t cause = vcpu->arch.host_cp0_cause;
  1045. uint32_t exccode = (cause >> CAUSEB_EXCCODE) & 0x1f;
  1046. uint32_t __user *opc = (uint32_t __user *) vcpu->arch.pc;
  1047. unsigned long badvaddr = vcpu->arch.host_cp0_badvaddr;
  1048. enum emulation_result er = EMULATE_DONE;
  1049. int ret = RESUME_GUEST;
  1050. /* re-enable HTW before enabling interrupts */
  1051. htw_start();
  1052. /* Set a default exit reason */
  1053. run->exit_reason = KVM_EXIT_UNKNOWN;
  1054. run->ready_for_interrupt_injection = 1;
  1055. /*
  1056. * Set the appropriate status bits based on host CPU features,
  1057. * before we hit the scheduler
  1058. */
  1059. kvm_mips_set_c0_status();
  1060. local_irq_enable();
  1061. kvm_debug("kvm_mips_handle_exit: cause: %#x, PC: %p, kvm_run: %p, kvm_vcpu: %p\n",
  1062. cause, opc, run, vcpu);
  1063. /*
  1064. * Do a privilege check, if in UM most of these exit conditions end up
  1065. * causing an exception to be delivered to the Guest Kernel
  1066. */
  1067. er = kvm_mips_check_privilege(cause, opc, run, vcpu);
  1068. if (er == EMULATE_PRIV_FAIL) {
  1069. goto skip_emul;
  1070. } else if (er == EMULATE_FAIL) {
  1071. run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
  1072. ret = RESUME_HOST;
  1073. goto skip_emul;
  1074. }
  1075. switch (exccode) {
  1076. case T_INT:
  1077. kvm_debug("[%d]T_INT @ %p\n", vcpu->vcpu_id, opc);
  1078. ++vcpu->stat.int_exits;
  1079. trace_kvm_exit(vcpu, INT_EXITS);
  1080. if (need_resched())
  1081. cond_resched();
  1082. ret = RESUME_GUEST;
  1083. break;
  1084. case T_COP_UNUSABLE:
  1085. kvm_debug("T_COP_UNUSABLE: @ PC: %p\n", opc);
  1086. ++vcpu->stat.cop_unusable_exits;
  1087. trace_kvm_exit(vcpu, COP_UNUSABLE_EXITS);
  1088. ret = kvm_mips_callbacks->handle_cop_unusable(vcpu);
  1089. /* XXXKYMA: Might need to return to user space */
  1090. if (run->exit_reason == KVM_EXIT_IRQ_WINDOW_OPEN)
  1091. ret = RESUME_HOST;
  1092. break;
  1093. case T_TLB_MOD:
  1094. ++vcpu->stat.tlbmod_exits;
  1095. trace_kvm_exit(vcpu, TLBMOD_EXITS);
  1096. ret = kvm_mips_callbacks->handle_tlb_mod(vcpu);
  1097. break;
  1098. case T_TLB_ST_MISS:
  1099. kvm_debug("TLB ST fault: cause %#x, status %#lx, PC: %p, BadVaddr: %#lx\n",
  1100. cause, kvm_read_c0_guest_status(vcpu->arch.cop0), opc,
  1101. badvaddr);
  1102. ++vcpu->stat.tlbmiss_st_exits;
  1103. trace_kvm_exit(vcpu, TLBMISS_ST_EXITS);
  1104. ret = kvm_mips_callbacks->handle_tlb_st_miss(vcpu);
  1105. break;
  1106. case T_TLB_LD_MISS:
  1107. kvm_debug("TLB LD fault: cause %#x, PC: %p, BadVaddr: %#lx\n",
  1108. cause, opc, badvaddr);
  1109. ++vcpu->stat.tlbmiss_ld_exits;
  1110. trace_kvm_exit(vcpu, TLBMISS_LD_EXITS);
  1111. ret = kvm_mips_callbacks->handle_tlb_ld_miss(vcpu);
  1112. break;
  1113. case T_ADDR_ERR_ST:
  1114. ++vcpu->stat.addrerr_st_exits;
  1115. trace_kvm_exit(vcpu, ADDRERR_ST_EXITS);
  1116. ret = kvm_mips_callbacks->handle_addr_err_st(vcpu);
  1117. break;
  1118. case T_ADDR_ERR_LD:
  1119. ++vcpu->stat.addrerr_ld_exits;
  1120. trace_kvm_exit(vcpu, ADDRERR_LD_EXITS);
  1121. ret = kvm_mips_callbacks->handle_addr_err_ld(vcpu);
  1122. break;
  1123. case T_SYSCALL:
  1124. ++vcpu->stat.syscall_exits;
  1125. trace_kvm_exit(vcpu, SYSCALL_EXITS);
  1126. ret = kvm_mips_callbacks->handle_syscall(vcpu);
  1127. break;
  1128. case T_RES_INST:
  1129. ++vcpu->stat.resvd_inst_exits;
  1130. trace_kvm_exit(vcpu, RESVD_INST_EXITS);
  1131. ret = kvm_mips_callbacks->handle_res_inst(vcpu);
  1132. break;
  1133. case T_BREAK:
  1134. ++vcpu->stat.break_inst_exits;
  1135. trace_kvm_exit(vcpu, BREAK_INST_EXITS);
  1136. ret = kvm_mips_callbacks->handle_break(vcpu);
  1137. break;
  1138. case T_TRAP:
  1139. ++vcpu->stat.trap_inst_exits;
  1140. trace_kvm_exit(vcpu, TRAP_INST_EXITS);
  1141. ret = kvm_mips_callbacks->handle_trap(vcpu);
  1142. break;
  1143. case T_MSAFPE:
  1144. ++vcpu->stat.msa_fpe_exits;
  1145. trace_kvm_exit(vcpu, MSA_FPE_EXITS);
  1146. ret = kvm_mips_callbacks->handle_msa_fpe(vcpu);
  1147. break;
  1148. case T_FPE:
  1149. ++vcpu->stat.fpe_exits;
  1150. trace_kvm_exit(vcpu, FPE_EXITS);
  1151. ret = kvm_mips_callbacks->handle_fpe(vcpu);
  1152. break;
  1153. case T_MSADIS:
  1154. ++vcpu->stat.msa_disabled_exits;
  1155. trace_kvm_exit(vcpu, MSA_DISABLED_EXITS);
  1156. ret = kvm_mips_callbacks->handle_msa_disabled(vcpu);
  1157. break;
  1158. default:
  1159. kvm_err("Exception Code: %d, not yet handled, @ PC: %p, inst: 0x%08x BadVaddr: %#lx Status: %#lx\n",
  1160. exccode, opc, kvm_get_inst(opc, vcpu), badvaddr,
  1161. kvm_read_c0_guest_status(vcpu->arch.cop0));
  1162. kvm_arch_vcpu_dump_regs(vcpu);
  1163. run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
  1164. ret = RESUME_HOST;
  1165. break;
  1166. }
  1167. skip_emul:
  1168. local_irq_disable();
  1169. if (er == EMULATE_DONE && !(ret & RESUME_HOST))
  1170. kvm_mips_deliver_interrupts(vcpu, cause);
  1171. if (!(ret & RESUME_HOST)) {
  1172. /* Only check for signals if not already exiting to userspace */
  1173. if (signal_pending(current)) {
  1174. run->exit_reason = KVM_EXIT_INTR;
  1175. ret = (-EINTR << 2) | RESUME_HOST;
  1176. ++vcpu->stat.signal_exits;
  1177. trace_kvm_exit(vcpu, SIGNAL_EXITS);
  1178. }
  1179. }
  1180. if (ret == RESUME_GUEST) {
  1181. /*
  1182. * If FPU / MSA are enabled (i.e. the guest's FPU / MSA context
  1183. * is live), restore FCR31 / MSACSR.
  1184. *
  1185. * This should be before returning to the guest exception
  1186. * vector, as it may well cause an [MSA] FP exception if there
  1187. * are pending exception bits unmasked. (see
  1188. * kvm_mips_csr_die_notifier() for how that is handled).
  1189. */
  1190. if (kvm_mips_guest_has_fpu(&vcpu->arch) &&
  1191. read_c0_status() & ST0_CU1)
  1192. __kvm_restore_fcsr(&vcpu->arch);
  1193. if (kvm_mips_guest_has_msa(&vcpu->arch) &&
  1194. read_c0_config5() & MIPS_CONF5_MSAEN)
  1195. __kvm_restore_msacsr(&vcpu->arch);
  1196. }
  1197. /* Disable HTW before returning to guest or host */
  1198. htw_stop();
  1199. return ret;
  1200. }
  1201. /* Enable FPU for guest and restore context */
  1202. void kvm_own_fpu(struct kvm_vcpu *vcpu)
  1203. {
  1204. struct mips_coproc *cop0 = vcpu->arch.cop0;
  1205. unsigned int sr, cfg5;
  1206. preempt_disable();
  1207. sr = kvm_read_c0_guest_status(cop0);
  1208. /*
  1209. * If MSA state is already live, it is undefined how it interacts with
  1210. * FR=0 FPU state, and we don't want to hit reserved instruction
  1211. * exceptions trying to save the MSA state later when CU=1 && FR=1, so
  1212. * play it safe and save it first.
  1213. *
  1214. * In theory we shouldn't ever hit this case since kvm_lose_fpu() should
  1215. * get called when guest CU1 is set, however we can't trust the guest
  1216. * not to clobber the status register directly via the commpage.
  1217. */
  1218. if (cpu_has_msa && sr & ST0_CU1 && !(sr & ST0_FR) &&
  1219. vcpu->arch.fpu_inuse & KVM_MIPS_FPU_MSA)
  1220. kvm_lose_fpu(vcpu);
  1221. /*
  1222. * Enable FPU for guest
  1223. * We set FR and FRE according to guest context
  1224. */
  1225. change_c0_status(ST0_CU1 | ST0_FR, sr);
  1226. if (cpu_has_fre) {
  1227. cfg5 = kvm_read_c0_guest_config5(cop0);
  1228. change_c0_config5(MIPS_CONF5_FRE, cfg5);
  1229. }
  1230. enable_fpu_hazard();
  1231. /* If guest FPU state not active, restore it now */
  1232. if (!(vcpu->arch.fpu_inuse & KVM_MIPS_FPU_FPU)) {
  1233. __kvm_restore_fpu(&vcpu->arch);
  1234. vcpu->arch.fpu_inuse |= KVM_MIPS_FPU_FPU;
  1235. }
  1236. preempt_enable();
  1237. }
  1238. #ifdef CONFIG_CPU_HAS_MSA
  1239. /* Enable MSA for guest and restore context */
  1240. void kvm_own_msa(struct kvm_vcpu *vcpu)
  1241. {
  1242. struct mips_coproc *cop0 = vcpu->arch.cop0;
  1243. unsigned int sr, cfg5;
  1244. preempt_disable();
  1245. /*
  1246. * Enable FPU if enabled in guest, since we're restoring FPU context
  1247. * anyway. We set FR and FRE according to guest context.
  1248. */
  1249. if (kvm_mips_guest_has_fpu(&vcpu->arch)) {
  1250. sr = kvm_read_c0_guest_status(cop0);
  1251. /*
  1252. * If FR=0 FPU state is already live, it is undefined how it
  1253. * interacts with MSA state, so play it safe and save it first.
  1254. */
  1255. if (!(sr & ST0_FR) &&
  1256. (vcpu->arch.fpu_inuse & (KVM_MIPS_FPU_FPU |
  1257. KVM_MIPS_FPU_MSA)) == KVM_MIPS_FPU_FPU)
  1258. kvm_lose_fpu(vcpu);
  1259. change_c0_status(ST0_CU1 | ST0_FR, sr);
  1260. if (sr & ST0_CU1 && cpu_has_fre) {
  1261. cfg5 = kvm_read_c0_guest_config5(cop0);
  1262. change_c0_config5(MIPS_CONF5_FRE, cfg5);
  1263. }
  1264. }
  1265. /* Enable MSA for guest */
  1266. set_c0_config5(MIPS_CONF5_MSAEN);
  1267. enable_fpu_hazard();
  1268. switch (vcpu->arch.fpu_inuse & (KVM_MIPS_FPU_FPU | KVM_MIPS_FPU_MSA)) {
  1269. case KVM_MIPS_FPU_FPU:
  1270. /*
  1271. * Guest FPU state already loaded, only restore upper MSA state
  1272. */
  1273. __kvm_restore_msa_upper(&vcpu->arch);
  1274. vcpu->arch.fpu_inuse |= KVM_MIPS_FPU_MSA;
  1275. break;
  1276. case 0:
  1277. /* Neither FPU or MSA already active, restore full MSA state */
  1278. __kvm_restore_msa(&vcpu->arch);
  1279. vcpu->arch.fpu_inuse |= KVM_MIPS_FPU_MSA;
  1280. if (kvm_mips_guest_has_fpu(&vcpu->arch))
  1281. vcpu->arch.fpu_inuse |= KVM_MIPS_FPU_FPU;
  1282. break;
  1283. default:
  1284. break;
  1285. }
  1286. preempt_enable();
  1287. }
  1288. #endif
  1289. /* Drop FPU & MSA without saving it */
  1290. void kvm_drop_fpu(struct kvm_vcpu *vcpu)
  1291. {
  1292. preempt_disable();
  1293. if (cpu_has_msa && vcpu->arch.fpu_inuse & KVM_MIPS_FPU_MSA) {
  1294. disable_msa();
  1295. vcpu->arch.fpu_inuse &= ~KVM_MIPS_FPU_MSA;
  1296. }
  1297. if (vcpu->arch.fpu_inuse & KVM_MIPS_FPU_FPU) {
  1298. clear_c0_status(ST0_CU1 | ST0_FR);
  1299. vcpu->arch.fpu_inuse &= ~KVM_MIPS_FPU_FPU;
  1300. }
  1301. preempt_enable();
  1302. }
  1303. /* Save and disable FPU & MSA */
  1304. void kvm_lose_fpu(struct kvm_vcpu *vcpu)
  1305. {
  1306. /*
  1307. * FPU & MSA get disabled in root context (hardware) when it is disabled
  1308. * in guest context (software), but the register state in the hardware
  1309. * may still be in use. This is why we explicitly re-enable the hardware
  1310. * before saving.
  1311. */
  1312. preempt_disable();
  1313. if (cpu_has_msa && vcpu->arch.fpu_inuse & KVM_MIPS_FPU_MSA) {
  1314. set_c0_config5(MIPS_CONF5_MSAEN);
  1315. enable_fpu_hazard();
  1316. __kvm_save_msa(&vcpu->arch);
  1317. /* Disable MSA & FPU */
  1318. disable_msa();
  1319. if (vcpu->arch.fpu_inuse & KVM_MIPS_FPU_FPU)
  1320. clear_c0_status(ST0_CU1 | ST0_FR);
  1321. vcpu->arch.fpu_inuse &= ~(KVM_MIPS_FPU_FPU | KVM_MIPS_FPU_MSA);
  1322. } else if (vcpu->arch.fpu_inuse & KVM_MIPS_FPU_FPU) {
  1323. set_c0_status(ST0_CU1);
  1324. enable_fpu_hazard();
  1325. __kvm_save_fpu(&vcpu->arch);
  1326. vcpu->arch.fpu_inuse &= ~KVM_MIPS_FPU_FPU;
  1327. /* Disable FPU */
  1328. clear_c0_status(ST0_CU1 | ST0_FR);
  1329. }
  1330. preempt_enable();
  1331. }
  1332. /*
  1333. * Step over a specific ctc1 to FCSR and a specific ctcmsa to MSACSR which are
  1334. * used to restore guest FCSR/MSACSR state and may trigger a "harmless" FP/MSAFP
  1335. * exception if cause bits are set in the value being written.
  1336. */
  1337. static int kvm_mips_csr_die_notify(struct notifier_block *self,
  1338. unsigned long cmd, void *ptr)
  1339. {
  1340. struct die_args *args = (struct die_args *)ptr;
  1341. struct pt_regs *regs = args->regs;
  1342. unsigned long pc;
  1343. /* Only interested in FPE and MSAFPE */
  1344. if (cmd != DIE_FP && cmd != DIE_MSAFP)
  1345. return NOTIFY_DONE;
  1346. /* Return immediately if guest context isn't active */
  1347. if (!(current->flags & PF_VCPU))
  1348. return NOTIFY_DONE;
  1349. /* Should never get here from user mode */
  1350. BUG_ON(user_mode(regs));
  1351. pc = instruction_pointer(regs);
  1352. switch (cmd) {
  1353. case DIE_FP:
  1354. /* match 2nd instruction in __kvm_restore_fcsr */
  1355. if (pc != (unsigned long)&__kvm_restore_fcsr + 4)
  1356. return NOTIFY_DONE;
  1357. break;
  1358. case DIE_MSAFP:
  1359. /* match 2nd/3rd instruction in __kvm_restore_msacsr */
  1360. if (!cpu_has_msa ||
  1361. pc < (unsigned long)&__kvm_restore_msacsr + 4 ||
  1362. pc > (unsigned long)&__kvm_restore_msacsr + 8)
  1363. return NOTIFY_DONE;
  1364. break;
  1365. }
  1366. /* Move PC forward a little and continue executing */
  1367. instruction_pointer(regs) += 4;
  1368. return NOTIFY_STOP;
  1369. }
  1370. static struct notifier_block kvm_mips_csr_die_notifier = {
  1371. .notifier_call = kvm_mips_csr_die_notify,
  1372. };
  1373. int __init kvm_mips_init(void)
  1374. {
  1375. int ret;
  1376. ret = kvm_init(NULL, sizeof(struct kvm_vcpu), 0, THIS_MODULE);
  1377. if (ret)
  1378. return ret;
  1379. register_die_notifier(&kvm_mips_csr_die_notifier);
  1380. /*
  1381. * On MIPS, kernel modules are executed from "mapped space", which
  1382. * requires TLBs. The TLB handling code is statically linked with
  1383. * the rest of the kernel (tlb.c) to avoid the possibility of
  1384. * double faulting. The issue is that the TLB code references
  1385. * routines that are part of the the KVM module, which are only
  1386. * available once the module is loaded.
  1387. */
  1388. kvm_mips_gfn_to_pfn = gfn_to_pfn;
  1389. kvm_mips_release_pfn_clean = kvm_release_pfn_clean;
  1390. kvm_mips_is_error_pfn = is_error_pfn;
  1391. return 0;
  1392. }
  1393. void __exit kvm_mips_exit(void)
  1394. {
  1395. kvm_exit();
  1396. kvm_mips_gfn_to_pfn = NULL;
  1397. kvm_mips_release_pfn_clean = NULL;
  1398. kvm_mips_is_error_pfn = NULL;
  1399. unregister_die_notifier(&kvm_mips_csr_die_notifier);
  1400. }
  1401. module_init(kvm_mips_init);
  1402. module_exit(kvm_mips_exit);
  1403. EXPORT_TRACEPOINT_SYMBOL(kvm_exit);