irq.c 4.7 KB

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  1. /*
  2. * linux/arch/arm/kernel/irq.c
  3. *
  4. * Copyright (C) 1992 Linus Torvalds
  5. * Modifications for ARM processor Copyright (C) 1995-2000 Russell King.
  6. *
  7. * Support for Dynamic Tick Timer Copyright (C) 2004-2005 Nokia Corporation.
  8. * Dynamic Tick Timer written by Tony Lindgren <tony@atomide.com> and
  9. * Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>.
  10. *
  11. * This program is free software; you can redistribute it and/or modify
  12. * it under the terms of the GNU General Public License version 2 as
  13. * published by the Free Software Foundation.
  14. *
  15. * This file contains the code used by various IRQ handling routines:
  16. * asking for different IRQ's should be done through these routines
  17. * instead of just grabbing them. Thus setups with different IRQ numbers
  18. * shouldn't result in any weird surprises, and installing new handlers
  19. * should be easier.
  20. *
  21. * IRQ's are in fact implemented a bit like signal handlers for the kernel.
  22. * Naturally it's not a 1:1 relation, but there are similarities.
  23. */
  24. #include <linux/kernel_stat.h>
  25. #include <linux/signal.h>
  26. #include <linux/ioport.h>
  27. #include <linux/interrupt.h>
  28. #include <linux/irq.h>
  29. #include <linux/irqchip.h>
  30. #include <linux/random.h>
  31. #include <linux/smp.h>
  32. #include <linux/init.h>
  33. #include <linux/seq_file.h>
  34. #include <linux/ratelimit.h>
  35. #include <linux/errno.h>
  36. #include <linux/list.h>
  37. #include <linux/kallsyms.h>
  38. #include <linux/proc_fs.h>
  39. #include <linux/export.h>
  40. #include <asm/hardware/cache-l2x0.h>
  41. #include <asm/outercache.h>
  42. #include <asm/exception.h>
  43. #include <asm/mach/arch.h>
  44. #include <asm/mach/irq.h>
  45. #include <asm/mach/time.h>
  46. unsigned long irq_err_count;
  47. int arch_show_interrupts(struct seq_file *p, int prec)
  48. {
  49. #ifdef CONFIG_FIQ
  50. show_fiq_list(p, prec);
  51. #endif
  52. #ifdef CONFIG_SMP
  53. show_ipi_list(p, prec);
  54. #endif
  55. seq_printf(p, "%*s: %10lu\n", prec, "Err", irq_err_count);
  56. return 0;
  57. }
  58. /*
  59. * handle_IRQ handles all hardware IRQ's. Decoded IRQs should
  60. * not come via this function. Instead, they should provide their
  61. * own 'handler'. Used by platform code implementing C-based 1st
  62. * level decoding.
  63. */
  64. void handle_IRQ(unsigned int irq, struct pt_regs *regs)
  65. {
  66. __handle_domain_irq(NULL, irq, false, regs);
  67. }
  68. /*
  69. * asm_do_IRQ is the interface to be used from assembly code.
  70. */
  71. asmlinkage void __exception_irq_entry
  72. asm_do_IRQ(unsigned int irq, struct pt_regs *regs)
  73. {
  74. handle_IRQ(irq, regs);
  75. }
  76. void __init init_IRQ(void)
  77. {
  78. int ret;
  79. if (IS_ENABLED(CONFIG_OF) && !machine_desc->init_irq)
  80. irqchip_init();
  81. else
  82. machine_desc->init_irq();
  83. if (IS_ENABLED(CONFIG_OF) && IS_ENABLED(CONFIG_CACHE_L2X0) &&
  84. (machine_desc->l2c_aux_mask || machine_desc->l2c_aux_val)) {
  85. if (!outer_cache.write_sec)
  86. outer_cache.write_sec = machine_desc->l2c_write_sec;
  87. ret = l2x0_of_init(machine_desc->l2c_aux_val,
  88. machine_desc->l2c_aux_mask);
  89. if (ret)
  90. pr_err("L2C: failed to init: %d\n", ret);
  91. }
  92. }
  93. #ifdef CONFIG_MULTI_IRQ_HANDLER
  94. void __init set_handle_irq(void (*handle_irq)(struct pt_regs *))
  95. {
  96. if (handle_arch_irq)
  97. return;
  98. handle_arch_irq = handle_irq;
  99. }
  100. #endif
  101. #ifdef CONFIG_SPARSE_IRQ
  102. int __init arch_probe_nr_irqs(void)
  103. {
  104. nr_irqs = machine_desc->nr_irqs ? machine_desc->nr_irqs : NR_IRQS;
  105. return nr_irqs;
  106. }
  107. #endif
  108. #ifdef CONFIG_HOTPLUG_CPU
  109. static bool migrate_one_irq(struct irq_desc *desc)
  110. {
  111. struct irq_data *d = irq_desc_get_irq_data(desc);
  112. const struct cpumask *affinity = irq_data_get_affinity_mask(d);
  113. struct irq_chip *c;
  114. bool ret = false;
  115. /*
  116. * If this is a per-CPU interrupt, or the affinity does not
  117. * include this CPU, then we have nothing to do.
  118. */
  119. if (irqd_is_per_cpu(d) || !cpumask_test_cpu(smp_processor_id(), affinity))
  120. return false;
  121. if (cpumask_any_and(affinity, cpu_online_mask) >= nr_cpu_ids) {
  122. affinity = cpu_online_mask;
  123. ret = true;
  124. }
  125. c = irq_data_get_irq_chip(d);
  126. if (!c->irq_set_affinity)
  127. pr_debug("IRQ%u: unable to set affinity\n", d->irq);
  128. else if (c->irq_set_affinity(d, affinity, false) == IRQ_SET_MASK_OK && ret)
  129. cpumask_copy(irq_data_get_affinity_mask(d), affinity);
  130. return ret;
  131. }
  132. /*
  133. * The current CPU has been marked offline. Migrate IRQs off this CPU.
  134. * If the affinity settings do not allow other CPUs, force them onto any
  135. * available CPU.
  136. *
  137. * Note: we must iterate over all IRQs, whether they have an attached
  138. * action structure or not, as we need to get chained interrupts too.
  139. */
  140. void migrate_irqs(void)
  141. {
  142. unsigned int i;
  143. struct irq_desc *desc;
  144. unsigned long flags;
  145. local_irq_save(flags);
  146. for_each_irq_desc(i, desc) {
  147. bool affinity_broken;
  148. raw_spin_lock(&desc->lock);
  149. affinity_broken = migrate_one_irq(desc);
  150. raw_spin_unlock(&desc->lock);
  151. if (affinity_broken)
  152. pr_warn_ratelimited("IRQ%u no longer affine to CPU%u\n",
  153. i, smp_processor_id());
  154. }
  155. local_irq_restore(flags);
  156. }
  157. #endif /* CONFIG_HOTPLUG_CPU */