main.c 93 KB

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  1. /*
  2. * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved.
  3. * Copyright (c) 2007, 2008 Mellanox Technologies. All rights reserved.
  4. *
  5. * This software is available to you under a choice of one of two
  6. * licenses. You may choose to be licensed under the terms of the GNU
  7. * General Public License (GPL) Version 2, available from the file
  8. * COPYING in the main directory of this source tree, or the
  9. * OpenIB.org BSD license below:
  10. *
  11. * Redistribution and use in source and binary forms, with or
  12. * without modification, are permitted provided that the following
  13. * conditions are met:
  14. *
  15. * - Redistributions of source code must retain the above
  16. * copyright notice, this list of conditions and the following
  17. * disclaimer.
  18. *
  19. * - Redistributions in binary form must reproduce the above
  20. * copyright notice, this list of conditions and the following
  21. * disclaimer in the documentation and/or other materials
  22. * provided with the distribution.
  23. *
  24. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  25. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  26. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  27. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  28. * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  29. * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  30. * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  31. * SOFTWARE.
  32. */
  33. #include <linux/module.h>
  34. #include <linux/init.h>
  35. #include <linux/slab.h>
  36. #include <linux/errno.h>
  37. #include <linux/netdevice.h>
  38. #include <linux/inetdevice.h>
  39. #include <linux/rtnetlink.h>
  40. #include <linux/if_vlan.h>
  41. #include <linux/sched/mm.h>
  42. #include <linux/sched/task.h>
  43. #include <net/ipv6.h>
  44. #include <net/addrconf.h>
  45. #include <net/devlink.h>
  46. #include <rdma/ib_smi.h>
  47. #include <rdma/ib_user_verbs.h>
  48. #include <rdma/ib_addr.h>
  49. #include <rdma/ib_cache.h>
  50. #include <net/bonding.h>
  51. #include <linux/mlx4/driver.h>
  52. #include <linux/mlx4/cmd.h>
  53. #include <linux/mlx4/qp.h>
  54. #include "mlx4_ib.h"
  55. #include <rdma/mlx4-abi.h>
  56. #define DRV_NAME MLX4_IB_DRV_NAME
  57. #define DRV_VERSION "4.0-0"
  58. #define MLX4_IB_FLOW_MAX_PRIO 0xFFF
  59. #define MLX4_IB_FLOW_QPN_MASK 0xFFFFFF
  60. #define MLX4_IB_CARD_REV_A0 0xA0
  61. MODULE_AUTHOR("Roland Dreier");
  62. MODULE_DESCRIPTION("Mellanox ConnectX HCA InfiniBand driver");
  63. MODULE_LICENSE("Dual BSD/GPL");
  64. int mlx4_ib_sm_guid_assign = 0;
  65. module_param_named(sm_guid_assign, mlx4_ib_sm_guid_assign, int, 0444);
  66. MODULE_PARM_DESC(sm_guid_assign, "Enable SM alias_GUID assignment if sm_guid_assign > 0 (Default: 0)");
  67. static const char mlx4_ib_version[] =
  68. DRV_NAME ": Mellanox ConnectX InfiniBand driver v"
  69. DRV_VERSION "\n";
  70. static void do_slave_init(struct mlx4_ib_dev *ibdev, int slave, int do_init);
  71. static enum rdma_link_layer mlx4_ib_port_link_layer(struct ib_device *device,
  72. u8 port_num);
  73. static struct workqueue_struct *wq;
  74. static void init_query_mad(struct ib_smp *mad)
  75. {
  76. mad->base_version = 1;
  77. mad->mgmt_class = IB_MGMT_CLASS_SUBN_LID_ROUTED;
  78. mad->class_version = 1;
  79. mad->method = IB_MGMT_METHOD_GET;
  80. }
  81. static int check_flow_steering_support(struct mlx4_dev *dev)
  82. {
  83. int eth_num_ports = 0;
  84. int ib_num_ports = 0;
  85. int dmfs = dev->caps.steering_mode == MLX4_STEERING_MODE_DEVICE_MANAGED;
  86. if (dmfs) {
  87. int i;
  88. mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_ETH)
  89. eth_num_ports++;
  90. mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_IB)
  91. ib_num_ports++;
  92. dmfs &= (!ib_num_ports ||
  93. (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_DMFS_IPOIB)) &&
  94. (!eth_num_ports ||
  95. (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_FS_EN));
  96. if (ib_num_ports && mlx4_is_mfunc(dev)) {
  97. pr_warn("Device managed flow steering is unavailable for IB port in multifunction env.\n");
  98. dmfs = 0;
  99. }
  100. }
  101. return dmfs;
  102. }
  103. static int num_ib_ports(struct mlx4_dev *dev)
  104. {
  105. int ib_ports = 0;
  106. int i;
  107. mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_IB)
  108. ib_ports++;
  109. return ib_ports;
  110. }
  111. static struct net_device *mlx4_ib_get_netdev(struct ib_device *device, u8 port_num)
  112. {
  113. struct mlx4_ib_dev *ibdev = to_mdev(device);
  114. struct net_device *dev;
  115. rcu_read_lock();
  116. dev = mlx4_get_protocol_dev(ibdev->dev, MLX4_PROT_ETH, port_num);
  117. if (dev) {
  118. if (mlx4_is_bonded(ibdev->dev)) {
  119. struct net_device *upper = NULL;
  120. upper = netdev_master_upper_dev_get_rcu(dev);
  121. if (upper) {
  122. struct net_device *active;
  123. active = bond_option_active_slave_get_rcu(netdev_priv(upper));
  124. if (active)
  125. dev = active;
  126. }
  127. }
  128. }
  129. if (dev)
  130. dev_hold(dev);
  131. rcu_read_unlock();
  132. return dev;
  133. }
  134. static int mlx4_ib_update_gids_v1(struct gid_entry *gids,
  135. struct mlx4_ib_dev *ibdev,
  136. u8 port_num)
  137. {
  138. struct mlx4_cmd_mailbox *mailbox;
  139. int err;
  140. struct mlx4_dev *dev = ibdev->dev;
  141. int i;
  142. union ib_gid *gid_tbl;
  143. mailbox = mlx4_alloc_cmd_mailbox(dev);
  144. if (IS_ERR(mailbox))
  145. return -ENOMEM;
  146. gid_tbl = mailbox->buf;
  147. for (i = 0; i < MLX4_MAX_PORT_GIDS; ++i)
  148. memcpy(&gid_tbl[i], &gids[i].gid, sizeof(union ib_gid));
  149. err = mlx4_cmd(dev, mailbox->dma,
  150. MLX4_SET_PORT_GID_TABLE << 8 | port_num,
  151. 1, MLX4_CMD_SET_PORT, MLX4_CMD_TIME_CLASS_B,
  152. MLX4_CMD_WRAPPED);
  153. if (mlx4_is_bonded(dev))
  154. err += mlx4_cmd(dev, mailbox->dma,
  155. MLX4_SET_PORT_GID_TABLE << 8 | 2,
  156. 1, MLX4_CMD_SET_PORT, MLX4_CMD_TIME_CLASS_B,
  157. MLX4_CMD_WRAPPED);
  158. mlx4_free_cmd_mailbox(dev, mailbox);
  159. return err;
  160. }
  161. static int mlx4_ib_update_gids_v1_v2(struct gid_entry *gids,
  162. struct mlx4_ib_dev *ibdev,
  163. u8 port_num)
  164. {
  165. struct mlx4_cmd_mailbox *mailbox;
  166. int err;
  167. struct mlx4_dev *dev = ibdev->dev;
  168. int i;
  169. struct {
  170. union ib_gid gid;
  171. __be32 rsrvd1[2];
  172. __be16 rsrvd2;
  173. u8 type;
  174. u8 version;
  175. __be32 rsrvd3;
  176. } *gid_tbl;
  177. mailbox = mlx4_alloc_cmd_mailbox(dev);
  178. if (IS_ERR(mailbox))
  179. return -ENOMEM;
  180. gid_tbl = mailbox->buf;
  181. for (i = 0; i < MLX4_MAX_PORT_GIDS; ++i) {
  182. memcpy(&gid_tbl[i].gid, &gids[i].gid, sizeof(union ib_gid));
  183. if (gids[i].gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP) {
  184. gid_tbl[i].version = 2;
  185. if (!ipv6_addr_v4mapped((struct in6_addr *)&gids[i].gid))
  186. gid_tbl[i].type = 1;
  187. }
  188. }
  189. err = mlx4_cmd(dev, mailbox->dma,
  190. MLX4_SET_PORT_ROCE_ADDR << 8 | port_num,
  191. 1, MLX4_CMD_SET_PORT, MLX4_CMD_TIME_CLASS_B,
  192. MLX4_CMD_WRAPPED);
  193. if (mlx4_is_bonded(dev))
  194. err += mlx4_cmd(dev, mailbox->dma,
  195. MLX4_SET_PORT_ROCE_ADDR << 8 | 2,
  196. 1, MLX4_CMD_SET_PORT, MLX4_CMD_TIME_CLASS_B,
  197. MLX4_CMD_WRAPPED);
  198. mlx4_free_cmd_mailbox(dev, mailbox);
  199. return err;
  200. }
  201. static int mlx4_ib_update_gids(struct gid_entry *gids,
  202. struct mlx4_ib_dev *ibdev,
  203. u8 port_num)
  204. {
  205. if (ibdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ROCE_V1_V2)
  206. return mlx4_ib_update_gids_v1_v2(gids, ibdev, port_num);
  207. return mlx4_ib_update_gids_v1(gids, ibdev, port_num);
  208. }
  209. static int mlx4_ib_add_gid(const struct ib_gid_attr *attr, void **context)
  210. {
  211. struct mlx4_ib_dev *ibdev = to_mdev(attr->device);
  212. struct mlx4_ib_iboe *iboe = &ibdev->iboe;
  213. struct mlx4_port_gid_table *port_gid_table;
  214. int free = -1, found = -1;
  215. int ret = 0;
  216. int hw_update = 0;
  217. int i;
  218. struct gid_entry *gids = NULL;
  219. if (!rdma_cap_roce_gid_table(attr->device, attr->port_num))
  220. return -EINVAL;
  221. if (attr->port_num > MLX4_MAX_PORTS)
  222. return -EINVAL;
  223. if (!context)
  224. return -EINVAL;
  225. port_gid_table = &iboe->gids[attr->port_num - 1];
  226. spin_lock_bh(&iboe->lock);
  227. for (i = 0; i < MLX4_MAX_PORT_GIDS; ++i) {
  228. if (!memcmp(&port_gid_table->gids[i].gid,
  229. &attr->gid, sizeof(attr->gid)) &&
  230. port_gid_table->gids[i].gid_type == attr->gid_type) {
  231. found = i;
  232. break;
  233. }
  234. if (free < 0 && rdma_is_zero_gid(&port_gid_table->gids[i].gid))
  235. free = i; /* HW has space */
  236. }
  237. if (found < 0) {
  238. if (free < 0) {
  239. ret = -ENOSPC;
  240. } else {
  241. port_gid_table->gids[free].ctx = kmalloc(sizeof(*port_gid_table->gids[free].ctx), GFP_ATOMIC);
  242. if (!port_gid_table->gids[free].ctx) {
  243. ret = -ENOMEM;
  244. } else {
  245. *context = port_gid_table->gids[free].ctx;
  246. memcpy(&port_gid_table->gids[free].gid,
  247. &attr->gid, sizeof(attr->gid));
  248. port_gid_table->gids[free].gid_type = attr->gid_type;
  249. port_gid_table->gids[free].ctx->real_index = free;
  250. port_gid_table->gids[free].ctx->refcount = 1;
  251. hw_update = 1;
  252. }
  253. }
  254. } else {
  255. struct gid_cache_context *ctx = port_gid_table->gids[found].ctx;
  256. *context = ctx;
  257. ctx->refcount++;
  258. }
  259. if (!ret && hw_update) {
  260. gids = kmalloc_array(MLX4_MAX_PORT_GIDS, sizeof(*gids),
  261. GFP_ATOMIC);
  262. if (!gids) {
  263. ret = -ENOMEM;
  264. } else {
  265. for (i = 0; i < MLX4_MAX_PORT_GIDS; i++) {
  266. memcpy(&gids[i].gid, &port_gid_table->gids[i].gid, sizeof(union ib_gid));
  267. gids[i].gid_type = port_gid_table->gids[i].gid_type;
  268. }
  269. }
  270. }
  271. spin_unlock_bh(&iboe->lock);
  272. if (!ret && hw_update) {
  273. ret = mlx4_ib_update_gids(gids, ibdev, attr->port_num);
  274. kfree(gids);
  275. }
  276. return ret;
  277. }
  278. static int mlx4_ib_del_gid(const struct ib_gid_attr *attr, void **context)
  279. {
  280. struct gid_cache_context *ctx = *context;
  281. struct mlx4_ib_dev *ibdev = to_mdev(attr->device);
  282. struct mlx4_ib_iboe *iboe = &ibdev->iboe;
  283. struct mlx4_port_gid_table *port_gid_table;
  284. int ret = 0;
  285. int hw_update = 0;
  286. struct gid_entry *gids = NULL;
  287. if (!rdma_cap_roce_gid_table(attr->device, attr->port_num))
  288. return -EINVAL;
  289. if (attr->port_num > MLX4_MAX_PORTS)
  290. return -EINVAL;
  291. port_gid_table = &iboe->gids[attr->port_num - 1];
  292. spin_lock_bh(&iboe->lock);
  293. if (ctx) {
  294. ctx->refcount--;
  295. if (!ctx->refcount) {
  296. unsigned int real_index = ctx->real_index;
  297. memset(&port_gid_table->gids[real_index].gid, 0,
  298. sizeof(port_gid_table->gids[real_index].gid));
  299. kfree(port_gid_table->gids[real_index].ctx);
  300. port_gid_table->gids[real_index].ctx = NULL;
  301. hw_update = 1;
  302. }
  303. }
  304. if (!ret && hw_update) {
  305. int i;
  306. gids = kmalloc_array(MLX4_MAX_PORT_GIDS, sizeof(*gids),
  307. GFP_ATOMIC);
  308. if (!gids) {
  309. ret = -ENOMEM;
  310. } else {
  311. for (i = 0; i < MLX4_MAX_PORT_GIDS; i++) {
  312. memcpy(&gids[i].gid,
  313. &port_gid_table->gids[i].gid,
  314. sizeof(union ib_gid));
  315. gids[i].gid_type =
  316. port_gid_table->gids[i].gid_type;
  317. }
  318. }
  319. }
  320. spin_unlock_bh(&iboe->lock);
  321. if (!ret && hw_update) {
  322. ret = mlx4_ib_update_gids(gids, ibdev, attr->port_num);
  323. kfree(gids);
  324. }
  325. return ret;
  326. }
  327. int mlx4_ib_gid_index_to_real_index(struct mlx4_ib_dev *ibdev,
  328. const struct ib_gid_attr *attr)
  329. {
  330. struct mlx4_ib_iboe *iboe = &ibdev->iboe;
  331. struct gid_cache_context *ctx = NULL;
  332. struct mlx4_port_gid_table *port_gid_table;
  333. int real_index = -EINVAL;
  334. int i;
  335. unsigned long flags;
  336. u8 port_num = attr->port_num;
  337. if (port_num > MLX4_MAX_PORTS)
  338. return -EINVAL;
  339. if (mlx4_is_bonded(ibdev->dev))
  340. port_num = 1;
  341. if (!rdma_cap_roce_gid_table(&ibdev->ib_dev, port_num))
  342. return attr->index;
  343. spin_lock_irqsave(&iboe->lock, flags);
  344. port_gid_table = &iboe->gids[port_num - 1];
  345. for (i = 0; i < MLX4_MAX_PORT_GIDS; ++i)
  346. if (!memcmp(&port_gid_table->gids[i].gid,
  347. &attr->gid, sizeof(attr->gid)) &&
  348. attr->gid_type == port_gid_table->gids[i].gid_type) {
  349. ctx = port_gid_table->gids[i].ctx;
  350. break;
  351. }
  352. if (ctx)
  353. real_index = ctx->real_index;
  354. spin_unlock_irqrestore(&iboe->lock, flags);
  355. return real_index;
  356. }
  357. #define field_avail(type, fld, sz) (offsetof(type, fld) + \
  358. sizeof(((type *)0)->fld) <= (sz))
  359. static int mlx4_ib_query_device(struct ib_device *ibdev,
  360. struct ib_device_attr *props,
  361. struct ib_udata *uhw)
  362. {
  363. struct mlx4_ib_dev *dev = to_mdev(ibdev);
  364. struct ib_smp *in_mad = NULL;
  365. struct ib_smp *out_mad = NULL;
  366. int err;
  367. int have_ib_ports;
  368. struct mlx4_uverbs_ex_query_device cmd;
  369. struct mlx4_uverbs_ex_query_device_resp resp = {.comp_mask = 0};
  370. struct mlx4_clock_params clock_params;
  371. if (uhw->inlen) {
  372. if (uhw->inlen < sizeof(cmd))
  373. return -EINVAL;
  374. err = ib_copy_from_udata(&cmd, uhw, sizeof(cmd));
  375. if (err)
  376. return err;
  377. if (cmd.comp_mask)
  378. return -EINVAL;
  379. if (cmd.reserved)
  380. return -EINVAL;
  381. }
  382. resp.response_length = offsetof(typeof(resp), response_length) +
  383. sizeof(resp.response_length);
  384. in_mad = kzalloc(sizeof *in_mad, GFP_KERNEL);
  385. out_mad = kmalloc(sizeof *out_mad, GFP_KERNEL);
  386. err = -ENOMEM;
  387. if (!in_mad || !out_mad)
  388. goto out;
  389. init_query_mad(in_mad);
  390. in_mad->attr_id = IB_SMP_ATTR_NODE_INFO;
  391. err = mlx4_MAD_IFC(to_mdev(ibdev), MLX4_MAD_IFC_IGNORE_KEYS,
  392. 1, NULL, NULL, in_mad, out_mad);
  393. if (err)
  394. goto out;
  395. memset(props, 0, sizeof *props);
  396. have_ib_ports = num_ib_ports(dev->dev);
  397. props->fw_ver = dev->dev->caps.fw_ver;
  398. props->device_cap_flags = IB_DEVICE_CHANGE_PHY_PORT |
  399. IB_DEVICE_PORT_ACTIVE_EVENT |
  400. IB_DEVICE_SYS_IMAGE_GUID |
  401. IB_DEVICE_RC_RNR_NAK_GEN |
  402. IB_DEVICE_BLOCK_MULTICAST_LOOPBACK;
  403. if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_BAD_PKEY_CNTR)
  404. props->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR;
  405. if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_BAD_QKEY_CNTR)
  406. props->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR;
  407. if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_APM && have_ib_ports)
  408. props->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG;
  409. if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_UD_AV_PORT)
  410. props->device_cap_flags |= IB_DEVICE_UD_AV_PORT_ENFORCE;
  411. if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_IPOIB_CSUM)
  412. props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM;
  413. if (dev->dev->caps.max_gso_sz &&
  414. (dev->dev->rev_id != MLX4_IB_CARD_REV_A0) &&
  415. (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_BLH))
  416. props->device_cap_flags |= IB_DEVICE_UD_TSO;
  417. if (dev->dev->caps.bmme_flags & MLX4_BMME_FLAG_RESERVED_LKEY)
  418. props->device_cap_flags |= IB_DEVICE_LOCAL_DMA_LKEY;
  419. if ((dev->dev->caps.bmme_flags & MLX4_BMME_FLAG_LOCAL_INV) &&
  420. (dev->dev->caps.bmme_flags & MLX4_BMME_FLAG_REMOTE_INV) &&
  421. (dev->dev->caps.bmme_flags & MLX4_BMME_FLAG_FAST_REG_WR))
  422. props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS;
  423. if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC)
  424. props->device_cap_flags |= IB_DEVICE_XRC;
  425. if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_MEM_WINDOW)
  426. props->device_cap_flags |= IB_DEVICE_MEM_WINDOW;
  427. if (dev->dev->caps.bmme_flags & MLX4_BMME_FLAG_TYPE_2_WIN) {
  428. if (dev->dev->caps.bmme_flags & MLX4_BMME_FLAG_WIN_TYPE_2B)
  429. props->device_cap_flags |= IB_DEVICE_MEM_WINDOW_TYPE_2B;
  430. else
  431. props->device_cap_flags |= IB_DEVICE_MEM_WINDOW_TYPE_2A;
  432. }
  433. if (dev->steering_support == MLX4_STEERING_MODE_DEVICE_MANAGED)
  434. props->device_cap_flags |= IB_DEVICE_MANAGED_FLOW_STEERING;
  435. props->device_cap_flags |= IB_DEVICE_RAW_IP_CSUM;
  436. props->vendor_id = be32_to_cpup((__be32 *) (out_mad->data + 36)) &
  437. 0xffffff;
  438. props->vendor_part_id = dev->dev->persist->pdev->device;
  439. props->hw_ver = be32_to_cpup((__be32 *) (out_mad->data + 32));
  440. memcpy(&props->sys_image_guid, out_mad->data + 4, 8);
  441. props->max_mr_size = ~0ull;
  442. props->page_size_cap = dev->dev->caps.page_size_cap;
  443. props->max_qp = dev->dev->quotas.qp;
  444. props->max_qp_wr = dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE;
  445. props->max_send_sge = dev->dev->caps.max_sq_sg;
  446. props->max_recv_sge = dev->dev->caps.max_rq_sg;
  447. props->max_sge_rd = MLX4_MAX_SGE_RD;
  448. props->max_cq = dev->dev->quotas.cq;
  449. props->max_cqe = dev->dev->caps.max_cqes;
  450. props->max_mr = dev->dev->quotas.mpt;
  451. props->max_pd = dev->dev->caps.num_pds - dev->dev->caps.reserved_pds;
  452. props->max_qp_rd_atom = dev->dev->caps.max_qp_dest_rdma;
  453. props->max_qp_init_rd_atom = dev->dev->caps.max_qp_init_rdma;
  454. props->max_res_rd_atom = props->max_qp_rd_atom * props->max_qp;
  455. props->max_srq = dev->dev->quotas.srq;
  456. props->max_srq_wr = dev->dev->caps.max_srq_wqes - 1;
  457. props->max_srq_sge = dev->dev->caps.max_srq_sge;
  458. props->max_fast_reg_page_list_len = MLX4_MAX_FAST_REG_PAGES;
  459. props->local_ca_ack_delay = dev->dev->caps.local_ca_ack_delay;
  460. props->atomic_cap = dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_ATOMIC ?
  461. IB_ATOMIC_HCA : IB_ATOMIC_NONE;
  462. props->masked_atomic_cap = props->atomic_cap;
  463. props->max_pkeys = dev->dev->caps.pkey_table_len[1];
  464. props->max_mcast_grp = dev->dev->caps.num_mgms + dev->dev->caps.num_amgms;
  465. props->max_mcast_qp_attach = dev->dev->caps.num_qp_per_mgm;
  466. props->max_total_mcast_qp_attach = props->max_mcast_qp_attach *
  467. props->max_mcast_grp;
  468. props->max_map_per_fmr = dev->dev->caps.max_fmr_maps;
  469. props->hca_core_clock = dev->dev->caps.hca_core_clock * 1000UL;
  470. props->timestamp_mask = 0xFFFFFFFFFFFFULL;
  471. props->max_ah = INT_MAX;
  472. if (mlx4_ib_port_link_layer(ibdev, 1) == IB_LINK_LAYER_ETHERNET ||
  473. mlx4_ib_port_link_layer(ibdev, 2) == IB_LINK_LAYER_ETHERNET) {
  474. if (dev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_RSS) {
  475. props->rss_caps.max_rwq_indirection_tables =
  476. props->max_qp;
  477. props->rss_caps.max_rwq_indirection_table_size =
  478. dev->dev->caps.max_rss_tbl_sz;
  479. props->rss_caps.supported_qpts = 1 << IB_QPT_RAW_PACKET;
  480. props->max_wq_type_rq = props->max_qp;
  481. }
  482. if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_FCS_KEEP)
  483. props->raw_packet_caps |= IB_RAW_PACKET_CAP_SCATTER_FCS;
  484. }
  485. props->cq_caps.max_cq_moderation_count = MLX4_MAX_CQ_COUNT;
  486. props->cq_caps.max_cq_moderation_period = MLX4_MAX_CQ_PERIOD;
  487. if (!mlx4_is_slave(dev->dev))
  488. err = mlx4_get_internal_clock_params(dev->dev, &clock_params);
  489. if (uhw->outlen >= resp.response_length + sizeof(resp.hca_core_clock_offset)) {
  490. resp.response_length += sizeof(resp.hca_core_clock_offset);
  491. if (!err && !mlx4_is_slave(dev->dev)) {
  492. resp.comp_mask |= MLX4_IB_QUERY_DEV_RESP_MASK_CORE_CLOCK_OFFSET;
  493. resp.hca_core_clock_offset = clock_params.offset % PAGE_SIZE;
  494. }
  495. }
  496. if (uhw->outlen >= resp.response_length +
  497. sizeof(resp.max_inl_recv_sz)) {
  498. resp.response_length += sizeof(resp.max_inl_recv_sz);
  499. resp.max_inl_recv_sz = dev->dev->caps.max_rq_sg *
  500. sizeof(struct mlx4_wqe_data_seg);
  501. }
  502. if (field_avail(typeof(resp), rss_caps, uhw->outlen)) {
  503. if (props->rss_caps.supported_qpts) {
  504. resp.rss_caps.rx_hash_function =
  505. MLX4_IB_RX_HASH_FUNC_TOEPLITZ;
  506. resp.rss_caps.rx_hash_fields_mask =
  507. MLX4_IB_RX_HASH_SRC_IPV4 |
  508. MLX4_IB_RX_HASH_DST_IPV4 |
  509. MLX4_IB_RX_HASH_SRC_IPV6 |
  510. MLX4_IB_RX_HASH_DST_IPV6 |
  511. MLX4_IB_RX_HASH_SRC_PORT_TCP |
  512. MLX4_IB_RX_HASH_DST_PORT_TCP |
  513. MLX4_IB_RX_HASH_SRC_PORT_UDP |
  514. MLX4_IB_RX_HASH_DST_PORT_UDP;
  515. if (dev->dev->caps.tunnel_offload_mode ==
  516. MLX4_TUNNEL_OFFLOAD_MODE_VXLAN)
  517. resp.rss_caps.rx_hash_fields_mask |=
  518. MLX4_IB_RX_HASH_INNER;
  519. }
  520. resp.response_length = offsetof(typeof(resp), rss_caps) +
  521. sizeof(resp.rss_caps);
  522. }
  523. if (field_avail(typeof(resp), tso_caps, uhw->outlen)) {
  524. if (dev->dev->caps.max_gso_sz &&
  525. ((mlx4_ib_port_link_layer(ibdev, 1) ==
  526. IB_LINK_LAYER_ETHERNET) ||
  527. (mlx4_ib_port_link_layer(ibdev, 2) ==
  528. IB_LINK_LAYER_ETHERNET))) {
  529. resp.tso_caps.max_tso = dev->dev->caps.max_gso_sz;
  530. resp.tso_caps.supported_qpts |=
  531. 1 << IB_QPT_RAW_PACKET;
  532. }
  533. resp.response_length = offsetof(typeof(resp), tso_caps) +
  534. sizeof(resp.tso_caps);
  535. }
  536. if (uhw->outlen) {
  537. err = ib_copy_to_udata(uhw, &resp, resp.response_length);
  538. if (err)
  539. goto out;
  540. }
  541. out:
  542. kfree(in_mad);
  543. kfree(out_mad);
  544. return err;
  545. }
  546. static enum rdma_link_layer
  547. mlx4_ib_port_link_layer(struct ib_device *device, u8 port_num)
  548. {
  549. struct mlx4_dev *dev = to_mdev(device)->dev;
  550. return dev->caps.port_mask[port_num] == MLX4_PORT_TYPE_IB ?
  551. IB_LINK_LAYER_INFINIBAND : IB_LINK_LAYER_ETHERNET;
  552. }
  553. static int ib_link_query_port(struct ib_device *ibdev, u8 port,
  554. struct ib_port_attr *props, int netw_view)
  555. {
  556. struct ib_smp *in_mad = NULL;
  557. struct ib_smp *out_mad = NULL;
  558. int ext_active_speed;
  559. int mad_ifc_flags = MLX4_MAD_IFC_IGNORE_KEYS;
  560. int err = -ENOMEM;
  561. in_mad = kzalloc(sizeof *in_mad, GFP_KERNEL);
  562. out_mad = kmalloc(sizeof *out_mad, GFP_KERNEL);
  563. if (!in_mad || !out_mad)
  564. goto out;
  565. init_query_mad(in_mad);
  566. in_mad->attr_id = IB_SMP_ATTR_PORT_INFO;
  567. in_mad->attr_mod = cpu_to_be32(port);
  568. if (mlx4_is_mfunc(to_mdev(ibdev)->dev) && netw_view)
  569. mad_ifc_flags |= MLX4_MAD_IFC_NET_VIEW;
  570. err = mlx4_MAD_IFC(to_mdev(ibdev), mad_ifc_flags, port, NULL, NULL,
  571. in_mad, out_mad);
  572. if (err)
  573. goto out;
  574. props->lid = be16_to_cpup((__be16 *) (out_mad->data + 16));
  575. props->lmc = out_mad->data[34] & 0x7;
  576. props->sm_lid = be16_to_cpup((__be16 *) (out_mad->data + 18));
  577. props->sm_sl = out_mad->data[36] & 0xf;
  578. props->state = out_mad->data[32] & 0xf;
  579. props->phys_state = out_mad->data[33] >> 4;
  580. props->port_cap_flags = be32_to_cpup((__be32 *) (out_mad->data + 20));
  581. if (netw_view)
  582. props->gid_tbl_len = out_mad->data[50];
  583. else
  584. props->gid_tbl_len = to_mdev(ibdev)->dev->caps.gid_table_len[port];
  585. props->max_msg_sz = to_mdev(ibdev)->dev->caps.max_msg_sz;
  586. props->pkey_tbl_len = to_mdev(ibdev)->dev->caps.pkey_table_len[port];
  587. props->bad_pkey_cntr = be16_to_cpup((__be16 *) (out_mad->data + 46));
  588. props->qkey_viol_cntr = be16_to_cpup((__be16 *) (out_mad->data + 48));
  589. props->active_width = out_mad->data[31] & 0xf;
  590. props->active_speed = out_mad->data[35] >> 4;
  591. props->max_mtu = out_mad->data[41] & 0xf;
  592. props->active_mtu = out_mad->data[36] >> 4;
  593. props->subnet_timeout = out_mad->data[51] & 0x1f;
  594. props->max_vl_num = out_mad->data[37] >> 4;
  595. props->init_type_reply = out_mad->data[41] >> 4;
  596. /* Check if extended speeds (EDR/FDR/...) are supported */
  597. if (props->port_cap_flags & IB_PORT_EXTENDED_SPEEDS_SUP) {
  598. ext_active_speed = out_mad->data[62] >> 4;
  599. switch (ext_active_speed) {
  600. case 1:
  601. props->active_speed = IB_SPEED_FDR;
  602. break;
  603. case 2:
  604. props->active_speed = IB_SPEED_EDR;
  605. break;
  606. }
  607. }
  608. /* If reported active speed is QDR, check if is FDR-10 */
  609. if (props->active_speed == IB_SPEED_QDR) {
  610. init_query_mad(in_mad);
  611. in_mad->attr_id = MLX4_ATTR_EXTENDED_PORT_INFO;
  612. in_mad->attr_mod = cpu_to_be32(port);
  613. err = mlx4_MAD_IFC(to_mdev(ibdev), mad_ifc_flags, port,
  614. NULL, NULL, in_mad, out_mad);
  615. if (err)
  616. goto out;
  617. /* Checking LinkSpeedActive for FDR-10 */
  618. if (out_mad->data[15] & 0x1)
  619. props->active_speed = IB_SPEED_FDR10;
  620. }
  621. /* Avoid wrong speed value returned by FW if the IB link is down. */
  622. if (props->state == IB_PORT_DOWN)
  623. props->active_speed = IB_SPEED_SDR;
  624. out:
  625. kfree(in_mad);
  626. kfree(out_mad);
  627. return err;
  628. }
  629. static u8 state_to_phys_state(enum ib_port_state state)
  630. {
  631. return state == IB_PORT_ACTIVE ? 5 : 3;
  632. }
  633. static int eth_link_query_port(struct ib_device *ibdev, u8 port,
  634. struct ib_port_attr *props)
  635. {
  636. struct mlx4_ib_dev *mdev = to_mdev(ibdev);
  637. struct mlx4_ib_iboe *iboe = &mdev->iboe;
  638. struct net_device *ndev;
  639. enum ib_mtu tmp;
  640. struct mlx4_cmd_mailbox *mailbox;
  641. int err = 0;
  642. int is_bonded = mlx4_is_bonded(mdev->dev);
  643. mailbox = mlx4_alloc_cmd_mailbox(mdev->dev);
  644. if (IS_ERR(mailbox))
  645. return PTR_ERR(mailbox);
  646. err = mlx4_cmd_box(mdev->dev, 0, mailbox->dma, port, 0,
  647. MLX4_CMD_QUERY_PORT, MLX4_CMD_TIME_CLASS_B,
  648. MLX4_CMD_WRAPPED);
  649. if (err)
  650. goto out;
  651. props->active_width = (((u8 *)mailbox->buf)[5] == 0x40) ||
  652. (((u8 *)mailbox->buf)[5] == 0x20 /*56Gb*/) ?
  653. IB_WIDTH_4X : IB_WIDTH_1X;
  654. props->active_speed = (((u8 *)mailbox->buf)[5] == 0x20 /*56Gb*/) ?
  655. IB_SPEED_FDR : IB_SPEED_QDR;
  656. props->port_cap_flags = IB_PORT_CM_SUP;
  657. props->ip_gids = true;
  658. props->gid_tbl_len = mdev->dev->caps.gid_table_len[port];
  659. props->max_msg_sz = mdev->dev->caps.max_msg_sz;
  660. props->pkey_tbl_len = 1;
  661. props->max_mtu = IB_MTU_4096;
  662. props->max_vl_num = 2;
  663. props->state = IB_PORT_DOWN;
  664. props->phys_state = state_to_phys_state(props->state);
  665. props->active_mtu = IB_MTU_256;
  666. spin_lock_bh(&iboe->lock);
  667. ndev = iboe->netdevs[port - 1];
  668. if (ndev && is_bonded) {
  669. rcu_read_lock(); /* required to get upper dev */
  670. ndev = netdev_master_upper_dev_get_rcu(ndev);
  671. rcu_read_unlock();
  672. }
  673. if (!ndev)
  674. goto out_unlock;
  675. tmp = iboe_get_mtu(ndev->mtu);
  676. props->active_mtu = tmp ? min(props->max_mtu, tmp) : IB_MTU_256;
  677. props->state = (netif_running(ndev) && netif_carrier_ok(ndev)) ?
  678. IB_PORT_ACTIVE : IB_PORT_DOWN;
  679. props->phys_state = state_to_phys_state(props->state);
  680. out_unlock:
  681. spin_unlock_bh(&iboe->lock);
  682. out:
  683. mlx4_free_cmd_mailbox(mdev->dev, mailbox);
  684. return err;
  685. }
  686. int __mlx4_ib_query_port(struct ib_device *ibdev, u8 port,
  687. struct ib_port_attr *props, int netw_view)
  688. {
  689. int err;
  690. /* props being zeroed by the caller, avoid zeroing it here */
  691. err = mlx4_ib_port_link_layer(ibdev, port) == IB_LINK_LAYER_INFINIBAND ?
  692. ib_link_query_port(ibdev, port, props, netw_view) :
  693. eth_link_query_port(ibdev, port, props);
  694. return err;
  695. }
  696. static int mlx4_ib_query_port(struct ib_device *ibdev, u8 port,
  697. struct ib_port_attr *props)
  698. {
  699. /* returns host view */
  700. return __mlx4_ib_query_port(ibdev, port, props, 0);
  701. }
  702. int __mlx4_ib_query_gid(struct ib_device *ibdev, u8 port, int index,
  703. union ib_gid *gid, int netw_view)
  704. {
  705. struct ib_smp *in_mad = NULL;
  706. struct ib_smp *out_mad = NULL;
  707. int err = -ENOMEM;
  708. struct mlx4_ib_dev *dev = to_mdev(ibdev);
  709. int clear = 0;
  710. int mad_ifc_flags = MLX4_MAD_IFC_IGNORE_KEYS;
  711. in_mad = kzalloc(sizeof *in_mad, GFP_KERNEL);
  712. out_mad = kmalloc(sizeof *out_mad, GFP_KERNEL);
  713. if (!in_mad || !out_mad)
  714. goto out;
  715. init_query_mad(in_mad);
  716. in_mad->attr_id = IB_SMP_ATTR_PORT_INFO;
  717. in_mad->attr_mod = cpu_to_be32(port);
  718. if (mlx4_is_mfunc(dev->dev) && netw_view)
  719. mad_ifc_flags |= MLX4_MAD_IFC_NET_VIEW;
  720. err = mlx4_MAD_IFC(dev, mad_ifc_flags, port, NULL, NULL, in_mad, out_mad);
  721. if (err)
  722. goto out;
  723. memcpy(gid->raw, out_mad->data + 8, 8);
  724. if (mlx4_is_mfunc(dev->dev) && !netw_view) {
  725. if (index) {
  726. /* For any index > 0, return the null guid */
  727. err = 0;
  728. clear = 1;
  729. goto out;
  730. }
  731. }
  732. init_query_mad(in_mad);
  733. in_mad->attr_id = IB_SMP_ATTR_GUID_INFO;
  734. in_mad->attr_mod = cpu_to_be32(index / 8);
  735. err = mlx4_MAD_IFC(dev, mad_ifc_flags, port,
  736. NULL, NULL, in_mad, out_mad);
  737. if (err)
  738. goto out;
  739. memcpy(gid->raw + 8, out_mad->data + (index % 8) * 8, 8);
  740. out:
  741. if (clear)
  742. memset(gid->raw + 8, 0, 8);
  743. kfree(in_mad);
  744. kfree(out_mad);
  745. return err;
  746. }
  747. static int mlx4_ib_query_gid(struct ib_device *ibdev, u8 port, int index,
  748. union ib_gid *gid)
  749. {
  750. if (rdma_protocol_ib(ibdev, port))
  751. return __mlx4_ib_query_gid(ibdev, port, index, gid, 0);
  752. return 0;
  753. }
  754. static int mlx4_ib_query_sl2vl(struct ib_device *ibdev, u8 port, u64 *sl2vl_tbl)
  755. {
  756. union sl2vl_tbl_to_u64 sl2vl64;
  757. struct ib_smp *in_mad = NULL;
  758. struct ib_smp *out_mad = NULL;
  759. int mad_ifc_flags = MLX4_MAD_IFC_IGNORE_KEYS;
  760. int err = -ENOMEM;
  761. int jj;
  762. if (mlx4_is_slave(to_mdev(ibdev)->dev)) {
  763. *sl2vl_tbl = 0;
  764. return 0;
  765. }
  766. in_mad = kzalloc(sizeof(*in_mad), GFP_KERNEL);
  767. out_mad = kmalloc(sizeof(*out_mad), GFP_KERNEL);
  768. if (!in_mad || !out_mad)
  769. goto out;
  770. init_query_mad(in_mad);
  771. in_mad->attr_id = IB_SMP_ATTR_SL_TO_VL_TABLE;
  772. in_mad->attr_mod = 0;
  773. if (mlx4_is_mfunc(to_mdev(ibdev)->dev))
  774. mad_ifc_flags |= MLX4_MAD_IFC_NET_VIEW;
  775. err = mlx4_MAD_IFC(to_mdev(ibdev), mad_ifc_flags, port, NULL, NULL,
  776. in_mad, out_mad);
  777. if (err)
  778. goto out;
  779. for (jj = 0; jj < 8; jj++)
  780. sl2vl64.sl8[jj] = ((struct ib_smp *)out_mad)->data[jj];
  781. *sl2vl_tbl = sl2vl64.sl64;
  782. out:
  783. kfree(in_mad);
  784. kfree(out_mad);
  785. return err;
  786. }
  787. static void mlx4_init_sl2vl_tbl(struct mlx4_ib_dev *mdev)
  788. {
  789. u64 sl2vl;
  790. int i;
  791. int err;
  792. for (i = 1; i <= mdev->dev->caps.num_ports; i++) {
  793. if (mdev->dev->caps.port_type[i] == MLX4_PORT_TYPE_ETH)
  794. continue;
  795. err = mlx4_ib_query_sl2vl(&mdev->ib_dev, i, &sl2vl);
  796. if (err) {
  797. pr_err("Unable to get default sl to vl mapping for port %d. Using all zeroes (%d)\n",
  798. i, err);
  799. sl2vl = 0;
  800. }
  801. atomic64_set(&mdev->sl2vl[i - 1], sl2vl);
  802. }
  803. }
  804. int __mlx4_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index,
  805. u16 *pkey, int netw_view)
  806. {
  807. struct ib_smp *in_mad = NULL;
  808. struct ib_smp *out_mad = NULL;
  809. int mad_ifc_flags = MLX4_MAD_IFC_IGNORE_KEYS;
  810. int err = -ENOMEM;
  811. in_mad = kzalloc(sizeof *in_mad, GFP_KERNEL);
  812. out_mad = kmalloc(sizeof *out_mad, GFP_KERNEL);
  813. if (!in_mad || !out_mad)
  814. goto out;
  815. init_query_mad(in_mad);
  816. in_mad->attr_id = IB_SMP_ATTR_PKEY_TABLE;
  817. in_mad->attr_mod = cpu_to_be32(index / 32);
  818. if (mlx4_is_mfunc(to_mdev(ibdev)->dev) && netw_view)
  819. mad_ifc_flags |= MLX4_MAD_IFC_NET_VIEW;
  820. err = mlx4_MAD_IFC(to_mdev(ibdev), mad_ifc_flags, port, NULL, NULL,
  821. in_mad, out_mad);
  822. if (err)
  823. goto out;
  824. *pkey = be16_to_cpu(((__be16 *) out_mad->data)[index % 32]);
  825. out:
  826. kfree(in_mad);
  827. kfree(out_mad);
  828. return err;
  829. }
  830. static int mlx4_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index, u16 *pkey)
  831. {
  832. return __mlx4_ib_query_pkey(ibdev, port, index, pkey, 0);
  833. }
  834. static int mlx4_ib_modify_device(struct ib_device *ibdev, int mask,
  835. struct ib_device_modify *props)
  836. {
  837. struct mlx4_cmd_mailbox *mailbox;
  838. unsigned long flags;
  839. if (mask & ~IB_DEVICE_MODIFY_NODE_DESC)
  840. return -EOPNOTSUPP;
  841. if (!(mask & IB_DEVICE_MODIFY_NODE_DESC))
  842. return 0;
  843. if (mlx4_is_slave(to_mdev(ibdev)->dev))
  844. return -EOPNOTSUPP;
  845. spin_lock_irqsave(&to_mdev(ibdev)->sm_lock, flags);
  846. memcpy(ibdev->node_desc, props->node_desc, IB_DEVICE_NODE_DESC_MAX);
  847. spin_unlock_irqrestore(&to_mdev(ibdev)->sm_lock, flags);
  848. /*
  849. * If possible, pass node desc to FW, so it can generate
  850. * a 144 trap. If cmd fails, just ignore.
  851. */
  852. mailbox = mlx4_alloc_cmd_mailbox(to_mdev(ibdev)->dev);
  853. if (IS_ERR(mailbox))
  854. return 0;
  855. memcpy(mailbox->buf, props->node_desc, IB_DEVICE_NODE_DESC_MAX);
  856. mlx4_cmd(to_mdev(ibdev)->dev, mailbox->dma, 1, 0,
  857. MLX4_CMD_SET_NODE, MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
  858. mlx4_free_cmd_mailbox(to_mdev(ibdev)->dev, mailbox);
  859. return 0;
  860. }
  861. static int mlx4_ib_SET_PORT(struct mlx4_ib_dev *dev, u8 port, int reset_qkey_viols,
  862. u32 cap_mask)
  863. {
  864. struct mlx4_cmd_mailbox *mailbox;
  865. int err;
  866. mailbox = mlx4_alloc_cmd_mailbox(dev->dev);
  867. if (IS_ERR(mailbox))
  868. return PTR_ERR(mailbox);
  869. if (dev->dev->flags & MLX4_FLAG_OLD_PORT_CMDS) {
  870. *(u8 *) mailbox->buf = !!reset_qkey_viols << 6;
  871. ((__be32 *) mailbox->buf)[2] = cpu_to_be32(cap_mask);
  872. } else {
  873. ((u8 *) mailbox->buf)[3] = !!reset_qkey_viols;
  874. ((__be32 *) mailbox->buf)[1] = cpu_to_be32(cap_mask);
  875. }
  876. err = mlx4_cmd(dev->dev, mailbox->dma, port, MLX4_SET_PORT_IB_OPCODE,
  877. MLX4_CMD_SET_PORT, MLX4_CMD_TIME_CLASS_B,
  878. MLX4_CMD_WRAPPED);
  879. mlx4_free_cmd_mailbox(dev->dev, mailbox);
  880. return err;
  881. }
  882. static int mlx4_ib_modify_port(struct ib_device *ibdev, u8 port, int mask,
  883. struct ib_port_modify *props)
  884. {
  885. struct mlx4_ib_dev *mdev = to_mdev(ibdev);
  886. u8 is_eth = mdev->dev->caps.port_type[port] == MLX4_PORT_TYPE_ETH;
  887. struct ib_port_attr attr;
  888. u32 cap_mask;
  889. int err;
  890. /* return OK if this is RoCE. CM calls ib_modify_port() regardless
  891. * of whether port link layer is ETH or IB. For ETH ports, qkey
  892. * violations and port capabilities are not meaningful.
  893. */
  894. if (is_eth)
  895. return 0;
  896. mutex_lock(&mdev->cap_mask_mutex);
  897. err = ib_query_port(ibdev, port, &attr);
  898. if (err)
  899. goto out;
  900. cap_mask = (attr.port_cap_flags | props->set_port_cap_mask) &
  901. ~props->clr_port_cap_mask;
  902. err = mlx4_ib_SET_PORT(mdev, port,
  903. !!(mask & IB_PORT_RESET_QKEY_CNTR),
  904. cap_mask);
  905. out:
  906. mutex_unlock(&to_mdev(ibdev)->cap_mask_mutex);
  907. return err;
  908. }
  909. static struct ib_ucontext *mlx4_ib_alloc_ucontext(struct ib_device *ibdev,
  910. struct ib_udata *udata)
  911. {
  912. struct mlx4_ib_dev *dev = to_mdev(ibdev);
  913. struct mlx4_ib_ucontext *context;
  914. struct mlx4_ib_alloc_ucontext_resp_v3 resp_v3;
  915. struct mlx4_ib_alloc_ucontext_resp resp;
  916. int err;
  917. if (!dev->ib_active)
  918. return ERR_PTR(-EAGAIN);
  919. if (ibdev->uverbs_abi_ver == MLX4_IB_UVERBS_NO_DEV_CAPS_ABI_VERSION) {
  920. resp_v3.qp_tab_size = dev->dev->caps.num_qps;
  921. resp_v3.bf_reg_size = dev->dev->caps.bf_reg_size;
  922. resp_v3.bf_regs_per_page = dev->dev->caps.bf_regs_per_page;
  923. } else {
  924. resp.dev_caps = dev->dev->caps.userspace_caps;
  925. resp.qp_tab_size = dev->dev->caps.num_qps;
  926. resp.bf_reg_size = dev->dev->caps.bf_reg_size;
  927. resp.bf_regs_per_page = dev->dev->caps.bf_regs_per_page;
  928. resp.cqe_size = dev->dev->caps.cqe_size;
  929. }
  930. context = kzalloc(sizeof(*context), GFP_KERNEL);
  931. if (!context)
  932. return ERR_PTR(-ENOMEM);
  933. err = mlx4_uar_alloc(to_mdev(ibdev)->dev, &context->uar);
  934. if (err) {
  935. kfree(context);
  936. return ERR_PTR(err);
  937. }
  938. INIT_LIST_HEAD(&context->db_page_list);
  939. mutex_init(&context->db_page_mutex);
  940. INIT_LIST_HEAD(&context->wqn_ranges_list);
  941. mutex_init(&context->wqn_ranges_mutex);
  942. if (ibdev->uverbs_abi_ver == MLX4_IB_UVERBS_NO_DEV_CAPS_ABI_VERSION)
  943. err = ib_copy_to_udata(udata, &resp_v3, sizeof(resp_v3));
  944. else
  945. err = ib_copy_to_udata(udata, &resp, sizeof(resp));
  946. if (err) {
  947. mlx4_uar_free(to_mdev(ibdev)->dev, &context->uar);
  948. kfree(context);
  949. return ERR_PTR(-EFAULT);
  950. }
  951. return &context->ibucontext;
  952. }
  953. static int mlx4_ib_dealloc_ucontext(struct ib_ucontext *ibcontext)
  954. {
  955. struct mlx4_ib_ucontext *context = to_mucontext(ibcontext);
  956. mlx4_uar_free(to_mdev(ibcontext->device)->dev, &context->uar);
  957. kfree(context);
  958. return 0;
  959. }
  960. static void mlx4_ib_vma_open(struct vm_area_struct *area)
  961. {
  962. /* vma_open is called when a new VMA is created on top of our VMA.
  963. * This is done through either mremap flow or split_vma (usually due
  964. * to mlock, madvise, munmap, etc.). We do not support a clone of the
  965. * vma, as this VMA is strongly hardware related. Therefore we set the
  966. * vm_ops of the newly created/cloned VMA to NULL, to prevent it from
  967. * calling us again and trying to do incorrect actions. We assume that
  968. * the original vma size is exactly a single page that there will be no
  969. * "splitting" operations on.
  970. */
  971. area->vm_ops = NULL;
  972. }
  973. static void mlx4_ib_vma_close(struct vm_area_struct *area)
  974. {
  975. struct mlx4_ib_vma_private_data *mlx4_ib_vma_priv_data;
  976. /* It's guaranteed that all VMAs opened on a FD are closed before the
  977. * file itself is closed, therefore no sync is needed with the regular
  978. * closing flow. (e.g. mlx4_ib_dealloc_ucontext) However need a sync
  979. * with accessing the vma as part of mlx4_ib_disassociate_ucontext.
  980. * The close operation is usually called under mm->mmap_sem except when
  981. * process is exiting. The exiting case is handled explicitly as part
  982. * of mlx4_ib_disassociate_ucontext.
  983. */
  984. mlx4_ib_vma_priv_data = (struct mlx4_ib_vma_private_data *)
  985. area->vm_private_data;
  986. /* set the vma context pointer to null in the mlx4_ib driver's private
  987. * data to protect against a race condition in mlx4_ib_dissassociate_ucontext().
  988. */
  989. mlx4_ib_vma_priv_data->vma = NULL;
  990. }
  991. static const struct vm_operations_struct mlx4_ib_vm_ops = {
  992. .open = mlx4_ib_vma_open,
  993. .close = mlx4_ib_vma_close
  994. };
  995. static void mlx4_ib_disassociate_ucontext(struct ib_ucontext *ibcontext)
  996. {
  997. int i;
  998. struct vm_area_struct *vma;
  999. struct mlx4_ib_ucontext *context = to_mucontext(ibcontext);
  1000. /* need to protect from a race on closing the vma as part of
  1001. * mlx4_ib_vma_close().
  1002. */
  1003. for (i = 0; i < HW_BAR_COUNT; i++) {
  1004. vma = context->hw_bar_info[i].vma;
  1005. if (!vma)
  1006. continue;
  1007. zap_vma_ptes(context->hw_bar_info[i].vma,
  1008. context->hw_bar_info[i].vma->vm_start, PAGE_SIZE);
  1009. context->hw_bar_info[i].vma->vm_flags &=
  1010. ~(VM_SHARED | VM_MAYSHARE);
  1011. /* context going to be destroyed, should not access ops any more */
  1012. context->hw_bar_info[i].vma->vm_ops = NULL;
  1013. }
  1014. }
  1015. static void mlx4_ib_set_vma_data(struct vm_area_struct *vma,
  1016. struct mlx4_ib_vma_private_data *vma_private_data)
  1017. {
  1018. vma_private_data->vma = vma;
  1019. vma->vm_private_data = vma_private_data;
  1020. vma->vm_ops = &mlx4_ib_vm_ops;
  1021. }
  1022. static int mlx4_ib_mmap(struct ib_ucontext *context, struct vm_area_struct *vma)
  1023. {
  1024. struct mlx4_ib_dev *dev = to_mdev(context->device);
  1025. struct mlx4_ib_ucontext *mucontext = to_mucontext(context);
  1026. if (vma->vm_end - vma->vm_start != PAGE_SIZE)
  1027. return -EINVAL;
  1028. if (vma->vm_pgoff == 0) {
  1029. /* We prevent double mmaping on same context */
  1030. if (mucontext->hw_bar_info[HW_BAR_DB].vma)
  1031. return -EINVAL;
  1032. vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
  1033. if (io_remap_pfn_range(vma, vma->vm_start,
  1034. to_mucontext(context)->uar.pfn,
  1035. PAGE_SIZE, vma->vm_page_prot))
  1036. return -EAGAIN;
  1037. mlx4_ib_set_vma_data(vma, &mucontext->hw_bar_info[HW_BAR_DB]);
  1038. } else if (vma->vm_pgoff == 1 && dev->dev->caps.bf_reg_size != 0) {
  1039. /* We prevent double mmaping on same context */
  1040. if (mucontext->hw_bar_info[HW_BAR_BF].vma)
  1041. return -EINVAL;
  1042. vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot);
  1043. if (io_remap_pfn_range(vma, vma->vm_start,
  1044. to_mucontext(context)->uar.pfn +
  1045. dev->dev->caps.num_uars,
  1046. PAGE_SIZE, vma->vm_page_prot))
  1047. return -EAGAIN;
  1048. mlx4_ib_set_vma_data(vma, &mucontext->hw_bar_info[HW_BAR_BF]);
  1049. } else if (vma->vm_pgoff == 3) {
  1050. struct mlx4_clock_params params;
  1051. int ret;
  1052. /* We prevent double mmaping on same context */
  1053. if (mucontext->hw_bar_info[HW_BAR_CLOCK].vma)
  1054. return -EINVAL;
  1055. ret = mlx4_get_internal_clock_params(dev->dev, &params);
  1056. if (ret)
  1057. return ret;
  1058. vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
  1059. if (io_remap_pfn_range(vma, vma->vm_start,
  1060. (pci_resource_start(dev->dev->persist->pdev,
  1061. params.bar) +
  1062. params.offset)
  1063. >> PAGE_SHIFT,
  1064. PAGE_SIZE, vma->vm_page_prot))
  1065. return -EAGAIN;
  1066. mlx4_ib_set_vma_data(vma,
  1067. &mucontext->hw_bar_info[HW_BAR_CLOCK]);
  1068. } else {
  1069. return -EINVAL;
  1070. }
  1071. return 0;
  1072. }
  1073. static struct ib_pd *mlx4_ib_alloc_pd(struct ib_device *ibdev,
  1074. struct ib_ucontext *context,
  1075. struct ib_udata *udata)
  1076. {
  1077. struct mlx4_ib_pd *pd;
  1078. int err;
  1079. pd = kzalloc(sizeof(*pd), GFP_KERNEL);
  1080. if (!pd)
  1081. return ERR_PTR(-ENOMEM);
  1082. err = mlx4_pd_alloc(to_mdev(ibdev)->dev, &pd->pdn);
  1083. if (err) {
  1084. kfree(pd);
  1085. return ERR_PTR(err);
  1086. }
  1087. if (context)
  1088. if (ib_copy_to_udata(udata, &pd->pdn, sizeof (__u32))) {
  1089. mlx4_pd_free(to_mdev(ibdev)->dev, pd->pdn);
  1090. kfree(pd);
  1091. return ERR_PTR(-EFAULT);
  1092. }
  1093. return &pd->ibpd;
  1094. }
  1095. static int mlx4_ib_dealloc_pd(struct ib_pd *pd)
  1096. {
  1097. mlx4_pd_free(to_mdev(pd->device)->dev, to_mpd(pd)->pdn);
  1098. kfree(pd);
  1099. return 0;
  1100. }
  1101. static struct ib_xrcd *mlx4_ib_alloc_xrcd(struct ib_device *ibdev,
  1102. struct ib_ucontext *context,
  1103. struct ib_udata *udata)
  1104. {
  1105. struct mlx4_ib_xrcd *xrcd;
  1106. struct ib_cq_init_attr cq_attr = {};
  1107. int err;
  1108. if (!(to_mdev(ibdev)->dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC))
  1109. return ERR_PTR(-ENOSYS);
  1110. xrcd = kmalloc(sizeof *xrcd, GFP_KERNEL);
  1111. if (!xrcd)
  1112. return ERR_PTR(-ENOMEM);
  1113. err = mlx4_xrcd_alloc(to_mdev(ibdev)->dev, &xrcd->xrcdn);
  1114. if (err)
  1115. goto err1;
  1116. xrcd->pd = ib_alloc_pd(ibdev, 0);
  1117. if (IS_ERR(xrcd->pd)) {
  1118. err = PTR_ERR(xrcd->pd);
  1119. goto err2;
  1120. }
  1121. cq_attr.cqe = 1;
  1122. xrcd->cq = ib_create_cq(ibdev, NULL, NULL, xrcd, &cq_attr);
  1123. if (IS_ERR(xrcd->cq)) {
  1124. err = PTR_ERR(xrcd->cq);
  1125. goto err3;
  1126. }
  1127. return &xrcd->ibxrcd;
  1128. err3:
  1129. ib_dealloc_pd(xrcd->pd);
  1130. err2:
  1131. mlx4_xrcd_free(to_mdev(ibdev)->dev, xrcd->xrcdn);
  1132. err1:
  1133. kfree(xrcd);
  1134. return ERR_PTR(err);
  1135. }
  1136. static int mlx4_ib_dealloc_xrcd(struct ib_xrcd *xrcd)
  1137. {
  1138. ib_destroy_cq(to_mxrcd(xrcd)->cq);
  1139. ib_dealloc_pd(to_mxrcd(xrcd)->pd);
  1140. mlx4_xrcd_free(to_mdev(xrcd->device)->dev, to_mxrcd(xrcd)->xrcdn);
  1141. kfree(xrcd);
  1142. return 0;
  1143. }
  1144. static int add_gid_entry(struct ib_qp *ibqp, union ib_gid *gid)
  1145. {
  1146. struct mlx4_ib_qp *mqp = to_mqp(ibqp);
  1147. struct mlx4_ib_dev *mdev = to_mdev(ibqp->device);
  1148. struct mlx4_ib_gid_entry *ge;
  1149. ge = kzalloc(sizeof *ge, GFP_KERNEL);
  1150. if (!ge)
  1151. return -ENOMEM;
  1152. ge->gid = *gid;
  1153. if (mlx4_ib_add_mc(mdev, mqp, gid)) {
  1154. ge->port = mqp->port;
  1155. ge->added = 1;
  1156. }
  1157. mutex_lock(&mqp->mutex);
  1158. list_add_tail(&ge->list, &mqp->gid_list);
  1159. mutex_unlock(&mqp->mutex);
  1160. return 0;
  1161. }
  1162. static void mlx4_ib_delete_counters_table(struct mlx4_ib_dev *ibdev,
  1163. struct mlx4_ib_counters *ctr_table)
  1164. {
  1165. struct counter_index *counter, *tmp_count;
  1166. mutex_lock(&ctr_table->mutex);
  1167. list_for_each_entry_safe(counter, tmp_count, &ctr_table->counters_list,
  1168. list) {
  1169. if (counter->allocated)
  1170. mlx4_counter_free(ibdev->dev, counter->index);
  1171. list_del(&counter->list);
  1172. kfree(counter);
  1173. }
  1174. mutex_unlock(&ctr_table->mutex);
  1175. }
  1176. int mlx4_ib_add_mc(struct mlx4_ib_dev *mdev, struct mlx4_ib_qp *mqp,
  1177. union ib_gid *gid)
  1178. {
  1179. struct net_device *ndev;
  1180. int ret = 0;
  1181. if (!mqp->port)
  1182. return 0;
  1183. spin_lock_bh(&mdev->iboe.lock);
  1184. ndev = mdev->iboe.netdevs[mqp->port - 1];
  1185. if (ndev)
  1186. dev_hold(ndev);
  1187. spin_unlock_bh(&mdev->iboe.lock);
  1188. if (ndev) {
  1189. ret = 1;
  1190. dev_put(ndev);
  1191. }
  1192. return ret;
  1193. }
  1194. struct mlx4_ib_steering {
  1195. struct list_head list;
  1196. struct mlx4_flow_reg_id reg_id;
  1197. union ib_gid gid;
  1198. };
  1199. #define LAST_ETH_FIELD vlan_tag
  1200. #define LAST_IB_FIELD sl
  1201. #define LAST_IPV4_FIELD dst_ip
  1202. #define LAST_TCP_UDP_FIELD src_port
  1203. /* Field is the last supported field */
  1204. #define FIELDS_NOT_SUPPORTED(filter, field)\
  1205. memchr_inv((void *)&filter.field +\
  1206. sizeof(filter.field), 0,\
  1207. sizeof(filter) -\
  1208. offsetof(typeof(filter), field) -\
  1209. sizeof(filter.field))
  1210. static int parse_flow_attr(struct mlx4_dev *dev,
  1211. u32 qp_num,
  1212. union ib_flow_spec *ib_spec,
  1213. struct _rule_hw *mlx4_spec)
  1214. {
  1215. enum mlx4_net_trans_rule_id type;
  1216. switch (ib_spec->type) {
  1217. case IB_FLOW_SPEC_ETH:
  1218. if (FIELDS_NOT_SUPPORTED(ib_spec->eth.mask, LAST_ETH_FIELD))
  1219. return -ENOTSUPP;
  1220. type = MLX4_NET_TRANS_RULE_ID_ETH;
  1221. memcpy(mlx4_spec->eth.dst_mac, ib_spec->eth.val.dst_mac,
  1222. ETH_ALEN);
  1223. memcpy(mlx4_spec->eth.dst_mac_msk, ib_spec->eth.mask.dst_mac,
  1224. ETH_ALEN);
  1225. mlx4_spec->eth.vlan_tag = ib_spec->eth.val.vlan_tag;
  1226. mlx4_spec->eth.vlan_tag_msk = ib_spec->eth.mask.vlan_tag;
  1227. break;
  1228. case IB_FLOW_SPEC_IB:
  1229. if (FIELDS_NOT_SUPPORTED(ib_spec->ib.mask, LAST_IB_FIELD))
  1230. return -ENOTSUPP;
  1231. type = MLX4_NET_TRANS_RULE_ID_IB;
  1232. mlx4_spec->ib.l3_qpn =
  1233. cpu_to_be32(qp_num);
  1234. mlx4_spec->ib.qpn_mask =
  1235. cpu_to_be32(MLX4_IB_FLOW_QPN_MASK);
  1236. break;
  1237. case IB_FLOW_SPEC_IPV4:
  1238. if (FIELDS_NOT_SUPPORTED(ib_spec->ipv4.mask, LAST_IPV4_FIELD))
  1239. return -ENOTSUPP;
  1240. type = MLX4_NET_TRANS_RULE_ID_IPV4;
  1241. mlx4_spec->ipv4.src_ip = ib_spec->ipv4.val.src_ip;
  1242. mlx4_spec->ipv4.src_ip_msk = ib_spec->ipv4.mask.src_ip;
  1243. mlx4_spec->ipv4.dst_ip = ib_spec->ipv4.val.dst_ip;
  1244. mlx4_spec->ipv4.dst_ip_msk = ib_spec->ipv4.mask.dst_ip;
  1245. break;
  1246. case IB_FLOW_SPEC_TCP:
  1247. case IB_FLOW_SPEC_UDP:
  1248. if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask, LAST_TCP_UDP_FIELD))
  1249. return -ENOTSUPP;
  1250. type = ib_spec->type == IB_FLOW_SPEC_TCP ?
  1251. MLX4_NET_TRANS_RULE_ID_TCP :
  1252. MLX4_NET_TRANS_RULE_ID_UDP;
  1253. mlx4_spec->tcp_udp.dst_port = ib_spec->tcp_udp.val.dst_port;
  1254. mlx4_spec->tcp_udp.dst_port_msk = ib_spec->tcp_udp.mask.dst_port;
  1255. mlx4_spec->tcp_udp.src_port = ib_spec->tcp_udp.val.src_port;
  1256. mlx4_spec->tcp_udp.src_port_msk = ib_spec->tcp_udp.mask.src_port;
  1257. break;
  1258. default:
  1259. return -EINVAL;
  1260. }
  1261. if (mlx4_map_sw_to_hw_steering_id(dev, type) < 0 ||
  1262. mlx4_hw_rule_sz(dev, type) < 0)
  1263. return -EINVAL;
  1264. mlx4_spec->id = cpu_to_be16(mlx4_map_sw_to_hw_steering_id(dev, type));
  1265. mlx4_spec->size = mlx4_hw_rule_sz(dev, type) >> 2;
  1266. return mlx4_hw_rule_sz(dev, type);
  1267. }
  1268. struct default_rules {
  1269. __u32 mandatory_fields[IB_FLOW_SPEC_SUPPORT_LAYERS];
  1270. __u32 mandatory_not_fields[IB_FLOW_SPEC_SUPPORT_LAYERS];
  1271. __u32 rules_create_list[IB_FLOW_SPEC_SUPPORT_LAYERS];
  1272. __u8 link_layer;
  1273. };
  1274. static const struct default_rules default_table[] = {
  1275. {
  1276. .mandatory_fields = {IB_FLOW_SPEC_IPV4},
  1277. .mandatory_not_fields = {IB_FLOW_SPEC_ETH},
  1278. .rules_create_list = {IB_FLOW_SPEC_IB},
  1279. .link_layer = IB_LINK_LAYER_INFINIBAND
  1280. }
  1281. };
  1282. static int __mlx4_ib_default_rules_match(struct ib_qp *qp,
  1283. struct ib_flow_attr *flow_attr)
  1284. {
  1285. int i, j, k;
  1286. void *ib_flow;
  1287. const struct default_rules *pdefault_rules = default_table;
  1288. u8 link_layer = rdma_port_get_link_layer(qp->device, flow_attr->port);
  1289. for (i = 0; i < ARRAY_SIZE(default_table); i++, pdefault_rules++) {
  1290. __u32 field_types[IB_FLOW_SPEC_SUPPORT_LAYERS];
  1291. memset(&field_types, 0, sizeof(field_types));
  1292. if (link_layer != pdefault_rules->link_layer)
  1293. continue;
  1294. ib_flow = flow_attr + 1;
  1295. /* we assume the specs are sorted */
  1296. for (j = 0, k = 0; k < IB_FLOW_SPEC_SUPPORT_LAYERS &&
  1297. j < flow_attr->num_of_specs; k++) {
  1298. union ib_flow_spec *current_flow =
  1299. (union ib_flow_spec *)ib_flow;
  1300. /* same layer but different type */
  1301. if (((current_flow->type & IB_FLOW_SPEC_LAYER_MASK) ==
  1302. (pdefault_rules->mandatory_fields[k] &
  1303. IB_FLOW_SPEC_LAYER_MASK)) &&
  1304. (current_flow->type !=
  1305. pdefault_rules->mandatory_fields[k]))
  1306. goto out;
  1307. /* same layer, try match next one */
  1308. if (current_flow->type ==
  1309. pdefault_rules->mandatory_fields[k]) {
  1310. j++;
  1311. ib_flow +=
  1312. ((union ib_flow_spec *)ib_flow)->size;
  1313. }
  1314. }
  1315. ib_flow = flow_attr + 1;
  1316. for (j = 0; j < flow_attr->num_of_specs;
  1317. j++, ib_flow += ((union ib_flow_spec *)ib_flow)->size)
  1318. for (k = 0; k < IB_FLOW_SPEC_SUPPORT_LAYERS; k++)
  1319. /* same layer and same type */
  1320. if (((union ib_flow_spec *)ib_flow)->type ==
  1321. pdefault_rules->mandatory_not_fields[k])
  1322. goto out;
  1323. return i;
  1324. }
  1325. out:
  1326. return -1;
  1327. }
  1328. static int __mlx4_ib_create_default_rules(
  1329. struct mlx4_ib_dev *mdev,
  1330. struct ib_qp *qp,
  1331. const struct default_rules *pdefault_rules,
  1332. struct _rule_hw *mlx4_spec) {
  1333. int size = 0;
  1334. int i;
  1335. for (i = 0; i < ARRAY_SIZE(pdefault_rules->rules_create_list); i++) {
  1336. int ret;
  1337. union ib_flow_spec ib_spec;
  1338. switch (pdefault_rules->rules_create_list[i]) {
  1339. case 0:
  1340. /* no rule */
  1341. continue;
  1342. case IB_FLOW_SPEC_IB:
  1343. ib_spec.type = IB_FLOW_SPEC_IB;
  1344. ib_spec.size = sizeof(struct ib_flow_spec_ib);
  1345. break;
  1346. default:
  1347. /* invalid rule */
  1348. return -EINVAL;
  1349. }
  1350. /* We must put empty rule, qpn is being ignored */
  1351. ret = parse_flow_attr(mdev->dev, 0, &ib_spec,
  1352. mlx4_spec);
  1353. if (ret < 0) {
  1354. pr_info("invalid parsing\n");
  1355. return -EINVAL;
  1356. }
  1357. mlx4_spec = (void *)mlx4_spec + ret;
  1358. size += ret;
  1359. }
  1360. return size;
  1361. }
  1362. static int __mlx4_ib_create_flow(struct ib_qp *qp, struct ib_flow_attr *flow_attr,
  1363. int domain,
  1364. enum mlx4_net_trans_promisc_mode flow_type,
  1365. u64 *reg_id)
  1366. {
  1367. int ret, i;
  1368. int size = 0;
  1369. void *ib_flow;
  1370. struct mlx4_ib_dev *mdev = to_mdev(qp->device);
  1371. struct mlx4_cmd_mailbox *mailbox;
  1372. struct mlx4_net_trans_rule_hw_ctrl *ctrl;
  1373. int default_flow;
  1374. static const u16 __mlx4_domain[] = {
  1375. [IB_FLOW_DOMAIN_USER] = MLX4_DOMAIN_UVERBS,
  1376. [IB_FLOW_DOMAIN_ETHTOOL] = MLX4_DOMAIN_ETHTOOL,
  1377. [IB_FLOW_DOMAIN_RFS] = MLX4_DOMAIN_RFS,
  1378. [IB_FLOW_DOMAIN_NIC] = MLX4_DOMAIN_NIC,
  1379. };
  1380. if (flow_attr->priority > MLX4_IB_FLOW_MAX_PRIO) {
  1381. pr_err("Invalid priority value %d\n", flow_attr->priority);
  1382. return -EINVAL;
  1383. }
  1384. if (domain >= IB_FLOW_DOMAIN_NUM) {
  1385. pr_err("Invalid domain value %d\n", domain);
  1386. return -EINVAL;
  1387. }
  1388. if (mlx4_map_sw_to_hw_steering_mode(mdev->dev, flow_type) < 0)
  1389. return -EINVAL;
  1390. mailbox = mlx4_alloc_cmd_mailbox(mdev->dev);
  1391. if (IS_ERR(mailbox))
  1392. return PTR_ERR(mailbox);
  1393. ctrl = mailbox->buf;
  1394. ctrl->prio = cpu_to_be16(__mlx4_domain[domain] |
  1395. flow_attr->priority);
  1396. ctrl->type = mlx4_map_sw_to_hw_steering_mode(mdev->dev, flow_type);
  1397. ctrl->port = flow_attr->port;
  1398. ctrl->qpn = cpu_to_be32(qp->qp_num);
  1399. ib_flow = flow_attr + 1;
  1400. size += sizeof(struct mlx4_net_trans_rule_hw_ctrl);
  1401. /* Add default flows */
  1402. default_flow = __mlx4_ib_default_rules_match(qp, flow_attr);
  1403. if (default_flow >= 0) {
  1404. ret = __mlx4_ib_create_default_rules(
  1405. mdev, qp, default_table + default_flow,
  1406. mailbox->buf + size);
  1407. if (ret < 0) {
  1408. mlx4_free_cmd_mailbox(mdev->dev, mailbox);
  1409. return -EINVAL;
  1410. }
  1411. size += ret;
  1412. }
  1413. for (i = 0; i < flow_attr->num_of_specs; i++) {
  1414. ret = parse_flow_attr(mdev->dev, qp->qp_num, ib_flow,
  1415. mailbox->buf + size);
  1416. if (ret < 0) {
  1417. mlx4_free_cmd_mailbox(mdev->dev, mailbox);
  1418. return -EINVAL;
  1419. }
  1420. ib_flow += ((union ib_flow_spec *) ib_flow)->size;
  1421. size += ret;
  1422. }
  1423. if (mlx4_is_master(mdev->dev) && flow_type == MLX4_FS_REGULAR &&
  1424. flow_attr->num_of_specs == 1) {
  1425. struct _rule_hw *rule_header = (struct _rule_hw *)(ctrl + 1);
  1426. enum ib_flow_spec_type header_spec =
  1427. ((union ib_flow_spec *)(flow_attr + 1))->type;
  1428. if (header_spec == IB_FLOW_SPEC_ETH)
  1429. mlx4_handle_eth_header_mcast_prio(ctrl, rule_header);
  1430. }
  1431. ret = mlx4_cmd_imm(mdev->dev, mailbox->dma, reg_id, size >> 2, 0,
  1432. MLX4_QP_FLOW_STEERING_ATTACH, MLX4_CMD_TIME_CLASS_A,
  1433. MLX4_CMD_NATIVE);
  1434. if (ret == -ENOMEM)
  1435. pr_err("mcg table is full. Fail to register network rule.\n");
  1436. else if (ret == -ENXIO)
  1437. pr_err("Device managed flow steering is disabled. Fail to register network rule.\n");
  1438. else if (ret)
  1439. pr_err("Invalid argument. Fail to register network rule.\n");
  1440. mlx4_free_cmd_mailbox(mdev->dev, mailbox);
  1441. return ret;
  1442. }
  1443. static int __mlx4_ib_destroy_flow(struct mlx4_dev *dev, u64 reg_id)
  1444. {
  1445. int err;
  1446. err = mlx4_cmd(dev, reg_id, 0, 0,
  1447. MLX4_QP_FLOW_STEERING_DETACH, MLX4_CMD_TIME_CLASS_A,
  1448. MLX4_CMD_NATIVE);
  1449. if (err)
  1450. pr_err("Fail to detach network rule. registration id = 0x%llx\n",
  1451. reg_id);
  1452. return err;
  1453. }
  1454. static int mlx4_ib_tunnel_steer_add(struct ib_qp *qp, struct ib_flow_attr *flow_attr,
  1455. u64 *reg_id)
  1456. {
  1457. void *ib_flow;
  1458. union ib_flow_spec *ib_spec;
  1459. struct mlx4_dev *dev = to_mdev(qp->device)->dev;
  1460. int err = 0;
  1461. if (dev->caps.tunnel_offload_mode != MLX4_TUNNEL_OFFLOAD_MODE_VXLAN ||
  1462. dev->caps.dmfs_high_steer_mode == MLX4_STEERING_DMFS_A0_STATIC)
  1463. return 0; /* do nothing */
  1464. ib_flow = flow_attr + 1;
  1465. ib_spec = (union ib_flow_spec *)ib_flow;
  1466. if (ib_spec->type != IB_FLOW_SPEC_ETH || flow_attr->num_of_specs != 1)
  1467. return 0; /* do nothing */
  1468. err = mlx4_tunnel_steer_add(to_mdev(qp->device)->dev, ib_spec->eth.val.dst_mac,
  1469. flow_attr->port, qp->qp_num,
  1470. MLX4_DOMAIN_UVERBS | (flow_attr->priority & 0xff),
  1471. reg_id);
  1472. return err;
  1473. }
  1474. static int mlx4_ib_add_dont_trap_rule(struct mlx4_dev *dev,
  1475. struct ib_flow_attr *flow_attr,
  1476. enum mlx4_net_trans_promisc_mode *type)
  1477. {
  1478. int err = 0;
  1479. if (!(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_DMFS_UC_MC_SNIFFER) ||
  1480. (dev->caps.dmfs_high_steer_mode == MLX4_STEERING_DMFS_A0_STATIC) ||
  1481. (flow_attr->num_of_specs > 1) || (flow_attr->priority != 0)) {
  1482. return -EOPNOTSUPP;
  1483. }
  1484. if (flow_attr->num_of_specs == 0) {
  1485. type[0] = MLX4_FS_MC_SNIFFER;
  1486. type[1] = MLX4_FS_UC_SNIFFER;
  1487. } else {
  1488. union ib_flow_spec *ib_spec;
  1489. ib_spec = (union ib_flow_spec *)(flow_attr + 1);
  1490. if (ib_spec->type != IB_FLOW_SPEC_ETH)
  1491. return -EINVAL;
  1492. /* if all is zero than MC and UC */
  1493. if (is_zero_ether_addr(ib_spec->eth.mask.dst_mac)) {
  1494. type[0] = MLX4_FS_MC_SNIFFER;
  1495. type[1] = MLX4_FS_UC_SNIFFER;
  1496. } else {
  1497. u8 mac[ETH_ALEN] = {ib_spec->eth.mask.dst_mac[0] ^ 0x01,
  1498. ib_spec->eth.mask.dst_mac[1],
  1499. ib_spec->eth.mask.dst_mac[2],
  1500. ib_spec->eth.mask.dst_mac[3],
  1501. ib_spec->eth.mask.dst_mac[4],
  1502. ib_spec->eth.mask.dst_mac[5]};
  1503. /* Above xor was only on MC bit, non empty mask is valid
  1504. * only if this bit is set and rest are zero.
  1505. */
  1506. if (!is_zero_ether_addr(&mac[0]))
  1507. return -EINVAL;
  1508. if (is_multicast_ether_addr(ib_spec->eth.val.dst_mac))
  1509. type[0] = MLX4_FS_MC_SNIFFER;
  1510. else
  1511. type[0] = MLX4_FS_UC_SNIFFER;
  1512. }
  1513. }
  1514. return err;
  1515. }
  1516. static struct ib_flow *mlx4_ib_create_flow(struct ib_qp *qp,
  1517. struct ib_flow_attr *flow_attr,
  1518. int domain, struct ib_udata *udata)
  1519. {
  1520. int err = 0, i = 0, j = 0;
  1521. struct mlx4_ib_flow *mflow;
  1522. enum mlx4_net_trans_promisc_mode type[2];
  1523. struct mlx4_dev *dev = (to_mdev(qp->device))->dev;
  1524. int is_bonded = mlx4_is_bonded(dev);
  1525. if (flow_attr->port < 1 || flow_attr->port > qp->device->phys_port_cnt)
  1526. return ERR_PTR(-EINVAL);
  1527. if (flow_attr->flags & ~IB_FLOW_ATTR_FLAGS_DONT_TRAP)
  1528. return ERR_PTR(-EOPNOTSUPP);
  1529. if ((flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP) &&
  1530. (flow_attr->type != IB_FLOW_ATTR_NORMAL))
  1531. return ERR_PTR(-EOPNOTSUPP);
  1532. if (udata &&
  1533. udata->inlen && !ib_is_udata_cleared(udata, 0, udata->inlen))
  1534. return ERR_PTR(-EOPNOTSUPP);
  1535. memset(type, 0, sizeof(type));
  1536. mflow = kzalloc(sizeof(*mflow), GFP_KERNEL);
  1537. if (!mflow) {
  1538. err = -ENOMEM;
  1539. goto err_free;
  1540. }
  1541. switch (flow_attr->type) {
  1542. case IB_FLOW_ATTR_NORMAL:
  1543. /* If dont trap flag (continue match) is set, under specific
  1544. * condition traffic be replicated to given qp,
  1545. * without stealing it
  1546. */
  1547. if (unlikely(flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP)) {
  1548. err = mlx4_ib_add_dont_trap_rule(dev,
  1549. flow_attr,
  1550. type);
  1551. if (err)
  1552. goto err_free;
  1553. } else {
  1554. type[0] = MLX4_FS_REGULAR;
  1555. }
  1556. break;
  1557. case IB_FLOW_ATTR_ALL_DEFAULT:
  1558. type[0] = MLX4_FS_ALL_DEFAULT;
  1559. break;
  1560. case IB_FLOW_ATTR_MC_DEFAULT:
  1561. type[0] = MLX4_FS_MC_DEFAULT;
  1562. break;
  1563. case IB_FLOW_ATTR_SNIFFER:
  1564. type[0] = MLX4_FS_MIRROR_RX_PORT;
  1565. type[1] = MLX4_FS_MIRROR_SX_PORT;
  1566. break;
  1567. default:
  1568. err = -EINVAL;
  1569. goto err_free;
  1570. }
  1571. while (i < ARRAY_SIZE(type) && type[i]) {
  1572. err = __mlx4_ib_create_flow(qp, flow_attr, domain, type[i],
  1573. &mflow->reg_id[i].id);
  1574. if (err)
  1575. goto err_create_flow;
  1576. if (is_bonded) {
  1577. /* Application always sees one port so the mirror rule
  1578. * must be on port #2
  1579. */
  1580. flow_attr->port = 2;
  1581. err = __mlx4_ib_create_flow(qp, flow_attr,
  1582. domain, type[j],
  1583. &mflow->reg_id[j].mirror);
  1584. flow_attr->port = 1;
  1585. if (err)
  1586. goto err_create_flow;
  1587. j++;
  1588. }
  1589. i++;
  1590. }
  1591. if (i < ARRAY_SIZE(type) && flow_attr->type == IB_FLOW_ATTR_NORMAL) {
  1592. err = mlx4_ib_tunnel_steer_add(qp, flow_attr,
  1593. &mflow->reg_id[i].id);
  1594. if (err)
  1595. goto err_create_flow;
  1596. if (is_bonded) {
  1597. flow_attr->port = 2;
  1598. err = mlx4_ib_tunnel_steer_add(qp, flow_attr,
  1599. &mflow->reg_id[j].mirror);
  1600. flow_attr->port = 1;
  1601. if (err)
  1602. goto err_create_flow;
  1603. j++;
  1604. }
  1605. /* function to create mirror rule */
  1606. i++;
  1607. }
  1608. return &mflow->ibflow;
  1609. err_create_flow:
  1610. while (i) {
  1611. (void)__mlx4_ib_destroy_flow(to_mdev(qp->device)->dev,
  1612. mflow->reg_id[i].id);
  1613. i--;
  1614. }
  1615. while (j) {
  1616. (void)__mlx4_ib_destroy_flow(to_mdev(qp->device)->dev,
  1617. mflow->reg_id[j].mirror);
  1618. j--;
  1619. }
  1620. err_free:
  1621. kfree(mflow);
  1622. return ERR_PTR(err);
  1623. }
  1624. static int mlx4_ib_destroy_flow(struct ib_flow *flow_id)
  1625. {
  1626. int err, ret = 0;
  1627. int i = 0;
  1628. struct mlx4_ib_dev *mdev = to_mdev(flow_id->qp->device);
  1629. struct mlx4_ib_flow *mflow = to_mflow(flow_id);
  1630. while (i < ARRAY_SIZE(mflow->reg_id) && mflow->reg_id[i].id) {
  1631. err = __mlx4_ib_destroy_flow(mdev->dev, mflow->reg_id[i].id);
  1632. if (err)
  1633. ret = err;
  1634. if (mflow->reg_id[i].mirror) {
  1635. err = __mlx4_ib_destroy_flow(mdev->dev,
  1636. mflow->reg_id[i].mirror);
  1637. if (err)
  1638. ret = err;
  1639. }
  1640. i++;
  1641. }
  1642. kfree(mflow);
  1643. return ret;
  1644. }
  1645. static int mlx4_ib_mcg_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
  1646. {
  1647. int err;
  1648. struct mlx4_ib_dev *mdev = to_mdev(ibqp->device);
  1649. struct mlx4_dev *dev = mdev->dev;
  1650. struct mlx4_ib_qp *mqp = to_mqp(ibqp);
  1651. struct mlx4_ib_steering *ib_steering = NULL;
  1652. enum mlx4_protocol prot = MLX4_PROT_IB_IPV6;
  1653. struct mlx4_flow_reg_id reg_id;
  1654. if (mdev->dev->caps.steering_mode ==
  1655. MLX4_STEERING_MODE_DEVICE_MANAGED) {
  1656. ib_steering = kmalloc(sizeof(*ib_steering), GFP_KERNEL);
  1657. if (!ib_steering)
  1658. return -ENOMEM;
  1659. }
  1660. err = mlx4_multicast_attach(mdev->dev, &mqp->mqp, gid->raw, mqp->port,
  1661. !!(mqp->flags &
  1662. MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK),
  1663. prot, &reg_id.id);
  1664. if (err) {
  1665. pr_err("multicast attach op failed, err %d\n", err);
  1666. goto err_malloc;
  1667. }
  1668. reg_id.mirror = 0;
  1669. if (mlx4_is_bonded(dev)) {
  1670. err = mlx4_multicast_attach(mdev->dev, &mqp->mqp, gid->raw,
  1671. (mqp->port == 1) ? 2 : 1,
  1672. !!(mqp->flags &
  1673. MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK),
  1674. prot, &reg_id.mirror);
  1675. if (err)
  1676. goto err_add;
  1677. }
  1678. err = add_gid_entry(ibqp, gid);
  1679. if (err)
  1680. goto err_add;
  1681. if (ib_steering) {
  1682. memcpy(ib_steering->gid.raw, gid->raw, 16);
  1683. ib_steering->reg_id = reg_id;
  1684. mutex_lock(&mqp->mutex);
  1685. list_add(&ib_steering->list, &mqp->steering_rules);
  1686. mutex_unlock(&mqp->mutex);
  1687. }
  1688. return 0;
  1689. err_add:
  1690. mlx4_multicast_detach(mdev->dev, &mqp->mqp, gid->raw,
  1691. prot, reg_id.id);
  1692. if (reg_id.mirror)
  1693. mlx4_multicast_detach(mdev->dev, &mqp->mqp, gid->raw,
  1694. prot, reg_id.mirror);
  1695. err_malloc:
  1696. kfree(ib_steering);
  1697. return err;
  1698. }
  1699. static struct mlx4_ib_gid_entry *find_gid_entry(struct mlx4_ib_qp *qp, u8 *raw)
  1700. {
  1701. struct mlx4_ib_gid_entry *ge;
  1702. struct mlx4_ib_gid_entry *tmp;
  1703. struct mlx4_ib_gid_entry *ret = NULL;
  1704. list_for_each_entry_safe(ge, tmp, &qp->gid_list, list) {
  1705. if (!memcmp(raw, ge->gid.raw, 16)) {
  1706. ret = ge;
  1707. break;
  1708. }
  1709. }
  1710. return ret;
  1711. }
  1712. static int mlx4_ib_mcg_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
  1713. {
  1714. int err;
  1715. struct mlx4_ib_dev *mdev = to_mdev(ibqp->device);
  1716. struct mlx4_dev *dev = mdev->dev;
  1717. struct mlx4_ib_qp *mqp = to_mqp(ibqp);
  1718. struct net_device *ndev;
  1719. struct mlx4_ib_gid_entry *ge;
  1720. struct mlx4_flow_reg_id reg_id = {0, 0};
  1721. enum mlx4_protocol prot = MLX4_PROT_IB_IPV6;
  1722. if (mdev->dev->caps.steering_mode ==
  1723. MLX4_STEERING_MODE_DEVICE_MANAGED) {
  1724. struct mlx4_ib_steering *ib_steering;
  1725. mutex_lock(&mqp->mutex);
  1726. list_for_each_entry(ib_steering, &mqp->steering_rules, list) {
  1727. if (!memcmp(ib_steering->gid.raw, gid->raw, 16)) {
  1728. list_del(&ib_steering->list);
  1729. break;
  1730. }
  1731. }
  1732. mutex_unlock(&mqp->mutex);
  1733. if (&ib_steering->list == &mqp->steering_rules) {
  1734. pr_err("Couldn't find reg_id for mgid. Steering rule is left attached\n");
  1735. return -EINVAL;
  1736. }
  1737. reg_id = ib_steering->reg_id;
  1738. kfree(ib_steering);
  1739. }
  1740. err = mlx4_multicast_detach(mdev->dev, &mqp->mqp, gid->raw,
  1741. prot, reg_id.id);
  1742. if (err)
  1743. return err;
  1744. if (mlx4_is_bonded(dev)) {
  1745. err = mlx4_multicast_detach(mdev->dev, &mqp->mqp, gid->raw,
  1746. prot, reg_id.mirror);
  1747. if (err)
  1748. return err;
  1749. }
  1750. mutex_lock(&mqp->mutex);
  1751. ge = find_gid_entry(mqp, gid->raw);
  1752. if (ge) {
  1753. spin_lock_bh(&mdev->iboe.lock);
  1754. ndev = ge->added ? mdev->iboe.netdevs[ge->port - 1] : NULL;
  1755. if (ndev)
  1756. dev_hold(ndev);
  1757. spin_unlock_bh(&mdev->iboe.lock);
  1758. if (ndev)
  1759. dev_put(ndev);
  1760. list_del(&ge->list);
  1761. kfree(ge);
  1762. } else
  1763. pr_warn("could not find mgid entry\n");
  1764. mutex_unlock(&mqp->mutex);
  1765. return 0;
  1766. }
  1767. static int init_node_data(struct mlx4_ib_dev *dev)
  1768. {
  1769. struct ib_smp *in_mad = NULL;
  1770. struct ib_smp *out_mad = NULL;
  1771. int mad_ifc_flags = MLX4_MAD_IFC_IGNORE_KEYS;
  1772. int err = -ENOMEM;
  1773. in_mad = kzalloc(sizeof *in_mad, GFP_KERNEL);
  1774. out_mad = kmalloc(sizeof *out_mad, GFP_KERNEL);
  1775. if (!in_mad || !out_mad)
  1776. goto out;
  1777. init_query_mad(in_mad);
  1778. in_mad->attr_id = IB_SMP_ATTR_NODE_DESC;
  1779. if (mlx4_is_master(dev->dev))
  1780. mad_ifc_flags |= MLX4_MAD_IFC_NET_VIEW;
  1781. err = mlx4_MAD_IFC(dev, mad_ifc_flags, 1, NULL, NULL, in_mad, out_mad);
  1782. if (err)
  1783. goto out;
  1784. memcpy(dev->ib_dev.node_desc, out_mad->data, IB_DEVICE_NODE_DESC_MAX);
  1785. in_mad->attr_id = IB_SMP_ATTR_NODE_INFO;
  1786. err = mlx4_MAD_IFC(dev, mad_ifc_flags, 1, NULL, NULL, in_mad, out_mad);
  1787. if (err)
  1788. goto out;
  1789. dev->dev->rev_id = be32_to_cpup((__be32 *) (out_mad->data + 32));
  1790. memcpy(&dev->ib_dev.node_guid, out_mad->data + 12, 8);
  1791. out:
  1792. kfree(in_mad);
  1793. kfree(out_mad);
  1794. return err;
  1795. }
  1796. static ssize_t show_hca(struct device *device, struct device_attribute *attr,
  1797. char *buf)
  1798. {
  1799. struct mlx4_ib_dev *dev =
  1800. container_of(device, struct mlx4_ib_dev, ib_dev.dev);
  1801. return sprintf(buf, "MT%d\n", dev->dev->persist->pdev->device);
  1802. }
  1803. static ssize_t show_rev(struct device *device, struct device_attribute *attr,
  1804. char *buf)
  1805. {
  1806. struct mlx4_ib_dev *dev =
  1807. container_of(device, struct mlx4_ib_dev, ib_dev.dev);
  1808. return sprintf(buf, "%x\n", dev->dev->rev_id);
  1809. }
  1810. static ssize_t show_board(struct device *device, struct device_attribute *attr,
  1811. char *buf)
  1812. {
  1813. struct mlx4_ib_dev *dev =
  1814. container_of(device, struct mlx4_ib_dev, ib_dev.dev);
  1815. return sprintf(buf, "%.*s\n", MLX4_BOARD_ID_LEN,
  1816. dev->dev->board_id);
  1817. }
  1818. static DEVICE_ATTR(hw_rev, S_IRUGO, show_rev, NULL);
  1819. static DEVICE_ATTR(hca_type, S_IRUGO, show_hca, NULL);
  1820. static DEVICE_ATTR(board_id, S_IRUGO, show_board, NULL);
  1821. static struct device_attribute *mlx4_class_attributes[] = {
  1822. &dev_attr_hw_rev,
  1823. &dev_attr_hca_type,
  1824. &dev_attr_board_id
  1825. };
  1826. struct diag_counter {
  1827. const char *name;
  1828. u32 offset;
  1829. };
  1830. #define DIAG_COUNTER(_name, _offset) \
  1831. { .name = #_name, .offset = _offset }
  1832. static const struct diag_counter diag_basic[] = {
  1833. DIAG_COUNTER(rq_num_lle, 0x00),
  1834. DIAG_COUNTER(sq_num_lle, 0x04),
  1835. DIAG_COUNTER(rq_num_lqpoe, 0x08),
  1836. DIAG_COUNTER(sq_num_lqpoe, 0x0C),
  1837. DIAG_COUNTER(rq_num_lpe, 0x18),
  1838. DIAG_COUNTER(sq_num_lpe, 0x1C),
  1839. DIAG_COUNTER(rq_num_wrfe, 0x20),
  1840. DIAG_COUNTER(sq_num_wrfe, 0x24),
  1841. DIAG_COUNTER(sq_num_mwbe, 0x2C),
  1842. DIAG_COUNTER(sq_num_bre, 0x34),
  1843. DIAG_COUNTER(sq_num_rire, 0x44),
  1844. DIAG_COUNTER(rq_num_rire, 0x48),
  1845. DIAG_COUNTER(sq_num_rae, 0x4C),
  1846. DIAG_COUNTER(rq_num_rae, 0x50),
  1847. DIAG_COUNTER(sq_num_roe, 0x54),
  1848. DIAG_COUNTER(sq_num_tree, 0x5C),
  1849. DIAG_COUNTER(sq_num_rree, 0x64),
  1850. DIAG_COUNTER(rq_num_rnr, 0x68),
  1851. DIAG_COUNTER(sq_num_rnr, 0x6C),
  1852. DIAG_COUNTER(rq_num_oos, 0x100),
  1853. DIAG_COUNTER(sq_num_oos, 0x104),
  1854. };
  1855. static const struct diag_counter diag_ext[] = {
  1856. DIAG_COUNTER(rq_num_dup, 0x130),
  1857. DIAG_COUNTER(sq_num_to, 0x134),
  1858. };
  1859. static const struct diag_counter diag_device_only[] = {
  1860. DIAG_COUNTER(num_cqovf, 0x1A0),
  1861. DIAG_COUNTER(rq_num_udsdprd, 0x118),
  1862. };
  1863. static struct rdma_hw_stats *mlx4_ib_alloc_hw_stats(struct ib_device *ibdev,
  1864. u8 port_num)
  1865. {
  1866. struct mlx4_ib_dev *dev = to_mdev(ibdev);
  1867. struct mlx4_ib_diag_counters *diag = dev->diag_counters;
  1868. if (!diag[!!port_num].name)
  1869. return NULL;
  1870. return rdma_alloc_hw_stats_struct(diag[!!port_num].name,
  1871. diag[!!port_num].num_counters,
  1872. RDMA_HW_STATS_DEFAULT_LIFESPAN);
  1873. }
  1874. static int mlx4_ib_get_hw_stats(struct ib_device *ibdev,
  1875. struct rdma_hw_stats *stats,
  1876. u8 port, int index)
  1877. {
  1878. struct mlx4_ib_dev *dev = to_mdev(ibdev);
  1879. struct mlx4_ib_diag_counters *diag = dev->diag_counters;
  1880. u32 hw_value[ARRAY_SIZE(diag_device_only) +
  1881. ARRAY_SIZE(diag_ext) + ARRAY_SIZE(diag_basic)] = {};
  1882. int ret;
  1883. int i;
  1884. ret = mlx4_query_diag_counters(dev->dev,
  1885. MLX4_OP_MOD_QUERY_TRANSPORT_CI_ERRORS,
  1886. diag[!!port].offset, hw_value,
  1887. diag[!!port].num_counters, port);
  1888. if (ret)
  1889. return ret;
  1890. for (i = 0; i < diag[!!port].num_counters; i++)
  1891. stats->value[i] = hw_value[i];
  1892. return diag[!!port].num_counters;
  1893. }
  1894. static int __mlx4_ib_alloc_diag_counters(struct mlx4_ib_dev *ibdev,
  1895. const char ***name,
  1896. u32 **offset,
  1897. u32 *num,
  1898. bool port)
  1899. {
  1900. u32 num_counters;
  1901. num_counters = ARRAY_SIZE(diag_basic);
  1902. if (ibdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_DIAG_PER_PORT)
  1903. num_counters += ARRAY_SIZE(diag_ext);
  1904. if (!port)
  1905. num_counters += ARRAY_SIZE(diag_device_only);
  1906. *name = kcalloc(num_counters, sizeof(**name), GFP_KERNEL);
  1907. if (!*name)
  1908. return -ENOMEM;
  1909. *offset = kcalloc(num_counters, sizeof(**offset), GFP_KERNEL);
  1910. if (!*offset)
  1911. goto err_name;
  1912. *num = num_counters;
  1913. return 0;
  1914. err_name:
  1915. kfree(*name);
  1916. return -ENOMEM;
  1917. }
  1918. static void mlx4_ib_fill_diag_counters(struct mlx4_ib_dev *ibdev,
  1919. const char **name,
  1920. u32 *offset,
  1921. bool port)
  1922. {
  1923. int i;
  1924. int j;
  1925. for (i = 0, j = 0; i < ARRAY_SIZE(diag_basic); i++, j++) {
  1926. name[i] = diag_basic[i].name;
  1927. offset[i] = diag_basic[i].offset;
  1928. }
  1929. if (ibdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_DIAG_PER_PORT) {
  1930. for (i = 0; i < ARRAY_SIZE(diag_ext); i++, j++) {
  1931. name[j] = diag_ext[i].name;
  1932. offset[j] = diag_ext[i].offset;
  1933. }
  1934. }
  1935. if (!port) {
  1936. for (i = 0; i < ARRAY_SIZE(diag_device_only); i++, j++) {
  1937. name[j] = diag_device_only[i].name;
  1938. offset[j] = diag_device_only[i].offset;
  1939. }
  1940. }
  1941. }
  1942. static int mlx4_ib_alloc_diag_counters(struct mlx4_ib_dev *ibdev)
  1943. {
  1944. struct mlx4_ib_diag_counters *diag = ibdev->diag_counters;
  1945. int i;
  1946. int ret;
  1947. bool per_port = !!(ibdev->dev->caps.flags2 &
  1948. MLX4_DEV_CAP_FLAG2_DIAG_PER_PORT);
  1949. if (mlx4_is_slave(ibdev->dev))
  1950. return 0;
  1951. for (i = 0; i < MLX4_DIAG_COUNTERS_TYPES; i++) {
  1952. /* i == 1 means we are building port counters */
  1953. if (i && !per_port)
  1954. continue;
  1955. ret = __mlx4_ib_alloc_diag_counters(ibdev, &diag[i].name,
  1956. &diag[i].offset,
  1957. &diag[i].num_counters, i);
  1958. if (ret)
  1959. goto err_alloc;
  1960. mlx4_ib_fill_diag_counters(ibdev, diag[i].name,
  1961. diag[i].offset, i);
  1962. }
  1963. ibdev->ib_dev.get_hw_stats = mlx4_ib_get_hw_stats;
  1964. ibdev->ib_dev.alloc_hw_stats = mlx4_ib_alloc_hw_stats;
  1965. return 0;
  1966. err_alloc:
  1967. if (i) {
  1968. kfree(diag[i - 1].name);
  1969. kfree(diag[i - 1].offset);
  1970. }
  1971. return ret;
  1972. }
  1973. static void mlx4_ib_diag_cleanup(struct mlx4_ib_dev *ibdev)
  1974. {
  1975. int i;
  1976. for (i = 0; i < MLX4_DIAG_COUNTERS_TYPES; i++) {
  1977. kfree(ibdev->diag_counters[i].offset);
  1978. kfree(ibdev->diag_counters[i].name);
  1979. }
  1980. }
  1981. #define MLX4_IB_INVALID_MAC ((u64)-1)
  1982. static void mlx4_ib_update_qps(struct mlx4_ib_dev *ibdev,
  1983. struct net_device *dev,
  1984. int port)
  1985. {
  1986. u64 new_smac = 0;
  1987. u64 release_mac = MLX4_IB_INVALID_MAC;
  1988. struct mlx4_ib_qp *qp;
  1989. read_lock(&dev_base_lock);
  1990. new_smac = mlx4_mac_to_u64(dev->dev_addr);
  1991. read_unlock(&dev_base_lock);
  1992. atomic64_set(&ibdev->iboe.mac[port - 1], new_smac);
  1993. /* no need for update QP1 and mac registration in non-SRIOV */
  1994. if (!mlx4_is_mfunc(ibdev->dev))
  1995. return;
  1996. mutex_lock(&ibdev->qp1_proxy_lock[port - 1]);
  1997. qp = ibdev->qp1_proxy[port - 1];
  1998. if (qp) {
  1999. int new_smac_index;
  2000. u64 old_smac;
  2001. struct mlx4_update_qp_params update_params;
  2002. mutex_lock(&qp->mutex);
  2003. old_smac = qp->pri.smac;
  2004. if (new_smac == old_smac)
  2005. goto unlock;
  2006. new_smac_index = mlx4_register_mac(ibdev->dev, port, new_smac);
  2007. if (new_smac_index < 0)
  2008. goto unlock;
  2009. update_params.smac_index = new_smac_index;
  2010. if (mlx4_update_qp(ibdev->dev, qp->mqp.qpn, MLX4_UPDATE_QP_SMAC,
  2011. &update_params)) {
  2012. release_mac = new_smac;
  2013. goto unlock;
  2014. }
  2015. /* if old port was zero, no mac was yet registered for this QP */
  2016. if (qp->pri.smac_port)
  2017. release_mac = old_smac;
  2018. qp->pri.smac = new_smac;
  2019. qp->pri.smac_port = port;
  2020. qp->pri.smac_index = new_smac_index;
  2021. }
  2022. unlock:
  2023. if (release_mac != MLX4_IB_INVALID_MAC)
  2024. mlx4_unregister_mac(ibdev->dev, port, release_mac);
  2025. if (qp)
  2026. mutex_unlock(&qp->mutex);
  2027. mutex_unlock(&ibdev->qp1_proxy_lock[port - 1]);
  2028. }
  2029. static void mlx4_ib_scan_netdevs(struct mlx4_ib_dev *ibdev,
  2030. struct net_device *dev,
  2031. unsigned long event)
  2032. {
  2033. struct mlx4_ib_iboe *iboe;
  2034. int update_qps_port = -1;
  2035. int port;
  2036. ASSERT_RTNL();
  2037. iboe = &ibdev->iboe;
  2038. spin_lock_bh(&iboe->lock);
  2039. mlx4_foreach_ib_transport_port(port, ibdev->dev) {
  2040. iboe->netdevs[port - 1] =
  2041. mlx4_get_protocol_dev(ibdev->dev, MLX4_PROT_ETH, port);
  2042. if (dev == iboe->netdevs[port - 1] &&
  2043. (event == NETDEV_CHANGEADDR || event == NETDEV_REGISTER ||
  2044. event == NETDEV_UP || event == NETDEV_CHANGE))
  2045. update_qps_port = port;
  2046. }
  2047. spin_unlock_bh(&iboe->lock);
  2048. if (update_qps_port > 0)
  2049. mlx4_ib_update_qps(ibdev, dev, update_qps_port);
  2050. }
  2051. static int mlx4_ib_netdev_event(struct notifier_block *this,
  2052. unsigned long event, void *ptr)
  2053. {
  2054. struct net_device *dev = netdev_notifier_info_to_dev(ptr);
  2055. struct mlx4_ib_dev *ibdev;
  2056. if (!net_eq(dev_net(dev), &init_net))
  2057. return NOTIFY_DONE;
  2058. ibdev = container_of(this, struct mlx4_ib_dev, iboe.nb);
  2059. mlx4_ib_scan_netdevs(ibdev, dev, event);
  2060. return NOTIFY_DONE;
  2061. }
  2062. static void init_pkeys(struct mlx4_ib_dev *ibdev)
  2063. {
  2064. int port;
  2065. int slave;
  2066. int i;
  2067. if (mlx4_is_master(ibdev->dev)) {
  2068. for (slave = 0; slave <= ibdev->dev->persist->num_vfs;
  2069. ++slave) {
  2070. for (port = 1; port <= ibdev->dev->caps.num_ports; ++port) {
  2071. for (i = 0;
  2072. i < ibdev->dev->phys_caps.pkey_phys_table_len[port];
  2073. ++i) {
  2074. ibdev->pkeys.virt2phys_pkey[slave][port - 1][i] =
  2075. /* master has the identity virt2phys pkey mapping */
  2076. (slave == mlx4_master_func_num(ibdev->dev) || !i) ? i :
  2077. ibdev->dev->phys_caps.pkey_phys_table_len[port] - 1;
  2078. mlx4_sync_pkey_table(ibdev->dev, slave, port, i,
  2079. ibdev->pkeys.virt2phys_pkey[slave][port - 1][i]);
  2080. }
  2081. }
  2082. }
  2083. /* initialize pkey cache */
  2084. for (port = 1; port <= ibdev->dev->caps.num_ports; ++port) {
  2085. for (i = 0;
  2086. i < ibdev->dev->phys_caps.pkey_phys_table_len[port];
  2087. ++i)
  2088. ibdev->pkeys.phys_pkey_cache[port-1][i] =
  2089. (i) ? 0 : 0xFFFF;
  2090. }
  2091. }
  2092. }
  2093. static void mlx4_ib_alloc_eqs(struct mlx4_dev *dev, struct mlx4_ib_dev *ibdev)
  2094. {
  2095. int i, j, eq = 0, total_eqs = 0;
  2096. ibdev->eq_table = kcalloc(dev->caps.num_comp_vectors,
  2097. sizeof(ibdev->eq_table[0]), GFP_KERNEL);
  2098. if (!ibdev->eq_table)
  2099. return;
  2100. for (i = 1; i <= dev->caps.num_ports; i++) {
  2101. for (j = 0; j < mlx4_get_eqs_per_port(dev, i);
  2102. j++, total_eqs++) {
  2103. if (i > 1 && mlx4_is_eq_shared(dev, total_eqs))
  2104. continue;
  2105. ibdev->eq_table[eq] = total_eqs;
  2106. if (!mlx4_assign_eq(dev, i,
  2107. &ibdev->eq_table[eq]))
  2108. eq++;
  2109. else
  2110. ibdev->eq_table[eq] = -1;
  2111. }
  2112. }
  2113. for (i = eq; i < dev->caps.num_comp_vectors;
  2114. ibdev->eq_table[i++] = -1)
  2115. ;
  2116. /* Advertise the new number of EQs to clients */
  2117. ibdev->ib_dev.num_comp_vectors = eq;
  2118. }
  2119. static void mlx4_ib_free_eqs(struct mlx4_dev *dev, struct mlx4_ib_dev *ibdev)
  2120. {
  2121. int i;
  2122. int total_eqs = ibdev->ib_dev.num_comp_vectors;
  2123. /* no eqs were allocated */
  2124. if (!ibdev->eq_table)
  2125. return;
  2126. /* Reset the advertised EQ number */
  2127. ibdev->ib_dev.num_comp_vectors = 0;
  2128. for (i = 0; i < total_eqs; i++)
  2129. mlx4_release_eq(dev, ibdev->eq_table[i]);
  2130. kfree(ibdev->eq_table);
  2131. ibdev->eq_table = NULL;
  2132. }
  2133. static int mlx4_port_immutable(struct ib_device *ibdev, u8 port_num,
  2134. struct ib_port_immutable *immutable)
  2135. {
  2136. struct ib_port_attr attr;
  2137. struct mlx4_ib_dev *mdev = to_mdev(ibdev);
  2138. int err;
  2139. if (mlx4_ib_port_link_layer(ibdev, port_num) == IB_LINK_LAYER_INFINIBAND) {
  2140. immutable->core_cap_flags = RDMA_CORE_PORT_IBA_IB;
  2141. immutable->max_mad_size = IB_MGMT_MAD_SIZE;
  2142. } else {
  2143. if (mdev->dev->caps.flags & MLX4_DEV_CAP_FLAG_IBOE)
  2144. immutable->core_cap_flags = RDMA_CORE_PORT_IBA_ROCE;
  2145. if (mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ROCE_V1_V2)
  2146. immutable->core_cap_flags = RDMA_CORE_PORT_IBA_ROCE |
  2147. RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP;
  2148. immutable->core_cap_flags |= RDMA_CORE_PORT_RAW_PACKET;
  2149. if (immutable->core_cap_flags & (RDMA_CORE_PORT_IBA_ROCE |
  2150. RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP))
  2151. immutable->max_mad_size = IB_MGMT_MAD_SIZE;
  2152. }
  2153. err = ib_query_port(ibdev, port_num, &attr);
  2154. if (err)
  2155. return err;
  2156. immutable->pkey_tbl_len = attr.pkey_tbl_len;
  2157. immutable->gid_tbl_len = attr.gid_tbl_len;
  2158. return 0;
  2159. }
  2160. static void get_fw_ver_str(struct ib_device *device, char *str)
  2161. {
  2162. struct mlx4_ib_dev *dev =
  2163. container_of(device, struct mlx4_ib_dev, ib_dev);
  2164. snprintf(str, IB_FW_VERSION_NAME_MAX, "%d.%d.%d",
  2165. (int) (dev->dev->caps.fw_ver >> 32),
  2166. (int) (dev->dev->caps.fw_ver >> 16) & 0xffff,
  2167. (int) dev->dev->caps.fw_ver & 0xffff);
  2168. }
  2169. static void *mlx4_ib_add(struct mlx4_dev *dev)
  2170. {
  2171. struct mlx4_ib_dev *ibdev;
  2172. int num_ports = 0;
  2173. int i, j;
  2174. int err;
  2175. struct mlx4_ib_iboe *iboe;
  2176. int ib_num_ports = 0;
  2177. int num_req_counters;
  2178. int allocated;
  2179. u32 counter_index;
  2180. struct counter_index *new_counter_index = NULL;
  2181. pr_info_once("%s", mlx4_ib_version);
  2182. num_ports = 0;
  2183. mlx4_foreach_ib_transport_port(i, dev)
  2184. num_ports++;
  2185. /* No point in registering a device with no ports... */
  2186. if (num_ports == 0)
  2187. return NULL;
  2188. ibdev = (struct mlx4_ib_dev *) ib_alloc_device(sizeof *ibdev);
  2189. if (!ibdev) {
  2190. dev_err(&dev->persist->pdev->dev,
  2191. "Device struct alloc failed\n");
  2192. return NULL;
  2193. }
  2194. iboe = &ibdev->iboe;
  2195. if (mlx4_pd_alloc(dev, &ibdev->priv_pdn))
  2196. goto err_dealloc;
  2197. if (mlx4_uar_alloc(dev, &ibdev->priv_uar))
  2198. goto err_pd;
  2199. ibdev->uar_map = ioremap((phys_addr_t) ibdev->priv_uar.pfn << PAGE_SHIFT,
  2200. PAGE_SIZE);
  2201. if (!ibdev->uar_map)
  2202. goto err_uar;
  2203. MLX4_INIT_DOORBELL_LOCK(&ibdev->uar_lock);
  2204. ibdev->dev = dev;
  2205. ibdev->bond_next_port = 0;
  2206. strlcpy(ibdev->ib_dev.name, "mlx4_%d", IB_DEVICE_NAME_MAX);
  2207. ibdev->ib_dev.owner = THIS_MODULE;
  2208. ibdev->ib_dev.node_type = RDMA_NODE_IB_CA;
  2209. ibdev->ib_dev.local_dma_lkey = dev->caps.reserved_lkey;
  2210. ibdev->num_ports = num_ports;
  2211. ibdev->ib_dev.phys_port_cnt = mlx4_is_bonded(dev) ?
  2212. 1 : ibdev->num_ports;
  2213. ibdev->ib_dev.num_comp_vectors = dev->caps.num_comp_vectors;
  2214. ibdev->ib_dev.dev.parent = &dev->persist->pdev->dev;
  2215. ibdev->ib_dev.get_netdev = mlx4_ib_get_netdev;
  2216. ibdev->ib_dev.add_gid = mlx4_ib_add_gid;
  2217. ibdev->ib_dev.del_gid = mlx4_ib_del_gid;
  2218. if (dev->caps.userspace_caps)
  2219. ibdev->ib_dev.uverbs_abi_ver = MLX4_IB_UVERBS_ABI_VERSION;
  2220. else
  2221. ibdev->ib_dev.uverbs_abi_ver = MLX4_IB_UVERBS_NO_DEV_CAPS_ABI_VERSION;
  2222. ibdev->ib_dev.uverbs_cmd_mask =
  2223. (1ull << IB_USER_VERBS_CMD_GET_CONTEXT) |
  2224. (1ull << IB_USER_VERBS_CMD_QUERY_DEVICE) |
  2225. (1ull << IB_USER_VERBS_CMD_QUERY_PORT) |
  2226. (1ull << IB_USER_VERBS_CMD_ALLOC_PD) |
  2227. (1ull << IB_USER_VERBS_CMD_DEALLOC_PD) |
  2228. (1ull << IB_USER_VERBS_CMD_REG_MR) |
  2229. (1ull << IB_USER_VERBS_CMD_REREG_MR) |
  2230. (1ull << IB_USER_VERBS_CMD_DEREG_MR) |
  2231. (1ull << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) |
  2232. (1ull << IB_USER_VERBS_CMD_CREATE_CQ) |
  2233. (1ull << IB_USER_VERBS_CMD_RESIZE_CQ) |
  2234. (1ull << IB_USER_VERBS_CMD_DESTROY_CQ) |
  2235. (1ull << IB_USER_VERBS_CMD_CREATE_QP) |
  2236. (1ull << IB_USER_VERBS_CMD_MODIFY_QP) |
  2237. (1ull << IB_USER_VERBS_CMD_QUERY_QP) |
  2238. (1ull << IB_USER_VERBS_CMD_DESTROY_QP) |
  2239. (1ull << IB_USER_VERBS_CMD_ATTACH_MCAST) |
  2240. (1ull << IB_USER_VERBS_CMD_DETACH_MCAST) |
  2241. (1ull << IB_USER_VERBS_CMD_CREATE_SRQ) |
  2242. (1ull << IB_USER_VERBS_CMD_MODIFY_SRQ) |
  2243. (1ull << IB_USER_VERBS_CMD_QUERY_SRQ) |
  2244. (1ull << IB_USER_VERBS_CMD_DESTROY_SRQ) |
  2245. (1ull << IB_USER_VERBS_CMD_CREATE_XSRQ) |
  2246. (1ull << IB_USER_VERBS_CMD_OPEN_QP);
  2247. ibdev->ib_dev.query_device = mlx4_ib_query_device;
  2248. ibdev->ib_dev.query_port = mlx4_ib_query_port;
  2249. ibdev->ib_dev.get_link_layer = mlx4_ib_port_link_layer;
  2250. ibdev->ib_dev.query_gid = mlx4_ib_query_gid;
  2251. ibdev->ib_dev.query_pkey = mlx4_ib_query_pkey;
  2252. ibdev->ib_dev.modify_device = mlx4_ib_modify_device;
  2253. ibdev->ib_dev.modify_port = mlx4_ib_modify_port;
  2254. ibdev->ib_dev.alloc_ucontext = mlx4_ib_alloc_ucontext;
  2255. ibdev->ib_dev.dealloc_ucontext = mlx4_ib_dealloc_ucontext;
  2256. ibdev->ib_dev.mmap = mlx4_ib_mmap;
  2257. ibdev->ib_dev.alloc_pd = mlx4_ib_alloc_pd;
  2258. ibdev->ib_dev.dealloc_pd = mlx4_ib_dealloc_pd;
  2259. ibdev->ib_dev.create_ah = mlx4_ib_create_ah;
  2260. ibdev->ib_dev.query_ah = mlx4_ib_query_ah;
  2261. ibdev->ib_dev.destroy_ah = mlx4_ib_destroy_ah;
  2262. ibdev->ib_dev.create_srq = mlx4_ib_create_srq;
  2263. ibdev->ib_dev.modify_srq = mlx4_ib_modify_srq;
  2264. ibdev->ib_dev.query_srq = mlx4_ib_query_srq;
  2265. ibdev->ib_dev.destroy_srq = mlx4_ib_destroy_srq;
  2266. ibdev->ib_dev.post_srq_recv = mlx4_ib_post_srq_recv;
  2267. ibdev->ib_dev.create_qp = mlx4_ib_create_qp;
  2268. ibdev->ib_dev.modify_qp = mlx4_ib_modify_qp;
  2269. ibdev->ib_dev.query_qp = mlx4_ib_query_qp;
  2270. ibdev->ib_dev.destroy_qp = mlx4_ib_destroy_qp;
  2271. ibdev->ib_dev.drain_sq = mlx4_ib_drain_sq;
  2272. ibdev->ib_dev.drain_rq = mlx4_ib_drain_rq;
  2273. ibdev->ib_dev.post_send = mlx4_ib_post_send;
  2274. ibdev->ib_dev.post_recv = mlx4_ib_post_recv;
  2275. ibdev->ib_dev.create_cq = mlx4_ib_create_cq;
  2276. ibdev->ib_dev.modify_cq = mlx4_ib_modify_cq;
  2277. ibdev->ib_dev.resize_cq = mlx4_ib_resize_cq;
  2278. ibdev->ib_dev.destroy_cq = mlx4_ib_destroy_cq;
  2279. ibdev->ib_dev.poll_cq = mlx4_ib_poll_cq;
  2280. ibdev->ib_dev.req_notify_cq = mlx4_ib_arm_cq;
  2281. ibdev->ib_dev.get_dma_mr = mlx4_ib_get_dma_mr;
  2282. ibdev->ib_dev.reg_user_mr = mlx4_ib_reg_user_mr;
  2283. ibdev->ib_dev.rereg_user_mr = mlx4_ib_rereg_user_mr;
  2284. ibdev->ib_dev.dereg_mr = mlx4_ib_dereg_mr;
  2285. ibdev->ib_dev.alloc_mr = mlx4_ib_alloc_mr;
  2286. ibdev->ib_dev.map_mr_sg = mlx4_ib_map_mr_sg;
  2287. ibdev->ib_dev.attach_mcast = mlx4_ib_mcg_attach;
  2288. ibdev->ib_dev.detach_mcast = mlx4_ib_mcg_detach;
  2289. ibdev->ib_dev.process_mad = mlx4_ib_process_mad;
  2290. ibdev->ib_dev.get_port_immutable = mlx4_port_immutable;
  2291. ibdev->ib_dev.get_dev_fw_str = get_fw_ver_str;
  2292. ibdev->ib_dev.disassociate_ucontext = mlx4_ib_disassociate_ucontext;
  2293. ibdev->ib_dev.uverbs_ex_cmd_mask |=
  2294. (1ull << IB_USER_VERBS_EX_CMD_MODIFY_CQ);
  2295. if ((dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_RSS) &&
  2296. ((mlx4_ib_port_link_layer(&ibdev->ib_dev, 1) ==
  2297. IB_LINK_LAYER_ETHERNET) ||
  2298. (mlx4_ib_port_link_layer(&ibdev->ib_dev, 2) ==
  2299. IB_LINK_LAYER_ETHERNET))) {
  2300. ibdev->ib_dev.create_wq = mlx4_ib_create_wq;
  2301. ibdev->ib_dev.modify_wq = mlx4_ib_modify_wq;
  2302. ibdev->ib_dev.destroy_wq = mlx4_ib_destroy_wq;
  2303. ibdev->ib_dev.create_rwq_ind_table =
  2304. mlx4_ib_create_rwq_ind_table;
  2305. ibdev->ib_dev.destroy_rwq_ind_table =
  2306. mlx4_ib_destroy_rwq_ind_table;
  2307. ibdev->ib_dev.uverbs_ex_cmd_mask |=
  2308. (1ull << IB_USER_VERBS_EX_CMD_CREATE_WQ) |
  2309. (1ull << IB_USER_VERBS_EX_CMD_MODIFY_WQ) |
  2310. (1ull << IB_USER_VERBS_EX_CMD_DESTROY_WQ) |
  2311. (1ull << IB_USER_VERBS_EX_CMD_CREATE_RWQ_IND_TBL) |
  2312. (1ull << IB_USER_VERBS_EX_CMD_DESTROY_RWQ_IND_TBL);
  2313. }
  2314. if (!mlx4_is_slave(ibdev->dev)) {
  2315. ibdev->ib_dev.alloc_fmr = mlx4_ib_fmr_alloc;
  2316. ibdev->ib_dev.map_phys_fmr = mlx4_ib_map_phys_fmr;
  2317. ibdev->ib_dev.unmap_fmr = mlx4_ib_unmap_fmr;
  2318. ibdev->ib_dev.dealloc_fmr = mlx4_ib_fmr_dealloc;
  2319. }
  2320. if (dev->caps.flags & MLX4_DEV_CAP_FLAG_MEM_WINDOW ||
  2321. dev->caps.bmme_flags & MLX4_BMME_FLAG_TYPE_2_WIN) {
  2322. ibdev->ib_dev.alloc_mw = mlx4_ib_alloc_mw;
  2323. ibdev->ib_dev.dealloc_mw = mlx4_ib_dealloc_mw;
  2324. ibdev->ib_dev.uverbs_cmd_mask |=
  2325. (1ull << IB_USER_VERBS_CMD_ALLOC_MW) |
  2326. (1ull << IB_USER_VERBS_CMD_DEALLOC_MW);
  2327. }
  2328. if (dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC) {
  2329. ibdev->ib_dev.alloc_xrcd = mlx4_ib_alloc_xrcd;
  2330. ibdev->ib_dev.dealloc_xrcd = mlx4_ib_dealloc_xrcd;
  2331. ibdev->ib_dev.uverbs_cmd_mask |=
  2332. (1ull << IB_USER_VERBS_CMD_OPEN_XRCD) |
  2333. (1ull << IB_USER_VERBS_CMD_CLOSE_XRCD);
  2334. }
  2335. if (check_flow_steering_support(dev)) {
  2336. ibdev->steering_support = MLX4_STEERING_MODE_DEVICE_MANAGED;
  2337. ibdev->ib_dev.create_flow = mlx4_ib_create_flow;
  2338. ibdev->ib_dev.destroy_flow = mlx4_ib_destroy_flow;
  2339. ibdev->ib_dev.uverbs_ex_cmd_mask |=
  2340. (1ull << IB_USER_VERBS_EX_CMD_CREATE_FLOW) |
  2341. (1ull << IB_USER_VERBS_EX_CMD_DESTROY_FLOW);
  2342. }
  2343. ibdev->ib_dev.uverbs_ex_cmd_mask |=
  2344. (1ull << IB_USER_VERBS_EX_CMD_QUERY_DEVICE) |
  2345. (1ull << IB_USER_VERBS_EX_CMD_CREATE_CQ) |
  2346. (1ull << IB_USER_VERBS_EX_CMD_CREATE_QP);
  2347. mlx4_ib_alloc_eqs(dev, ibdev);
  2348. spin_lock_init(&iboe->lock);
  2349. if (init_node_data(ibdev))
  2350. goto err_map;
  2351. mlx4_init_sl2vl_tbl(ibdev);
  2352. for (i = 0; i < ibdev->num_ports; ++i) {
  2353. mutex_init(&ibdev->counters_table[i].mutex);
  2354. INIT_LIST_HEAD(&ibdev->counters_table[i].counters_list);
  2355. }
  2356. num_req_counters = mlx4_is_bonded(dev) ? 1 : ibdev->num_ports;
  2357. for (i = 0; i < num_req_counters; ++i) {
  2358. mutex_init(&ibdev->qp1_proxy_lock[i]);
  2359. allocated = 0;
  2360. if (mlx4_ib_port_link_layer(&ibdev->ib_dev, i + 1) ==
  2361. IB_LINK_LAYER_ETHERNET) {
  2362. err = mlx4_counter_alloc(ibdev->dev, &counter_index,
  2363. MLX4_RES_USAGE_DRIVER);
  2364. /* if failed to allocate a new counter, use default */
  2365. if (err)
  2366. counter_index =
  2367. mlx4_get_default_counter_index(dev,
  2368. i + 1);
  2369. else
  2370. allocated = 1;
  2371. } else { /* IB_LINK_LAYER_INFINIBAND use the default counter */
  2372. counter_index = mlx4_get_default_counter_index(dev,
  2373. i + 1);
  2374. }
  2375. new_counter_index = kmalloc(sizeof(*new_counter_index),
  2376. GFP_KERNEL);
  2377. if (!new_counter_index) {
  2378. if (allocated)
  2379. mlx4_counter_free(ibdev->dev, counter_index);
  2380. goto err_counter;
  2381. }
  2382. new_counter_index->index = counter_index;
  2383. new_counter_index->allocated = allocated;
  2384. list_add_tail(&new_counter_index->list,
  2385. &ibdev->counters_table[i].counters_list);
  2386. ibdev->counters_table[i].default_counter = counter_index;
  2387. pr_info("counter index %d for port %d allocated %d\n",
  2388. counter_index, i + 1, allocated);
  2389. }
  2390. if (mlx4_is_bonded(dev))
  2391. for (i = 1; i < ibdev->num_ports ; ++i) {
  2392. new_counter_index =
  2393. kmalloc(sizeof(struct counter_index),
  2394. GFP_KERNEL);
  2395. if (!new_counter_index)
  2396. goto err_counter;
  2397. new_counter_index->index = counter_index;
  2398. new_counter_index->allocated = 0;
  2399. list_add_tail(&new_counter_index->list,
  2400. &ibdev->counters_table[i].counters_list);
  2401. ibdev->counters_table[i].default_counter =
  2402. counter_index;
  2403. }
  2404. mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_IB)
  2405. ib_num_ports++;
  2406. spin_lock_init(&ibdev->sm_lock);
  2407. mutex_init(&ibdev->cap_mask_mutex);
  2408. INIT_LIST_HEAD(&ibdev->qp_list);
  2409. spin_lock_init(&ibdev->reset_flow_resource_lock);
  2410. if (ibdev->steering_support == MLX4_STEERING_MODE_DEVICE_MANAGED &&
  2411. ib_num_ports) {
  2412. ibdev->steer_qpn_count = MLX4_IB_UC_MAX_NUM_QPS;
  2413. err = mlx4_qp_reserve_range(dev, ibdev->steer_qpn_count,
  2414. MLX4_IB_UC_STEER_QPN_ALIGN,
  2415. &ibdev->steer_qpn_base, 0,
  2416. MLX4_RES_USAGE_DRIVER);
  2417. if (err)
  2418. goto err_counter;
  2419. ibdev->ib_uc_qpns_bitmap =
  2420. kmalloc_array(BITS_TO_LONGS(ibdev->steer_qpn_count),
  2421. sizeof(long),
  2422. GFP_KERNEL);
  2423. if (!ibdev->ib_uc_qpns_bitmap)
  2424. goto err_steer_qp_release;
  2425. if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_DMFS_IPOIB) {
  2426. bitmap_zero(ibdev->ib_uc_qpns_bitmap,
  2427. ibdev->steer_qpn_count);
  2428. err = mlx4_FLOW_STEERING_IB_UC_QP_RANGE(
  2429. dev, ibdev->steer_qpn_base,
  2430. ibdev->steer_qpn_base +
  2431. ibdev->steer_qpn_count - 1);
  2432. if (err)
  2433. goto err_steer_free_bitmap;
  2434. } else {
  2435. bitmap_fill(ibdev->ib_uc_qpns_bitmap,
  2436. ibdev->steer_qpn_count);
  2437. }
  2438. }
  2439. for (j = 1; j <= ibdev->dev->caps.num_ports; j++)
  2440. atomic64_set(&iboe->mac[j - 1], ibdev->dev->caps.def_mac[j]);
  2441. if (mlx4_ib_alloc_diag_counters(ibdev))
  2442. goto err_steer_free_bitmap;
  2443. ibdev->ib_dev.driver_id = RDMA_DRIVER_MLX4;
  2444. if (ib_register_device(&ibdev->ib_dev, NULL))
  2445. goto err_diag_counters;
  2446. if (mlx4_ib_mad_init(ibdev))
  2447. goto err_reg;
  2448. if (mlx4_ib_init_sriov(ibdev))
  2449. goto err_mad;
  2450. if (!iboe->nb.notifier_call) {
  2451. iboe->nb.notifier_call = mlx4_ib_netdev_event;
  2452. err = register_netdevice_notifier(&iboe->nb);
  2453. if (err) {
  2454. iboe->nb.notifier_call = NULL;
  2455. goto err_notif;
  2456. }
  2457. }
  2458. if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ROCE_V1_V2) {
  2459. err = mlx4_config_roce_v2_port(dev, ROCE_V2_UDP_DPORT);
  2460. if (err)
  2461. goto err_notif;
  2462. }
  2463. for (j = 0; j < ARRAY_SIZE(mlx4_class_attributes); ++j) {
  2464. if (device_create_file(&ibdev->ib_dev.dev,
  2465. mlx4_class_attributes[j]))
  2466. goto err_notif;
  2467. }
  2468. ibdev->ib_active = true;
  2469. mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_IB)
  2470. devlink_port_type_ib_set(mlx4_get_devlink_port(dev, i),
  2471. &ibdev->ib_dev);
  2472. if (mlx4_is_mfunc(ibdev->dev))
  2473. init_pkeys(ibdev);
  2474. /* create paravirt contexts for any VFs which are active */
  2475. if (mlx4_is_master(ibdev->dev)) {
  2476. for (j = 0; j < MLX4_MFUNC_MAX; j++) {
  2477. if (j == mlx4_master_func_num(ibdev->dev))
  2478. continue;
  2479. if (mlx4_is_slave_active(ibdev->dev, j))
  2480. do_slave_init(ibdev, j, 1);
  2481. }
  2482. }
  2483. return ibdev;
  2484. err_notif:
  2485. if (ibdev->iboe.nb.notifier_call) {
  2486. if (unregister_netdevice_notifier(&ibdev->iboe.nb))
  2487. pr_warn("failure unregistering notifier\n");
  2488. ibdev->iboe.nb.notifier_call = NULL;
  2489. }
  2490. flush_workqueue(wq);
  2491. mlx4_ib_close_sriov(ibdev);
  2492. err_mad:
  2493. mlx4_ib_mad_cleanup(ibdev);
  2494. err_reg:
  2495. ib_unregister_device(&ibdev->ib_dev);
  2496. err_diag_counters:
  2497. mlx4_ib_diag_cleanup(ibdev);
  2498. err_steer_free_bitmap:
  2499. kfree(ibdev->ib_uc_qpns_bitmap);
  2500. err_steer_qp_release:
  2501. mlx4_qp_release_range(dev, ibdev->steer_qpn_base,
  2502. ibdev->steer_qpn_count);
  2503. err_counter:
  2504. for (i = 0; i < ibdev->num_ports; ++i)
  2505. mlx4_ib_delete_counters_table(ibdev, &ibdev->counters_table[i]);
  2506. err_map:
  2507. mlx4_ib_free_eqs(dev, ibdev);
  2508. iounmap(ibdev->uar_map);
  2509. err_uar:
  2510. mlx4_uar_free(dev, &ibdev->priv_uar);
  2511. err_pd:
  2512. mlx4_pd_free(dev, ibdev->priv_pdn);
  2513. err_dealloc:
  2514. ib_dealloc_device(&ibdev->ib_dev);
  2515. return NULL;
  2516. }
  2517. int mlx4_ib_steer_qp_alloc(struct mlx4_ib_dev *dev, int count, int *qpn)
  2518. {
  2519. int offset;
  2520. WARN_ON(!dev->ib_uc_qpns_bitmap);
  2521. offset = bitmap_find_free_region(dev->ib_uc_qpns_bitmap,
  2522. dev->steer_qpn_count,
  2523. get_count_order(count));
  2524. if (offset < 0)
  2525. return offset;
  2526. *qpn = dev->steer_qpn_base + offset;
  2527. return 0;
  2528. }
  2529. void mlx4_ib_steer_qp_free(struct mlx4_ib_dev *dev, u32 qpn, int count)
  2530. {
  2531. if (!qpn ||
  2532. dev->steering_support != MLX4_STEERING_MODE_DEVICE_MANAGED)
  2533. return;
  2534. if (WARN(qpn < dev->steer_qpn_base, "qpn = %u, steer_qpn_base = %u\n",
  2535. qpn, dev->steer_qpn_base))
  2536. /* not supposed to be here */
  2537. return;
  2538. bitmap_release_region(dev->ib_uc_qpns_bitmap,
  2539. qpn - dev->steer_qpn_base,
  2540. get_count_order(count));
  2541. }
  2542. int mlx4_ib_steer_qp_reg(struct mlx4_ib_dev *mdev, struct mlx4_ib_qp *mqp,
  2543. int is_attach)
  2544. {
  2545. int err;
  2546. size_t flow_size;
  2547. struct ib_flow_attr *flow = NULL;
  2548. struct ib_flow_spec_ib *ib_spec;
  2549. if (is_attach) {
  2550. flow_size = sizeof(struct ib_flow_attr) +
  2551. sizeof(struct ib_flow_spec_ib);
  2552. flow = kzalloc(flow_size, GFP_KERNEL);
  2553. if (!flow)
  2554. return -ENOMEM;
  2555. flow->port = mqp->port;
  2556. flow->num_of_specs = 1;
  2557. flow->size = flow_size;
  2558. ib_spec = (struct ib_flow_spec_ib *)(flow + 1);
  2559. ib_spec->type = IB_FLOW_SPEC_IB;
  2560. ib_spec->size = sizeof(struct ib_flow_spec_ib);
  2561. /* Add an empty rule for IB L2 */
  2562. memset(&ib_spec->mask, 0, sizeof(ib_spec->mask));
  2563. err = __mlx4_ib_create_flow(&mqp->ibqp, flow,
  2564. IB_FLOW_DOMAIN_NIC,
  2565. MLX4_FS_REGULAR,
  2566. &mqp->reg_id);
  2567. } else {
  2568. err = __mlx4_ib_destroy_flow(mdev->dev, mqp->reg_id);
  2569. }
  2570. kfree(flow);
  2571. return err;
  2572. }
  2573. static void mlx4_ib_remove(struct mlx4_dev *dev, void *ibdev_ptr)
  2574. {
  2575. struct mlx4_ib_dev *ibdev = ibdev_ptr;
  2576. int p;
  2577. int i;
  2578. mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_IB)
  2579. devlink_port_type_clear(mlx4_get_devlink_port(dev, i));
  2580. ibdev->ib_active = false;
  2581. flush_workqueue(wq);
  2582. mlx4_ib_close_sriov(ibdev);
  2583. mlx4_ib_mad_cleanup(ibdev);
  2584. ib_unregister_device(&ibdev->ib_dev);
  2585. mlx4_ib_diag_cleanup(ibdev);
  2586. if (ibdev->iboe.nb.notifier_call) {
  2587. if (unregister_netdevice_notifier(&ibdev->iboe.nb))
  2588. pr_warn("failure unregistering notifier\n");
  2589. ibdev->iboe.nb.notifier_call = NULL;
  2590. }
  2591. mlx4_qp_release_range(dev, ibdev->steer_qpn_base,
  2592. ibdev->steer_qpn_count);
  2593. kfree(ibdev->ib_uc_qpns_bitmap);
  2594. iounmap(ibdev->uar_map);
  2595. for (p = 0; p < ibdev->num_ports; ++p)
  2596. mlx4_ib_delete_counters_table(ibdev, &ibdev->counters_table[p]);
  2597. mlx4_foreach_port(p, dev, MLX4_PORT_TYPE_IB)
  2598. mlx4_CLOSE_PORT(dev, p);
  2599. mlx4_ib_free_eqs(dev, ibdev);
  2600. mlx4_uar_free(dev, &ibdev->priv_uar);
  2601. mlx4_pd_free(dev, ibdev->priv_pdn);
  2602. ib_dealloc_device(&ibdev->ib_dev);
  2603. }
  2604. static void do_slave_init(struct mlx4_ib_dev *ibdev, int slave, int do_init)
  2605. {
  2606. struct mlx4_ib_demux_work **dm = NULL;
  2607. struct mlx4_dev *dev = ibdev->dev;
  2608. int i;
  2609. unsigned long flags;
  2610. struct mlx4_active_ports actv_ports;
  2611. unsigned int ports;
  2612. unsigned int first_port;
  2613. if (!mlx4_is_master(dev))
  2614. return;
  2615. actv_ports = mlx4_get_active_ports(dev, slave);
  2616. ports = bitmap_weight(actv_ports.ports, dev->caps.num_ports);
  2617. first_port = find_first_bit(actv_ports.ports, dev->caps.num_ports);
  2618. dm = kcalloc(ports, sizeof(*dm), GFP_ATOMIC);
  2619. if (!dm)
  2620. return;
  2621. for (i = 0; i < ports; i++) {
  2622. dm[i] = kmalloc(sizeof (struct mlx4_ib_demux_work), GFP_ATOMIC);
  2623. if (!dm[i]) {
  2624. while (--i >= 0)
  2625. kfree(dm[i]);
  2626. goto out;
  2627. }
  2628. INIT_WORK(&dm[i]->work, mlx4_ib_tunnels_update_work);
  2629. dm[i]->port = first_port + i + 1;
  2630. dm[i]->slave = slave;
  2631. dm[i]->do_init = do_init;
  2632. dm[i]->dev = ibdev;
  2633. }
  2634. /* initialize or tear down tunnel QPs for the slave */
  2635. spin_lock_irqsave(&ibdev->sriov.going_down_lock, flags);
  2636. if (!ibdev->sriov.is_going_down) {
  2637. for (i = 0; i < ports; i++)
  2638. queue_work(ibdev->sriov.demux[i].ud_wq, &dm[i]->work);
  2639. spin_unlock_irqrestore(&ibdev->sriov.going_down_lock, flags);
  2640. } else {
  2641. spin_unlock_irqrestore(&ibdev->sriov.going_down_lock, flags);
  2642. for (i = 0; i < ports; i++)
  2643. kfree(dm[i]);
  2644. }
  2645. out:
  2646. kfree(dm);
  2647. return;
  2648. }
  2649. static void mlx4_ib_handle_catas_error(struct mlx4_ib_dev *ibdev)
  2650. {
  2651. struct mlx4_ib_qp *mqp;
  2652. unsigned long flags_qp;
  2653. unsigned long flags_cq;
  2654. struct mlx4_ib_cq *send_mcq, *recv_mcq;
  2655. struct list_head cq_notify_list;
  2656. struct mlx4_cq *mcq;
  2657. unsigned long flags;
  2658. pr_warn("mlx4_ib_handle_catas_error was started\n");
  2659. INIT_LIST_HEAD(&cq_notify_list);
  2660. /* Go over qp list reside on that ibdev, sync with create/destroy qp.*/
  2661. spin_lock_irqsave(&ibdev->reset_flow_resource_lock, flags);
  2662. list_for_each_entry(mqp, &ibdev->qp_list, qps_list) {
  2663. spin_lock_irqsave(&mqp->sq.lock, flags_qp);
  2664. if (mqp->sq.tail != mqp->sq.head) {
  2665. send_mcq = to_mcq(mqp->ibqp.send_cq);
  2666. spin_lock_irqsave(&send_mcq->lock, flags_cq);
  2667. if (send_mcq->mcq.comp &&
  2668. mqp->ibqp.send_cq->comp_handler) {
  2669. if (!send_mcq->mcq.reset_notify_added) {
  2670. send_mcq->mcq.reset_notify_added = 1;
  2671. list_add_tail(&send_mcq->mcq.reset_notify,
  2672. &cq_notify_list);
  2673. }
  2674. }
  2675. spin_unlock_irqrestore(&send_mcq->lock, flags_cq);
  2676. }
  2677. spin_unlock_irqrestore(&mqp->sq.lock, flags_qp);
  2678. /* Now, handle the QP's receive queue */
  2679. spin_lock_irqsave(&mqp->rq.lock, flags_qp);
  2680. /* no handling is needed for SRQ */
  2681. if (!mqp->ibqp.srq) {
  2682. if (mqp->rq.tail != mqp->rq.head) {
  2683. recv_mcq = to_mcq(mqp->ibqp.recv_cq);
  2684. spin_lock_irqsave(&recv_mcq->lock, flags_cq);
  2685. if (recv_mcq->mcq.comp &&
  2686. mqp->ibqp.recv_cq->comp_handler) {
  2687. if (!recv_mcq->mcq.reset_notify_added) {
  2688. recv_mcq->mcq.reset_notify_added = 1;
  2689. list_add_tail(&recv_mcq->mcq.reset_notify,
  2690. &cq_notify_list);
  2691. }
  2692. }
  2693. spin_unlock_irqrestore(&recv_mcq->lock,
  2694. flags_cq);
  2695. }
  2696. }
  2697. spin_unlock_irqrestore(&mqp->rq.lock, flags_qp);
  2698. }
  2699. list_for_each_entry(mcq, &cq_notify_list, reset_notify) {
  2700. mcq->comp(mcq);
  2701. }
  2702. spin_unlock_irqrestore(&ibdev->reset_flow_resource_lock, flags);
  2703. pr_warn("mlx4_ib_handle_catas_error ended\n");
  2704. }
  2705. static void handle_bonded_port_state_event(struct work_struct *work)
  2706. {
  2707. struct ib_event_work *ew =
  2708. container_of(work, struct ib_event_work, work);
  2709. struct mlx4_ib_dev *ibdev = ew->ib_dev;
  2710. enum ib_port_state bonded_port_state = IB_PORT_NOP;
  2711. int i;
  2712. struct ib_event ibev;
  2713. kfree(ew);
  2714. spin_lock_bh(&ibdev->iboe.lock);
  2715. for (i = 0; i < MLX4_MAX_PORTS; ++i) {
  2716. struct net_device *curr_netdev = ibdev->iboe.netdevs[i];
  2717. enum ib_port_state curr_port_state;
  2718. if (!curr_netdev)
  2719. continue;
  2720. curr_port_state =
  2721. (netif_running(curr_netdev) &&
  2722. netif_carrier_ok(curr_netdev)) ?
  2723. IB_PORT_ACTIVE : IB_PORT_DOWN;
  2724. bonded_port_state = (bonded_port_state != IB_PORT_ACTIVE) ?
  2725. curr_port_state : IB_PORT_ACTIVE;
  2726. }
  2727. spin_unlock_bh(&ibdev->iboe.lock);
  2728. ibev.device = &ibdev->ib_dev;
  2729. ibev.element.port_num = 1;
  2730. ibev.event = (bonded_port_state == IB_PORT_ACTIVE) ?
  2731. IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR;
  2732. ib_dispatch_event(&ibev);
  2733. }
  2734. void mlx4_ib_sl2vl_update(struct mlx4_ib_dev *mdev, int port)
  2735. {
  2736. u64 sl2vl;
  2737. int err;
  2738. err = mlx4_ib_query_sl2vl(&mdev->ib_dev, port, &sl2vl);
  2739. if (err) {
  2740. pr_err("Unable to get current sl to vl mapping for port %d. Using all zeroes (%d)\n",
  2741. port, err);
  2742. sl2vl = 0;
  2743. }
  2744. atomic64_set(&mdev->sl2vl[port - 1], sl2vl);
  2745. }
  2746. static void ib_sl2vl_update_work(struct work_struct *work)
  2747. {
  2748. struct ib_event_work *ew = container_of(work, struct ib_event_work, work);
  2749. struct mlx4_ib_dev *mdev = ew->ib_dev;
  2750. int port = ew->port;
  2751. mlx4_ib_sl2vl_update(mdev, port);
  2752. kfree(ew);
  2753. }
  2754. void mlx4_sched_ib_sl2vl_update_work(struct mlx4_ib_dev *ibdev,
  2755. int port)
  2756. {
  2757. struct ib_event_work *ew;
  2758. ew = kmalloc(sizeof(*ew), GFP_ATOMIC);
  2759. if (ew) {
  2760. INIT_WORK(&ew->work, ib_sl2vl_update_work);
  2761. ew->port = port;
  2762. ew->ib_dev = ibdev;
  2763. queue_work(wq, &ew->work);
  2764. }
  2765. }
  2766. static void mlx4_ib_event(struct mlx4_dev *dev, void *ibdev_ptr,
  2767. enum mlx4_dev_event event, unsigned long param)
  2768. {
  2769. struct ib_event ibev;
  2770. struct mlx4_ib_dev *ibdev = to_mdev((struct ib_device *) ibdev_ptr);
  2771. struct mlx4_eqe *eqe = NULL;
  2772. struct ib_event_work *ew;
  2773. int p = 0;
  2774. if (mlx4_is_bonded(dev) &&
  2775. ((event == MLX4_DEV_EVENT_PORT_UP) ||
  2776. (event == MLX4_DEV_EVENT_PORT_DOWN))) {
  2777. ew = kmalloc(sizeof(*ew), GFP_ATOMIC);
  2778. if (!ew)
  2779. return;
  2780. INIT_WORK(&ew->work, handle_bonded_port_state_event);
  2781. ew->ib_dev = ibdev;
  2782. queue_work(wq, &ew->work);
  2783. return;
  2784. }
  2785. if (event == MLX4_DEV_EVENT_PORT_MGMT_CHANGE)
  2786. eqe = (struct mlx4_eqe *)param;
  2787. else
  2788. p = (int) param;
  2789. switch (event) {
  2790. case MLX4_DEV_EVENT_PORT_UP:
  2791. if (p > ibdev->num_ports)
  2792. return;
  2793. if (!mlx4_is_slave(dev) &&
  2794. rdma_port_get_link_layer(&ibdev->ib_dev, p) ==
  2795. IB_LINK_LAYER_INFINIBAND) {
  2796. if (mlx4_is_master(dev))
  2797. mlx4_ib_invalidate_all_guid_record(ibdev, p);
  2798. if (ibdev->dev->flags & MLX4_FLAG_SECURE_HOST &&
  2799. !(ibdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_SL_TO_VL_CHANGE_EVENT))
  2800. mlx4_sched_ib_sl2vl_update_work(ibdev, p);
  2801. }
  2802. ibev.event = IB_EVENT_PORT_ACTIVE;
  2803. break;
  2804. case MLX4_DEV_EVENT_PORT_DOWN:
  2805. if (p > ibdev->num_ports)
  2806. return;
  2807. ibev.event = IB_EVENT_PORT_ERR;
  2808. break;
  2809. case MLX4_DEV_EVENT_CATASTROPHIC_ERROR:
  2810. ibdev->ib_active = false;
  2811. ibev.event = IB_EVENT_DEVICE_FATAL;
  2812. mlx4_ib_handle_catas_error(ibdev);
  2813. break;
  2814. case MLX4_DEV_EVENT_PORT_MGMT_CHANGE:
  2815. ew = kmalloc(sizeof *ew, GFP_ATOMIC);
  2816. if (!ew)
  2817. break;
  2818. INIT_WORK(&ew->work, handle_port_mgmt_change_event);
  2819. memcpy(&ew->ib_eqe, eqe, sizeof *eqe);
  2820. ew->ib_dev = ibdev;
  2821. /* need to queue only for port owner, which uses GEN_EQE */
  2822. if (mlx4_is_master(dev))
  2823. queue_work(wq, &ew->work);
  2824. else
  2825. handle_port_mgmt_change_event(&ew->work);
  2826. return;
  2827. case MLX4_DEV_EVENT_SLAVE_INIT:
  2828. /* here, p is the slave id */
  2829. do_slave_init(ibdev, p, 1);
  2830. if (mlx4_is_master(dev)) {
  2831. int i;
  2832. for (i = 1; i <= ibdev->num_ports; i++) {
  2833. if (rdma_port_get_link_layer(&ibdev->ib_dev, i)
  2834. == IB_LINK_LAYER_INFINIBAND)
  2835. mlx4_ib_slave_alias_guid_event(ibdev,
  2836. p, i,
  2837. 1);
  2838. }
  2839. }
  2840. return;
  2841. case MLX4_DEV_EVENT_SLAVE_SHUTDOWN:
  2842. if (mlx4_is_master(dev)) {
  2843. int i;
  2844. for (i = 1; i <= ibdev->num_ports; i++) {
  2845. if (rdma_port_get_link_layer(&ibdev->ib_dev, i)
  2846. == IB_LINK_LAYER_INFINIBAND)
  2847. mlx4_ib_slave_alias_guid_event(ibdev,
  2848. p, i,
  2849. 0);
  2850. }
  2851. }
  2852. /* here, p is the slave id */
  2853. do_slave_init(ibdev, p, 0);
  2854. return;
  2855. default:
  2856. return;
  2857. }
  2858. ibev.device = ibdev_ptr;
  2859. ibev.element.port_num = mlx4_is_bonded(ibdev->dev) ? 1 : (u8)p;
  2860. ib_dispatch_event(&ibev);
  2861. }
  2862. static struct mlx4_interface mlx4_ib_interface = {
  2863. .add = mlx4_ib_add,
  2864. .remove = mlx4_ib_remove,
  2865. .event = mlx4_ib_event,
  2866. .protocol = MLX4_PROT_IB_IPV6,
  2867. .flags = MLX4_INTFF_BONDING
  2868. };
  2869. static int __init mlx4_ib_init(void)
  2870. {
  2871. int err;
  2872. wq = alloc_ordered_workqueue("mlx4_ib", WQ_MEM_RECLAIM);
  2873. if (!wq)
  2874. return -ENOMEM;
  2875. err = mlx4_ib_mcg_init();
  2876. if (err)
  2877. goto clean_wq;
  2878. err = mlx4_register_interface(&mlx4_ib_interface);
  2879. if (err)
  2880. goto clean_mcg;
  2881. return 0;
  2882. clean_mcg:
  2883. mlx4_ib_mcg_destroy();
  2884. clean_wq:
  2885. destroy_workqueue(wq);
  2886. return err;
  2887. }
  2888. static void __exit mlx4_ib_cleanup(void)
  2889. {
  2890. mlx4_unregister_interface(&mlx4_ib_interface);
  2891. mlx4_ib_mcg_destroy();
  2892. destroy_workqueue(wq);
  2893. }
  2894. module_init(mlx4_ib_init);
  2895. module_exit(mlx4_ib_cleanup);