gfx_v8_0.c 147 KB

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  1. /*
  2. * Copyright 2014 Advanced Micro Devices, Inc.
  3. *
  4. * Permission is hereby granted, free of charge, to any person obtaining a
  5. * copy of this software and associated documentation files (the "Software"),
  6. * to deal in the Software without restriction, including without limitation
  7. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8. * and/or sell copies of the Software, and to permit persons to whom the
  9. * Software is furnished to do so, subject to the following conditions:
  10. *
  11. * The above copyright notice and this permission notice shall be included in
  12. * all copies or substantial portions of the Software.
  13. *
  14. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  17. * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18. * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19. * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20. * OTHER DEALINGS IN THE SOFTWARE.
  21. *
  22. */
  23. #include <linux/firmware.h>
  24. #include "drmP.h"
  25. #include "amdgpu.h"
  26. #include "amdgpu_gfx.h"
  27. #include "vi.h"
  28. #include "vid.h"
  29. #include "amdgpu_ucode.h"
  30. #include "clearstate_vi.h"
  31. #include "gmc/gmc_8_2_d.h"
  32. #include "gmc/gmc_8_2_sh_mask.h"
  33. #include "oss/oss_3_0_d.h"
  34. #include "oss/oss_3_0_sh_mask.h"
  35. #include "bif/bif_5_0_d.h"
  36. #include "bif/bif_5_0_sh_mask.h"
  37. #include "gca/gfx_8_0_d.h"
  38. #include "gca/gfx_8_0_enum.h"
  39. #include "gca/gfx_8_0_sh_mask.h"
  40. #include "gca/gfx_8_0_enum.h"
  41. #include "uvd/uvd_5_0_d.h"
  42. #include "uvd/uvd_5_0_sh_mask.h"
  43. #include "dce/dce_10_0_d.h"
  44. #include "dce/dce_10_0_sh_mask.h"
  45. #define GFX8_NUM_GFX_RINGS 1
  46. #define GFX8_NUM_COMPUTE_RINGS 8
  47. #define TOPAZ_GB_ADDR_CONFIG_GOLDEN 0x22010001
  48. #define CARRIZO_GB_ADDR_CONFIG_GOLDEN 0x22010001
  49. #define TONGA_GB_ADDR_CONFIG_GOLDEN 0x22011003
  50. #define ARRAY_MODE(x) ((x) << GB_TILE_MODE0__ARRAY_MODE__SHIFT)
  51. #define PIPE_CONFIG(x) ((x) << GB_TILE_MODE0__PIPE_CONFIG__SHIFT)
  52. #define TILE_SPLIT(x) ((x) << GB_TILE_MODE0__TILE_SPLIT__SHIFT)
  53. #define MICRO_TILE_MODE_NEW(x) ((x) << GB_TILE_MODE0__MICRO_TILE_MODE_NEW__SHIFT)
  54. #define SAMPLE_SPLIT(x) ((x) << GB_TILE_MODE0__SAMPLE_SPLIT__SHIFT)
  55. #define BANK_WIDTH(x) ((x) << GB_MACROTILE_MODE0__BANK_WIDTH__SHIFT)
  56. #define BANK_HEIGHT(x) ((x) << GB_MACROTILE_MODE0__BANK_HEIGHT__SHIFT)
  57. #define MACRO_TILE_ASPECT(x) ((x) << GB_MACROTILE_MODE0__MACRO_TILE_ASPECT__SHIFT)
  58. #define NUM_BANKS(x) ((x) << GB_MACROTILE_MODE0__NUM_BANKS__SHIFT)
  59. MODULE_FIRMWARE("amdgpu/carrizo_ce.bin");
  60. MODULE_FIRMWARE("amdgpu/carrizo_pfp.bin");
  61. MODULE_FIRMWARE("amdgpu/carrizo_me.bin");
  62. MODULE_FIRMWARE("amdgpu/carrizo_mec.bin");
  63. MODULE_FIRMWARE("amdgpu/carrizo_mec2.bin");
  64. MODULE_FIRMWARE("amdgpu/carrizo_rlc.bin");
  65. MODULE_FIRMWARE("amdgpu/tonga_ce.bin");
  66. MODULE_FIRMWARE("amdgpu/tonga_pfp.bin");
  67. MODULE_FIRMWARE("amdgpu/tonga_me.bin");
  68. MODULE_FIRMWARE("amdgpu/tonga_mec.bin");
  69. MODULE_FIRMWARE("amdgpu/tonga_mec2.bin");
  70. MODULE_FIRMWARE("amdgpu/tonga_rlc.bin");
  71. MODULE_FIRMWARE("amdgpu/topaz_ce.bin");
  72. MODULE_FIRMWARE("amdgpu/topaz_pfp.bin");
  73. MODULE_FIRMWARE("amdgpu/topaz_me.bin");
  74. MODULE_FIRMWARE("amdgpu/topaz_mec.bin");
  75. MODULE_FIRMWARE("amdgpu/topaz_mec2.bin");
  76. MODULE_FIRMWARE("amdgpu/topaz_rlc.bin");
  77. MODULE_FIRMWARE("amdgpu/fiji_ce.bin");
  78. MODULE_FIRMWARE("amdgpu/fiji_pfp.bin");
  79. MODULE_FIRMWARE("amdgpu/fiji_me.bin");
  80. MODULE_FIRMWARE("amdgpu/fiji_mec.bin");
  81. MODULE_FIRMWARE("amdgpu/fiji_mec2.bin");
  82. MODULE_FIRMWARE("amdgpu/fiji_rlc.bin");
  83. static const struct amdgpu_gds_reg_offset amdgpu_gds_reg_offset[] =
  84. {
  85. {mmGDS_VMID0_BASE, mmGDS_VMID0_SIZE, mmGDS_GWS_VMID0, mmGDS_OA_VMID0},
  86. {mmGDS_VMID1_BASE, mmGDS_VMID1_SIZE, mmGDS_GWS_VMID1, mmGDS_OA_VMID1},
  87. {mmGDS_VMID2_BASE, mmGDS_VMID2_SIZE, mmGDS_GWS_VMID2, mmGDS_OA_VMID2},
  88. {mmGDS_VMID3_BASE, mmGDS_VMID3_SIZE, mmGDS_GWS_VMID3, mmGDS_OA_VMID3},
  89. {mmGDS_VMID4_BASE, mmGDS_VMID4_SIZE, mmGDS_GWS_VMID4, mmGDS_OA_VMID4},
  90. {mmGDS_VMID5_BASE, mmGDS_VMID5_SIZE, mmGDS_GWS_VMID5, mmGDS_OA_VMID5},
  91. {mmGDS_VMID6_BASE, mmGDS_VMID6_SIZE, mmGDS_GWS_VMID6, mmGDS_OA_VMID6},
  92. {mmGDS_VMID7_BASE, mmGDS_VMID7_SIZE, mmGDS_GWS_VMID7, mmGDS_OA_VMID7},
  93. {mmGDS_VMID8_BASE, mmGDS_VMID8_SIZE, mmGDS_GWS_VMID8, mmGDS_OA_VMID8},
  94. {mmGDS_VMID9_BASE, mmGDS_VMID9_SIZE, mmGDS_GWS_VMID9, mmGDS_OA_VMID9},
  95. {mmGDS_VMID10_BASE, mmGDS_VMID10_SIZE, mmGDS_GWS_VMID10, mmGDS_OA_VMID10},
  96. {mmGDS_VMID11_BASE, mmGDS_VMID11_SIZE, mmGDS_GWS_VMID11, mmGDS_OA_VMID11},
  97. {mmGDS_VMID12_BASE, mmGDS_VMID12_SIZE, mmGDS_GWS_VMID12, mmGDS_OA_VMID12},
  98. {mmGDS_VMID13_BASE, mmGDS_VMID13_SIZE, mmGDS_GWS_VMID13, mmGDS_OA_VMID13},
  99. {mmGDS_VMID14_BASE, mmGDS_VMID14_SIZE, mmGDS_GWS_VMID14, mmGDS_OA_VMID14},
  100. {mmGDS_VMID15_BASE, mmGDS_VMID15_SIZE, mmGDS_GWS_VMID15, mmGDS_OA_VMID15}
  101. };
  102. static const u32 golden_settings_tonga_a11[] =
  103. {
  104. mmCB_HW_CONTROL, 0xfffdf3cf, 0x00007208,
  105. mmCB_HW_CONTROL_3, 0x00000040, 0x00000040,
  106. mmDB_DEBUG2, 0xf00fffff, 0x00000400,
  107. mmGB_GPU_ID, 0x0000000f, 0x00000000,
  108. mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
  109. mmPA_SC_FIFO_DEPTH_CNTL, 0x000003ff, 0x000000fc,
  110. mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
  111. mmSQ_RANDOM_WAVE_PRI, 0x001fffff, 0x000006fd,
  112. mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,
  113. mmTCC_CTRL, 0x00100000, 0xf31fff7f,
  114. mmTCC_EXE_DISABLE, 0x00000002, 0x00000002,
  115. mmTCP_ADDR_CONFIG, 0x000003ff, 0x000002fb,
  116. mmTCP_CHAN_STEER_HI, 0xffffffff, 0x0000543b,
  117. mmTCP_CHAN_STEER_LO, 0xffffffff, 0xa9210876,
  118. mmVGT_RESET_DEBUG, 0x00000004, 0x00000004,
  119. };
  120. static const u32 tonga_golden_common_all[] =
  121. {
  122. mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
  123. mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x16000012,
  124. mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x0000002A,
  125. mmGB_ADDR_CONFIG, 0xffffffff, 0x22011003,
  126. mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
  127. mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
  128. mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00007FBF,
  129. mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00007FAF
  130. };
  131. static const u32 tonga_mgcg_cgcg_init[] =
  132. {
  133. mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xffffffff,
  134. mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
  135. mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
  136. mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100,
  137. mmCGTT_CP_CLK_CTRL, 0xffffffff, 0x00000100,
  138. mmCGTT_CPC_CLK_CTRL, 0xffffffff, 0x00000100,
  139. mmCGTT_CPF_CLK_CTRL, 0xffffffff, 0x40000100,
  140. mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100,
  141. mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100,
  142. mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100,
  143. mmCGTT_WD_CLK_CTRL, 0xffffffff, 0x06000100,
  144. mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100,
  145. mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100,
  146. mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100,
  147. mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100,
  148. mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100,
  149. mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100,
  150. mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100,
  151. mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100,
  152. mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100,
  153. mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100,
  154. mmCGTT_SX_CLK_CTRL4, 0xffffffff, 0x00000100,
  155. mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0x00000100,
  156. mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100,
  157. mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100,
  158. mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100,
  159. mmTA_CGTT_CTRL, 0xffffffff, 0x00000100,
  160. mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
  161. mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
  162. mmTD_CGTT_CTRL, 0xffffffff, 0x00000100,
  163. mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
  164. mmCGTS_CU0_SP0_CTRL_REG, 0xffffffff, 0x00010000,
  165. mmCGTS_CU0_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
  166. mmCGTS_CU0_TA_SQC_CTRL_REG, 0xffffffff, 0x00040007,
  167. mmCGTS_CU0_SP1_CTRL_REG, 0xffffffff, 0x00060005,
  168. mmCGTS_CU0_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
  169. mmCGTS_CU1_SP0_CTRL_REG, 0xffffffff, 0x00010000,
  170. mmCGTS_CU1_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
  171. mmCGTS_CU1_TA_CTRL_REG, 0xffffffff, 0x00040007,
  172. mmCGTS_CU1_SP1_CTRL_REG, 0xffffffff, 0x00060005,
  173. mmCGTS_CU1_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
  174. mmCGTS_CU2_SP0_CTRL_REG, 0xffffffff, 0x00010000,
  175. mmCGTS_CU2_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
  176. mmCGTS_CU2_TA_CTRL_REG, 0xffffffff, 0x00040007,
  177. mmCGTS_CU2_SP1_CTRL_REG, 0xffffffff, 0x00060005,
  178. mmCGTS_CU2_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
  179. mmCGTS_CU3_SP0_CTRL_REG, 0xffffffff, 0x00010000,
  180. mmCGTS_CU3_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
  181. mmCGTS_CU3_TA_CTRL_REG, 0xffffffff, 0x00040007,
  182. mmCGTS_CU3_SP1_CTRL_REG, 0xffffffff, 0x00060005,
  183. mmCGTS_CU3_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
  184. mmCGTS_CU4_SP0_CTRL_REG, 0xffffffff, 0x00010000,
  185. mmCGTS_CU4_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
  186. mmCGTS_CU4_TA_SQC_CTRL_REG, 0xffffffff, 0x00040007,
  187. mmCGTS_CU4_SP1_CTRL_REG, 0xffffffff, 0x00060005,
  188. mmCGTS_CU4_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
  189. mmCGTS_CU5_SP0_CTRL_REG, 0xffffffff, 0x00010000,
  190. mmCGTS_CU5_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
  191. mmCGTS_CU5_TA_CTRL_REG, 0xffffffff, 0x00040007,
  192. mmCGTS_CU5_SP1_CTRL_REG, 0xffffffff, 0x00060005,
  193. mmCGTS_CU5_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
  194. mmCGTS_CU6_SP0_CTRL_REG, 0xffffffff, 0x00010000,
  195. mmCGTS_CU6_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
  196. mmCGTS_CU6_TA_CTRL_REG, 0xffffffff, 0x00040007,
  197. mmCGTS_CU6_SP1_CTRL_REG, 0xffffffff, 0x00060005,
  198. mmCGTS_CU6_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
  199. mmCGTS_CU7_SP0_CTRL_REG, 0xffffffff, 0x00010000,
  200. mmCGTS_CU7_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
  201. mmCGTS_CU7_TA_CTRL_REG, 0xffffffff, 0x00040007,
  202. mmCGTS_CU7_SP1_CTRL_REG, 0xffffffff, 0x00060005,
  203. mmCGTS_CU7_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
  204. mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96e00200,
  205. mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100,
  206. mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003c,
  207. mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001,
  208. };
  209. static const u32 fiji_golden_common_all[] =
  210. {
  211. mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
  212. mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x3a00161a,
  213. mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x0000002e,
  214. mmGB_ADDR_CONFIG, 0xffffffff, 0x12011003,
  215. mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
  216. mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
  217. mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00007FBF,
  218. mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00007FAF
  219. };
  220. static const u32 golden_settings_fiji_a10[] =
  221. {
  222. mmCB_HW_CONTROL_3, 0x000001ff, 0x00000040,
  223. mmDB_DEBUG2, 0xf00fffff, 0x00000400,
  224. mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
  225. mmPA_SC_FIFO_DEPTH_CNTL, 0x000003ff, 0x00000100,
  226. mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
  227. mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,
  228. mmTCC_CTRL, 0x00100000, 0xf30fff7f,
  229. mmTCP_ADDR_CONFIG, 0x000003ff, 0x000000ff,
  230. mmTCP_CHAN_STEER_HI, 0xffffffff, 0x7d6cf5e4,
  231. mmTCP_CHAN_STEER_LO, 0xffffffff, 0x3928b1a0,
  232. };
  233. static const u32 fiji_mgcg_cgcg_init[] =
  234. {
  235. mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xffffffc0,
  236. mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
  237. mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
  238. mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100,
  239. mmCGTT_CP_CLK_CTRL, 0xffffffff, 0x00000100,
  240. mmCGTT_CPC_CLK_CTRL, 0xffffffff, 0x00000100,
  241. mmCGTT_CPF_CLK_CTRL, 0xffffffff, 0x40000100,
  242. mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100,
  243. mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100,
  244. mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100,
  245. mmCGTT_WD_CLK_CTRL, 0xffffffff, 0x06000100,
  246. mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100,
  247. mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100,
  248. mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100,
  249. mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100,
  250. mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100,
  251. mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100,
  252. mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100,
  253. mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100,
  254. mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100,
  255. mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100,
  256. mmCGTT_SX_CLK_CTRL4, 0xffffffff, 0x00000100,
  257. mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0x00000100,
  258. mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100,
  259. mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100,
  260. mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100,
  261. mmTA_CGTT_CTRL, 0xffffffff, 0x00000100,
  262. mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
  263. mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
  264. mmTD_CGTT_CTRL, 0xffffffff, 0x00000100,
  265. mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
  266. mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96e00200,
  267. mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100,
  268. mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003c,
  269. mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001,
  270. };
  271. static const u32 golden_settings_iceland_a11[] =
  272. {
  273. mmCB_HW_CONTROL_3, 0x00000040, 0x00000040,
  274. mmDB_DEBUG2, 0xf00fffff, 0x00000400,
  275. mmDB_DEBUG3, 0xc0000000, 0xc0000000,
  276. mmGB_GPU_ID, 0x0000000f, 0x00000000,
  277. mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
  278. mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
  279. mmPA_SC_RASTER_CONFIG, 0x3f3fffff, 0x00000002,
  280. mmPA_SC_RASTER_CONFIG_1, 0x0000003f, 0x00000000,
  281. mmSQ_RANDOM_WAVE_PRI, 0x001fffff, 0x000006fd,
  282. mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,
  283. mmTCC_CTRL, 0x00100000, 0xf31fff7f,
  284. mmTCC_EXE_DISABLE, 0x00000002, 0x00000002,
  285. mmTCP_ADDR_CONFIG, 0x000003ff, 0x000000f1,
  286. mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000,
  287. mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00000010,
  288. };
  289. static const u32 iceland_golden_common_all[] =
  290. {
  291. mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
  292. mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x00000002,
  293. mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x00000000,
  294. mmGB_ADDR_CONFIG, 0xffffffff, 0x22010001,
  295. mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
  296. mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
  297. mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00007FBF,
  298. mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00007FAF
  299. };
  300. static const u32 iceland_mgcg_cgcg_init[] =
  301. {
  302. mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xffffffff,
  303. mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
  304. mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
  305. mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100,
  306. mmCGTT_CP_CLK_CTRL, 0xffffffff, 0xc0000100,
  307. mmCGTT_CPC_CLK_CTRL, 0xffffffff, 0xc0000100,
  308. mmCGTT_CPF_CLK_CTRL, 0xffffffff, 0xc0000100,
  309. mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100,
  310. mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100,
  311. mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100,
  312. mmCGTT_WD_CLK_CTRL, 0xffffffff, 0x06000100,
  313. mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100,
  314. mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100,
  315. mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100,
  316. mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100,
  317. mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100,
  318. mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100,
  319. mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100,
  320. mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100,
  321. mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100,
  322. mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100,
  323. mmCGTT_SX_CLK_CTRL4, 0xffffffff, 0x00000100,
  324. mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0xff000100,
  325. mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100,
  326. mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100,
  327. mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100,
  328. mmTA_CGTT_CTRL, 0xffffffff, 0x00000100,
  329. mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
  330. mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
  331. mmTD_CGTT_CTRL, 0xffffffff, 0x00000100,
  332. mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
  333. mmCGTS_CU0_SP0_CTRL_REG, 0xffffffff, 0x00010000,
  334. mmCGTS_CU0_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
  335. mmCGTS_CU0_TA_SQC_CTRL_REG, 0xffffffff, 0x0f840f87,
  336. mmCGTS_CU0_SP1_CTRL_REG, 0xffffffff, 0x00060005,
  337. mmCGTS_CU0_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
  338. mmCGTS_CU1_SP0_CTRL_REG, 0xffffffff, 0x00010000,
  339. mmCGTS_CU1_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
  340. mmCGTS_CU1_TA_CTRL_REG, 0xffffffff, 0x00040007,
  341. mmCGTS_CU1_SP1_CTRL_REG, 0xffffffff, 0x00060005,
  342. mmCGTS_CU1_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
  343. mmCGTS_CU2_SP0_CTRL_REG, 0xffffffff, 0x00010000,
  344. mmCGTS_CU2_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
  345. mmCGTS_CU2_TA_CTRL_REG, 0xffffffff, 0x00040007,
  346. mmCGTS_CU2_SP1_CTRL_REG, 0xffffffff, 0x00060005,
  347. mmCGTS_CU2_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
  348. mmCGTS_CU3_SP0_CTRL_REG, 0xffffffff, 0x00010000,
  349. mmCGTS_CU3_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
  350. mmCGTS_CU3_TA_CTRL_REG, 0xffffffff, 0x00040007,
  351. mmCGTS_CU3_SP1_CTRL_REG, 0xffffffff, 0x00060005,
  352. mmCGTS_CU3_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
  353. mmCGTS_CU4_SP0_CTRL_REG, 0xffffffff, 0x00010000,
  354. mmCGTS_CU4_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
  355. mmCGTS_CU4_TA_SQC_CTRL_REG, 0xffffffff, 0x0f840f87,
  356. mmCGTS_CU4_SP1_CTRL_REG, 0xffffffff, 0x00060005,
  357. mmCGTS_CU4_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
  358. mmCGTS_CU5_SP0_CTRL_REG, 0xffffffff, 0x00010000,
  359. mmCGTS_CU5_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
  360. mmCGTS_CU5_TA_CTRL_REG, 0xffffffff, 0x00040007,
  361. mmCGTS_CU5_SP1_CTRL_REG, 0xffffffff, 0x00060005,
  362. mmCGTS_CU5_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
  363. mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96e00200,
  364. mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100,
  365. mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003c,
  366. };
  367. static const u32 cz_golden_settings_a11[] =
  368. {
  369. mmCB_HW_CONTROL_3, 0x00000040, 0x00000040,
  370. mmDB_DEBUG2, 0xf00fffff, 0x00000400,
  371. mmGB_GPU_ID, 0x0000000f, 0x00000000,
  372. mmPA_SC_ENHANCE, 0xffffffff, 0x00000001,
  373. mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
  374. mmSQ_RANDOM_WAVE_PRI, 0x001fffff, 0x000006fd,
  375. mmTA_CNTL_AUX, 0x000f000f, 0x00010000,
  376. mmTCC_EXE_DISABLE, 0x00000002, 0x00000002,
  377. mmTCP_ADDR_CONFIG, 0x0000000f, 0x000000f3,
  378. mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00001302
  379. };
  380. static const u32 cz_golden_common_all[] =
  381. {
  382. mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
  383. mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x00000002,
  384. mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x00000000,
  385. mmGB_ADDR_CONFIG, 0xffffffff, 0x22010001,
  386. mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
  387. mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
  388. mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00007FBF,
  389. mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00007FAF
  390. };
  391. static const u32 cz_mgcg_cgcg_init[] =
  392. {
  393. mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xffffffff,
  394. mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
  395. mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
  396. mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100,
  397. mmCGTT_CP_CLK_CTRL, 0xffffffff, 0x00000100,
  398. mmCGTT_CPC_CLK_CTRL, 0xffffffff, 0x00000100,
  399. mmCGTT_CPF_CLK_CTRL, 0xffffffff, 0x00000100,
  400. mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100,
  401. mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100,
  402. mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100,
  403. mmCGTT_WD_CLK_CTRL, 0xffffffff, 0x06000100,
  404. mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100,
  405. mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100,
  406. mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100,
  407. mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100,
  408. mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100,
  409. mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100,
  410. mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100,
  411. mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100,
  412. mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100,
  413. mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100,
  414. mmCGTT_SX_CLK_CTRL4, 0xffffffff, 0x00000100,
  415. mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0x00000100,
  416. mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100,
  417. mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100,
  418. mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100,
  419. mmTA_CGTT_CTRL, 0xffffffff, 0x00000100,
  420. mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
  421. mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
  422. mmTD_CGTT_CTRL, 0xffffffff, 0x00000100,
  423. mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
  424. mmCGTS_CU0_SP0_CTRL_REG, 0xffffffff, 0x00010000,
  425. mmCGTS_CU0_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
  426. mmCGTS_CU0_TA_SQC_CTRL_REG, 0xffffffff, 0x00040007,
  427. mmCGTS_CU0_SP1_CTRL_REG, 0xffffffff, 0x00060005,
  428. mmCGTS_CU0_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
  429. mmCGTS_CU1_SP0_CTRL_REG, 0xffffffff, 0x00010000,
  430. mmCGTS_CU1_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
  431. mmCGTS_CU1_TA_CTRL_REG, 0xffffffff, 0x00040007,
  432. mmCGTS_CU1_SP1_CTRL_REG, 0xffffffff, 0x00060005,
  433. mmCGTS_CU1_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
  434. mmCGTS_CU2_SP0_CTRL_REG, 0xffffffff, 0x00010000,
  435. mmCGTS_CU2_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
  436. mmCGTS_CU2_TA_CTRL_REG, 0xffffffff, 0x00040007,
  437. mmCGTS_CU2_SP1_CTRL_REG, 0xffffffff, 0x00060005,
  438. mmCGTS_CU2_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
  439. mmCGTS_CU3_SP0_CTRL_REG, 0xffffffff, 0x00010000,
  440. mmCGTS_CU3_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
  441. mmCGTS_CU3_TA_CTRL_REG, 0xffffffff, 0x00040007,
  442. mmCGTS_CU3_SP1_CTRL_REG, 0xffffffff, 0x00060005,
  443. mmCGTS_CU3_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
  444. mmCGTS_CU4_SP0_CTRL_REG, 0xffffffff, 0x00010000,
  445. mmCGTS_CU4_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
  446. mmCGTS_CU4_TA_SQC_CTRL_REG, 0xffffffff, 0x00040007,
  447. mmCGTS_CU4_SP1_CTRL_REG, 0xffffffff, 0x00060005,
  448. mmCGTS_CU4_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
  449. mmCGTS_CU5_SP0_CTRL_REG, 0xffffffff, 0x00010000,
  450. mmCGTS_CU5_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
  451. mmCGTS_CU5_TA_CTRL_REG, 0xffffffff, 0x00040007,
  452. mmCGTS_CU5_SP1_CTRL_REG, 0xffffffff, 0x00060005,
  453. mmCGTS_CU5_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
  454. mmCGTS_CU6_SP0_CTRL_REG, 0xffffffff, 0x00010000,
  455. mmCGTS_CU6_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
  456. mmCGTS_CU6_TA_CTRL_REG, 0xffffffff, 0x00040007,
  457. mmCGTS_CU6_SP1_CTRL_REG, 0xffffffff, 0x00060005,
  458. mmCGTS_CU6_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
  459. mmCGTS_CU7_SP0_CTRL_REG, 0xffffffff, 0x00010000,
  460. mmCGTS_CU7_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
  461. mmCGTS_CU7_TA_CTRL_REG, 0xffffffff, 0x00040007,
  462. mmCGTS_CU7_SP1_CTRL_REG, 0xffffffff, 0x00060005,
  463. mmCGTS_CU7_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
  464. mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96e00200,
  465. mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100,
  466. mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003f,
  467. mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001,
  468. };
  469. static void gfx_v8_0_set_ring_funcs(struct amdgpu_device *adev);
  470. static void gfx_v8_0_set_irq_funcs(struct amdgpu_device *adev);
  471. static void gfx_v8_0_set_gds_init(struct amdgpu_device *adev);
  472. static void gfx_v8_0_init_golden_registers(struct amdgpu_device *adev)
  473. {
  474. switch (adev->asic_type) {
  475. case CHIP_TOPAZ:
  476. amdgpu_program_register_sequence(adev,
  477. iceland_mgcg_cgcg_init,
  478. (const u32)ARRAY_SIZE(iceland_mgcg_cgcg_init));
  479. amdgpu_program_register_sequence(adev,
  480. golden_settings_iceland_a11,
  481. (const u32)ARRAY_SIZE(golden_settings_iceland_a11));
  482. amdgpu_program_register_sequence(adev,
  483. iceland_golden_common_all,
  484. (const u32)ARRAY_SIZE(iceland_golden_common_all));
  485. break;
  486. case CHIP_FIJI:
  487. amdgpu_program_register_sequence(adev,
  488. fiji_mgcg_cgcg_init,
  489. (const u32)ARRAY_SIZE(fiji_mgcg_cgcg_init));
  490. amdgpu_program_register_sequence(adev,
  491. golden_settings_fiji_a10,
  492. (const u32)ARRAY_SIZE(golden_settings_fiji_a10));
  493. amdgpu_program_register_sequence(adev,
  494. fiji_golden_common_all,
  495. (const u32)ARRAY_SIZE(fiji_golden_common_all));
  496. break;
  497. case CHIP_TONGA:
  498. amdgpu_program_register_sequence(adev,
  499. tonga_mgcg_cgcg_init,
  500. (const u32)ARRAY_SIZE(tonga_mgcg_cgcg_init));
  501. amdgpu_program_register_sequence(adev,
  502. golden_settings_tonga_a11,
  503. (const u32)ARRAY_SIZE(golden_settings_tonga_a11));
  504. amdgpu_program_register_sequence(adev,
  505. tonga_golden_common_all,
  506. (const u32)ARRAY_SIZE(tonga_golden_common_all));
  507. break;
  508. case CHIP_CARRIZO:
  509. amdgpu_program_register_sequence(adev,
  510. cz_mgcg_cgcg_init,
  511. (const u32)ARRAY_SIZE(cz_mgcg_cgcg_init));
  512. amdgpu_program_register_sequence(adev,
  513. cz_golden_settings_a11,
  514. (const u32)ARRAY_SIZE(cz_golden_settings_a11));
  515. amdgpu_program_register_sequence(adev,
  516. cz_golden_common_all,
  517. (const u32)ARRAY_SIZE(cz_golden_common_all));
  518. break;
  519. default:
  520. break;
  521. }
  522. }
  523. static void gfx_v8_0_scratch_init(struct amdgpu_device *adev)
  524. {
  525. int i;
  526. adev->gfx.scratch.num_reg = 7;
  527. adev->gfx.scratch.reg_base = mmSCRATCH_REG0;
  528. for (i = 0; i < adev->gfx.scratch.num_reg; i++) {
  529. adev->gfx.scratch.free[i] = true;
  530. adev->gfx.scratch.reg[i] = adev->gfx.scratch.reg_base + i;
  531. }
  532. }
  533. static int gfx_v8_0_ring_test_ring(struct amdgpu_ring *ring)
  534. {
  535. struct amdgpu_device *adev = ring->adev;
  536. uint32_t scratch;
  537. uint32_t tmp = 0;
  538. unsigned i;
  539. int r;
  540. r = amdgpu_gfx_scratch_get(adev, &scratch);
  541. if (r) {
  542. DRM_ERROR("amdgpu: cp failed to get scratch reg (%d).\n", r);
  543. return r;
  544. }
  545. WREG32(scratch, 0xCAFEDEAD);
  546. r = amdgpu_ring_lock(ring, 3);
  547. if (r) {
  548. DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n",
  549. ring->idx, r);
  550. amdgpu_gfx_scratch_free(adev, scratch);
  551. return r;
  552. }
  553. amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
  554. amdgpu_ring_write(ring, (scratch - PACKET3_SET_UCONFIG_REG_START));
  555. amdgpu_ring_write(ring, 0xDEADBEEF);
  556. amdgpu_ring_unlock_commit(ring);
  557. for (i = 0; i < adev->usec_timeout; i++) {
  558. tmp = RREG32(scratch);
  559. if (tmp == 0xDEADBEEF)
  560. break;
  561. DRM_UDELAY(1);
  562. }
  563. if (i < adev->usec_timeout) {
  564. DRM_INFO("ring test on %d succeeded in %d usecs\n",
  565. ring->idx, i);
  566. } else {
  567. DRM_ERROR("amdgpu: ring %d test failed (scratch(0x%04X)=0x%08X)\n",
  568. ring->idx, scratch, tmp);
  569. r = -EINVAL;
  570. }
  571. amdgpu_gfx_scratch_free(adev, scratch);
  572. return r;
  573. }
  574. static int gfx_v8_0_ring_test_ib(struct amdgpu_ring *ring)
  575. {
  576. struct amdgpu_device *adev = ring->adev;
  577. struct amdgpu_ib ib;
  578. uint32_t scratch;
  579. uint32_t tmp = 0;
  580. unsigned i;
  581. int r;
  582. r = amdgpu_gfx_scratch_get(adev, &scratch);
  583. if (r) {
  584. DRM_ERROR("amdgpu: failed to get scratch reg (%d).\n", r);
  585. return r;
  586. }
  587. WREG32(scratch, 0xCAFEDEAD);
  588. r = amdgpu_ib_get(ring, NULL, 256, &ib);
  589. if (r) {
  590. DRM_ERROR("amdgpu: failed to get ib (%d).\n", r);
  591. amdgpu_gfx_scratch_free(adev, scratch);
  592. return r;
  593. }
  594. ib.ptr[0] = PACKET3(PACKET3_SET_UCONFIG_REG, 1);
  595. ib.ptr[1] = ((scratch - PACKET3_SET_UCONFIG_REG_START));
  596. ib.ptr[2] = 0xDEADBEEF;
  597. ib.length_dw = 3;
  598. r = amdgpu_ib_schedule(adev, 1, &ib, AMDGPU_FENCE_OWNER_UNDEFINED);
  599. if (r) {
  600. amdgpu_gfx_scratch_free(adev, scratch);
  601. amdgpu_ib_free(adev, &ib);
  602. DRM_ERROR("amdgpu: failed to schedule ib (%d).\n", r);
  603. return r;
  604. }
  605. r = amdgpu_fence_wait(ib.fence, false);
  606. if (r) {
  607. DRM_ERROR("amdgpu: fence wait failed (%d).\n", r);
  608. amdgpu_gfx_scratch_free(adev, scratch);
  609. amdgpu_ib_free(adev, &ib);
  610. return r;
  611. }
  612. for (i = 0; i < adev->usec_timeout; i++) {
  613. tmp = RREG32(scratch);
  614. if (tmp == 0xDEADBEEF)
  615. break;
  616. DRM_UDELAY(1);
  617. }
  618. if (i < adev->usec_timeout) {
  619. DRM_INFO("ib test on ring %d succeeded in %u usecs\n",
  620. ib.fence->ring->idx, i);
  621. } else {
  622. DRM_ERROR("amdgpu: ib test failed (scratch(0x%04X)=0x%08X)\n",
  623. scratch, tmp);
  624. r = -EINVAL;
  625. }
  626. amdgpu_gfx_scratch_free(adev, scratch);
  627. amdgpu_ib_free(adev, &ib);
  628. return r;
  629. }
  630. static int gfx_v8_0_init_microcode(struct amdgpu_device *adev)
  631. {
  632. const char *chip_name;
  633. char fw_name[30];
  634. int err;
  635. struct amdgpu_firmware_info *info = NULL;
  636. const struct common_firmware_header *header = NULL;
  637. const struct gfx_firmware_header_v1_0 *cp_hdr;
  638. DRM_DEBUG("\n");
  639. switch (adev->asic_type) {
  640. case CHIP_TOPAZ:
  641. chip_name = "topaz";
  642. break;
  643. case CHIP_TONGA:
  644. chip_name = "tonga";
  645. break;
  646. case CHIP_CARRIZO:
  647. chip_name = "carrizo";
  648. break;
  649. case CHIP_FIJI:
  650. chip_name = "fiji";
  651. break;
  652. default:
  653. BUG();
  654. }
  655. snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp.bin", chip_name);
  656. err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev);
  657. if (err)
  658. goto out;
  659. err = amdgpu_ucode_validate(adev->gfx.pfp_fw);
  660. if (err)
  661. goto out;
  662. cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
  663. adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
  664. adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
  665. snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me.bin", chip_name);
  666. err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev);
  667. if (err)
  668. goto out;
  669. err = amdgpu_ucode_validate(adev->gfx.me_fw);
  670. if (err)
  671. goto out;
  672. cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
  673. adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
  674. adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
  675. snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce.bin", chip_name);
  676. err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev);
  677. if (err)
  678. goto out;
  679. err = amdgpu_ucode_validate(adev->gfx.ce_fw);
  680. if (err)
  681. goto out;
  682. cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
  683. adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
  684. adev->gfx.ce_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
  685. snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name);
  686. err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev);
  687. if (err)
  688. goto out;
  689. err = amdgpu_ucode_validate(adev->gfx.rlc_fw);
  690. cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.rlc_fw->data;
  691. adev->gfx.rlc_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
  692. adev->gfx.rlc_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
  693. snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin", chip_name);
  694. err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev);
  695. if (err)
  696. goto out;
  697. err = amdgpu_ucode_validate(adev->gfx.mec_fw);
  698. if (err)
  699. goto out;
  700. cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
  701. adev->gfx.mec_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
  702. adev->gfx.mec_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
  703. snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2.bin", chip_name);
  704. err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev);
  705. if (!err) {
  706. err = amdgpu_ucode_validate(adev->gfx.mec2_fw);
  707. if (err)
  708. goto out;
  709. cp_hdr = (const struct gfx_firmware_header_v1_0 *)
  710. adev->gfx.mec2_fw->data;
  711. adev->gfx.mec2_fw_version = le32_to_cpu(
  712. cp_hdr->header.ucode_version);
  713. adev->gfx.mec2_feature_version = le32_to_cpu(
  714. cp_hdr->ucode_feature_version);
  715. } else {
  716. err = 0;
  717. adev->gfx.mec2_fw = NULL;
  718. }
  719. if (adev->firmware.smu_load) {
  720. info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_PFP];
  721. info->ucode_id = AMDGPU_UCODE_ID_CP_PFP;
  722. info->fw = adev->gfx.pfp_fw;
  723. header = (const struct common_firmware_header *)info->fw->data;
  724. adev->firmware.fw_size +=
  725. ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
  726. info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_ME];
  727. info->ucode_id = AMDGPU_UCODE_ID_CP_ME;
  728. info->fw = adev->gfx.me_fw;
  729. header = (const struct common_firmware_header *)info->fw->data;
  730. adev->firmware.fw_size +=
  731. ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
  732. info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_CE];
  733. info->ucode_id = AMDGPU_UCODE_ID_CP_CE;
  734. info->fw = adev->gfx.ce_fw;
  735. header = (const struct common_firmware_header *)info->fw->data;
  736. adev->firmware.fw_size +=
  737. ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
  738. info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_G];
  739. info->ucode_id = AMDGPU_UCODE_ID_RLC_G;
  740. info->fw = adev->gfx.rlc_fw;
  741. header = (const struct common_firmware_header *)info->fw->data;
  742. adev->firmware.fw_size +=
  743. ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
  744. info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1];
  745. info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1;
  746. info->fw = adev->gfx.mec_fw;
  747. header = (const struct common_firmware_header *)info->fw->data;
  748. adev->firmware.fw_size +=
  749. ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
  750. if (adev->gfx.mec2_fw) {
  751. info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2];
  752. info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2;
  753. info->fw = adev->gfx.mec2_fw;
  754. header = (const struct common_firmware_header *)info->fw->data;
  755. adev->firmware.fw_size +=
  756. ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
  757. }
  758. }
  759. out:
  760. if (err) {
  761. dev_err(adev->dev,
  762. "gfx8: Failed to load firmware \"%s\"\n",
  763. fw_name);
  764. release_firmware(adev->gfx.pfp_fw);
  765. adev->gfx.pfp_fw = NULL;
  766. release_firmware(adev->gfx.me_fw);
  767. adev->gfx.me_fw = NULL;
  768. release_firmware(adev->gfx.ce_fw);
  769. adev->gfx.ce_fw = NULL;
  770. release_firmware(adev->gfx.rlc_fw);
  771. adev->gfx.rlc_fw = NULL;
  772. release_firmware(adev->gfx.mec_fw);
  773. adev->gfx.mec_fw = NULL;
  774. release_firmware(adev->gfx.mec2_fw);
  775. adev->gfx.mec2_fw = NULL;
  776. }
  777. return err;
  778. }
  779. static void gfx_v8_0_mec_fini(struct amdgpu_device *adev)
  780. {
  781. int r;
  782. if (adev->gfx.mec.hpd_eop_obj) {
  783. r = amdgpu_bo_reserve(adev->gfx.mec.hpd_eop_obj, false);
  784. if (unlikely(r != 0))
  785. dev_warn(adev->dev, "(%d) reserve HPD EOP bo failed\n", r);
  786. amdgpu_bo_unpin(adev->gfx.mec.hpd_eop_obj);
  787. amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
  788. amdgpu_bo_unref(&adev->gfx.mec.hpd_eop_obj);
  789. adev->gfx.mec.hpd_eop_obj = NULL;
  790. }
  791. }
  792. #define MEC_HPD_SIZE 2048
  793. static int gfx_v8_0_mec_init(struct amdgpu_device *adev)
  794. {
  795. int r;
  796. u32 *hpd;
  797. /*
  798. * we assign only 1 pipe because all other pipes will
  799. * be handled by KFD
  800. */
  801. adev->gfx.mec.num_mec = 1;
  802. adev->gfx.mec.num_pipe = 1;
  803. adev->gfx.mec.num_queue = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe * 8;
  804. if (adev->gfx.mec.hpd_eop_obj == NULL) {
  805. r = amdgpu_bo_create(adev,
  806. adev->gfx.mec.num_mec *adev->gfx.mec.num_pipe * MEC_HPD_SIZE * 2,
  807. PAGE_SIZE, true,
  808. AMDGPU_GEM_DOMAIN_GTT, 0, NULL,
  809. &adev->gfx.mec.hpd_eop_obj);
  810. if (r) {
  811. dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r);
  812. return r;
  813. }
  814. }
  815. r = amdgpu_bo_reserve(adev->gfx.mec.hpd_eop_obj, false);
  816. if (unlikely(r != 0)) {
  817. gfx_v8_0_mec_fini(adev);
  818. return r;
  819. }
  820. r = amdgpu_bo_pin(adev->gfx.mec.hpd_eop_obj, AMDGPU_GEM_DOMAIN_GTT,
  821. &adev->gfx.mec.hpd_eop_gpu_addr);
  822. if (r) {
  823. dev_warn(adev->dev, "(%d) pin HDP EOP bo failed\n", r);
  824. gfx_v8_0_mec_fini(adev);
  825. return r;
  826. }
  827. r = amdgpu_bo_kmap(adev->gfx.mec.hpd_eop_obj, (void **)&hpd);
  828. if (r) {
  829. dev_warn(adev->dev, "(%d) map HDP EOP bo failed\n", r);
  830. gfx_v8_0_mec_fini(adev);
  831. return r;
  832. }
  833. memset(hpd, 0, adev->gfx.mec.num_mec *adev->gfx.mec.num_pipe * MEC_HPD_SIZE * 2);
  834. amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj);
  835. amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
  836. return 0;
  837. }
  838. static int gfx_v8_0_sw_init(void *handle)
  839. {
  840. int i, r;
  841. struct amdgpu_ring *ring;
  842. struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  843. /* EOP Event */
  844. r = amdgpu_irq_add_id(adev, 181, &adev->gfx.eop_irq);
  845. if (r)
  846. return r;
  847. /* Privileged reg */
  848. r = amdgpu_irq_add_id(adev, 184, &adev->gfx.priv_reg_irq);
  849. if (r)
  850. return r;
  851. /* Privileged inst */
  852. r = amdgpu_irq_add_id(adev, 185, &adev->gfx.priv_inst_irq);
  853. if (r)
  854. return r;
  855. adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE;
  856. gfx_v8_0_scratch_init(adev);
  857. r = gfx_v8_0_init_microcode(adev);
  858. if (r) {
  859. DRM_ERROR("Failed to load gfx firmware!\n");
  860. return r;
  861. }
  862. r = gfx_v8_0_mec_init(adev);
  863. if (r) {
  864. DRM_ERROR("Failed to init MEC BOs!\n");
  865. return r;
  866. }
  867. r = amdgpu_wb_get(adev, &adev->gfx.ce_sync_offs);
  868. if (r) {
  869. DRM_ERROR("(%d) gfx.ce_sync_offs wb alloc failed\n", r);
  870. return r;
  871. }
  872. /* set up the gfx ring */
  873. for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
  874. ring = &adev->gfx.gfx_ring[i];
  875. ring->ring_obj = NULL;
  876. sprintf(ring->name, "gfx");
  877. /* no gfx doorbells on iceland */
  878. if (adev->asic_type != CHIP_TOPAZ) {
  879. ring->use_doorbell = true;
  880. ring->doorbell_index = AMDGPU_DOORBELL_GFX_RING0;
  881. }
  882. r = amdgpu_ring_init(adev, ring, 1024 * 1024,
  883. PACKET3(PACKET3_NOP, 0x3FFF), 0xf,
  884. &adev->gfx.eop_irq, AMDGPU_CP_IRQ_GFX_EOP,
  885. AMDGPU_RING_TYPE_GFX);
  886. if (r)
  887. return r;
  888. }
  889. /* set up the compute queues */
  890. for (i = 0; i < adev->gfx.num_compute_rings; i++) {
  891. unsigned irq_type;
  892. /* max 32 queues per MEC */
  893. if ((i >= 32) || (i >= AMDGPU_MAX_COMPUTE_RINGS)) {
  894. DRM_ERROR("Too many (%d) compute rings!\n", i);
  895. break;
  896. }
  897. ring = &adev->gfx.compute_ring[i];
  898. ring->ring_obj = NULL;
  899. ring->use_doorbell = true;
  900. ring->doorbell_index = AMDGPU_DOORBELL_MEC_RING0 + i;
  901. ring->me = 1; /* first MEC */
  902. ring->pipe = i / 8;
  903. ring->queue = i % 8;
  904. sprintf(ring->name, "comp %d.%d.%d", ring->me, ring->pipe, ring->queue);
  905. irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP + ring->pipe;
  906. /* type-2 packets are deprecated on MEC, use type-3 instead */
  907. r = amdgpu_ring_init(adev, ring, 1024 * 1024,
  908. PACKET3(PACKET3_NOP, 0x3FFF), 0xf,
  909. &adev->gfx.eop_irq, irq_type,
  910. AMDGPU_RING_TYPE_COMPUTE);
  911. if (r)
  912. return r;
  913. }
  914. /* reserve GDS, GWS and OA resource for gfx */
  915. r = amdgpu_bo_create(adev, adev->gds.mem.gfx_partition_size,
  916. PAGE_SIZE, true,
  917. AMDGPU_GEM_DOMAIN_GDS, 0,
  918. NULL, &adev->gds.gds_gfx_bo);
  919. if (r)
  920. return r;
  921. r = amdgpu_bo_create(adev, adev->gds.gws.gfx_partition_size,
  922. PAGE_SIZE, true,
  923. AMDGPU_GEM_DOMAIN_GWS, 0,
  924. NULL, &adev->gds.gws_gfx_bo);
  925. if (r)
  926. return r;
  927. r = amdgpu_bo_create(adev, adev->gds.oa.gfx_partition_size,
  928. PAGE_SIZE, true,
  929. AMDGPU_GEM_DOMAIN_OA, 0,
  930. NULL, &adev->gds.oa_gfx_bo);
  931. if (r)
  932. return r;
  933. adev->gfx.ce_ram_size = 0x8000;
  934. return 0;
  935. }
  936. static int gfx_v8_0_sw_fini(void *handle)
  937. {
  938. int i;
  939. struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  940. amdgpu_bo_unref(&adev->gds.oa_gfx_bo);
  941. amdgpu_bo_unref(&adev->gds.gws_gfx_bo);
  942. amdgpu_bo_unref(&adev->gds.gds_gfx_bo);
  943. for (i = 0; i < adev->gfx.num_gfx_rings; i++)
  944. amdgpu_ring_fini(&adev->gfx.gfx_ring[i]);
  945. for (i = 0; i < adev->gfx.num_compute_rings; i++)
  946. amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
  947. amdgpu_wb_free(adev, adev->gfx.ce_sync_offs);
  948. gfx_v8_0_mec_fini(adev);
  949. return 0;
  950. }
  951. static void gfx_v8_0_tiling_mode_table_init(struct amdgpu_device *adev)
  952. {
  953. const u32 num_tile_mode_states = 32;
  954. const u32 num_secondary_tile_mode_states = 16;
  955. u32 reg_offset, gb_tile_moden, split_equal_to_row_size;
  956. switch (adev->gfx.config.mem_row_size_in_kb) {
  957. case 1:
  958. split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_1KB;
  959. break;
  960. case 2:
  961. default:
  962. split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_2KB;
  963. break;
  964. case 4:
  965. split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_4KB;
  966. break;
  967. }
  968. switch (adev->asic_type) {
  969. case CHIP_TOPAZ:
  970. for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
  971. switch (reg_offset) {
  972. case 0:
  973. gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
  974. PIPE_CONFIG(ADDR_SURF_P2) |
  975. TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
  976. MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
  977. break;
  978. case 1:
  979. gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
  980. PIPE_CONFIG(ADDR_SURF_P2) |
  981. TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
  982. MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
  983. break;
  984. case 2:
  985. gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
  986. PIPE_CONFIG(ADDR_SURF_P2) |
  987. TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
  988. MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
  989. break;
  990. case 3:
  991. gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
  992. PIPE_CONFIG(ADDR_SURF_P2) |
  993. TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
  994. MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
  995. break;
  996. case 4:
  997. gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
  998. PIPE_CONFIG(ADDR_SURF_P2) |
  999. TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
  1000. MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
  1001. break;
  1002. case 5:
  1003. gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
  1004. PIPE_CONFIG(ADDR_SURF_P2) |
  1005. TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
  1006. MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
  1007. break;
  1008. case 6:
  1009. gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
  1010. PIPE_CONFIG(ADDR_SURF_P2) |
  1011. TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
  1012. MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
  1013. break;
  1014. case 8:
  1015. gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
  1016. PIPE_CONFIG(ADDR_SURF_P2));
  1017. break;
  1018. case 9:
  1019. gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
  1020. PIPE_CONFIG(ADDR_SURF_P2) |
  1021. MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
  1022. SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
  1023. break;
  1024. case 10:
  1025. gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
  1026. PIPE_CONFIG(ADDR_SURF_P2) |
  1027. MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
  1028. SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
  1029. break;
  1030. case 11:
  1031. gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
  1032. PIPE_CONFIG(ADDR_SURF_P2) |
  1033. MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
  1034. SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
  1035. break;
  1036. case 13:
  1037. gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
  1038. PIPE_CONFIG(ADDR_SURF_P2) |
  1039. MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
  1040. SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
  1041. break;
  1042. case 14:
  1043. gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
  1044. PIPE_CONFIG(ADDR_SURF_P2) |
  1045. MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
  1046. SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
  1047. break;
  1048. case 15:
  1049. gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
  1050. PIPE_CONFIG(ADDR_SURF_P2) |
  1051. MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
  1052. SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
  1053. break;
  1054. case 16:
  1055. gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
  1056. PIPE_CONFIG(ADDR_SURF_P2) |
  1057. MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
  1058. SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
  1059. break;
  1060. case 18:
  1061. gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
  1062. PIPE_CONFIG(ADDR_SURF_P2) |
  1063. MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
  1064. SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
  1065. break;
  1066. case 19:
  1067. gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
  1068. PIPE_CONFIG(ADDR_SURF_P2) |
  1069. MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
  1070. SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
  1071. break;
  1072. case 20:
  1073. gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
  1074. PIPE_CONFIG(ADDR_SURF_P2) |
  1075. MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
  1076. SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
  1077. break;
  1078. case 21:
  1079. gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
  1080. PIPE_CONFIG(ADDR_SURF_P2) |
  1081. MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
  1082. SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
  1083. break;
  1084. case 22:
  1085. gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
  1086. PIPE_CONFIG(ADDR_SURF_P2) |
  1087. MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
  1088. SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
  1089. break;
  1090. case 24:
  1091. gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
  1092. PIPE_CONFIG(ADDR_SURF_P2) |
  1093. MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
  1094. SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
  1095. break;
  1096. case 25:
  1097. gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
  1098. PIPE_CONFIG(ADDR_SURF_P2) |
  1099. MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
  1100. SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
  1101. break;
  1102. case 26:
  1103. gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
  1104. PIPE_CONFIG(ADDR_SURF_P2) |
  1105. MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
  1106. SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
  1107. break;
  1108. case 27:
  1109. gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
  1110. PIPE_CONFIG(ADDR_SURF_P2) |
  1111. MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
  1112. SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
  1113. break;
  1114. case 28:
  1115. gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
  1116. PIPE_CONFIG(ADDR_SURF_P2) |
  1117. MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
  1118. SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
  1119. break;
  1120. case 29:
  1121. gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
  1122. PIPE_CONFIG(ADDR_SURF_P2) |
  1123. MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
  1124. SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
  1125. break;
  1126. case 7:
  1127. case 12:
  1128. case 17:
  1129. case 23:
  1130. /* unused idx */
  1131. continue;
  1132. default:
  1133. gb_tile_moden = 0;
  1134. break;
  1135. };
  1136. adev->gfx.config.tile_mode_array[reg_offset] = gb_tile_moden;
  1137. WREG32(mmGB_TILE_MODE0 + reg_offset, gb_tile_moden);
  1138. }
  1139. for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) {
  1140. switch (reg_offset) {
  1141. case 0:
  1142. gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
  1143. BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
  1144. MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
  1145. NUM_BANKS(ADDR_SURF_8_BANK));
  1146. break;
  1147. case 1:
  1148. gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
  1149. BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
  1150. MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
  1151. NUM_BANKS(ADDR_SURF_8_BANK));
  1152. break;
  1153. case 2:
  1154. gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
  1155. BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
  1156. MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
  1157. NUM_BANKS(ADDR_SURF_8_BANK));
  1158. break;
  1159. case 3:
  1160. gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
  1161. BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
  1162. MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
  1163. NUM_BANKS(ADDR_SURF_8_BANK));
  1164. break;
  1165. case 4:
  1166. gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
  1167. BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
  1168. MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
  1169. NUM_BANKS(ADDR_SURF_8_BANK));
  1170. break;
  1171. case 5:
  1172. gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
  1173. BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
  1174. MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
  1175. NUM_BANKS(ADDR_SURF_8_BANK));
  1176. break;
  1177. case 6:
  1178. gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
  1179. BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
  1180. MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
  1181. NUM_BANKS(ADDR_SURF_8_BANK));
  1182. break;
  1183. case 8:
  1184. gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
  1185. BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
  1186. MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
  1187. NUM_BANKS(ADDR_SURF_16_BANK));
  1188. break;
  1189. case 9:
  1190. gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
  1191. BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
  1192. MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
  1193. NUM_BANKS(ADDR_SURF_16_BANK));
  1194. break;
  1195. case 10:
  1196. gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
  1197. BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
  1198. MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
  1199. NUM_BANKS(ADDR_SURF_16_BANK));
  1200. break;
  1201. case 11:
  1202. gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
  1203. BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
  1204. MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
  1205. NUM_BANKS(ADDR_SURF_16_BANK));
  1206. break;
  1207. case 12:
  1208. gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
  1209. BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
  1210. MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
  1211. NUM_BANKS(ADDR_SURF_16_BANK));
  1212. break;
  1213. case 13:
  1214. gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
  1215. BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
  1216. MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
  1217. NUM_BANKS(ADDR_SURF_16_BANK));
  1218. break;
  1219. case 14:
  1220. gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
  1221. BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
  1222. MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
  1223. NUM_BANKS(ADDR_SURF_8_BANK));
  1224. break;
  1225. case 7:
  1226. /* unused idx */
  1227. continue;
  1228. default:
  1229. gb_tile_moden = 0;
  1230. break;
  1231. };
  1232. adev->gfx.config.macrotile_mode_array[reg_offset] = gb_tile_moden;
  1233. WREG32(mmGB_MACROTILE_MODE0 + reg_offset, gb_tile_moden);
  1234. }
  1235. case CHIP_FIJI:
  1236. case CHIP_TONGA:
  1237. for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
  1238. switch (reg_offset) {
  1239. case 0:
  1240. gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
  1241. PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
  1242. TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
  1243. MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
  1244. break;
  1245. case 1:
  1246. gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
  1247. PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
  1248. TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
  1249. MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
  1250. break;
  1251. case 2:
  1252. gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
  1253. PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
  1254. TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
  1255. MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
  1256. break;
  1257. case 3:
  1258. gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
  1259. PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
  1260. TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
  1261. MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
  1262. break;
  1263. case 4:
  1264. gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
  1265. PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
  1266. TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
  1267. MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
  1268. break;
  1269. case 5:
  1270. gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
  1271. PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
  1272. TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
  1273. MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
  1274. break;
  1275. case 6:
  1276. gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
  1277. PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
  1278. TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
  1279. MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
  1280. break;
  1281. case 7:
  1282. gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
  1283. PIPE_CONFIG(ADDR_SURF_P4_16x16) |
  1284. TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
  1285. MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
  1286. break;
  1287. case 8:
  1288. gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
  1289. PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16));
  1290. break;
  1291. case 9:
  1292. gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
  1293. PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
  1294. MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
  1295. SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
  1296. break;
  1297. case 10:
  1298. gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
  1299. PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
  1300. MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
  1301. SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
  1302. break;
  1303. case 11:
  1304. gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
  1305. PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
  1306. MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
  1307. SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
  1308. break;
  1309. case 12:
  1310. gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
  1311. PIPE_CONFIG(ADDR_SURF_P4_16x16) |
  1312. MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
  1313. SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
  1314. break;
  1315. case 13:
  1316. gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
  1317. PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
  1318. MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
  1319. SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
  1320. break;
  1321. case 14:
  1322. gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
  1323. PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
  1324. MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
  1325. SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
  1326. break;
  1327. case 15:
  1328. gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
  1329. PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
  1330. MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
  1331. SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
  1332. break;
  1333. case 16:
  1334. gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
  1335. PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
  1336. MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
  1337. SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
  1338. break;
  1339. case 17:
  1340. gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
  1341. PIPE_CONFIG(ADDR_SURF_P4_16x16) |
  1342. MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
  1343. SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
  1344. break;
  1345. case 18:
  1346. gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
  1347. PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
  1348. MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
  1349. SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
  1350. break;
  1351. case 19:
  1352. gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
  1353. PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
  1354. MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
  1355. SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
  1356. break;
  1357. case 20:
  1358. gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
  1359. PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
  1360. MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
  1361. SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
  1362. break;
  1363. case 21:
  1364. gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
  1365. PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
  1366. MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
  1367. SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
  1368. break;
  1369. case 22:
  1370. gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
  1371. PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
  1372. MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
  1373. SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
  1374. break;
  1375. case 23:
  1376. gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
  1377. PIPE_CONFIG(ADDR_SURF_P4_16x16) |
  1378. MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
  1379. SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
  1380. break;
  1381. case 24:
  1382. gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
  1383. PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
  1384. MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
  1385. SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
  1386. break;
  1387. case 25:
  1388. gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
  1389. PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
  1390. MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
  1391. SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
  1392. break;
  1393. case 26:
  1394. gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
  1395. PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
  1396. MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
  1397. SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
  1398. break;
  1399. case 27:
  1400. gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
  1401. PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
  1402. MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
  1403. SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
  1404. break;
  1405. case 28:
  1406. gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
  1407. PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
  1408. MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
  1409. SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
  1410. break;
  1411. case 29:
  1412. gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
  1413. PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
  1414. MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
  1415. SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
  1416. break;
  1417. case 30:
  1418. gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
  1419. PIPE_CONFIG(ADDR_SURF_P4_16x16) |
  1420. MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
  1421. SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
  1422. break;
  1423. default:
  1424. gb_tile_moden = 0;
  1425. break;
  1426. };
  1427. adev->gfx.config.tile_mode_array[reg_offset] = gb_tile_moden;
  1428. WREG32(mmGB_TILE_MODE0 + reg_offset, gb_tile_moden);
  1429. }
  1430. for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) {
  1431. switch (reg_offset) {
  1432. case 0:
  1433. gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
  1434. BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
  1435. MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
  1436. NUM_BANKS(ADDR_SURF_16_BANK));
  1437. break;
  1438. case 1:
  1439. gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
  1440. BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
  1441. MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
  1442. NUM_BANKS(ADDR_SURF_16_BANK));
  1443. break;
  1444. case 2:
  1445. gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
  1446. BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
  1447. MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
  1448. NUM_BANKS(ADDR_SURF_16_BANK));
  1449. break;
  1450. case 3:
  1451. gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
  1452. BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
  1453. MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
  1454. NUM_BANKS(ADDR_SURF_16_BANK));
  1455. break;
  1456. case 4:
  1457. gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
  1458. BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
  1459. MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
  1460. NUM_BANKS(ADDR_SURF_16_BANK));
  1461. break;
  1462. case 5:
  1463. gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
  1464. BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
  1465. MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
  1466. NUM_BANKS(ADDR_SURF_16_BANK));
  1467. break;
  1468. case 6:
  1469. gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
  1470. BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
  1471. MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
  1472. NUM_BANKS(ADDR_SURF_16_BANK));
  1473. break;
  1474. case 8:
  1475. gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
  1476. BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
  1477. MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
  1478. NUM_BANKS(ADDR_SURF_16_BANK));
  1479. break;
  1480. case 9:
  1481. gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
  1482. BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
  1483. MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
  1484. NUM_BANKS(ADDR_SURF_16_BANK));
  1485. break;
  1486. case 10:
  1487. gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
  1488. BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
  1489. MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
  1490. NUM_BANKS(ADDR_SURF_16_BANK));
  1491. break;
  1492. case 11:
  1493. gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
  1494. BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
  1495. MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
  1496. NUM_BANKS(ADDR_SURF_16_BANK));
  1497. break;
  1498. case 12:
  1499. gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
  1500. BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
  1501. MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
  1502. NUM_BANKS(ADDR_SURF_8_BANK));
  1503. break;
  1504. case 13:
  1505. gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
  1506. BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
  1507. MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
  1508. NUM_BANKS(ADDR_SURF_4_BANK));
  1509. break;
  1510. case 14:
  1511. gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
  1512. BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
  1513. MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
  1514. NUM_BANKS(ADDR_SURF_4_BANK));
  1515. break;
  1516. case 7:
  1517. /* unused idx */
  1518. continue;
  1519. default:
  1520. gb_tile_moden = 0;
  1521. break;
  1522. };
  1523. adev->gfx.config.macrotile_mode_array[reg_offset] = gb_tile_moden;
  1524. WREG32(mmGB_MACROTILE_MODE0 + reg_offset, gb_tile_moden);
  1525. }
  1526. break;
  1527. case CHIP_CARRIZO:
  1528. default:
  1529. for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
  1530. switch (reg_offset) {
  1531. case 0:
  1532. gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
  1533. PIPE_CONFIG(ADDR_SURF_P2) |
  1534. TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
  1535. MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
  1536. break;
  1537. case 1:
  1538. gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
  1539. PIPE_CONFIG(ADDR_SURF_P2) |
  1540. TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
  1541. MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
  1542. break;
  1543. case 2:
  1544. gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
  1545. PIPE_CONFIG(ADDR_SURF_P2) |
  1546. TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
  1547. MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
  1548. break;
  1549. case 3:
  1550. gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
  1551. PIPE_CONFIG(ADDR_SURF_P2) |
  1552. TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
  1553. MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
  1554. break;
  1555. case 4:
  1556. gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
  1557. PIPE_CONFIG(ADDR_SURF_P2) |
  1558. TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
  1559. MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
  1560. break;
  1561. case 5:
  1562. gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
  1563. PIPE_CONFIG(ADDR_SURF_P2) |
  1564. TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
  1565. MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
  1566. break;
  1567. case 6:
  1568. gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
  1569. PIPE_CONFIG(ADDR_SURF_P2) |
  1570. TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
  1571. MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
  1572. break;
  1573. case 8:
  1574. gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
  1575. PIPE_CONFIG(ADDR_SURF_P2));
  1576. break;
  1577. case 9:
  1578. gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
  1579. PIPE_CONFIG(ADDR_SURF_P2) |
  1580. MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
  1581. SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
  1582. break;
  1583. case 10:
  1584. gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
  1585. PIPE_CONFIG(ADDR_SURF_P2) |
  1586. MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
  1587. SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
  1588. break;
  1589. case 11:
  1590. gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
  1591. PIPE_CONFIG(ADDR_SURF_P2) |
  1592. MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
  1593. SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
  1594. break;
  1595. case 13:
  1596. gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
  1597. PIPE_CONFIG(ADDR_SURF_P2) |
  1598. MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
  1599. SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
  1600. break;
  1601. case 14:
  1602. gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
  1603. PIPE_CONFIG(ADDR_SURF_P2) |
  1604. MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
  1605. SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
  1606. break;
  1607. case 15:
  1608. gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
  1609. PIPE_CONFIG(ADDR_SURF_P2) |
  1610. MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
  1611. SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
  1612. break;
  1613. case 16:
  1614. gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
  1615. PIPE_CONFIG(ADDR_SURF_P2) |
  1616. MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
  1617. SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
  1618. break;
  1619. case 18:
  1620. gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
  1621. PIPE_CONFIG(ADDR_SURF_P2) |
  1622. MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
  1623. SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
  1624. break;
  1625. case 19:
  1626. gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
  1627. PIPE_CONFIG(ADDR_SURF_P2) |
  1628. MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
  1629. SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
  1630. break;
  1631. case 20:
  1632. gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
  1633. PIPE_CONFIG(ADDR_SURF_P2) |
  1634. MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
  1635. SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
  1636. break;
  1637. case 21:
  1638. gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
  1639. PIPE_CONFIG(ADDR_SURF_P2) |
  1640. MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
  1641. SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
  1642. break;
  1643. case 22:
  1644. gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
  1645. PIPE_CONFIG(ADDR_SURF_P2) |
  1646. MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
  1647. SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
  1648. break;
  1649. case 24:
  1650. gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
  1651. PIPE_CONFIG(ADDR_SURF_P2) |
  1652. MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
  1653. SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
  1654. break;
  1655. case 25:
  1656. gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
  1657. PIPE_CONFIG(ADDR_SURF_P2) |
  1658. MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
  1659. SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
  1660. break;
  1661. case 26:
  1662. gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
  1663. PIPE_CONFIG(ADDR_SURF_P2) |
  1664. MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
  1665. SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
  1666. break;
  1667. case 27:
  1668. gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
  1669. PIPE_CONFIG(ADDR_SURF_P2) |
  1670. MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
  1671. SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
  1672. break;
  1673. case 28:
  1674. gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
  1675. PIPE_CONFIG(ADDR_SURF_P2) |
  1676. MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
  1677. SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
  1678. break;
  1679. case 29:
  1680. gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
  1681. PIPE_CONFIG(ADDR_SURF_P2) |
  1682. MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
  1683. SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
  1684. break;
  1685. case 7:
  1686. case 12:
  1687. case 17:
  1688. case 23:
  1689. /* unused idx */
  1690. continue;
  1691. default:
  1692. gb_tile_moden = 0;
  1693. break;
  1694. };
  1695. adev->gfx.config.tile_mode_array[reg_offset] = gb_tile_moden;
  1696. WREG32(mmGB_TILE_MODE0 + reg_offset, gb_tile_moden);
  1697. }
  1698. for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) {
  1699. switch (reg_offset) {
  1700. case 0:
  1701. gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
  1702. BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
  1703. MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
  1704. NUM_BANKS(ADDR_SURF_8_BANK));
  1705. break;
  1706. case 1:
  1707. gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
  1708. BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
  1709. MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
  1710. NUM_BANKS(ADDR_SURF_8_BANK));
  1711. break;
  1712. case 2:
  1713. gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
  1714. BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
  1715. MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
  1716. NUM_BANKS(ADDR_SURF_8_BANK));
  1717. break;
  1718. case 3:
  1719. gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
  1720. BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
  1721. MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
  1722. NUM_BANKS(ADDR_SURF_8_BANK));
  1723. break;
  1724. case 4:
  1725. gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
  1726. BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
  1727. MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
  1728. NUM_BANKS(ADDR_SURF_8_BANK));
  1729. break;
  1730. case 5:
  1731. gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
  1732. BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
  1733. MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
  1734. NUM_BANKS(ADDR_SURF_8_BANK));
  1735. break;
  1736. case 6:
  1737. gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
  1738. BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
  1739. MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
  1740. NUM_BANKS(ADDR_SURF_8_BANK));
  1741. break;
  1742. case 8:
  1743. gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
  1744. BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
  1745. MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
  1746. NUM_BANKS(ADDR_SURF_16_BANK));
  1747. break;
  1748. case 9:
  1749. gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
  1750. BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
  1751. MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
  1752. NUM_BANKS(ADDR_SURF_16_BANK));
  1753. break;
  1754. case 10:
  1755. gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
  1756. BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
  1757. MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
  1758. NUM_BANKS(ADDR_SURF_16_BANK));
  1759. break;
  1760. case 11:
  1761. gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
  1762. BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
  1763. MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
  1764. NUM_BANKS(ADDR_SURF_16_BANK));
  1765. break;
  1766. case 12:
  1767. gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
  1768. BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
  1769. MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
  1770. NUM_BANKS(ADDR_SURF_16_BANK));
  1771. break;
  1772. case 13:
  1773. gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
  1774. BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
  1775. MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
  1776. NUM_BANKS(ADDR_SURF_16_BANK));
  1777. break;
  1778. case 14:
  1779. gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
  1780. BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
  1781. MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
  1782. NUM_BANKS(ADDR_SURF_8_BANK));
  1783. break;
  1784. case 7:
  1785. /* unused idx */
  1786. continue;
  1787. default:
  1788. gb_tile_moden = 0;
  1789. break;
  1790. };
  1791. adev->gfx.config.macrotile_mode_array[reg_offset] = gb_tile_moden;
  1792. WREG32(mmGB_MACROTILE_MODE0 + reg_offset, gb_tile_moden);
  1793. }
  1794. }
  1795. }
  1796. static u32 gfx_v8_0_create_bitmask(u32 bit_width)
  1797. {
  1798. u32 i, mask = 0;
  1799. for (i = 0; i < bit_width; i++) {
  1800. mask <<= 1;
  1801. mask |= 1;
  1802. }
  1803. return mask;
  1804. }
  1805. void gfx_v8_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num)
  1806. {
  1807. u32 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES, 1);
  1808. if ((se_num == 0xffffffff) && (sh_num == 0xffffffff)) {
  1809. data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_BROADCAST_WRITES, 1);
  1810. data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1);
  1811. } else if (se_num == 0xffffffff) {
  1812. data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num);
  1813. data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1);
  1814. } else if (sh_num == 0xffffffff) {
  1815. data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_BROADCAST_WRITES, 1);
  1816. data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num);
  1817. } else {
  1818. data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num);
  1819. data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num);
  1820. }
  1821. WREG32(mmGRBM_GFX_INDEX, data);
  1822. }
  1823. static u32 gfx_v8_0_get_rb_disabled(struct amdgpu_device *adev,
  1824. u32 max_rb_num_per_se,
  1825. u32 sh_per_se)
  1826. {
  1827. u32 data, mask;
  1828. data = RREG32(mmCC_RB_BACKEND_DISABLE);
  1829. data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK;
  1830. data |= RREG32(mmGC_USER_RB_BACKEND_DISABLE);
  1831. data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT;
  1832. mask = gfx_v8_0_create_bitmask(max_rb_num_per_se / sh_per_se);
  1833. return data & mask;
  1834. }
  1835. static void gfx_v8_0_setup_rb(struct amdgpu_device *adev,
  1836. u32 se_num, u32 sh_per_se,
  1837. u32 max_rb_num_per_se)
  1838. {
  1839. int i, j;
  1840. u32 data, mask;
  1841. u32 disabled_rbs = 0;
  1842. u32 enabled_rbs = 0;
  1843. mutex_lock(&adev->grbm_idx_mutex);
  1844. for (i = 0; i < se_num; i++) {
  1845. for (j = 0; j < sh_per_se; j++) {
  1846. gfx_v8_0_select_se_sh(adev, i, j);
  1847. data = gfx_v8_0_get_rb_disabled(adev,
  1848. max_rb_num_per_se, sh_per_se);
  1849. disabled_rbs |= data << ((i * sh_per_se + j) *
  1850. RB_BITMAP_WIDTH_PER_SH);
  1851. }
  1852. }
  1853. gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
  1854. mutex_unlock(&adev->grbm_idx_mutex);
  1855. mask = 1;
  1856. for (i = 0; i < max_rb_num_per_se * se_num; i++) {
  1857. if (!(disabled_rbs & mask))
  1858. enabled_rbs |= mask;
  1859. mask <<= 1;
  1860. }
  1861. adev->gfx.config.backend_enable_mask = enabled_rbs;
  1862. mutex_lock(&adev->grbm_idx_mutex);
  1863. for (i = 0; i < se_num; i++) {
  1864. gfx_v8_0_select_se_sh(adev, i, 0xffffffff);
  1865. data = 0;
  1866. for (j = 0; j < sh_per_se; j++) {
  1867. switch (enabled_rbs & 3) {
  1868. case 0:
  1869. if (j == 0)
  1870. data |= (RASTER_CONFIG_RB_MAP_3 <<
  1871. PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT);
  1872. else
  1873. data |= (RASTER_CONFIG_RB_MAP_0 <<
  1874. PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT);
  1875. break;
  1876. case 1:
  1877. data |= (RASTER_CONFIG_RB_MAP_0 <<
  1878. (i * sh_per_se + j) * 2);
  1879. break;
  1880. case 2:
  1881. data |= (RASTER_CONFIG_RB_MAP_3 <<
  1882. (i * sh_per_se + j) * 2);
  1883. break;
  1884. case 3:
  1885. default:
  1886. data |= (RASTER_CONFIG_RB_MAP_2 <<
  1887. (i * sh_per_se + j) * 2);
  1888. break;
  1889. }
  1890. enabled_rbs >>= 2;
  1891. }
  1892. WREG32(mmPA_SC_RASTER_CONFIG, data);
  1893. }
  1894. gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
  1895. mutex_unlock(&adev->grbm_idx_mutex);
  1896. }
  1897. /**
  1898. * gmc_v8_0_init_compute_vmid - gart enable
  1899. *
  1900. * @rdev: amdgpu_device pointer
  1901. *
  1902. * Initialize compute vmid sh_mem registers
  1903. *
  1904. */
  1905. #define DEFAULT_SH_MEM_BASES (0x6000)
  1906. #define FIRST_COMPUTE_VMID (8)
  1907. #define LAST_COMPUTE_VMID (16)
  1908. static void gmc_v8_0_init_compute_vmid(struct amdgpu_device *adev)
  1909. {
  1910. int i;
  1911. uint32_t sh_mem_config;
  1912. uint32_t sh_mem_bases;
  1913. /*
  1914. * Configure apertures:
  1915. * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB)
  1916. * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB)
  1917. * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB)
  1918. */
  1919. sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16);
  1920. sh_mem_config = SH_MEM_ADDRESS_MODE_HSA64 <<
  1921. SH_MEM_CONFIG__ADDRESS_MODE__SHIFT |
  1922. SH_MEM_ALIGNMENT_MODE_UNALIGNED <<
  1923. SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT |
  1924. MTYPE_CC << SH_MEM_CONFIG__DEFAULT_MTYPE__SHIFT |
  1925. SH_MEM_CONFIG__PRIVATE_ATC_MASK;
  1926. mutex_lock(&adev->srbm_mutex);
  1927. for (i = FIRST_COMPUTE_VMID; i < LAST_COMPUTE_VMID; i++) {
  1928. vi_srbm_select(adev, 0, 0, 0, i);
  1929. /* CP and shaders */
  1930. WREG32(mmSH_MEM_CONFIG, sh_mem_config);
  1931. WREG32(mmSH_MEM_APE1_BASE, 1);
  1932. WREG32(mmSH_MEM_APE1_LIMIT, 0);
  1933. WREG32(mmSH_MEM_BASES, sh_mem_bases);
  1934. }
  1935. vi_srbm_select(adev, 0, 0, 0, 0);
  1936. mutex_unlock(&adev->srbm_mutex);
  1937. }
  1938. static void gfx_v8_0_gpu_init(struct amdgpu_device *adev)
  1939. {
  1940. u32 gb_addr_config;
  1941. u32 mc_shared_chmap, mc_arb_ramcfg;
  1942. u32 dimm00_addr_map, dimm01_addr_map, dimm10_addr_map, dimm11_addr_map;
  1943. u32 tmp;
  1944. int i;
  1945. switch (adev->asic_type) {
  1946. case CHIP_TOPAZ:
  1947. adev->gfx.config.max_shader_engines = 1;
  1948. adev->gfx.config.max_tile_pipes = 2;
  1949. adev->gfx.config.max_cu_per_sh = 6;
  1950. adev->gfx.config.max_sh_per_se = 1;
  1951. adev->gfx.config.max_backends_per_se = 2;
  1952. adev->gfx.config.max_texture_channel_caches = 2;
  1953. adev->gfx.config.max_gprs = 256;
  1954. adev->gfx.config.max_gs_threads = 32;
  1955. adev->gfx.config.max_hw_contexts = 8;
  1956. adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
  1957. adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
  1958. adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
  1959. adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
  1960. gb_addr_config = TOPAZ_GB_ADDR_CONFIG_GOLDEN;
  1961. break;
  1962. case CHIP_FIJI:
  1963. adev->gfx.config.max_shader_engines = 4;
  1964. adev->gfx.config.max_tile_pipes = 16;
  1965. adev->gfx.config.max_cu_per_sh = 16;
  1966. adev->gfx.config.max_sh_per_se = 1;
  1967. adev->gfx.config.max_backends_per_se = 4;
  1968. adev->gfx.config.max_texture_channel_caches = 8;
  1969. adev->gfx.config.max_gprs = 256;
  1970. adev->gfx.config.max_gs_threads = 32;
  1971. adev->gfx.config.max_hw_contexts = 8;
  1972. adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
  1973. adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
  1974. adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
  1975. adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
  1976. gb_addr_config = TONGA_GB_ADDR_CONFIG_GOLDEN;
  1977. break;
  1978. case CHIP_TONGA:
  1979. adev->gfx.config.max_shader_engines = 4;
  1980. adev->gfx.config.max_tile_pipes = 8;
  1981. adev->gfx.config.max_cu_per_sh = 8;
  1982. adev->gfx.config.max_sh_per_se = 1;
  1983. adev->gfx.config.max_backends_per_se = 2;
  1984. adev->gfx.config.max_texture_channel_caches = 8;
  1985. adev->gfx.config.max_gprs = 256;
  1986. adev->gfx.config.max_gs_threads = 32;
  1987. adev->gfx.config.max_hw_contexts = 8;
  1988. adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
  1989. adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
  1990. adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
  1991. adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
  1992. gb_addr_config = TONGA_GB_ADDR_CONFIG_GOLDEN;
  1993. break;
  1994. case CHIP_CARRIZO:
  1995. adev->gfx.config.max_shader_engines = 1;
  1996. adev->gfx.config.max_tile_pipes = 2;
  1997. adev->gfx.config.max_sh_per_se = 1;
  1998. adev->gfx.config.max_backends_per_se = 2;
  1999. switch (adev->pdev->revision) {
  2000. case 0xc4:
  2001. case 0x84:
  2002. case 0xc8:
  2003. case 0xcc:
  2004. /* B10 */
  2005. adev->gfx.config.max_cu_per_sh = 8;
  2006. break;
  2007. case 0xc5:
  2008. case 0x81:
  2009. case 0x85:
  2010. case 0xc9:
  2011. case 0xcd:
  2012. /* B8 */
  2013. adev->gfx.config.max_cu_per_sh = 6;
  2014. break;
  2015. case 0xc6:
  2016. case 0xca:
  2017. case 0xce:
  2018. /* B6 */
  2019. adev->gfx.config.max_cu_per_sh = 6;
  2020. break;
  2021. case 0xc7:
  2022. case 0x87:
  2023. case 0xcb:
  2024. default:
  2025. /* B4 */
  2026. adev->gfx.config.max_cu_per_sh = 4;
  2027. break;
  2028. }
  2029. adev->gfx.config.max_texture_channel_caches = 2;
  2030. adev->gfx.config.max_gprs = 256;
  2031. adev->gfx.config.max_gs_threads = 32;
  2032. adev->gfx.config.max_hw_contexts = 8;
  2033. adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
  2034. adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
  2035. adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
  2036. adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
  2037. gb_addr_config = CARRIZO_GB_ADDR_CONFIG_GOLDEN;
  2038. break;
  2039. default:
  2040. adev->gfx.config.max_shader_engines = 2;
  2041. adev->gfx.config.max_tile_pipes = 4;
  2042. adev->gfx.config.max_cu_per_sh = 2;
  2043. adev->gfx.config.max_sh_per_se = 1;
  2044. adev->gfx.config.max_backends_per_se = 2;
  2045. adev->gfx.config.max_texture_channel_caches = 4;
  2046. adev->gfx.config.max_gprs = 256;
  2047. adev->gfx.config.max_gs_threads = 32;
  2048. adev->gfx.config.max_hw_contexts = 8;
  2049. adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
  2050. adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
  2051. adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
  2052. adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
  2053. gb_addr_config = TONGA_GB_ADDR_CONFIG_GOLDEN;
  2054. break;
  2055. }
  2056. tmp = RREG32(mmGRBM_CNTL);
  2057. tmp = REG_SET_FIELD(tmp, GRBM_CNTL, READ_TIMEOUT, 0xff);
  2058. WREG32(mmGRBM_CNTL, tmp);
  2059. mc_shared_chmap = RREG32(mmMC_SHARED_CHMAP);
  2060. adev->gfx.config.mc_arb_ramcfg = RREG32(mmMC_ARB_RAMCFG);
  2061. mc_arb_ramcfg = adev->gfx.config.mc_arb_ramcfg;
  2062. adev->gfx.config.num_tile_pipes = adev->gfx.config.max_tile_pipes;
  2063. adev->gfx.config.mem_max_burst_length_bytes = 256;
  2064. if (adev->flags & AMD_IS_APU) {
  2065. /* Get memory bank mapping mode. */
  2066. tmp = RREG32(mmMC_FUS_DRAM0_BANK_ADDR_MAPPING);
  2067. dimm00_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM0ADDRMAP);
  2068. dimm01_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM1ADDRMAP);
  2069. tmp = RREG32(mmMC_FUS_DRAM1_BANK_ADDR_MAPPING);
  2070. dimm10_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM1_BANK_ADDR_MAPPING, DIMM0ADDRMAP);
  2071. dimm11_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM1_BANK_ADDR_MAPPING, DIMM1ADDRMAP);
  2072. /* Validate settings in case only one DIMM installed. */
  2073. if ((dimm00_addr_map == 0) || (dimm00_addr_map == 3) || (dimm00_addr_map == 4) || (dimm00_addr_map > 12))
  2074. dimm00_addr_map = 0;
  2075. if ((dimm01_addr_map == 0) || (dimm01_addr_map == 3) || (dimm01_addr_map == 4) || (dimm01_addr_map > 12))
  2076. dimm01_addr_map = 0;
  2077. if ((dimm10_addr_map == 0) || (dimm10_addr_map == 3) || (dimm10_addr_map == 4) || (dimm10_addr_map > 12))
  2078. dimm10_addr_map = 0;
  2079. if ((dimm11_addr_map == 0) || (dimm11_addr_map == 3) || (dimm11_addr_map == 4) || (dimm11_addr_map > 12))
  2080. dimm11_addr_map = 0;
  2081. /* If DIMM Addr map is 8GB, ROW size should be 2KB. Otherwise 1KB. */
  2082. /* If ROW size(DIMM1) != ROW size(DMIMM0), ROW size should be larger one. */
  2083. if ((dimm00_addr_map == 11) || (dimm01_addr_map == 11) || (dimm10_addr_map == 11) || (dimm11_addr_map == 11))
  2084. adev->gfx.config.mem_row_size_in_kb = 2;
  2085. else
  2086. adev->gfx.config.mem_row_size_in_kb = 1;
  2087. } else {
  2088. tmp = REG_GET_FIELD(mc_arb_ramcfg, MC_ARB_RAMCFG, NOOFCOLS);
  2089. adev->gfx.config.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024;
  2090. if (adev->gfx.config.mem_row_size_in_kb > 4)
  2091. adev->gfx.config.mem_row_size_in_kb = 4;
  2092. }
  2093. adev->gfx.config.shader_engine_tile_size = 32;
  2094. adev->gfx.config.num_gpus = 1;
  2095. adev->gfx.config.multi_gpu_tile_size = 64;
  2096. /* fix up row size */
  2097. switch (adev->gfx.config.mem_row_size_in_kb) {
  2098. case 1:
  2099. default:
  2100. gb_addr_config = REG_SET_FIELD(gb_addr_config, GB_ADDR_CONFIG, ROW_SIZE, 0);
  2101. break;
  2102. case 2:
  2103. gb_addr_config = REG_SET_FIELD(gb_addr_config, GB_ADDR_CONFIG, ROW_SIZE, 1);
  2104. break;
  2105. case 4:
  2106. gb_addr_config = REG_SET_FIELD(gb_addr_config, GB_ADDR_CONFIG, ROW_SIZE, 2);
  2107. break;
  2108. }
  2109. adev->gfx.config.gb_addr_config = gb_addr_config;
  2110. WREG32(mmGB_ADDR_CONFIG, gb_addr_config);
  2111. WREG32(mmHDP_ADDR_CONFIG, gb_addr_config);
  2112. WREG32(mmDMIF_ADDR_CALC, gb_addr_config);
  2113. WREG32(mmSDMA0_TILING_CONFIG + SDMA0_REGISTER_OFFSET,
  2114. gb_addr_config & 0x70);
  2115. WREG32(mmSDMA0_TILING_CONFIG + SDMA1_REGISTER_OFFSET,
  2116. gb_addr_config & 0x70);
  2117. WREG32(mmUVD_UDEC_ADDR_CONFIG, gb_addr_config);
  2118. WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, gb_addr_config);
  2119. WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, gb_addr_config);
  2120. gfx_v8_0_tiling_mode_table_init(adev);
  2121. gfx_v8_0_setup_rb(adev, adev->gfx.config.max_shader_engines,
  2122. adev->gfx.config.max_sh_per_se,
  2123. adev->gfx.config.max_backends_per_se);
  2124. /* XXX SH_MEM regs */
  2125. /* where to put LDS, scratch, GPUVM in FSA64 space */
  2126. mutex_lock(&adev->srbm_mutex);
  2127. for (i = 0; i < 16; i++) {
  2128. vi_srbm_select(adev, 0, 0, 0, i);
  2129. /* CP and shaders */
  2130. if (i == 0) {
  2131. tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, DEFAULT_MTYPE, MTYPE_UC);
  2132. tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, APE1_MTYPE, MTYPE_UC);
  2133. tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, ALIGNMENT_MODE,
  2134. SH_MEM_ALIGNMENT_MODE_UNALIGNED);
  2135. WREG32(mmSH_MEM_CONFIG, tmp);
  2136. } else {
  2137. tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, DEFAULT_MTYPE, MTYPE_NC);
  2138. tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, APE1_MTYPE, MTYPE_NC);
  2139. tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, ALIGNMENT_MODE,
  2140. SH_MEM_ALIGNMENT_MODE_UNALIGNED);
  2141. WREG32(mmSH_MEM_CONFIG, tmp);
  2142. }
  2143. WREG32(mmSH_MEM_APE1_BASE, 1);
  2144. WREG32(mmSH_MEM_APE1_LIMIT, 0);
  2145. WREG32(mmSH_MEM_BASES, 0);
  2146. }
  2147. vi_srbm_select(adev, 0, 0, 0, 0);
  2148. mutex_unlock(&adev->srbm_mutex);
  2149. gmc_v8_0_init_compute_vmid(adev);
  2150. mutex_lock(&adev->grbm_idx_mutex);
  2151. /*
  2152. * making sure that the following register writes will be broadcasted
  2153. * to all the shaders
  2154. */
  2155. gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
  2156. WREG32(mmPA_SC_FIFO_SIZE,
  2157. (adev->gfx.config.sc_prim_fifo_size_frontend <<
  2158. PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT) |
  2159. (adev->gfx.config.sc_prim_fifo_size_backend <<
  2160. PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT) |
  2161. (adev->gfx.config.sc_hiz_tile_fifo_size <<
  2162. PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT) |
  2163. (adev->gfx.config.sc_earlyz_tile_fifo_size <<
  2164. PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT));
  2165. mutex_unlock(&adev->grbm_idx_mutex);
  2166. }
  2167. static void gfx_v8_0_wait_for_rlc_serdes(struct amdgpu_device *adev)
  2168. {
  2169. u32 i, j, k;
  2170. u32 mask;
  2171. mutex_lock(&adev->grbm_idx_mutex);
  2172. for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
  2173. for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
  2174. gfx_v8_0_select_se_sh(adev, i, j);
  2175. for (k = 0; k < adev->usec_timeout; k++) {
  2176. if (RREG32(mmRLC_SERDES_CU_MASTER_BUSY) == 0)
  2177. break;
  2178. udelay(1);
  2179. }
  2180. }
  2181. }
  2182. gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
  2183. mutex_unlock(&adev->grbm_idx_mutex);
  2184. mask = RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK |
  2185. RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY_MASK |
  2186. RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY_MASK |
  2187. RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY_MASK;
  2188. for (k = 0; k < adev->usec_timeout; k++) {
  2189. if ((RREG32(mmRLC_SERDES_NONCU_MASTER_BUSY) & mask) == 0)
  2190. break;
  2191. udelay(1);
  2192. }
  2193. }
  2194. static void gfx_v8_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
  2195. bool enable)
  2196. {
  2197. u32 tmp = RREG32(mmCP_INT_CNTL_RING0);
  2198. if (enable) {
  2199. tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, 1);
  2200. tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, 1);
  2201. tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, 1);
  2202. tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, 1);
  2203. } else {
  2204. tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, 0);
  2205. tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, 0);
  2206. tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, 0);
  2207. tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, 0);
  2208. }
  2209. WREG32(mmCP_INT_CNTL_RING0, tmp);
  2210. }
  2211. void gfx_v8_0_rlc_stop(struct amdgpu_device *adev)
  2212. {
  2213. u32 tmp = RREG32(mmRLC_CNTL);
  2214. tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0);
  2215. WREG32(mmRLC_CNTL, tmp);
  2216. gfx_v8_0_enable_gui_idle_interrupt(adev, false);
  2217. gfx_v8_0_wait_for_rlc_serdes(adev);
  2218. }
  2219. static void gfx_v8_0_rlc_reset(struct amdgpu_device *adev)
  2220. {
  2221. u32 tmp = RREG32(mmGRBM_SOFT_RESET);
  2222. tmp = REG_SET_FIELD(tmp, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
  2223. WREG32(mmGRBM_SOFT_RESET, tmp);
  2224. udelay(50);
  2225. tmp = REG_SET_FIELD(tmp, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0);
  2226. WREG32(mmGRBM_SOFT_RESET, tmp);
  2227. udelay(50);
  2228. }
  2229. static void gfx_v8_0_rlc_start(struct amdgpu_device *adev)
  2230. {
  2231. u32 tmp = RREG32(mmRLC_CNTL);
  2232. tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 1);
  2233. WREG32(mmRLC_CNTL, tmp);
  2234. /* carrizo do enable cp interrupt after cp inited */
  2235. if (adev->asic_type != CHIP_CARRIZO)
  2236. gfx_v8_0_enable_gui_idle_interrupt(adev, true);
  2237. udelay(50);
  2238. }
  2239. static int gfx_v8_0_rlc_load_microcode(struct amdgpu_device *adev)
  2240. {
  2241. const struct rlc_firmware_header_v2_0 *hdr;
  2242. const __le32 *fw_data;
  2243. unsigned i, fw_size;
  2244. if (!adev->gfx.rlc_fw)
  2245. return -EINVAL;
  2246. hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
  2247. amdgpu_ucode_print_rlc_hdr(&hdr->header);
  2248. fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
  2249. le32_to_cpu(hdr->header.ucode_array_offset_bytes));
  2250. fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
  2251. WREG32(mmRLC_GPM_UCODE_ADDR, 0);
  2252. for (i = 0; i < fw_size; i++)
  2253. WREG32(mmRLC_GPM_UCODE_DATA, le32_to_cpup(fw_data++));
  2254. WREG32(mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version);
  2255. return 0;
  2256. }
  2257. static int gfx_v8_0_rlc_resume(struct amdgpu_device *adev)
  2258. {
  2259. int r;
  2260. gfx_v8_0_rlc_stop(adev);
  2261. /* disable CG */
  2262. WREG32(mmRLC_CGCG_CGLS_CTRL, 0);
  2263. /* disable PG */
  2264. WREG32(mmRLC_PG_CNTL, 0);
  2265. gfx_v8_0_rlc_reset(adev);
  2266. if (!adev->firmware.smu_load) {
  2267. /* legacy rlc firmware loading */
  2268. r = gfx_v8_0_rlc_load_microcode(adev);
  2269. if (r)
  2270. return r;
  2271. } else {
  2272. r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
  2273. AMDGPU_UCODE_ID_RLC_G);
  2274. if (r)
  2275. return -EINVAL;
  2276. }
  2277. gfx_v8_0_rlc_start(adev);
  2278. return 0;
  2279. }
  2280. static void gfx_v8_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)
  2281. {
  2282. int i;
  2283. u32 tmp = RREG32(mmCP_ME_CNTL);
  2284. if (enable) {
  2285. tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, 0);
  2286. tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, 0);
  2287. tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, 0);
  2288. } else {
  2289. tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, 1);
  2290. tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, 1);
  2291. tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, 1);
  2292. for (i = 0; i < adev->gfx.num_gfx_rings; i++)
  2293. adev->gfx.gfx_ring[i].ready = false;
  2294. }
  2295. WREG32(mmCP_ME_CNTL, tmp);
  2296. udelay(50);
  2297. }
  2298. static int gfx_v8_0_cp_gfx_load_microcode(struct amdgpu_device *adev)
  2299. {
  2300. const struct gfx_firmware_header_v1_0 *pfp_hdr;
  2301. const struct gfx_firmware_header_v1_0 *ce_hdr;
  2302. const struct gfx_firmware_header_v1_0 *me_hdr;
  2303. const __le32 *fw_data;
  2304. unsigned i, fw_size;
  2305. if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw)
  2306. return -EINVAL;
  2307. pfp_hdr = (const struct gfx_firmware_header_v1_0 *)
  2308. adev->gfx.pfp_fw->data;
  2309. ce_hdr = (const struct gfx_firmware_header_v1_0 *)
  2310. adev->gfx.ce_fw->data;
  2311. me_hdr = (const struct gfx_firmware_header_v1_0 *)
  2312. adev->gfx.me_fw->data;
  2313. amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header);
  2314. amdgpu_ucode_print_gfx_hdr(&ce_hdr->header);
  2315. amdgpu_ucode_print_gfx_hdr(&me_hdr->header);
  2316. gfx_v8_0_cp_gfx_enable(adev, false);
  2317. /* PFP */
  2318. fw_data = (const __le32 *)
  2319. (adev->gfx.pfp_fw->data +
  2320. le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes));
  2321. fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes) / 4;
  2322. WREG32(mmCP_PFP_UCODE_ADDR, 0);
  2323. for (i = 0; i < fw_size; i++)
  2324. WREG32(mmCP_PFP_UCODE_DATA, le32_to_cpup(fw_data++));
  2325. WREG32(mmCP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version);
  2326. /* CE */
  2327. fw_data = (const __le32 *)
  2328. (adev->gfx.ce_fw->data +
  2329. le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes));
  2330. fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes) / 4;
  2331. WREG32(mmCP_CE_UCODE_ADDR, 0);
  2332. for (i = 0; i < fw_size; i++)
  2333. WREG32(mmCP_CE_UCODE_DATA, le32_to_cpup(fw_data++));
  2334. WREG32(mmCP_CE_UCODE_ADDR, adev->gfx.ce_fw_version);
  2335. /* ME */
  2336. fw_data = (const __le32 *)
  2337. (adev->gfx.me_fw->data +
  2338. le32_to_cpu(me_hdr->header.ucode_array_offset_bytes));
  2339. fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes) / 4;
  2340. WREG32(mmCP_ME_RAM_WADDR, 0);
  2341. for (i = 0; i < fw_size; i++)
  2342. WREG32(mmCP_ME_RAM_DATA, le32_to_cpup(fw_data++));
  2343. WREG32(mmCP_ME_RAM_WADDR, adev->gfx.me_fw_version);
  2344. return 0;
  2345. }
  2346. static u32 gfx_v8_0_get_csb_size(struct amdgpu_device *adev)
  2347. {
  2348. u32 count = 0;
  2349. const struct cs_section_def *sect = NULL;
  2350. const struct cs_extent_def *ext = NULL;
  2351. /* begin clear state */
  2352. count += 2;
  2353. /* context control state */
  2354. count += 3;
  2355. for (sect = vi_cs_data; sect->section != NULL; ++sect) {
  2356. for (ext = sect->section; ext->extent != NULL; ++ext) {
  2357. if (sect->id == SECT_CONTEXT)
  2358. count += 2 + ext->reg_count;
  2359. else
  2360. return 0;
  2361. }
  2362. }
  2363. /* pa_sc_raster_config/pa_sc_raster_config1 */
  2364. count += 4;
  2365. /* end clear state */
  2366. count += 2;
  2367. /* clear state */
  2368. count += 2;
  2369. return count;
  2370. }
  2371. static int gfx_v8_0_cp_gfx_start(struct amdgpu_device *adev)
  2372. {
  2373. struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0];
  2374. const struct cs_section_def *sect = NULL;
  2375. const struct cs_extent_def *ext = NULL;
  2376. int r, i;
  2377. /* init the CP */
  2378. WREG32(mmCP_MAX_CONTEXT, adev->gfx.config.max_hw_contexts - 1);
  2379. WREG32(mmCP_ENDIAN_SWAP, 0);
  2380. WREG32(mmCP_DEVICE_ID, 1);
  2381. gfx_v8_0_cp_gfx_enable(adev, true);
  2382. r = amdgpu_ring_lock(ring, gfx_v8_0_get_csb_size(adev) + 4);
  2383. if (r) {
  2384. DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
  2385. return r;
  2386. }
  2387. /* clear state buffer */
  2388. amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
  2389. amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
  2390. amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
  2391. amdgpu_ring_write(ring, 0x80000000);
  2392. amdgpu_ring_write(ring, 0x80000000);
  2393. for (sect = vi_cs_data; sect->section != NULL; ++sect) {
  2394. for (ext = sect->section; ext->extent != NULL; ++ext) {
  2395. if (sect->id == SECT_CONTEXT) {
  2396. amdgpu_ring_write(ring,
  2397. PACKET3(PACKET3_SET_CONTEXT_REG,
  2398. ext->reg_count));
  2399. amdgpu_ring_write(ring,
  2400. ext->reg_index - PACKET3_SET_CONTEXT_REG_START);
  2401. for (i = 0; i < ext->reg_count; i++)
  2402. amdgpu_ring_write(ring, ext->extent[i]);
  2403. }
  2404. }
  2405. }
  2406. amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
  2407. amdgpu_ring_write(ring, mmPA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START);
  2408. switch (adev->asic_type) {
  2409. case CHIP_TONGA:
  2410. case CHIP_FIJI:
  2411. amdgpu_ring_write(ring, 0x16000012);
  2412. amdgpu_ring_write(ring, 0x0000002A);
  2413. break;
  2414. case CHIP_TOPAZ:
  2415. case CHIP_CARRIZO:
  2416. amdgpu_ring_write(ring, 0x00000002);
  2417. amdgpu_ring_write(ring, 0x00000000);
  2418. break;
  2419. default:
  2420. BUG();
  2421. }
  2422. amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
  2423. amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
  2424. amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
  2425. amdgpu_ring_write(ring, 0);
  2426. /* init the CE partitions */
  2427. amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
  2428. amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE));
  2429. amdgpu_ring_write(ring, 0x8000);
  2430. amdgpu_ring_write(ring, 0x8000);
  2431. amdgpu_ring_unlock_commit(ring);
  2432. return 0;
  2433. }
  2434. static int gfx_v8_0_cp_gfx_resume(struct amdgpu_device *adev)
  2435. {
  2436. struct amdgpu_ring *ring;
  2437. u32 tmp;
  2438. u32 rb_bufsz;
  2439. u64 rb_addr, rptr_addr;
  2440. int r;
  2441. /* Set the write pointer delay */
  2442. WREG32(mmCP_RB_WPTR_DELAY, 0);
  2443. /* set the RB to use vmid 0 */
  2444. WREG32(mmCP_RB_VMID, 0);
  2445. /* Set ring buffer size */
  2446. ring = &adev->gfx.gfx_ring[0];
  2447. rb_bufsz = order_base_2(ring->ring_size / 8);
  2448. tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz);
  2449. tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2);
  2450. tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, MTYPE, 3);
  2451. tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, MIN_IB_AVAILSZ, 1);
  2452. #ifdef __BIG_ENDIAN
  2453. tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1);
  2454. #endif
  2455. WREG32(mmCP_RB0_CNTL, tmp);
  2456. /* Initialize the ring buffer's read and write pointers */
  2457. WREG32(mmCP_RB0_CNTL, tmp | CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK);
  2458. ring->wptr = 0;
  2459. WREG32(mmCP_RB0_WPTR, ring->wptr);
  2460. /* set the wb address wether it's enabled or not */
  2461. rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
  2462. WREG32(mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr));
  2463. WREG32(mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF);
  2464. mdelay(1);
  2465. WREG32(mmCP_RB0_CNTL, tmp);
  2466. rb_addr = ring->gpu_addr >> 8;
  2467. WREG32(mmCP_RB0_BASE, rb_addr);
  2468. WREG32(mmCP_RB0_BASE_HI, upper_32_bits(rb_addr));
  2469. /* no gfx doorbells on iceland */
  2470. if (adev->asic_type != CHIP_TOPAZ) {
  2471. tmp = RREG32(mmCP_RB_DOORBELL_CONTROL);
  2472. if (ring->use_doorbell) {
  2473. tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
  2474. DOORBELL_OFFSET, ring->doorbell_index);
  2475. tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
  2476. DOORBELL_EN, 1);
  2477. } else {
  2478. tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
  2479. DOORBELL_EN, 0);
  2480. }
  2481. WREG32(mmCP_RB_DOORBELL_CONTROL, tmp);
  2482. if (adev->asic_type == CHIP_TONGA) {
  2483. tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,
  2484. DOORBELL_RANGE_LOWER,
  2485. AMDGPU_DOORBELL_GFX_RING0);
  2486. WREG32(mmCP_RB_DOORBELL_RANGE_LOWER, tmp);
  2487. WREG32(mmCP_RB_DOORBELL_RANGE_UPPER,
  2488. CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK);
  2489. }
  2490. }
  2491. /* start the ring */
  2492. gfx_v8_0_cp_gfx_start(adev);
  2493. ring->ready = true;
  2494. r = amdgpu_ring_test_ring(ring);
  2495. if (r) {
  2496. ring->ready = false;
  2497. return r;
  2498. }
  2499. return 0;
  2500. }
  2501. static void gfx_v8_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)
  2502. {
  2503. int i;
  2504. if (enable) {
  2505. WREG32(mmCP_MEC_CNTL, 0);
  2506. } else {
  2507. WREG32(mmCP_MEC_CNTL, (CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK));
  2508. for (i = 0; i < adev->gfx.num_compute_rings; i++)
  2509. adev->gfx.compute_ring[i].ready = false;
  2510. }
  2511. udelay(50);
  2512. }
  2513. static int gfx_v8_0_cp_compute_start(struct amdgpu_device *adev)
  2514. {
  2515. gfx_v8_0_cp_compute_enable(adev, true);
  2516. return 0;
  2517. }
  2518. static int gfx_v8_0_cp_compute_load_microcode(struct amdgpu_device *adev)
  2519. {
  2520. const struct gfx_firmware_header_v1_0 *mec_hdr;
  2521. const __le32 *fw_data;
  2522. unsigned i, fw_size;
  2523. if (!adev->gfx.mec_fw)
  2524. return -EINVAL;
  2525. gfx_v8_0_cp_compute_enable(adev, false);
  2526. mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
  2527. amdgpu_ucode_print_gfx_hdr(&mec_hdr->header);
  2528. fw_data = (const __le32 *)
  2529. (adev->gfx.mec_fw->data +
  2530. le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
  2531. fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes) / 4;
  2532. /* MEC1 */
  2533. WREG32(mmCP_MEC_ME1_UCODE_ADDR, 0);
  2534. for (i = 0; i < fw_size; i++)
  2535. WREG32(mmCP_MEC_ME1_UCODE_DATA, le32_to_cpup(fw_data+i));
  2536. WREG32(mmCP_MEC_ME1_UCODE_ADDR, adev->gfx.mec_fw_version);
  2537. /* Loading MEC2 firmware is only necessary if MEC2 should run different microcode than MEC1. */
  2538. if (adev->gfx.mec2_fw) {
  2539. const struct gfx_firmware_header_v1_0 *mec2_hdr;
  2540. mec2_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec2_fw->data;
  2541. amdgpu_ucode_print_gfx_hdr(&mec2_hdr->header);
  2542. fw_data = (const __le32 *)
  2543. (adev->gfx.mec2_fw->data +
  2544. le32_to_cpu(mec2_hdr->header.ucode_array_offset_bytes));
  2545. fw_size = le32_to_cpu(mec2_hdr->header.ucode_size_bytes) / 4;
  2546. WREG32(mmCP_MEC_ME2_UCODE_ADDR, 0);
  2547. for (i = 0; i < fw_size; i++)
  2548. WREG32(mmCP_MEC_ME2_UCODE_DATA, le32_to_cpup(fw_data+i));
  2549. WREG32(mmCP_MEC_ME2_UCODE_ADDR, adev->gfx.mec2_fw_version);
  2550. }
  2551. return 0;
  2552. }
  2553. struct vi_mqd {
  2554. uint32_t header; /* ordinal0 */
  2555. uint32_t compute_dispatch_initiator; /* ordinal1 */
  2556. uint32_t compute_dim_x; /* ordinal2 */
  2557. uint32_t compute_dim_y; /* ordinal3 */
  2558. uint32_t compute_dim_z; /* ordinal4 */
  2559. uint32_t compute_start_x; /* ordinal5 */
  2560. uint32_t compute_start_y; /* ordinal6 */
  2561. uint32_t compute_start_z; /* ordinal7 */
  2562. uint32_t compute_num_thread_x; /* ordinal8 */
  2563. uint32_t compute_num_thread_y; /* ordinal9 */
  2564. uint32_t compute_num_thread_z; /* ordinal10 */
  2565. uint32_t compute_pipelinestat_enable; /* ordinal11 */
  2566. uint32_t compute_perfcount_enable; /* ordinal12 */
  2567. uint32_t compute_pgm_lo; /* ordinal13 */
  2568. uint32_t compute_pgm_hi; /* ordinal14 */
  2569. uint32_t compute_tba_lo; /* ordinal15 */
  2570. uint32_t compute_tba_hi; /* ordinal16 */
  2571. uint32_t compute_tma_lo; /* ordinal17 */
  2572. uint32_t compute_tma_hi; /* ordinal18 */
  2573. uint32_t compute_pgm_rsrc1; /* ordinal19 */
  2574. uint32_t compute_pgm_rsrc2; /* ordinal20 */
  2575. uint32_t compute_vmid; /* ordinal21 */
  2576. uint32_t compute_resource_limits; /* ordinal22 */
  2577. uint32_t compute_static_thread_mgmt_se0; /* ordinal23 */
  2578. uint32_t compute_static_thread_mgmt_se1; /* ordinal24 */
  2579. uint32_t compute_tmpring_size; /* ordinal25 */
  2580. uint32_t compute_static_thread_mgmt_se2; /* ordinal26 */
  2581. uint32_t compute_static_thread_mgmt_se3; /* ordinal27 */
  2582. uint32_t compute_restart_x; /* ordinal28 */
  2583. uint32_t compute_restart_y; /* ordinal29 */
  2584. uint32_t compute_restart_z; /* ordinal30 */
  2585. uint32_t compute_thread_trace_enable; /* ordinal31 */
  2586. uint32_t compute_misc_reserved; /* ordinal32 */
  2587. uint32_t compute_dispatch_id; /* ordinal33 */
  2588. uint32_t compute_threadgroup_id; /* ordinal34 */
  2589. uint32_t compute_relaunch; /* ordinal35 */
  2590. uint32_t compute_wave_restore_addr_lo; /* ordinal36 */
  2591. uint32_t compute_wave_restore_addr_hi; /* ordinal37 */
  2592. uint32_t compute_wave_restore_control; /* ordinal38 */
  2593. uint32_t reserved9; /* ordinal39 */
  2594. uint32_t reserved10; /* ordinal40 */
  2595. uint32_t reserved11; /* ordinal41 */
  2596. uint32_t reserved12; /* ordinal42 */
  2597. uint32_t reserved13; /* ordinal43 */
  2598. uint32_t reserved14; /* ordinal44 */
  2599. uint32_t reserved15; /* ordinal45 */
  2600. uint32_t reserved16; /* ordinal46 */
  2601. uint32_t reserved17; /* ordinal47 */
  2602. uint32_t reserved18; /* ordinal48 */
  2603. uint32_t reserved19; /* ordinal49 */
  2604. uint32_t reserved20; /* ordinal50 */
  2605. uint32_t reserved21; /* ordinal51 */
  2606. uint32_t reserved22; /* ordinal52 */
  2607. uint32_t reserved23; /* ordinal53 */
  2608. uint32_t reserved24; /* ordinal54 */
  2609. uint32_t reserved25; /* ordinal55 */
  2610. uint32_t reserved26; /* ordinal56 */
  2611. uint32_t reserved27; /* ordinal57 */
  2612. uint32_t reserved28; /* ordinal58 */
  2613. uint32_t reserved29; /* ordinal59 */
  2614. uint32_t reserved30; /* ordinal60 */
  2615. uint32_t reserved31; /* ordinal61 */
  2616. uint32_t reserved32; /* ordinal62 */
  2617. uint32_t reserved33; /* ordinal63 */
  2618. uint32_t reserved34; /* ordinal64 */
  2619. uint32_t compute_user_data_0; /* ordinal65 */
  2620. uint32_t compute_user_data_1; /* ordinal66 */
  2621. uint32_t compute_user_data_2; /* ordinal67 */
  2622. uint32_t compute_user_data_3; /* ordinal68 */
  2623. uint32_t compute_user_data_4; /* ordinal69 */
  2624. uint32_t compute_user_data_5; /* ordinal70 */
  2625. uint32_t compute_user_data_6; /* ordinal71 */
  2626. uint32_t compute_user_data_7; /* ordinal72 */
  2627. uint32_t compute_user_data_8; /* ordinal73 */
  2628. uint32_t compute_user_data_9; /* ordinal74 */
  2629. uint32_t compute_user_data_10; /* ordinal75 */
  2630. uint32_t compute_user_data_11; /* ordinal76 */
  2631. uint32_t compute_user_data_12; /* ordinal77 */
  2632. uint32_t compute_user_data_13; /* ordinal78 */
  2633. uint32_t compute_user_data_14; /* ordinal79 */
  2634. uint32_t compute_user_data_15; /* ordinal80 */
  2635. uint32_t cp_compute_csinvoc_count_lo; /* ordinal81 */
  2636. uint32_t cp_compute_csinvoc_count_hi; /* ordinal82 */
  2637. uint32_t reserved35; /* ordinal83 */
  2638. uint32_t reserved36; /* ordinal84 */
  2639. uint32_t reserved37; /* ordinal85 */
  2640. uint32_t cp_mqd_query_time_lo; /* ordinal86 */
  2641. uint32_t cp_mqd_query_time_hi; /* ordinal87 */
  2642. uint32_t cp_mqd_connect_start_time_lo; /* ordinal88 */
  2643. uint32_t cp_mqd_connect_start_time_hi; /* ordinal89 */
  2644. uint32_t cp_mqd_connect_end_time_lo; /* ordinal90 */
  2645. uint32_t cp_mqd_connect_end_time_hi; /* ordinal91 */
  2646. uint32_t cp_mqd_connect_end_wf_count; /* ordinal92 */
  2647. uint32_t cp_mqd_connect_end_pq_rptr; /* ordinal93 */
  2648. uint32_t cp_mqd_connect_end_pq_wptr; /* ordinal94 */
  2649. uint32_t cp_mqd_connect_end_ib_rptr; /* ordinal95 */
  2650. uint32_t reserved38; /* ordinal96 */
  2651. uint32_t reserved39; /* ordinal97 */
  2652. uint32_t cp_mqd_save_start_time_lo; /* ordinal98 */
  2653. uint32_t cp_mqd_save_start_time_hi; /* ordinal99 */
  2654. uint32_t cp_mqd_save_end_time_lo; /* ordinal100 */
  2655. uint32_t cp_mqd_save_end_time_hi; /* ordinal101 */
  2656. uint32_t cp_mqd_restore_start_time_lo; /* ordinal102 */
  2657. uint32_t cp_mqd_restore_start_time_hi; /* ordinal103 */
  2658. uint32_t cp_mqd_restore_end_time_lo; /* ordinal104 */
  2659. uint32_t cp_mqd_restore_end_time_hi; /* ordinal105 */
  2660. uint32_t reserved40; /* ordinal106 */
  2661. uint32_t reserved41; /* ordinal107 */
  2662. uint32_t gds_cs_ctxsw_cnt0; /* ordinal108 */
  2663. uint32_t gds_cs_ctxsw_cnt1; /* ordinal109 */
  2664. uint32_t gds_cs_ctxsw_cnt2; /* ordinal110 */
  2665. uint32_t gds_cs_ctxsw_cnt3; /* ordinal111 */
  2666. uint32_t reserved42; /* ordinal112 */
  2667. uint32_t reserved43; /* ordinal113 */
  2668. uint32_t cp_pq_exe_status_lo; /* ordinal114 */
  2669. uint32_t cp_pq_exe_status_hi; /* ordinal115 */
  2670. uint32_t cp_packet_id_lo; /* ordinal116 */
  2671. uint32_t cp_packet_id_hi; /* ordinal117 */
  2672. uint32_t cp_packet_exe_status_lo; /* ordinal118 */
  2673. uint32_t cp_packet_exe_status_hi; /* ordinal119 */
  2674. uint32_t gds_save_base_addr_lo; /* ordinal120 */
  2675. uint32_t gds_save_base_addr_hi; /* ordinal121 */
  2676. uint32_t gds_save_mask_lo; /* ordinal122 */
  2677. uint32_t gds_save_mask_hi; /* ordinal123 */
  2678. uint32_t ctx_save_base_addr_lo; /* ordinal124 */
  2679. uint32_t ctx_save_base_addr_hi; /* ordinal125 */
  2680. uint32_t reserved44; /* ordinal126 */
  2681. uint32_t reserved45; /* ordinal127 */
  2682. uint32_t cp_mqd_base_addr_lo; /* ordinal128 */
  2683. uint32_t cp_mqd_base_addr_hi; /* ordinal129 */
  2684. uint32_t cp_hqd_active; /* ordinal130 */
  2685. uint32_t cp_hqd_vmid; /* ordinal131 */
  2686. uint32_t cp_hqd_persistent_state; /* ordinal132 */
  2687. uint32_t cp_hqd_pipe_priority; /* ordinal133 */
  2688. uint32_t cp_hqd_queue_priority; /* ordinal134 */
  2689. uint32_t cp_hqd_quantum; /* ordinal135 */
  2690. uint32_t cp_hqd_pq_base_lo; /* ordinal136 */
  2691. uint32_t cp_hqd_pq_base_hi; /* ordinal137 */
  2692. uint32_t cp_hqd_pq_rptr; /* ordinal138 */
  2693. uint32_t cp_hqd_pq_rptr_report_addr_lo; /* ordinal139 */
  2694. uint32_t cp_hqd_pq_rptr_report_addr_hi; /* ordinal140 */
  2695. uint32_t cp_hqd_pq_wptr_poll_addr; /* ordinal141 */
  2696. uint32_t cp_hqd_pq_wptr_poll_addr_hi; /* ordinal142 */
  2697. uint32_t cp_hqd_pq_doorbell_control; /* ordinal143 */
  2698. uint32_t cp_hqd_pq_wptr; /* ordinal144 */
  2699. uint32_t cp_hqd_pq_control; /* ordinal145 */
  2700. uint32_t cp_hqd_ib_base_addr_lo; /* ordinal146 */
  2701. uint32_t cp_hqd_ib_base_addr_hi; /* ordinal147 */
  2702. uint32_t cp_hqd_ib_rptr; /* ordinal148 */
  2703. uint32_t cp_hqd_ib_control; /* ordinal149 */
  2704. uint32_t cp_hqd_iq_timer; /* ordinal150 */
  2705. uint32_t cp_hqd_iq_rptr; /* ordinal151 */
  2706. uint32_t cp_hqd_dequeue_request; /* ordinal152 */
  2707. uint32_t cp_hqd_dma_offload; /* ordinal153 */
  2708. uint32_t cp_hqd_sema_cmd; /* ordinal154 */
  2709. uint32_t cp_hqd_msg_type; /* ordinal155 */
  2710. uint32_t cp_hqd_atomic0_preop_lo; /* ordinal156 */
  2711. uint32_t cp_hqd_atomic0_preop_hi; /* ordinal157 */
  2712. uint32_t cp_hqd_atomic1_preop_lo; /* ordinal158 */
  2713. uint32_t cp_hqd_atomic1_preop_hi; /* ordinal159 */
  2714. uint32_t cp_hqd_hq_status0; /* ordinal160 */
  2715. uint32_t cp_hqd_hq_control0; /* ordinal161 */
  2716. uint32_t cp_mqd_control; /* ordinal162 */
  2717. uint32_t cp_hqd_hq_status1; /* ordinal163 */
  2718. uint32_t cp_hqd_hq_control1; /* ordinal164 */
  2719. uint32_t cp_hqd_eop_base_addr_lo; /* ordinal165 */
  2720. uint32_t cp_hqd_eop_base_addr_hi; /* ordinal166 */
  2721. uint32_t cp_hqd_eop_control; /* ordinal167 */
  2722. uint32_t cp_hqd_eop_rptr; /* ordinal168 */
  2723. uint32_t cp_hqd_eop_wptr; /* ordinal169 */
  2724. uint32_t cp_hqd_eop_done_events; /* ordinal170 */
  2725. uint32_t cp_hqd_ctx_save_base_addr_lo; /* ordinal171 */
  2726. uint32_t cp_hqd_ctx_save_base_addr_hi; /* ordinal172 */
  2727. uint32_t cp_hqd_ctx_save_control; /* ordinal173 */
  2728. uint32_t cp_hqd_cntl_stack_offset; /* ordinal174 */
  2729. uint32_t cp_hqd_cntl_stack_size; /* ordinal175 */
  2730. uint32_t cp_hqd_wg_state_offset; /* ordinal176 */
  2731. uint32_t cp_hqd_ctx_save_size; /* ordinal177 */
  2732. uint32_t cp_hqd_gds_resource_state; /* ordinal178 */
  2733. uint32_t cp_hqd_error; /* ordinal179 */
  2734. uint32_t cp_hqd_eop_wptr_mem; /* ordinal180 */
  2735. uint32_t cp_hqd_eop_dones; /* ordinal181 */
  2736. uint32_t reserved46; /* ordinal182 */
  2737. uint32_t reserved47; /* ordinal183 */
  2738. uint32_t reserved48; /* ordinal184 */
  2739. uint32_t reserved49; /* ordinal185 */
  2740. uint32_t reserved50; /* ordinal186 */
  2741. uint32_t reserved51; /* ordinal187 */
  2742. uint32_t reserved52; /* ordinal188 */
  2743. uint32_t reserved53; /* ordinal189 */
  2744. uint32_t reserved54; /* ordinal190 */
  2745. uint32_t reserved55; /* ordinal191 */
  2746. uint32_t iqtimer_pkt_header; /* ordinal192 */
  2747. uint32_t iqtimer_pkt_dw0; /* ordinal193 */
  2748. uint32_t iqtimer_pkt_dw1; /* ordinal194 */
  2749. uint32_t iqtimer_pkt_dw2; /* ordinal195 */
  2750. uint32_t iqtimer_pkt_dw3; /* ordinal196 */
  2751. uint32_t iqtimer_pkt_dw4; /* ordinal197 */
  2752. uint32_t iqtimer_pkt_dw5; /* ordinal198 */
  2753. uint32_t iqtimer_pkt_dw6; /* ordinal199 */
  2754. uint32_t iqtimer_pkt_dw7; /* ordinal200 */
  2755. uint32_t iqtimer_pkt_dw8; /* ordinal201 */
  2756. uint32_t iqtimer_pkt_dw9; /* ordinal202 */
  2757. uint32_t iqtimer_pkt_dw10; /* ordinal203 */
  2758. uint32_t iqtimer_pkt_dw11; /* ordinal204 */
  2759. uint32_t iqtimer_pkt_dw12; /* ordinal205 */
  2760. uint32_t iqtimer_pkt_dw13; /* ordinal206 */
  2761. uint32_t iqtimer_pkt_dw14; /* ordinal207 */
  2762. uint32_t iqtimer_pkt_dw15; /* ordinal208 */
  2763. uint32_t iqtimer_pkt_dw16; /* ordinal209 */
  2764. uint32_t iqtimer_pkt_dw17; /* ordinal210 */
  2765. uint32_t iqtimer_pkt_dw18; /* ordinal211 */
  2766. uint32_t iqtimer_pkt_dw19; /* ordinal212 */
  2767. uint32_t iqtimer_pkt_dw20; /* ordinal213 */
  2768. uint32_t iqtimer_pkt_dw21; /* ordinal214 */
  2769. uint32_t iqtimer_pkt_dw22; /* ordinal215 */
  2770. uint32_t iqtimer_pkt_dw23; /* ordinal216 */
  2771. uint32_t iqtimer_pkt_dw24; /* ordinal217 */
  2772. uint32_t iqtimer_pkt_dw25; /* ordinal218 */
  2773. uint32_t iqtimer_pkt_dw26; /* ordinal219 */
  2774. uint32_t iqtimer_pkt_dw27; /* ordinal220 */
  2775. uint32_t iqtimer_pkt_dw28; /* ordinal221 */
  2776. uint32_t iqtimer_pkt_dw29; /* ordinal222 */
  2777. uint32_t iqtimer_pkt_dw30; /* ordinal223 */
  2778. uint32_t iqtimer_pkt_dw31; /* ordinal224 */
  2779. uint32_t reserved56; /* ordinal225 */
  2780. uint32_t reserved57; /* ordinal226 */
  2781. uint32_t reserved58; /* ordinal227 */
  2782. uint32_t set_resources_header; /* ordinal228 */
  2783. uint32_t set_resources_dw1; /* ordinal229 */
  2784. uint32_t set_resources_dw2; /* ordinal230 */
  2785. uint32_t set_resources_dw3; /* ordinal231 */
  2786. uint32_t set_resources_dw4; /* ordinal232 */
  2787. uint32_t set_resources_dw5; /* ordinal233 */
  2788. uint32_t set_resources_dw6; /* ordinal234 */
  2789. uint32_t set_resources_dw7; /* ordinal235 */
  2790. uint32_t reserved59; /* ordinal236 */
  2791. uint32_t reserved60; /* ordinal237 */
  2792. uint32_t reserved61; /* ordinal238 */
  2793. uint32_t reserved62; /* ordinal239 */
  2794. uint32_t reserved63; /* ordinal240 */
  2795. uint32_t reserved64; /* ordinal241 */
  2796. uint32_t reserved65; /* ordinal242 */
  2797. uint32_t reserved66; /* ordinal243 */
  2798. uint32_t reserved67; /* ordinal244 */
  2799. uint32_t reserved68; /* ordinal245 */
  2800. uint32_t reserved69; /* ordinal246 */
  2801. uint32_t reserved70; /* ordinal247 */
  2802. uint32_t reserved71; /* ordinal248 */
  2803. uint32_t reserved72; /* ordinal249 */
  2804. uint32_t reserved73; /* ordinal250 */
  2805. uint32_t reserved74; /* ordinal251 */
  2806. uint32_t reserved75; /* ordinal252 */
  2807. uint32_t reserved76; /* ordinal253 */
  2808. uint32_t reserved77; /* ordinal254 */
  2809. uint32_t reserved78; /* ordinal255 */
  2810. uint32_t reserved_t[256]; /* Reserve 256 dword buffer used by ucode */
  2811. };
  2812. static void gfx_v8_0_cp_compute_fini(struct amdgpu_device *adev)
  2813. {
  2814. int i, r;
  2815. for (i = 0; i < adev->gfx.num_compute_rings; i++) {
  2816. struct amdgpu_ring *ring = &adev->gfx.compute_ring[i];
  2817. if (ring->mqd_obj) {
  2818. r = amdgpu_bo_reserve(ring->mqd_obj, false);
  2819. if (unlikely(r != 0))
  2820. dev_warn(adev->dev, "(%d) reserve MQD bo failed\n", r);
  2821. amdgpu_bo_unpin(ring->mqd_obj);
  2822. amdgpu_bo_unreserve(ring->mqd_obj);
  2823. amdgpu_bo_unref(&ring->mqd_obj);
  2824. ring->mqd_obj = NULL;
  2825. }
  2826. }
  2827. }
  2828. static int gfx_v8_0_cp_compute_resume(struct amdgpu_device *adev)
  2829. {
  2830. int r, i, j;
  2831. u32 tmp;
  2832. bool use_doorbell = true;
  2833. u64 hqd_gpu_addr;
  2834. u64 mqd_gpu_addr;
  2835. u64 eop_gpu_addr;
  2836. u64 wb_gpu_addr;
  2837. u32 *buf;
  2838. struct vi_mqd *mqd;
  2839. /* init the pipes */
  2840. mutex_lock(&adev->srbm_mutex);
  2841. for (i = 0; i < (adev->gfx.mec.num_pipe * adev->gfx.mec.num_mec); i++) {
  2842. int me = (i < 4) ? 1 : 2;
  2843. int pipe = (i < 4) ? i : (i - 4);
  2844. eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr + (i * MEC_HPD_SIZE);
  2845. eop_gpu_addr >>= 8;
  2846. vi_srbm_select(adev, me, pipe, 0, 0);
  2847. /* write the EOP addr */
  2848. WREG32(mmCP_HQD_EOP_BASE_ADDR, eop_gpu_addr);
  2849. WREG32(mmCP_HQD_EOP_BASE_ADDR_HI, upper_32_bits(eop_gpu_addr));
  2850. /* set the VMID assigned */
  2851. WREG32(mmCP_HQD_VMID, 0);
  2852. /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
  2853. tmp = RREG32(mmCP_HQD_EOP_CONTROL);
  2854. tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE,
  2855. (order_base_2(MEC_HPD_SIZE / 4) - 1));
  2856. WREG32(mmCP_HQD_EOP_CONTROL, tmp);
  2857. }
  2858. vi_srbm_select(adev, 0, 0, 0, 0);
  2859. mutex_unlock(&adev->srbm_mutex);
  2860. /* init the queues. Just two for now. */
  2861. for (i = 0; i < adev->gfx.num_compute_rings; i++) {
  2862. struct amdgpu_ring *ring = &adev->gfx.compute_ring[i];
  2863. if (ring->mqd_obj == NULL) {
  2864. r = amdgpu_bo_create(adev,
  2865. sizeof(struct vi_mqd),
  2866. PAGE_SIZE, true,
  2867. AMDGPU_GEM_DOMAIN_GTT, 0, NULL,
  2868. &ring->mqd_obj);
  2869. if (r) {
  2870. dev_warn(adev->dev, "(%d) create MQD bo failed\n", r);
  2871. return r;
  2872. }
  2873. }
  2874. r = amdgpu_bo_reserve(ring->mqd_obj, false);
  2875. if (unlikely(r != 0)) {
  2876. gfx_v8_0_cp_compute_fini(adev);
  2877. return r;
  2878. }
  2879. r = amdgpu_bo_pin(ring->mqd_obj, AMDGPU_GEM_DOMAIN_GTT,
  2880. &mqd_gpu_addr);
  2881. if (r) {
  2882. dev_warn(adev->dev, "(%d) pin MQD bo failed\n", r);
  2883. gfx_v8_0_cp_compute_fini(adev);
  2884. return r;
  2885. }
  2886. r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&buf);
  2887. if (r) {
  2888. dev_warn(adev->dev, "(%d) map MQD bo failed\n", r);
  2889. gfx_v8_0_cp_compute_fini(adev);
  2890. return r;
  2891. }
  2892. /* init the mqd struct */
  2893. memset(buf, 0, sizeof(struct vi_mqd));
  2894. mqd = (struct vi_mqd *)buf;
  2895. mqd->header = 0xC0310800;
  2896. mqd->compute_pipelinestat_enable = 0x00000001;
  2897. mqd->compute_static_thread_mgmt_se0 = 0xffffffff;
  2898. mqd->compute_static_thread_mgmt_se1 = 0xffffffff;
  2899. mqd->compute_static_thread_mgmt_se2 = 0xffffffff;
  2900. mqd->compute_static_thread_mgmt_se3 = 0xffffffff;
  2901. mqd->compute_misc_reserved = 0x00000003;
  2902. mutex_lock(&adev->srbm_mutex);
  2903. vi_srbm_select(adev, ring->me,
  2904. ring->pipe,
  2905. ring->queue, 0);
  2906. /* disable wptr polling */
  2907. tmp = RREG32(mmCP_PQ_WPTR_POLL_CNTL);
  2908. tmp = REG_SET_FIELD(tmp, CP_PQ_WPTR_POLL_CNTL, EN, 0);
  2909. WREG32(mmCP_PQ_WPTR_POLL_CNTL, tmp);
  2910. mqd->cp_hqd_eop_base_addr_lo =
  2911. RREG32(mmCP_HQD_EOP_BASE_ADDR);
  2912. mqd->cp_hqd_eop_base_addr_hi =
  2913. RREG32(mmCP_HQD_EOP_BASE_ADDR_HI);
  2914. /* enable doorbell? */
  2915. tmp = RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL);
  2916. if (use_doorbell) {
  2917. tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_EN, 1);
  2918. } else {
  2919. tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_EN, 0);
  2920. }
  2921. WREG32(mmCP_HQD_PQ_DOORBELL_CONTROL, tmp);
  2922. mqd->cp_hqd_pq_doorbell_control = tmp;
  2923. /* disable the queue if it's active */
  2924. mqd->cp_hqd_dequeue_request = 0;
  2925. mqd->cp_hqd_pq_rptr = 0;
  2926. mqd->cp_hqd_pq_wptr= 0;
  2927. if (RREG32(mmCP_HQD_ACTIVE) & 1) {
  2928. WREG32(mmCP_HQD_DEQUEUE_REQUEST, 1);
  2929. for (j = 0; j < adev->usec_timeout; j++) {
  2930. if (!(RREG32(mmCP_HQD_ACTIVE) & 1))
  2931. break;
  2932. udelay(1);
  2933. }
  2934. WREG32(mmCP_HQD_DEQUEUE_REQUEST, mqd->cp_hqd_dequeue_request);
  2935. WREG32(mmCP_HQD_PQ_RPTR, mqd->cp_hqd_pq_rptr);
  2936. WREG32(mmCP_HQD_PQ_WPTR, mqd->cp_hqd_pq_wptr);
  2937. }
  2938. /* set the pointer to the MQD */
  2939. mqd->cp_mqd_base_addr_lo = mqd_gpu_addr & 0xfffffffc;
  2940. mqd->cp_mqd_base_addr_hi = upper_32_bits(mqd_gpu_addr);
  2941. WREG32(mmCP_MQD_BASE_ADDR, mqd->cp_mqd_base_addr_lo);
  2942. WREG32(mmCP_MQD_BASE_ADDR_HI, mqd->cp_mqd_base_addr_hi);
  2943. /* set MQD vmid to 0 */
  2944. tmp = RREG32(mmCP_MQD_CONTROL);
  2945. tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);
  2946. WREG32(mmCP_MQD_CONTROL, tmp);
  2947. mqd->cp_mqd_control = tmp;
  2948. /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
  2949. hqd_gpu_addr = ring->gpu_addr >> 8;
  2950. mqd->cp_hqd_pq_base_lo = hqd_gpu_addr;
  2951. mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);
  2952. WREG32(mmCP_HQD_PQ_BASE, mqd->cp_hqd_pq_base_lo);
  2953. WREG32(mmCP_HQD_PQ_BASE_HI, mqd->cp_hqd_pq_base_hi);
  2954. /* set up the HQD, this is similar to CP_RB0_CNTL */
  2955. tmp = RREG32(mmCP_HQD_PQ_CONTROL);
  2956. tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,
  2957. (order_base_2(ring->ring_size / 4) - 1));
  2958. tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,
  2959. ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8));
  2960. #ifdef __BIG_ENDIAN
  2961. tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1);
  2962. #endif
  2963. tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0);
  2964. tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ROQ_PQ_IB_FLIP, 0);
  2965. tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);
  2966. tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);
  2967. WREG32(mmCP_HQD_PQ_CONTROL, tmp);
  2968. mqd->cp_hqd_pq_control = tmp;
  2969. /* set the wb address wether it's enabled or not */
  2970. wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
  2971. mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc;
  2972. mqd->cp_hqd_pq_rptr_report_addr_hi =
  2973. upper_32_bits(wb_gpu_addr) & 0xffff;
  2974. WREG32(mmCP_HQD_PQ_RPTR_REPORT_ADDR,
  2975. mqd->cp_hqd_pq_rptr_report_addr_lo);
  2976. WREG32(mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI,
  2977. mqd->cp_hqd_pq_rptr_report_addr_hi);
  2978. /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
  2979. wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
  2980. mqd->cp_hqd_pq_wptr_poll_addr = wb_gpu_addr & 0xfffffffc;
  2981. mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
  2982. WREG32(mmCP_HQD_PQ_WPTR_POLL_ADDR, mqd->cp_hqd_pq_wptr_poll_addr);
  2983. WREG32(mmCP_HQD_PQ_WPTR_POLL_ADDR_HI,
  2984. mqd->cp_hqd_pq_wptr_poll_addr_hi);
  2985. /* enable the doorbell if requested */
  2986. if (use_doorbell) {
  2987. if (adev->asic_type == CHIP_CARRIZO) {
  2988. WREG32(mmCP_MEC_DOORBELL_RANGE_LOWER,
  2989. AMDGPU_DOORBELL_KIQ << 2);
  2990. WREG32(mmCP_MEC_DOORBELL_RANGE_UPPER,
  2991. AMDGPU_DOORBELL_MEC_RING7 << 2);
  2992. }
  2993. tmp = RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL);
  2994. tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
  2995. DOORBELL_OFFSET, ring->doorbell_index);
  2996. tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_EN, 1);
  2997. tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_SOURCE, 0);
  2998. tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_HIT, 0);
  2999. mqd->cp_hqd_pq_doorbell_control = tmp;
  3000. } else {
  3001. mqd->cp_hqd_pq_doorbell_control = 0;
  3002. }
  3003. WREG32(mmCP_HQD_PQ_DOORBELL_CONTROL,
  3004. mqd->cp_hqd_pq_doorbell_control);
  3005. /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
  3006. ring->wptr = 0;
  3007. mqd->cp_hqd_pq_wptr = ring->wptr;
  3008. WREG32(mmCP_HQD_PQ_WPTR, mqd->cp_hqd_pq_wptr);
  3009. mqd->cp_hqd_pq_rptr = RREG32(mmCP_HQD_PQ_RPTR);
  3010. /* set the vmid for the queue */
  3011. mqd->cp_hqd_vmid = 0;
  3012. WREG32(mmCP_HQD_VMID, mqd->cp_hqd_vmid);
  3013. tmp = RREG32(mmCP_HQD_PERSISTENT_STATE);
  3014. tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53);
  3015. WREG32(mmCP_HQD_PERSISTENT_STATE, tmp);
  3016. mqd->cp_hqd_persistent_state = tmp;
  3017. /* activate the queue */
  3018. mqd->cp_hqd_active = 1;
  3019. WREG32(mmCP_HQD_ACTIVE, mqd->cp_hqd_active);
  3020. vi_srbm_select(adev, 0, 0, 0, 0);
  3021. mutex_unlock(&adev->srbm_mutex);
  3022. amdgpu_bo_kunmap(ring->mqd_obj);
  3023. amdgpu_bo_unreserve(ring->mqd_obj);
  3024. }
  3025. if (use_doorbell) {
  3026. tmp = RREG32(mmCP_PQ_STATUS);
  3027. tmp = REG_SET_FIELD(tmp, CP_PQ_STATUS, DOORBELL_ENABLE, 1);
  3028. WREG32(mmCP_PQ_STATUS, tmp);
  3029. }
  3030. r = gfx_v8_0_cp_compute_start(adev);
  3031. if (r)
  3032. return r;
  3033. for (i = 0; i < adev->gfx.num_compute_rings; i++) {
  3034. struct amdgpu_ring *ring = &adev->gfx.compute_ring[i];
  3035. ring->ready = true;
  3036. r = amdgpu_ring_test_ring(ring);
  3037. if (r)
  3038. ring->ready = false;
  3039. }
  3040. return 0;
  3041. }
  3042. static int gfx_v8_0_cp_resume(struct amdgpu_device *adev)
  3043. {
  3044. int r;
  3045. if (adev->asic_type != CHIP_CARRIZO)
  3046. gfx_v8_0_enable_gui_idle_interrupt(adev, false);
  3047. if (!adev->firmware.smu_load) {
  3048. /* legacy firmware loading */
  3049. r = gfx_v8_0_cp_gfx_load_microcode(adev);
  3050. if (r)
  3051. return r;
  3052. r = gfx_v8_0_cp_compute_load_microcode(adev);
  3053. if (r)
  3054. return r;
  3055. } else {
  3056. r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
  3057. AMDGPU_UCODE_ID_CP_CE);
  3058. if (r)
  3059. return -EINVAL;
  3060. r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
  3061. AMDGPU_UCODE_ID_CP_PFP);
  3062. if (r)
  3063. return -EINVAL;
  3064. r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
  3065. AMDGPU_UCODE_ID_CP_ME);
  3066. if (r)
  3067. return -EINVAL;
  3068. r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
  3069. AMDGPU_UCODE_ID_CP_MEC1);
  3070. if (r)
  3071. return -EINVAL;
  3072. }
  3073. r = gfx_v8_0_cp_gfx_resume(adev);
  3074. if (r)
  3075. return r;
  3076. r = gfx_v8_0_cp_compute_resume(adev);
  3077. if (r)
  3078. return r;
  3079. gfx_v8_0_enable_gui_idle_interrupt(adev, true);
  3080. return 0;
  3081. }
  3082. static void gfx_v8_0_cp_enable(struct amdgpu_device *adev, bool enable)
  3083. {
  3084. gfx_v8_0_cp_gfx_enable(adev, enable);
  3085. gfx_v8_0_cp_compute_enable(adev, enable);
  3086. }
  3087. static int gfx_v8_0_hw_init(void *handle)
  3088. {
  3089. int r;
  3090. struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  3091. gfx_v8_0_init_golden_registers(adev);
  3092. gfx_v8_0_gpu_init(adev);
  3093. r = gfx_v8_0_rlc_resume(adev);
  3094. if (r)
  3095. return r;
  3096. r = gfx_v8_0_cp_resume(adev);
  3097. if (r)
  3098. return r;
  3099. return r;
  3100. }
  3101. static int gfx_v8_0_hw_fini(void *handle)
  3102. {
  3103. struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  3104. gfx_v8_0_cp_enable(adev, false);
  3105. gfx_v8_0_rlc_stop(adev);
  3106. gfx_v8_0_cp_compute_fini(adev);
  3107. return 0;
  3108. }
  3109. static int gfx_v8_0_suspend(void *handle)
  3110. {
  3111. struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  3112. return gfx_v8_0_hw_fini(adev);
  3113. }
  3114. static int gfx_v8_0_resume(void *handle)
  3115. {
  3116. struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  3117. return gfx_v8_0_hw_init(adev);
  3118. }
  3119. static bool gfx_v8_0_is_idle(void *handle)
  3120. {
  3121. struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  3122. if (REG_GET_FIELD(RREG32(mmGRBM_STATUS), GRBM_STATUS, GUI_ACTIVE))
  3123. return false;
  3124. else
  3125. return true;
  3126. }
  3127. static int gfx_v8_0_wait_for_idle(void *handle)
  3128. {
  3129. unsigned i;
  3130. u32 tmp;
  3131. struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  3132. for (i = 0; i < adev->usec_timeout; i++) {
  3133. /* read MC_STATUS */
  3134. tmp = RREG32(mmGRBM_STATUS) & GRBM_STATUS__GUI_ACTIVE_MASK;
  3135. if (!REG_GET_FIELD(tmp, GRBM_STATUS, GUI_ACTIVE))
  3136. return 0;
  3137. udelay(1);
  3138. }
  3139. return -ETIMEDOUT;
  3140. }
  3141. static void gfx_v8_0_print_status(void *handle)
  3142. {
  3143. int i;
  3144. struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  3145. dev_info(adev->dev, "GFX 8.x registers\n");
  3146. dev_info(adev->dev, " GRBM_STATUS=0x%08X\n",
  3147. RREG32(mmGRBM_STATUS));
  3148. dev_info(adev->dev, " GRBM_STATUS2=0x%08X\n",
  3149. RREG32(mmGRBM_STATUS2));
  3150. dev_info(adev->dev, " GRBM_STATUS_SE0=0x%08X\n",
  3151. RREG32(mmGRBM_STATUS_SE0));
  3152. dev_info(adev->dev, " GRBM_STATUS_SE1=0x%08X\n",
  3153. RREG32(mmGRBM_STATUS_SE1));
  3154. dev_info(adev->dev, " GRBM_STATUS_SE2=0x%08X\n",
  3155. RREG32(mmGRBM_STATUS_SE2));
  3156. dev_info(adev->dev, " GRBM_STATUS_SE3=0x%08X\n",
  3157. RREG32(mmGRBM_STATUS_SE3));
  3158. dev_info(adev->dev, " CP_STAT = 0x%08x\n", RREG32(mmCP_STAT));
  3159. dev_info(adev->dev, " CP_STALLED_STAT1 = 0x%08x\n",
  3160. RREG32(mmCP_STALLED_STAT1));
  3161. dev_info(adev->dev, " CP_STALLED_STAT2 = 0x%08x\n",
  3162. RREG32(mmCP_STALLED_STAT2));
  3163. dev_info(adev->dev, " CP_STALLED_STAT3 = 0x%08x\n",
  3164. RREG32(mmCP_STALLED_STAT3));
  3165. dev_info(adev->dev, " CP_CPF_BUSY_STAT = 0x%08x\n",
  3166. RREG32(mmCP_CPF_BUSY_STAT));
  3167. dev_info(adev->dev, " CP_CPF_STALLED_STAT1 = 0x%08x\n",
  3168. RREG32(mmCP_CPF_STALLED_STAT1));
  3169. dev_info(adev->dev, " CP_CPF_STATUS = 0x%08x\n", RREG32(mmCP_CPF_STATUS));
  3170. dev_info(adev->dev, " CP_CPC_BUSY_STAT = 0x%08x\n", RREG32(mmCP_CPC_BUSY_STAT));
  3171. dev_info(adev->dev, " CP_CPC_STALLED_STAT1 = 0x%08x\n",
  3172. RREG32(mmCP_CPC_STALLED_STAT1));
  3173. dev_info(adev->dev, " CP_CPC_STATUS = 0x%08x\n", RREG32(mmCP_CPC_STATUS));
  3174. for (i = 0; i < 32; i++) {
  3175. dev_info(adev->dev, " GB_TILE_MODE%d=0x%08X\n",
  3176. i, RREG32(mmGB_TILE_MODE0 + (i * 4)));
  3177. }
  3178. for (i = 0; i < 16; i++) {
  3179. dev_info(adev->dev, " GB_MACROTILE_MODE%d=0x%08X\n",
  3180. i, RREG32(mmGB_MACROTILE_MODE0 + (i * 4)));
  3181. }
  3182. for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
  3183. dev_info(adev->dev, " se: %d\n", i);
  3184. gfx_v8_0_select_se_sh(adev, i, 0xffffffff);
  3185. dev_info(adev->dev, " PA_SC_RASTER_CONFIG=0x%08X\n",
  3186. RREG32(mmPA_SC_RASTER_CONFIG));
  3187. dev_info(adev->dev, " PA_SC_RASTER_CONFIG_1=0x%08X\n",
  3188. RREG32(mmPA_SC_RASTER_CONFIG_1));
  3189. }
  3190. gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
  3191. dev_info(adev->dev, " GB_ADDR_CONFIG=0x%08X\n",
  3192. RREG32(mmGB_ADDR_CONFIG));
  3193. dev_info(adev->dev, " HDP_ADDR_CONFIG=0x%08X\n",
  3194. RREG32(mmHDP_ADDR_CONFIG));
  3195. dev_info(adev->dev, " DMIF_ADDR_CALC=0x%08X\n",
  3196. RREG32(mmDMIF_ADDR_CALC));
  3197. dev_info(adev->dev, " SDMA0_TILING_CONFIG=0x%08X\n",
  3198. RREG32(mmSDMA0_TILING_CONFIG + SDMA0_REGISTER_OFFSET));
  3199. dev_info(adev->dev, " SDMA1_TILING_CONFIG=0x%08X\n",
  3200. RREG32(mmSDMA0_TILING_CONFIG + SDMA1_REGISTER_OFFSET));
  3201. dev_info(adev->dev, " UVD_UDEC_ADDR_CONFIG=0x%08X\n",
  3202. RREG32(mmUVD_UDEC_ADDR_CONFIG));
  3203. dev_info(adev->dev, " UVD_UDEC_DB_ADDR_CONFIG=0x%08X\n",
  3204. RREG32(mmUVD_UDEC_DB_ADDR_CONFIG));
  3205. dev_info(adev->dev, " UVD_UDEC_DBW_ADDR_CONFIG=0x%08X\n",
  3206. RREG32(mmUVD_UDEC_DBW_ADDR_CONFIG));
  3207. dev_info(adev->dev, " CP_MEQ_THRESHOLDS=0x%08X\n",
  3208. RREG32(mmCP_MEQ_THRESHOLDS));
  3209. dev_info(adev->dev, " SX_DEBUG_1=0x%08X\n",
  3210. RREG32(mmSX_DEBUG_1));
  3211. dev_info(adev->dev, " TA_CNTL_AUX=0x%08X\n",
  3212. RREG32(mmTA_CNTL_AUX));
  3213. dev_info(adev->dev, " SPI_CONFIG_CNTL=0x%08X\n",
  3214. RREG32(mmSPI_CONFIG_CNTL));
  3215. dev_info(adev->dev, " SQ_CONFIG=0x%08X\n",
  3216. RREG32(mmSQ_CONFIG));
  3217. dev_info(adev->dev, " DB_DEBUG=0x%08X\n",
  3218. RREG32(mmDB_DEBUG));
  3219. dev_info(adev->dev, " DB_DEBUG2=0x%08X\n",
  3220. RREG32(mmDB_DEBUG2));
  3221. dev_info(adev->dev, " DB_DEBUG3=0x%08X\n",
  3222. RREG32(mmDB_DEBUG3));
  3223. dev_info(adev->dev, " CB_HW_CONTROL=0x%08X\n",
  3224. RREG32(mmCB_HW_CONTROL));
  3225. dev_info(adev->dev, " SPI_CONFIG_CNTL_1=0x%08X\n",
  3226. RREG32(mmSPI_CONFIG_CNTL_1));
  3227. dev_info(adev->dev, " PA_SC_FIFO_SIZE=0x%08X\n",
  3228. RREG32(mmPA_SC_FIFO_SIZE));
  3229. dev_info(adev->dev, " VGT_NUM_INSTANCES=0x%08X\n",
  3230. RREG32(mmVGT_NUM_INSTANCES));
  3231. dev_info(adev->dev, " CP_PERFMON_CNTL=0x%08X\n",
  3232. RREG32(mmCP_PERFMON_CNTL));
  3233. dev_info(adev->dev, " PA_SC_FORCE_EOV_MAX_CNTS=0x%08X\n",
  3234. RREG32(mmPA_SC_FORCE_EOV_MAX_CNTS));
  3235. dev_info(adev->dev, " VGT_CACHE_INVALIDATION=0x%08X\n",
  3236. RREG32(mmVGT_CACHE_INVALIDATION));
  3237. dev_info(adev->dev, " VGT_GS_VERTEX_REUSE=0x%08X\n",
  3238. RREG32(mmVGT_GS_VERTEX_REUSE));
  3239. dev_info(adev->dev, " PA_SC_LINE_STIPPLE_STATE=0x%08X\n",
  3240. RREG32(mmPA_SC_LINE_STIPPLE_STATE));
  3241. dev_info(adev->dev, " PA_CL_ENHANCE=0x%08X\n",
  3242. RREG32(mmPA_CL_ENHANCE));
  3243. dev_info(adev->dev, " PA_SC_ENHANCE=0x%08X\n",
  3244. RREG32(mmPA_SC_ENHANCE));
  3245. dev_info(adev->dev, " CP_ME_CNTL=0x%08X\n",
  3246. RREG32(mmCP_ME_CNTL));
  3247. dev_info(adev->dev, " CP_MAX_CONTEXT=0x%08X\n",
  3248. RREG32(mmCP_MAX_CONTEXT));
  3249. dev_info(adev->dev, " CP_ENDIAN_SWAP=0x%08X\n",
  3250. RREG32(mmCP_ENDIAN_SWAP));
  3251. dev_info(adev->dev, " CP_DEVICE_ID=0x%08X\n",
  3252. RREG32(mmCP_DEVICE_ID));
  3253. dev_info(adev->dev, " CP_SEM_WAIT_TIMER=0x%08X\n",
  3254. RREG32(mmCP_SEM_WAIT_TIMER));
  3255. dev_info(adev->dev, " CP_RB_WPTR_DELAY=0x%08X\n",
  3256. RREG32(mmCP_RB_WPTR_DELAY));
  3257. dev_info(adev->dev, " CP_RB_VMID=0x%08X\n",
  3258. RREG32(mmCP_RB_VMID));
  3259. dev_info(adev->dev, " CP_RB0_CNTL=0x%08X\n",
  3260. RREG32(mmCP_RB0_CNTL));
  3261. dev_info(adev->dev, " CP_RB0_WPTR=0x%08X\n",
  3262. RREG32(mmCP_RB0_WPTR));
  3263. dev_info(adev->dev, " CP_RB0_RPTR_ADDR=0x%08X\n",
  3264. RREG32(mmCP_RB0_RPTR_ADDR));
  3265. dev_info(adev->dev, " CP_RB0_RPTR_ADDR_HI=0x%08X\n",
  3266. RREG32(mmCP_RB0_RPTR_ADDR_HI));
  3267. dev_info(adev->dev, " CP_RB0_CNTL=0x%08X\n",
  3268. RREG32(mmCP_RB0_CNTL));
  3269. dev_info(adev->dev, " CP_RB0_BASE=0x%08X\n",
  3270. RREG32(mmCP_RB0_BASE));
  3271. dev_info(adev->dev, " CP_RB0_BASE_HI=0x%08X\n",
  3272. RREG32(mmCP_RB0_BASE_HI));
  3273. dev_info(adev->dev, " CP_MEC_CNTL=0x%08X\n",
  3274. RREG32(mmCP_MEC_CNTL));
  3275. dev_info(adev->dev, " CP_CPF_DEBUG=0x%08X\n",
  3276. RREG32(mmCP_CPF_DEBUG));
  3277. dev_info(adev->dev, " SCRATCH_ADDR=0x%08X\n",
  3278. RREG32(mmSCRATCH_ADDR));
  3279. dev_info(adev->dev, " SCRATCH_UMSK=0x%08X\n",
  3280. RREG32(mmSCRATCH_UMSK));
  3281. dev_info(adev->dev, " CP_INT_CNTL_RING0=0x%08X\n",
  3282. RREG32(mmCP_INT_CNTL_RING0));
  3283. dev_info(adev->dev, " RLC_LB_CNTL=0x%08X\n",
  3284. RREG32(mmRLC_LB_CNTL));
  3285. dev_info(adev->dev, " RLC_CNTL=0x%08X\n",
  3286. RREG32(mmRLC_CNTL));
  3287. dev_info(adev->dev, " RLC_CGCG_CGLS_CTRL=0x%08X\n",
  3288. RREG32(mmRLC_CGCG_CGLS_CTRL));
  3289. dev_info(adev->dev, " RLC_LB_CNTR_INIT=0x%08X\n",
  3290. RREG32(mmRLC_LB_CNTR_INIT));
  3291. dev_info(adev->dev, " RLC_LB_CNTR_MAX=0x%08X\n",
  3292. RREG32(mmRLC_LB_CNTR_MAX));
  3293. dev_info(adev->dev, " RLC_LB_INIT_CU_MASK=0x%08X\n",
  3294. RREG32(mmRLC_LB_INIT_CU_MASK));
  3295. dev_info(adev->dev, " RLC_LB_PARAMS=0x%08X\n",
  3296. RREG32(mmRLC_LB_PARAMS));
  3297. dev_info(adev->dev, " RLC_LB_CNTL=0x%08X\n",
  3298. RREG32(mmRLC_LB_CNTL));
  3299. dev_info(adev->dev, " RLC_MC_CNTL=0x%08X\n",
  3300. RREG32(mmRLC_MC_CNTL));
  3301. dev_info(adev->dev, " RLC_UCODE_CNTL=0x%08X\n",
  3302. RREG32(mmRLC_UCODE_CNTL));
  3303. mutex_lock(&adev->srbm_mutex);
  3304. for (i = 0; i < 16; i++) {
  3305. vi_srbm_select(adev, 0, 0, 0, i);
  3306. dev_info(adev->dev, " VM %d:\n", i);
  3307. dev_info(adev->dev, " SH_MEM_CONFIG=0x%08X\n",
  3308. RREG32(mmSH_MEM_CONFIG));
  3309. dev_info(adev->dev, " SH_MEM_APE1_BASE=0x%08X\n",
  3310. RREG32(mmSH_MEM_APE1_BASE));
  3311. dev_info(adev->dev, " SH_MEM_APE1_LIMIT=0x%08X\n",
  3312. RREG32(mmSH_MEM_APE1_LIMIT));
  3313. dev_info(adev->dev, " SH_MEM_BASES=0x%08X\n",
  3314. RREG32(mmSH_MEM_BASES));
  3315. }
  3316. vi_srbm_select(adev, 0, 0, 0, 0);
  3317. mutex_unlock(&adev->srbm_mutex);
  3318. }
  3319. static int gfx_v8_0_soft_reset(void *handle)
  3320. {
  3321. u32 grbm_soft_reset = 0, srbm_soft_reset = 0;
  3322. u32 tmp;
  3323. struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  3324. /* GRBM_STATUS */
  3325. tmp = RREG32(mmGRBM_STATUS);
  3326. if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK |
  3327. GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK |
  3328. GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__VGT_BUSY_MASK |
  3329. GRBM_STATUS__DB_BUSY_MASK | GRBM_STATUS__CB_BUSY_MASK |
  3330. GRBM_STATUS__GDS_BUSY_MASK | GRBM_STATUS__SPI_BUSY_MASK |
  3331. GRBM_STATUS__IA_BUSY_MASK | GRBM_STATUS__IA_BUSY_NO_DMA_MASK)) {
  3332. grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
  3333. GRBM_SOFT_RESET, SOFT_RESET_CP, 1);
  3334. grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
  3335. GRBM_SOFT_RESET, SOFT_RESET_GFX, 1);
  3336. }
  3337. if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) {
  3338. grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
  3339. GRBM_SOFT_RESET, SOFT_RESET_CP, 1);
  3340. srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
  3341. SRBM_SOFT_RESET, SOFT_RESET_GRBM, 1);
  3342. }
  3343. /* GRBM_STATUS2 */
  3344. tmp = RREG32(mmGRBM_STATUS2);
  3345. if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY))
  3346. grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
  3347. GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
  3348. /* SRBM_STATUS */
  3349. tmp = RREG32(mmSRBM_STATUS);
  3350. if (REG_GET_FIELD(tmp, SRBM_STATUS, GRBM_RQ_PENDING))
  3351. srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
  3352. SRBM_SOFT_RESET, SOFT_RESET_GRBM, 1);
  3353. if (grbm_soft_reset || srbm_soft_reset) {
  3354. gfx_v8_0_print_status((void *)adev);
  3355. /* stop the rlc */
  3356. gfx_v8_0_rlc_stop(adev);
  3357. /* Disable GFX parsing/prefetching */
  3358. gfx_v8_0_cp_gfx_enable(adev, false);
  3359. /* Disable MEC parsing/prefetching */
  3360. /* XXX todo */
  3361. if (grbm_soft_reset) {
  3362. tmp = RREG32(mmGRBM_SOFT_RESET);
  3363. tmp |= grbm_soft_reset;
  3364. dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
  3365. WREG32(mmGRBM_SOFT_RESET, tmp);
  3366. tmp = RREG32(mmGRBM_SOFT_RESET);
  3367. udelay(50);
  3368. tmp &= ~grbm_soft_reset;
  3369. WREG32(mmGRBM_SOFT_RESET, tmp);
  3370. tmp = RREG32(mmGRBM_SOFT_RESET);
  3371. }
  3372. if (srbm_soft_reset) {
  3373. tmp = RREG32(mmSRBM_SOFT_RESET);
  3374. tmp |= srbm_soft_reset;
  3375. dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
  3376. WREG32(mmSRBM_SOFT_RESET, tmp);
  3377. tmp = RREG32(mmSRBM_SOFT_RESET);
  3378. udelay(50);
  3379. tmp &= ~srbm_soft_reset;
  3380. WREG32(mmSRBM_SOFT_RESET, tmp);
  3381. tmp = RREG32(mmSRBM_SOFT_RESET);
  3382. }
  3383. /* Wait a little for things to settle down */
  3384. udelay(50);
  3385. gfx_v8_0_print_status((void *)adev);
  3386. }
  3387. return 0;
  3388. }
  3389. /**
  3390. * gfx_v8_0_get_gpu_clock_counter - return GPU clock counter snapshot
  3391. *
  3392. * @adev: amdgpu_device pointer
  3393. *
  3394. * Fetches a GPU clock counter snapshot.
  3395. * Returns the 64 bit clock counter snapshot.
  3396. */
  3397. uint64_t gfx_v8_0_get_gpu_clock_counter(struct amdgpu_device *adev)
  3398. {
  3399. uint64_t clock;
  3400. mutex_lock(&adev->gfx.gpu_clock_mutex);
  3401. WREG32(mmRLC_CAPTURE_GPU_CLOCK_COUNT, 1);
  3402. clock = (uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_LSB) |
  3403. ((uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_MSB) << 32ULL);
  3404. mutex_unlock(&adev->gfx.gpu_clock_mutex);
  3405. return clock;
  3406. }
  3407. static void gfx_v8_0_ring_emit_gds_switch(struct amdgpu_ring *ring,
  3408. uint32_t vmid,
  3409. uint32_t gds_base, uint32_t gds_size,
  3410. uint32_t gws_base, uint32_t gws_size,
  3411. uint32_t oa_base, uint32_t oa_size)
  3412. {
  3413. gds_base = gds_base >> AMDGPU_GDS_SHIFT;
  3414. gds_size = gds_size >> AMDGPU_GDS_SHIFT;
  3415. gws_base = gws_base >> AMDGPU_GWS_SHIFT;
  3416. gws_size = gws_size >> AMDGPU_GWS_SHIFT;
  3417. oa_base = oa_base >> AMDGPU_OA_SHIFT;
  3418. oa_size = oa_size >> AMDGPU_OA_SHIFT;
  3419. /* GDS Base */
  3420. amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
  3421. amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
  3422. WRITE_DATA_DST_SEL(0)));
  3423. amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].mem_base);
  3424. amdgpu_ring_write(ring, 0);
  3425. amdgpu_ring_write(ring, gds_base);
  3426. /* GDS Size */
  3427. amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
  3428. amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
  3429. WRITE_DATA_DST_SEL(0)));
  3430. amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].mem_size);
  3431. amdgpu_ring_write(ring, 0);
  3432. amdgpu_ring_write(ring, gds_size);
  3433. /* GWS */
  3434. amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
  3435. amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
  3436. WRITE_DATA_DST_SEL(0)));
  3437. amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].gws);
  3438. amdgpu_ring_write(ring, 0);
  3439. amdgpu_ring_write(ring, gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base);
  3440. /* OA */
  3441. amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
  3442. amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
  3443. WRITE_DATA_DST_SEL(0)));
  3444. amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].oa);
  3445. amdgpu_ring_write(ring, 0);
  3446. amdgpu_ring_write(ring, (1 << (oa_size + oa_base)) - (1 << oa_base));
  3447. }
  3448. static int gfx_v8_0_early_init(void *handle)
  3449. {
  3450. struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  3451. adev->gfx.num_gfx_rings = GFX8_NUM_GFX_RINGS;
  3452. adev->gfx.num_compute_rings = GFX8_NUM_COMPUTE_RINGS;
  3453. gfx_v8_0_set_ring_funcs(adev);
  3454. gfx_v8_0_set_irq_funcs(adev);
  3455. gfx_v8_0_set_gds_init(adev);
  3456. return 0;
  3457. }
  3458. static int gfx_v8_0_set_powergating_state(void *handle,
  3459. enum amd_powergating_state state)
  3460. {
  3461. return 0;
  3462. }
  3463. static int gfx_v8_0_set_clockgating_state(void *handle,
  3464. enum amd_clockgating_state state)
  3465. {
  3466. return 0;
  3467. }
  3468. static u32 gfx_v8_0_ring_get_rptr_gfx(struct amdgpu_ring *ring)
  3469. {
  3470. u32 rptr;
  3471. rptr = ring->adev->wb.wb[ring->rptr_offs];
  3472. return rptr;
  3473. }
  3474. static u32 gfx_v8_0_ring_get_wptr_gfx(struct amdgpu_ring *ring)
  3475. {
  3476. struct amdgpu_device *adev = ring->adev;
  3477. u32 wptr;
  3478. if (ring->use_doorbell)
  3479. /* XXX check if swapping is necessary on BE */
  3480. wptr = ring->adev->wb.wb[ring->wptr_offs];
  3481. else
  3482. wptr = RREG32(mmCP_RB0_WPTR);
  3483. return wptr;
  3484. }
  3485. static void gfx_v8_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
  3486. {
  3487. struct amdgpu_device *adev = ring->adev;
  3488. if (ring->use_doorbell) {
  3489. /* XXX check if swapping is necessary on BE */
  3490. adev->wb.wb[ring->wptr_offs] = ring->wptr;
  3491. WDOORBELL32(ring->doorbell_index, ring->wptr);
  3492. } else {
  3493. WREG32(mmCP_RB0_WPTR, ring->wptr);
  3494. (void)RREG32(mmCP_RB0_WPTR);
  3495. }
  3496. }
  3497. static void gfx_v8_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
  3498. {
  3499. u32 ref_and_mask, reg_mem_engine;
  3500. if (ring->type == AMDGPU_RING_TYPE_COMPUTE) {
  3501. switch (ring->me) {
  3502. case 1:
  3503. ref_and_mask = GPU_HDP_FLUSH_DONE__CP2_MASK << ring->pipe;
  3504. break;
  3505. case 2:
  3506. ref_and_mask = GPU_HDP_FLUSH_DONE__CP6_MASK << ring->pipe;
  3507. break;
  3508. default:
  3509. return;
  3510. }
  3511. reg_mem_engine = 0;
  3512. } else {
  3513. ref_and_mask = GPU_HDP_FLUSH_DONE__CP0_MASK;
  3514. reg_mem_engine = WAIT_REG_MEM_ENGINE(1); /* pfp */
  3515. }
  3516. amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
  3517. amdgpu_ring_write(ring, (WAIT_REG_MEM_OPERATION(1) | /* write, wait, write */
  3518. WAIT_REG_MEM_FUNCTION(3) | /* == */
  3519. reg_mem_engine));
  3520. amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ);
  3521. amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE);
  3522. amdgpu_ring_write(ring, ref_and_mask);
  3523. amdgpu_ring_write(ring, ref_and_mask);
  3524. amdgpu_ring_write(ring, 0x20); /* poll interval */
  3525. }
  3526. static void gfx_v8_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
  3527. struct amdgpu_ib *ib)
  3528. {
  3529. bool need_ctx_switch = ring->current_ctx != ib->ctx;
  3530. u32 header, control = 0;
  3531. u32 next_rptr = ring->wptr + 5;
  3532. /* drop the CE preamble IB for the same context */
  3533. if ((ib->flags & AMDGPU_IB_FLAG_PREAMBLE) && !need_ctx_switch)
  3534. return;
  3535. if (need_ctx_switch)
  3536. next_rptr += 2;
  3537. next_rptr += 4;
  3538. amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
  3539. amdgpu_ring_write(ring, WRITE_DATA_DST_SEL(5) | WR_CONFIRM);
  3540. amdgpu_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
  3541. amdgpu_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xffffffff);
  3542. amdgpu_ring_write(ring, next_rptr);
  3543. /* insert SWITCH_BUFFER packet before first IB in the ring frame */
  3544. if (need_ctx_switch) {
  3545. amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
  3546. amdgpu_ring_write(ring, 0);
  3547. }
  3548. if (ib->flags & AMDGPU_IB_FLAG_CE)
  3549. header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2);
  3550. else
  3551. header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
  3552. control |= ib->length_dw |
  3553. (ib->vm ? (ib->vm->ids[ring->idx].id << 24) : 0);
  3554. amdgpu_ring_write(ring, header);
  3555. amdgpu_ring_write(ring,
  3556. #ifdef __BIG_ENDIAN
  3557. (2 << 0) |
  3558. #endif
  3559. (ib->gpu_addr & 0xFFFFFFFC));
  3560. amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF);
  3561. amdgpu_ring_write(ring, control);
  3562. }
  3563. static void gfx_v8_0_ring_emit_ib_compute(struct amdgpu_ring *ring,
  3564. struct amdgpu_ib *ib)
  3565. {
  3566. u32 header, control = 0;
  3567. u32 next_rptr = ring->wptr + 5;
  3568. control |= INDIRECT_BUFFER_VALID;
  3569. next_rptr += 4;
  3570. amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
  3571. amdgpu_ring_write(ring, WRITE_DATA_DST_SEL(5) | WR_CONFIRM);
  3572. amdgpu_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
  3573. amdgpu_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xffffffff);
  3574. amdgpu_ring_write(ring, next_rptr);
  3575. header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
  3576. control |= ib->length_dw |
  3577. (ib->vm ? (ib->vm->ids[ring->idx].id << 24) : 0);
  3578. amdgpu_ring_write(ring, header);
  3579. amdgpu_ring_write(ring,
  3580. #ifdef __BIG_ENDIAN
  3581. (2 << 0) |
  3582. #endif
  3583. (ib->gpu_addr & 0xFFFFFFFC));
  3584. amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF);
  3585. amdgpu_ring_write(ring, control);
  3586. }
  3587. static void gfx_v8_0_ring_emit_fence_gfx(struct amdgpu_ring *ring, u64 addr,
  3588. u64 seq, unsigned flags)
  3589. {
  3590. bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
  3591. bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
  3592. /* EVENT_WRITE_EOP - flush caches, send int */
  3593. amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
  3594. amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN |
  3595. EOP_TC_ACTION_EN |
  3596. EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
  3597. EVENT_INDEX(5)));
  3598. amdgpu_ring_write(ring, addr & 0xfffffffc);
  3599. amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) |
  3600. DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0));
  3601. amdgpu_ring_write(ring, lower_32_bits(seq));
  3602. amdgpu_ring_write(ring, upper_32_bits(seq));
  3603. }
  3604. /**
  3605. * gfx_v8_0_ring_emit_semaphore - emit a semaphore on the CP ring
  3606. *
  3607. * @ring: amdgpu ring buffer object
  3608. * @semaphore: amdgpu semaphore object
  3609. * @emit_wait: Is this a sempahore wait?
  3610. *
  3611. * Emits a semaphore signal/wait packet to the CP ring and prevents the PFP
  3612. * from running ahead of semaphore waits.
  3613. */
  3614. static bool gfx_v8_0_ring_emit_semaphore(struct amdgpu_ring *ring,
  3615. struct amdgpu_semaphore *semaphore,
  3616. bool emit_wait)
  3617. {
  3618. uint64_t addr = semaphore->gpu_addr;
  3619. unsigned sel = emit_wait ? PACKET3_SEM_SEL_WAIT : PACKET3_SEM_SEL_SIGNAL;
  3620. if (ring->adev->asic_type == CHIP_TOPAZ ||
  3621. ring->adev->asic_type == CHIP_TONGA ||
  3622. ring->adev->asic_type == CHIP_FIJI)
  3623. /* we got a hw semaphore bug in VI TONGA, return false to switch back to sw fence wait */
  3624. return false;
  3625. else {
  3626. amdgpu_ring_write(ring, PACKET3(PACKET3_MEM_SEMAPHORE, 2));
  3627. amdgpu_ring_write(ring, lower_32_bits(addr));
  3628. amdgpu_ring_write(ring, upper_32_bits(addr));
  3629. amdgpu_ring_write(ring, sel);
  3630. }
  3631. if (emit_wait && (ring->type == AMDGPU_RING_TYPE_GFX)) {
  3632. /* Prevent the PFP from running ahead of the semaphore wait */
  3633. amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
  3634. amdgpu_ring_write(ring, 0x0);
  3635. }
  3636. return true;
  3637. }
  3638. static void gfx_v8_0_ce_sync_me(struct amdgpu_ring *ring)
  3639. {
  3640. struct amdgpu_device *adev = ring->adev;
  3641. u64 gpu_addr = adev->wb.gpu_addr + adev->gfx.ce_sync_offs * 4;
  3642. /* instruct DE to set a magic number */
  3643. amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
  3644. amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
  3645. WRITE_DATA_DST_SEL(5)));
  3646. amdgpu_ring_write(ring, gpu_addr & 0xfffffffc);
  3647. amdgpu_ring_write(ring, upper_32_bits(gpu_addr) & 0xffffffff);
  3648. amdgpu_ring_write(ring, 1);
  3649. /* let CE wait till condition satisfied */
  3650. amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
  3651. amdgpu_ring_write(ring, (WAIT_REG_MEM_OPERATION(0) | /* wait */
  3652. WAIT_REG_MEM_MEM_SPACE(1) | /* memory */
  3653. WAIT_REG_MEM_FUNCTION(3) | /* == */
  3654. WAIT_REG_MEM_ENGINE(2))); /* ce */
  3655. amdgpu_ring_write(ring, gpu_addr & 0xfffffffc);
  3656. amdgpu_ring_write(ring, upper_32_bits(gpu_addr) & 0xffffffff);
  3657. amdgpu_ring_write(ring, 1);
  3658. amdgpu_ring_write(ring, 0xffffffff);
  3659. amdgpu_ring_write(ring, 4); /* poll interval */
  3660. /* instruct CE to reset wb of ce_sync to zero */
  3661. amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
  3662. amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(2) |
  3663. WRITE_DATA_DST_SEL(5) |
  3664. WR_CONFIRM));
  3665. amdgpu_ring_write(ring, gpu_addr & 0xfffffffc);
  3666. amdgpu_ring_write(ring, upper_32_bits(gpu_addr) & 0xffffffff);
  3667. amdgpu_ring_write(ring, 0);
  3668. }
  3669. static void gfx_v8_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
  3670. unsigned vm_id, uint64_t pd_addr)
  3671. {
  3672. int usepfp = (ring->type == AMDGPU_RING_TYPE_GFX);
  3673. amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
  3674. amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) |
  3675. WRITE_DATA_DST_SEL(0)));
  3676. if (vm_id < 8) {
  3677. amdgpu_ring_write(ring,
  3678. (mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vm_id));
  3679. } else {
  3680. amdgpu_ring_write(ring,
  3681. (mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vm_id - 8));
  3682. }
  3683. amdgpu_ring_write(ring, 0);
  3684. amdgpu_ring_write(ring, pd_addr >> 12);
  3685. /* bits 0-15 are the VM contexts0-15 */
  3686. /* invalidate the cache */
  3687. amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
  3688. amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
  3689. WRITE_DATA_DST_SEL(0)));
  3690. amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);
  3691. amdgpu_ring_write(ring, 0);
  3692. amdgpu_ring_write(ring, 1 << vm_id);
  3693. /* wait for the invalidate to complete */
  3694. amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
  3695. amdgpu_ring_write(ring, (WAIT_REG_MEM_OPERATION(0) | /* wait */
  3696. WAIT_REG_MEM_FUNCTION(0) | /* always */
  3697. WAIT_REG_MEM_ENGINE(0))); /* me */
  3698. amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);
  3699. amdgpu_ring_write(ring, 0);
  3700. amdgpu_ring_write(ring, 0); /* ref */
  3701. amdgpu_ring_write(ring, 0); /* mask */
  3702. amdgpu_ring_write(ring, 0x20); /* poll interval */
  3703. /* compute doesn't have PFP */
  3704. if (usepfp) {
  3705. /* sync PFP to ME, otherwise we might get invalid PFP reads */
  3706. amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
  3707. amdgpu_ring_write(ring, 0x0);
  3708. /* synce CE with ME to prevent CE fetch CEIB before context switch done */
  3709. gfx_v8_0_ce_sync_me(ring);
  3710. }
  3711. }
  3712. static bool gfx_v8_0_ring_is_lockup(struct amdgpu_ring *ring)
  3713. {
  3714. if (gfx_v8_0_is_idle(ring->adev)) {
  3715. amdgpu_ring_lockup_update(ring);
  3716. return false;
  3717. }
  3718. return amdgpu_ring_test_lockup(ring);
  3719. }
  3720. static u32 gfx_v8_0_ring_get_rptr_compute(struct amdgpu_ring *ring)
  3721. {
  3722. return ring->adev->wb.wb[ring->rptr_offs];
  3723. }
  3724. static u32 gfx_v8_0_ring_get_wptr_compute(struct amdgpu_ring *ring)
  3725. {
  3726. return ring->adev->wb.wb[ring->wptr_offs];
  3727. }
  3728. static void gfx_v8_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
  3729. {
  3730. struct amdgpu_device *adev = ring->adev;
  3731. /* XXX check if swapping is necessary on BE */
  3732. adev->wb.wb[ring->wptr_offs] = ring->wptr;
  3733. WDOORBELL32(ring->doorbell_index, ring->wptr);
  3734. }
  3735. static void gfx_v8_0_ring_emit_fence_compute(struct amdgpu_ring *ring,
  3736. u64 addr, u64 seq,
  3737. unsigned flags)
  3738. {
  3739. bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
  3740. bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
  3741. /* RELEASE_MEM - flush caches, send int */
  3742. amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 5));
  3743. amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN |
  3744. EOP_TC_ACTION_EN |
  3745. EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
  3746. EVENT_INDEX(5)));
  3747. amdgpu_ring_write(ring, DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0));
  3748. amdgpu_ring_write(ring, addr & 0xfffffffc);
  3749. amdgpu_ring_write(ring, upper_32_bits(addr));
  3750. amdgpu_ring_write(ring, lower_32_bits(seq));
  3751. amdgpu_ring_write(ring, upper_32_bits(seq));
  3752. }
  3753. static void gfx_v8_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,
  3754. enum amdgpu_interrupt_state state)
  3755. {
  3756. u32 cp_int_cntl;
  3757. switch (state) {
  3758. case AMDGPU_IRQ_STATE_DISABLE:
  3759. cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
  3760. cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
  3761. TIME_STAMP_INT_ENABLE, 0);
  3762. WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
  3763. break;
  3764. case AMDGPU_IRQ_STATE_ENABLE:
  3765. cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
  3766. cp_int_cntl =
  3767. REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
  3768. TIME_STAMP_INT_ENABLE, 1);
  3769. WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
  3770. break;
  3771. default:
  3772. break;
  3773. }
  3774. }
  3775. static void gfx_v8_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev,
  3776. int me, int pipe,
  3777. enum amdgpu_interrupt_state state)
  3778. {
  3779. u32 mec_int_cntl, mec_int_cntl_reg;
  3780. /*
  3781. * amdgpu controls only pipe 0 of MEC1. That's why this function only
  3782. * handles the setting of interrupts for this specific pipe. All other
  3783. * pipes' interrupts are set by amdkfd.
  3784. */
  3785. if (me == 1) {
  3786. switch (pipe) {
  3787. case 0:
  3788. mec_int_cntl_reg = mmCP_ME1_PIPE0_INT_CNTL;
  3789. break;
  3790. default:
  3791. DRM_DEBUG("invalid pipe %d\n", pipe);
  3792. return;
  3793. }
  3794. } else {
  3795. DRM_DEBUG("invalid me %d\n", me);
  3796. return;
  3797. }
  3798. switch (state) {
  3799. case AMDGPU_IRQ_STATE_DISABLE:
  3800. mec_int_cntl = RREG32(mec_int_cntl_reg);
  3801. mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
  3802. TIME_STAMP_INT_ENABLE, 0);
  3803. WREG32(mec_int_cntl_reg, mec_int_cntl);
  3804. break;
  3805. case AMDGPU_IRQ_STATE_ENABLE:
  3806. mec_int_cntl = RREG32(mec_int_cntl_reg);
  3807. mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
  3808. TIME_STAMP_INT_ENABLE, 1);
  3809. WREG32(mec_int_cntl_reg, mec_int_cntl);
  3810. break;
  3811. default:
  3812. break;
  3813. }
  3814. }
  3815. static int gfx_v8_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
  3816. struct amdgpu_irq_src *source,
  3817. unsigned type,
  3818. enum amdgpu_interrupt_state state)
  3819. {
  3820. u32 cp_int_cntl;
  3821. switch (state) {
  3822. case AMDGPU_IRQ_STATE_DISABLE:
  3823. cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
  3824. cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
  3825. PRIV_REG_INT_ENABLE, 0);
  3826. WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
  3827. break;
  3828. case AMDGPU_IRQ_STATE_ENABLE:
  3829. cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
  3830. cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
  3831. PRIV_REG_INT_ENABLE, 0);
  3832. WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
  3833. break;
  3834. default:
  3835. break;
  3836. }
  3837. return 0;
  3838. }
  3839. static int gfx_v8_0_set_priv_inst_fault_state(struct amdgpu_device *adev,
  3840. struct amdgpu_irq_src *source,
  3841. unsigned type,
  3842. enum amdgpu_interrupt_state state)
  3843. {
  3844. u32 cp_int_cntl;
  3845. switch (state) {
  3846. case AMDGPU_IRQ_STATE_DISABLE:
  3847. cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
  3848. cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
  3849. PRIV_INSTR_INT_ENABLE, 0);
  3850. WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
  3851. break;
  3852. case AMDGPU_IRQ_STATE_ENABLE:
  3853. cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
  3854. cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
  3855. PRIV_INSTR_INT_ENABLE, 1);
  3856. WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
  3857. break;
  3858. default:
  3859. break;
  3860. }
  3861. return 0;
  3862. }
  3863. static int gfx_v8_0_set_eop_interrupt_state(struct amdgpu_device *adev,
  3864. struct amdgpu_irq_src *src,
  3865. unsigned type,
  3866. enum amdgpu_interrupt_state state)
  3867. {
  3868. switch (type) {
  3869. case AMDGPU_CP_IRQ_GFX_EOP:
  3870. gfx_v8_0_set_gfx_eop_interrupt_state(adev, state);
  3871. break;
  3872. case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP:
  3873. gfx_v8_0_set_compute_eop_interrupt_state(adev, 1, 0, state);
  3874. break;
  3875. case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP:
  3876. gfx_v8_0_set_compute_eop_interrupt_state(adev, 1, 1, state);
  3877. break;
  3878. case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP:
  3879. gfx_v8_0_set_compute_eop_interrupt_state(adev, 1, 2, state);
  3880. break;
  3881. case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP:
  3882. gfx_v8_0_set_compute_eop_interrupt_state(adev, 1, 3, state);
  3883. break;
  3884. case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP:
  3885. gfx_v8_0_set_compute_eop_interrupt_state(adev, 2, 0, state);
  3886. break;
  3887. case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP:
  3888. gfx_v8_0_set_compute_eop_interrupt_state(adev, 2, 1, state);
  3889. break;
  3890. case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP:
  3891. gfx_v8_0_set_compute_eop_interrupt_state(adev, 2, 2, state);
  3892. break;
  3893. case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP:
  3894. gfx_v8_0_set_compute_eop_interrupt_state(adev, 2, 3, state);
  3895. break;
  3896. default:
  3897. break;
  3898. }
  3899. return 0;
  3900. }
  3901. static int gfx_v8_0_eop_irq(struct amdgpu_device *adev,
  3902. struct amdgpu_irq_src *source,
  3903. struct amdgpu_iv_entry *entry)
  3904. {
  3905. int i;
  3906. u8 me_id, pipe_id, queue_id;
  3907. struct amdgpu_ring *ring;
  3908. DRM_DEBUG("IH: CP EOP\n");
  3909. me_id = (entry->ring_id & 0x0c) >> 2;
  3910. pipe_id = (entry->ring_id & 0x03) >> 0;
  3911. queue_id = (entry->ring_id & 0x70) >> 4;
  3912. switch (me_id) {
  3913. case 0:
  3914. amdgpu_fence_process(&adev->gfx.gfx_ring[0]);
  3915. break;
  3916. case 1:
  3917. case 2:
  3918. for (i = 0; i < adev->gfx.num_compute_rings; i++) {
  3919. ring = &adev->gfx.compute_ring[i];
  3920. /* Per-queue interrupt is supported for MEC starting from VI.
  3921. * The interrupt can only be enabled/disabled per pipe instead of per queue.
  3922. */
  3923. if ((ring->me == me_id) && (ring->pipe == pipe_id) && (ring->queue == queue_id))
  3924. amdgpu_fence_process(ring);
  3925. }
  3926. break;
  3927. }
  3928. return 0;
  3929. }
  3930. static int gfx_v8_0_priv_reg_irq(struct amdgpu_device *adev,
  3931. struct amdgpu_irq_src *source,
  3932. struct amdgpu_iv_entry *entry)
  3933. {
  3934. DRM_ERROR("Illegal register access in command stream\n");
  3935. schedule_work(&adev->reset_work);
  3936. return 0;
  3937. }
  3938. static int gfx_v8_0_priv_inst_irq(struct amdgpu_device *adev,
  3939. struct amdgpu_irq_src *source,
  3940. struct amdgpu_iv_entry *entry)
  3941. {
  3942. DRM_ERROR("Illegal instruction in command stream\n");
  3943. schedule_work(&adev->reset_work);
  3944. return 0;
  3945. }
  3946. const struct amd_ip_funcs gfx_v8_0_ip_funcs = {
  3947. .early_init = gfx_v8_0_early_init,
  3948. .late_init = NULL,
  3949. .sw_init = gfx_v8_0_sw_init,
  3950. .sw_fini = gfx_v8_0_sw_fini,
  3951. .hw_init = gfx_v8_0_hw_init,
  3952. .hw_fini = gfx_v8_0_hw_fini,
  3953. .suspend = gfx_v8_0_suspend,
  3954. .resume = gfx_v8_0_resume,
  3955. .is_idle = gfx_v8_0_is_idle,
  3956. .wait_for_idle = gfx_v8_0_wait_for_idle,
  3957. .soft_reset = gfx_v8_0_soft_reset,
  3958. .print_status = gfx_v8_0_print_status,
  3959. .set_clockgating_state = gfx_v8_0_set_clockgating_state,
  3960. .set_powergating_state = gfx_v8_0_set_powergating_state,
  3961. };
  3962. static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_gfx = {
  3963. .get_rptr = gfx_v8_0_ring_get_rptr_gfx,
  3964. .get_wptr = gfx_v8_0_ring_get_wptr_gfx,
  3965. .set_wptr = gfx_v8_0_ring_set_wptr_gfx,
  3966. .parse_cs = NULL,
  3967. .emit_ib = gfx_v8_0_ring_emit_ib_gfx,
  3968. .emit_fence = gfx_v8_0_ring_emit_fence_gfx,
  3969. .emit_semaphore = gfx_v8_0_ring_emit_semaphore,
  3970. .emit_vm_flush = gfx_v8_0_ring_emit_vm_flush,
  3971. .emit_gds_switch = gfx_v8_0_ring_emit_gds_switch,
  3972. .emit_hdp_flush = gfx_v8_0_ring_emit_hdp_flush,
  3973. .test_ring = gfx_v8_0_ring_test_ring,
  3974. .test_ib = gfx_v8_0_ring_test_ib,
  3975. .is_lockup = gfx_v8_0_ring_is_lockup,
  3976. };
  3977. static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_compute = {
  3978. .get_rptr = gfx_v8_0_ring_get_rptr_compute,
  3979. .get_wptr = gfx_v8_0_ring_get_wptr_compute,
  3980. .set_wptr = gfx_v8_0_ring_set_wptr_compute,
  3981. .parse_cs = NULL,
  3982. .emit_ib = gfx_v8_0_ring_emit_ib_compute,
  3983. .emit_fence = gfx_v8_0_ring_emit_fence_compute,
  3984. .emit_semaphore = gfx_v8_0_ring_emit_semaphore,
  3985. .emit_vm_flush = gfx_v8_0_ring_emit_vm_flush,
  3986. .emit_gds_switch = gfx_v8_0_ring_emit_gds_switch,
  3987. .emit_hdp_flush = gfx_v8_0_ring_emit_hdp_flush,
  3988. .test_ring = gfx_v8_0_ring_test_ring,
  3989. .test_ib = gfx_v8_0_ring_test_ib,
  3990. .is_lockup = gfx_v8_0_ring_is_lockup,
  3991. };
  3992. static void gfx_v8_0_set_ring_funcs(struct amdgpu_device *adev)
  3993. {
  3994. int i;
  3995. for (i = 0; i < adev->gfx.num_gfx_rings; i++)
  3996. adev->gfx.gfx_ring[i].funcs = &gfx_v8_0_ring_funcs_gfx;
  3997. for (i = 0; i < adev->gfx.num_compute_rings; i++)
  3998. adev->gfx.compute_ring[i].funcs = &gfx_v8_0_ring_funcs_compute;
  3999. }
  4000. static const struct amdgpu_irq_src_funcs gfx_v8_0_eop_irq_funcs = {
  4001. .set = gfx_v8_0_set_eop_interrupt_state,
  4002. .process = gfx_v8_0_eop_irq,
  4003. };
  4004. static const struct amdgpu_irq_src_funcs gfx_v8_0_priv_reg_irq_funcs = {
  4005. .set = gfx_v8_0_set_priv_reg_fault_state,
  4006. .process = gfx_v8_0_priv_reg_irq,
  4007. };
  4008. static const struct amdgpu_irq_src_funcs gfx_v8_0_priv_inst_irq_funcs = {
  4009. .set = gfx_v8_0_set_priv_inst_fault_state,
  4010. .process = gfx_v8_0_priv_inst_irq,
  4011. };
  4012. static void gfx_v8_0_set_irq_funcs(struct amdgpu_device *adev)
  4013. {
  4014. adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST;
  4015. adev->gfx.eop_irq.funcs = &gfx_v8_0_eop_irq_funcs;
  4016. adev->gfx.priv_reg_irq.num_types = 1;
  4017. adev->gfx.priv_reg_irq.funcs = &gfx_v8_0_priv_reg_irq_funcs;
  4018. adev->gfx.priv_inst_irq.num_types = 1;
  4019. adev->gfx.priv_inst_irq.funcs = &gfx_v8_0_priv_inst_irq_funcs;
  4020. }
  4021. static void gfx_v8_0_set_gds_init(struct amdgpu_device *adev)
  4022. {
  4023. /* init asci gds info */
  4024. adev->gds.mem.total_size = RREG32(mmGDS_VMID0_SIZE);
  4025. adev->gds.gws.total_size = 64;
  4026. adev->gds.oa.total_size = 16;
  4027. if (adev->gds.mem.total_size == 64 * 1024) {
  4028. adev->gds.mem.gfx_partition_size = 4096;
  4029. adev->gds.mem.cs_partition_size = 4096;
  4030. adev->gds.gws.gfx_partition_size = 4;
  4031. adev->gds.gws.cs_partition_size = 4;
  4032. adev->gds.oa.gfx_partition_size = 4;
  4033. adev->gds.oa.cs_partition_size = 1;
  4034. } else {
  4035. adev->gds.mem.gfx_partition_size = 1024;
  4036. adev->gds.mem.cs_partition_size = 1024;
  4037. adev->gds.gws.gfx_partition_size = 16;
  4038. adev->gds.gws.cs_partition_size = 16;
  4039. adev->gds.oa.gfx_partition_size = 4;
  4040. adev->gds.oa.cs_partition_size = 4;
  4041. }
  4042. }
  4043. static u32 gfx_v8_0_get_cu_active_bitmap(struct amdgpu_device *adev,
  4044. u32 se, u32 sh)
  4045. {
  4046. u32 mask = 0, tmp, tmp1;
  4047. int i;
  4048. gfx_v8_0_select_se_sh(adev, se, sh);
  4049. tmp = RREG32(mmCC_GC_SHADER_ARRAY_CONFIG);
  4050. tmp1 = RREG32(mmGC_USER_SHADER_ARRAY_CONFIG);
  4051. gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
  4052. tmp &= 0xffff0000;
  4053. tmp |= tmp1;
  4054. tmp >>= 16;
  4055. for (i = 0; i < adev->gfx.config.max_cu_per_sh; i ++) {
  4056. mask <<= 1;
  4057. mask |= 1;
  4058. }
  4059. return (~tmp) & mask;
  4060. }
  4061. int gfx_v8_0_get_cu_info(struct amdgpu_device *adev,
  4062. struct amdgpu_cu_info *cu_info)
  4063. {
  4064. int i, j, k, counter, active_cu_number = 0;
  4065. u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0;
  4066. if (!adev || !cu_info)
  4067. return -EINVAL;
  4068. mutex_lock(&adev->grbm_idx_mutex);
  4069. for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
  4070. for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
  4071. mask = 1;
  4072. ao_bitmap = 0;
  4073. counter = 0;
  4074. bitmap = gfx_v8_0_get_cu_active_bitmap(adev, i, j);
  4075. cu_info->bitmap[i][j] = bitmap;
  4076. for (k = 0; k < adev->gfx.config.max_cu_per_sh; k ++) {
  4077. if (bitmap & mask) {
  4078. if (counter < 2)
  4079. ao_bitmap |= mask;
  4080. counter ++;
  4081. }
  4082. mask <<= 1;
  4083. }
  4084. active_cu_number += counter;
  4085. ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8));
  4086. }
  4087. }
  4088. cu_info->number = active_cu_number;
  4089. cu_info->ao_cu_mask = ao_cu_mask;
  4090. mutex_unlock(&adev->grbm_idx_mutex);
  4091. return 0;
  4092. }