oxygen_pcm.c 22 KB

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  1. /*
  2. * C-Media CMI8788 driver - PCM code
  3. *
  4. * Copyright (c) Clemens Ladisch <clemens@ladisch.de>
  5. *
  6. *
  7. * This driver is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License, version 2.
  9. *
  10. * This driver is distributed in the hope that it will be useful,
  11. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. * GNU General Public License for more details.
  14. *
  15. * You should have received a copy of the GNU General Public License
  16. * along with this driver; if not, write to the Free Software
  17. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  18. */
  19. #include <linux/pci.h>
  20. #include <sound/control.h>
  21. #include <sound/core.h>
  22. #include <sound/pcm.h>
  23. #include <sound/pcm_params.h>
  24. #include "oxygen.h"
  25. /* most DMA channels have a 16-bit counter for 32-bit words */
  26. #define BUFFER_BYTES_MAX ((1 << 16) * 4)
  27. /* the multichannel DMA channel has a 24-bit counter */
  28. #define BUFFER_BYTES_MAX_MULTICH ((1 << 24) * 4)
  29. #define FIFO_BYTES 256
  30. #define FIFO_BYTES_MULTICH 1024
  31. #define PERIOD_BYTES_MIN 64
  32. #define DEFAULT_BUFFER_BYTES (BUFFER_BYTES_MAX / 2)
  33. #define DEFAULT_BUFFER_BYTES_MULTICH (1024 * 1024)
  34. static const struct snd_pcm_hardware oxygen_stereo_hardware = {
  35. .info = SNDRV_PCM_INFO_MMAP |
  36. SNDRV_PCM_INFO_MMAP_VALID |
  37. SNDRV_PCM_INFO_INTERLEAVED |
  38. SNDRV_PCM_INFO_PAUSE |
  39. SNDRV_PCM_INFO_SYNC_START |
  40. SNDRV_PCM_INFO_NO_PERIOD_WAKEUP,
  41. .formats = SNDRV_PCM_FMTBIT_S16_LE |
  42. SNDRV_PCM_FMTBIT_S32_LE,
  43. .rates = SNDRV_PCM_RATE_32000 |
  44. SNDRV_PCM_RATE_44100 |
  45. SNDRV_PCM_RATE_48000 |
  46. SNDRV_PCM_RATE_64000 |
  47. SNDRV_PCM_RATE_88200 |
  48. SNDRV_PCM_RATE_96000 |
  49. SNDRV_PCM_RATE_176400 |
  50. SNDRV_PCM_RATE_192000,
  51. .rate_min = 32000,
  52. .rate_max = 192000,
  53. .channels_min = 2,
  54. .channels_max = 2,
  55. .buffer_bytes_max = BUFFER_BYTES_MAX,
  56. .period_bytes_min = PERIOD_BYTES_MIN,
  57. .period_bytes_max = BUFFER_BYTES_MAX,
  58. .periods_min = 1,
  59. .periods_max = BUFFER_BYTES_MAX / PERIOD_BYTES_MIN,
  60. .fifo_size = FIFO_BYTES,
  61. };
  62. static const struct snd_pcm_hardware oxygen_multichannel_hardware = {
  63. .info = SNDRV_PCM_INFO_MMAP |
  64. SNDRV_PCM_INFO_MMAP_VALID |
  65. SNDRV_PCM_INFO_INTERLEAVED |
  66. SNDRV_PCM_INFO_PAUSE |
  67. SNDRV_PCM_INFO_SYNC_START |
  68. SNDRV_PCM_INFO_NO_PERIOD_WAKEUP,
  69. .formats = SNDRV_PCM_FMTBIT_S16_LE |
  70. SNDRV_PCM_FMTBIT_S32_LE,
  71. .rates = SNDRV_PCM_RATE_32000 |
  72. SNDRV_PCM_RATE_44100 |
  73. SNDRV_PCM_RATE_48000 |
  74. SNDRV_PCM_RATE_64000 |
  75. SNDRV_PCM_RATE_88200 |
  76. SNDRV_PCM_RATE_96000 |
  77. SNDRV_PCM_RATE_176400 |
  78. SNDRV_PCM_RATE_192000,
  79. .rate_min = 32000,
  80. .rate_max = 192000,
  81. .channels_min = 2,
  82. .channels_max = 8,
  83. .buffer_bytes_max = BUFFER_BYTES_MAX_MULTICH,
  84. .period_bytes_min = PERIOD_BYTES_MIN,
  85. .period_bytes_max = BUFFER_BYTES_MAX_MULTICH,
  86. .periods_min = 1,
  87. .periods_max = BUFFER_BYTES_MAX_MULTICH / PERIOD_BYTES_MIN,
  88. .fifo_size = FIFO_BYTES_MULTICH,
  89. };
  90. static const struct snd_pcm_hardware oxygen_ac97_hardware = {
  91. .info = SNDRV_PCM_INFO_MMAP |
  92. SNDRV_PCM_INFO_MMAP_VALID |
  93. SNDRV_PCM_INFO_INTERLEAVED |
  94. SNDRV_PCM_INFO_PAUSE |
  95. SNDRV_PCM_INFO_SYNC_START |
  96. SNDRV_PCM_INFO_NO_PERIOD_WAKEUP,
  97. .formats = SNDRV_PCM_FMTBIT_S16_LE,
  98. .rates = SNDRV_PCM_RATE_48000,
  99. .rate_min = 48000,
  100. .rate_max = 48000,
  101. .channels_min = 2,
  102. .channels_max = 2,
  103. .buffer_bytes_max = BUFFER_BYTES_MAX,
  104. .period_bytes_min = PERIOD_BYTES_MIN,
  105. .period_bytes_max = BUFFER_BYTES_MAX,
  106. .periods_min = 1,
  107. .periods_max = BUFFER_BYTES_MAX / PERIOD_BYTES_MIN,
  108. .fifo_size = FIFO_BYTES,
  109. };
  110. static const struct snd_pcm_hardware *const oxygen_hardware[PCM_COUNT] = {
  111. [PCM_A] = &oxygen_stereo_hardware,
  112. [PCM_B] = &oxygen_stereo_hardware,
  113. [PCM_C] = &oxygen_stereo_hardware,
  114. [PCM_SPDIF] = &oxygen_stereo_hardware,
  115. [PCM_MULTICH] = &oxygen_multichannel_hardware,
  116. [PCM_AC97] = &oxygen_ac97_hardware,
  117. };
  118. static inline unsigned int
  119. oxygen_substream_channel(struct snd_pcm_substream *substream)
  120. {
  121. return (unsigned int)(uintptr_t)substream->runtime->private_data;
  122. }
  123. static int oxygen_open(struct snd_pcm_substream *substream,
  124. unsigned int channel)
  125. {
  126. struct oxygen *chip = snd_pcm_substream_chip(substream);
  127. struct snd_pcm_runtime *runtime = substream->runtime;
  128. int err;
  129. runtime->private_data = (void *)(uintptr_t)channel;
  130. if (channel == PCM_B && chip->has_ac97_1 &&
  131. (chip->model.device_config & CAPTURE_2_FROM_AC97_1))
  132. runtime->hw = oxygen_ac97_hardware;
  133. else
  134. runtime->hw = *oxygen_hardware[channel];
  135. switch (channel) {
  136. case PCM_C:
  137. runtime->hw.rates &= ~(SNDRV_PCM_RATE_32000 |
  138. SNDRV_PCM_RATE_64000);
  139. runtime->hw.rate_min = 44100;
  140. /* fall through */
  141. case PCM_A:
  142. case PCM_B:
  143. runtime->hw.fifo_size = 0;
  144. break;
  145. case PCM_MULTICH:
  146. runtime->hw.channels_max = chip->model.dac_channels_pcm;
  147. break;
  148. }
  149. if (chip->model.pcm_hardware_filter)
  150. chip->model.pcm_hardware_filter(channel, &runtime->hw);
  151. err = snd_pcm_hw_constraint_step(runtime, 0,
  152. SNDRV_PCM_HW_PARAM_PERIOD_BYTES, 32);
  153. if (err < 0)
  154. return err;
  155. err = snd_pcm_hw_constraint_step(runtime, 0,
  156. SNDRV_PCM_HW_PARAM_BUFFER_BYTES, 32);
  157. if (err < 0)
  158. return err;
  159. if (runtime->hw.formats & SNDRV_PCM_FMTBIT_S32_LE) {
  160. err = snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
  161. if (err < 0)
  162. return err;
  163. }
  164. if (runtime->hw.channels_max > 2) {
  165. err = snd_pcm_hw_constraint_step(runtime, 0,
  166. SNDRV_PCM_HW_PARAM_CHANNELS,
  167. 2);
  168. if (err < 0)
  169. return err;
  170. }
  171. snd_pcm_set_sync(substream);
  172. chip->streams[channel] = substream;
  173. mutex_lock(&chip->mutex);
  174. chip->pcm_active |= 1 << channel;
  175. if (channel == PCM_SPDIF) {
  176. chip->spdif_pcm_bits = chip->spdif_bits;
  177. chip->controls[CONTROL_SPDIF_PCM]->vd[0].access &=
  178. ~SNDRV_CTL_ELEM_ACCESS_INACTIVE;
  179. snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE |
  180. SNDRV_CTL_EVENT_MASK_INFO,
  181. &chip->controls[CONTROL_SPDIF_PCM]->id);
  182. }
  183. mutex_unlock(&chip->mutex);
  184. return 0;
  185. }
  186. static int oxygen_rec_a_open(struct snd_pcm_substream *substream)
  187. {
  188. return oxygen_open(substream, PCM_A);
  189. }
  190. static int oxygen_rec_b_open(struct snd_pcm_substream *substream)
  191. {
  192. return oxygen_open(substream, PCM_B);
  193. }
  194. static int oxygen_rec_c_open(struct snd_pcm_substream *substream)
  195. {
  196. return oxygen_open(substream, PCM_C);
  197. }
  198. static int oxygen_spdif_open(struct snd_pcm_substream *substream)
  199. {
  200. return oxygen_open(substream, PCM_SPDIF);
  201. }
  202. static int oxygen_multich_open(struct snd_pcm_substream *substream)
  203. {
  204. return oxygen_open(substream, PCM_MULTICH);
  205. }
  206. static int oxygen_ac97_open(struct snd_pcm_substream *substream)
  207. {
  208. return oxygen_open(substream, PCM_AC97);
  209. }
  210. static int oxygen_close(struct snd_pcm_substream *substream)
  211. {
  212. struct oxygen *chip = snd_pcm_substream_chip(substream);
  213. unsigned int channel = oxygen_substream_channel(substream);
  214. mutex_lock(&chip->mutex);
  215. chip->pcm_active &= ~(1 << channel);
  216. if (channel == PCM_SPDIF) {
  217. chip->controls[CONTROL_SPDIF_PCM]->vd[0].access |=
  218. SNDRV_CTL_ELEM_ACCESS_INACTIVE;
  219. snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE |
  220. SNDRV_CTL_EVENT_MASK_INFO,
  221. &chip->controls[CONTROL_SPDIF_PCM]->id);
  222. }
  223. if (channel == PCM_SPDIF || channel == PCM_MULTICH)
  224. oxygen_update_spdif_source(chip);
  225. mutex_unlock(&chip->mutex);
  226. chip->streams[channel] = NULL;
  227. return 0;
  228. }
  229. static unsigned int oxygen_format(struct snd_pcm_hw_params *hw_params)
  230. {
  231. if (params_format(hw_params) == SNDRV_PCM_FORMAT_S32_LE)
  232. return OXYGEN_FORMAT_24;
  233. else
  234. return OXYGEN_FORMAT_16;
  235. }
  236. static unsigned int oxygen_rate(struct snd_pcm_hw_params *hw_params)
  237. {
  238. switch (params_rate(hw_params)) {
  239. case 32000:
  240. return OXYGEN_RATE_32000;
  241. case 44100:
  242. return OXYGEN_RATE_44100;
  243. default: /* 48000 */
  244. return OXYGEN_RATE_48000;
  245. case 64000:
  246. return OXYGEN_RATE_64000;
  247. case 88200:
  248. return OXYGEN_RATE_88200;
  249. case 96000:
  250. return OXYGEN_RATE_96000;
  251. case 176400:
  252. return OXYGEN_RATE_176400;
  253. case 192000:
  254. return OXYGEN_RATE_192000;
  255. }
  256. }
  257. static unsigned int oxygen_i2s_bits(struct snd_pcm_hw_params *hw_params)
  258. {
  259. if (params_format(hw_params) == SNDRV_PCM_FORMAT_S32_LE)
  260. return OXYGEN_I2S_BITS_24;
  261. else
  262. return OXYGEN_I2S_BITS_16;
  263. }
  264. static unsigned int oxygen_play_channels(struct snd_pcm_hw_params *hw_params)
  265. {
  266. switch (params_channels(hw_params)) {
  267. default: /* 2 */
  268. return OXYGEN_PLAY_CHANNELS_2;
  269. case 4:
  270. return OXYGEN_PLAY_CHANNELS_4;
  271. case 6:
  272. return OXYGEN_PLAY_CHANNELS_6;
  273. case 8:
  274. return OXYGEN_PLAY_CHANNELS_8;
  275. }
  276. }
  277. static const unsigned int channel_base_registers[PCM_COUNT] = {
  278. [PCM_A] = OXYGEN_DMA_A_ADDRESS,
  279. [PCM_B] = OXYGEN_DMA_B_ADDRESS,
  280. [PCM_C] = OXYGEN_DMA_C_ADDRESS,
  281. [PCM_SPDIF] = OXYGEN_DMA_SPDIF_ADDRESS,
  282. [PCM_MULTICH] = OXYGEN_DMA_MULTICH_ADDRESS,
  283. [PCM_AC97] = OXYGEN_DMA_AC97_ADDRESS,
  284. };
  285. static int oxygen_hw_params(struct snd_pcm_substream *substream,
  286. struct snd_pcm_hw_params *hw_params)
  287. {
  288. struct oxygen *chip = snd_pcm_substream_chip(substream);
  289. unsigned int channel = oxygen_substream_channel(substream);
  290. int err;
  291. err = snd_pcm_lib_malloc_pages(substream,
  292. params_buffer_bytes(hw_params));
  293. if (err < 0)
  294. return err;
  295. oxygen_write32(chip, channel_base_registers[channel],
  296. (u32)substream->runtime->dma_addr);
  297. if (channel == PCM_MULTICH) {
  298. oxygen_write32(chip, OXYGEN_DMA_MULTICH_COUNT,
  299. params_buffer_bytes(hw_params) / 4 - 1);
  300. oxygen_write32(chip, OXYGEN_DMA_MULTICH_TCOUNT,
  301. params_period_bytes(hw_params) / 4 - 1);
  302. } else {
  303. oxygen_write16(chip, channel_base_registers[channel] + 4,
  304. params_buffer_bytes(hw_params) / 4 - 1);
  305. oxygen_write16(chip, channel_base_registers[channel] + 6,
  306. params_period_bytes(hw_params) / 4 - 1);
  307. }
  308. return 0;
  309. }
  310. static u16 get_mclk(struct oxygen *chip, unsigned int channel,
  311. struct snd_pcm_hw_params *params)
  312. {
  313. unsigned int mclks, shift;
  314. if (channel == PCM_MULTICH)
  315. mclks = chip->model.dac_mclks;
  316. else
  317. mclks = chip->model.adc_mclks;
  318. if (params_rate(params) <= 48000)
  319. shift = 0;
  320. else if (params_rate(params) <= 96000)
  321. shift = 2;
  322. else
  323. shift = 4;
  324. return OXYGEN_I2S_MCLK(mclks >> shift);
  325. }
  326. static int oxygen_rec_a_hw_params(struct snd_pcm_substream *substream,
  327. struct snd_pcm_hw_params *hw_params)
  328. {
  329. struct oxygen *chip = snd_pcm_substream_chip(substream);
  330. int err;
  331. err = oxygen_hw_params(substream, hw_params);
  332. if (err < 0)
  333. return err;
  334. spin_lock_irq(&chip->reg_lock);
  335. oxygen_write8_masked(chip, OXYGEN_REC_FORMAT,
  336. oxygen_format(hw_params) << OXYGEN_REC_FORMAT_A_SHIFT,
  337. OXYGEN_REC_FORMAT_A_MASK);
  338. oxygen_write16_masked(chip, OXYGEN_I2S_A_FORMAT,
  339. oxygen_rate(hw_params) |
  340. chip->model.adc_i2s_format |
  341. get_mclk(chip, PCM_A, hw_params) |
  342. oxygen_i2s_bits(hw_params),
  343. OXYGEN_I2S_RATE_MASK |
  344. OXYGEN_I2S_FORMAT_MASK |
  345. OXYGEN_I2S_MCLK_MASK |
  346. OXYGEN_I2S_BITS_MASK);
  347. spin_unlock_irq(&chip->reg_lock);
  348. mutex_lock(&chip->mutex);
  349. chip->model.set_adc_params(chip, hw_params);
  350. mutex_unlock(&chip->mutex);
  351. return 0;
  352. }
  353. static int oxygen_rec_b_hw_params(struct snd_pcm_substream *substream,
  354. struct snd_pcm_hw_params *hw_params)
  355. {
  356. struct oxygen *chip = snd_pcm_substream_chip(substream);
  357. int is_ac97;
  358. int err;
  359. err = oxygen_hw_params(substream, hw_params);
  360. if (err < 0)
  361. return err;
  362. is_ac97 = chip->has_ac97_1 &&
  363. (chip->model.device_config & CAPTURE_2_FROM_AC97_1);
  364. spin_lock_irq(&chip->reg_lock);
  365. oxygen_write8_masked(chip, OXYGEN_REC_FORMAT,
  366. oxygen_format(hw_params) << OXYGEN_REC_FORMAT_B_SHIFT,
  367. OXYGEN_REC_FORMAT_B_MASK);
  368. if (!is_ac97)
  369. oxygen_write16_masked(chip, OXYGEN_I2S_B_FORMAT,
  370. oxygen_rate(hw_params) |
  371. chip->model.adc_i2s_format |
  372. get_mclk(chip, PCM_B, hw_params) |
  373. oxygen_i2s_bits(hw_params),
  374. OXYGEN_I2S_RATE_MASK |
  375. OXYGEN_I2S_FORMAT_MASK |
  376. OXYGEN_I2S_MCLK_MASK |
  377. OXYGEN_I2S_BITS_MASK);
  378. spin_unlock_irq(&chip->reg_lock);
  379. if (!is_ac97) {
  380. mutex_lock(&chip->mutex);
  381. chip->model.set_adc_params(chip, hw_params);
  382. mutex_unlock(&chip->mutex);
  383. }
  384. return 0;
  385. }
  386. static int oxygen_rec_c_hw_params(struct snd_pcm_substream *substream,
  387. struct snd_pcm_hw_params *hw_params)
  388. {
  389. struct oxygen *chip = snd_pcm_substream_chip(substream);
  390. int err;
  391. err = oxygen_hw_params(substream, hw_params);
  392. if (err < 0)
  393. return err;
  394. spin_lock_irq(&chip->reg_lock);
  395. oxygen_write8_masked(chip, OXYGEN_REC_FORMAT,
  396. oxygen_format(hw_params) << OXYGEN_REC_FORMAT_C_SHIFT,
  397. OXYGEN_REC_FORMAT_C_MASK);
  398. spin_unlock_irq(&chip->reg_lock);
  399. return 0;
  400. }
  401. static int oxygen_spdif_hw_params(struct snd_pcm_substream *substream,
  402. struct snd_pcm_hw_params *hw_params)
  403. {
  404. struct oxygen *chip = snd_pcm_substream_chip(substream);
  405. int err;
  406. err = oxygen_hw_params(substream, hw_params);
  407. if (err < 0)
  408. return err;
  409. mutex_lock(&chip->mutex);
  410. spin_lock_irq(&chip->reg_lock);
  411. oxygen_clear_bits32(chip, OXYGEN_SPDIF_CONTROL,
  412. OXYGEN_SPDIF_OUT_ENABLE);
  413. oxygen_write8_masked(chip, OXYGEN_PLAY_FORMAT,
  414. oxygen_format(hw_params) << OXYGEN_SPDIF_FORMAT_SHIFT,
  415. OXYGEN_SPDIF_FORMAT_MASK);
  416. oxygen_write32_masked(chip, OXYGEN_SPDIF_CONTROL,
  417. oxygen_rate(hw_params) << OXYGEN_SPDIF_OUT_RATE_SHIFT,
  418. OXYGEN_SPDIF_OUT_RATE_MASK);
  419. oxygen_update_spdif_source(chip);
  420. spin_unlock_irq(&chip->reg_lock);
  421. mutex_unlock(&chip->mutex);
  422. return 0;
  423. }
  424. static int oxygen_multich_hw_params(struct snd_pcm_substream *substream,
  425. struct snd_pcm_hw_params *hw_params)
  426. {
  427. struct oxygen *chip = snd_pcm_substream_chip(substream);
  428. int err;
  429. err = oxygen_hw_params(substream, hw_params);
  430. if (err < 0)
  431. return err;
  432. mutex_lock(&chip->mutex);
  433. spin_lock_irq(&chip->reg_lock);
  434. oxygen_write8_masked(chip, OXYGEN_PLAY_CHANNELS,
  435. oxygen_play_channels(hw_params),
  436. OXYGEN_PLAY_CHANNELS_MASK);
  437. oxygen_write8_masked(chip, OXYGEN_PLAY_FORMAT,
  438. oxygen_format(hw_params) << OXYGEN_MULTICH_FORMAT_SHIFT,
  439. OXYGEN_MULTICH_FORMAT_MASK);
  440. oxygen_write16_masked(chip, OXYGEN_I2S_MULTICH_FORMAT,
  441. oxygen_rate(hw_params) |
  442. chip->model.dac_i2s_format |
  443. get_mclk(chip, PCM_MULTICH, hw_params) |
  444. oxygen_i2s_bits(hw_params),
  445. OXYGEN_I2S_RATE_MASK |
  446. OXYGEN_I2S_FORMAT_MASK |
  447. OXYGEN_I2S_MCLK_MASK |
  448. OXYGEN_I2S_BITS_MASK);
  449. oxygen_update_spdif_source(chip);
  450. spin_unlock_irq(&chip->reg_lock);
  451. chip->model.set_dac_params(chip, hw_params);
  452. oxygen_update_dac_routing(chip);
  453. mutex_unlock(&chip->mutex);
  454. return 0;
  455. }
  456. static int oxygen_hw_free(struct snd_pcm_substream *substream)
  457. {
  458. struct oxygen *chip = snd_pcm_substream_chip(substream);
  459. unsigned int channel = oxygen_substream_channel(substream);
  460. unsigned int channel_mask = 1 << channel;
  461. spin_lock_irq(&chip->reg_lock);
  462. chip->interrupt_mask &= ~channel_mask;
  463. oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, chip->interrupt_mask);
  464. oxygen_set_bits8(chip, OXYGEN_DMA_FLUSH, channel_mask);
  465. oxygen_clear_bits8(chip, OXYGEN_DMA_FLUSH, channel_mask);
  466. spin_unlock_irq(&chip->reg_lock);
  467. return snd_pcm_lib_free_pages(substream);
  468. }
  469. static int oxygen_spdif_hw_free(struct snd_pcm_substream *substream)
  470. {
  471. struct oxygen *chip = snd_pcm_substream_chip(substream);
  472. spin_lock_irq(&chip->reg_lock);
  473. oxygen_clear_bits32(chip, OXYGEN_SPDIF_CONTROL,
  474. OXYGEN_SPDIF_OUT_ENABLE);
  475. spin_unlock_irq(&chip->reg_lock);
  476. return oxygen_hw_free(substream);
  477. }
  478. static int oxygen_prepare(struct snd_pcm_substream *substream)
  479. {
  480. struct oxygen *chip = snd_pcm_substream_chip(substream);
  481. unsigned int channel = oxygen_substream_channel(substream);
  482. unsigned int channel_mask = 1 << channel;
  483. spin_lock_irq(&chip->reg_lock);
  484. oxygen_set_bits8(chip, OXYGEN_DMA_FLUSH, channel_mask);
  485. oxygen_clear_bits8(chip, OXYGEN_DMA_FLUSH, channel_mask);
  486. if (substream->runtime->no_period_wakeup)
  487. chip->interrupt_mask &= ~channel_mask;
  488. else
  489. chip->interrupt_mask |= channel_mask;
  490. oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, chip->interrupt_mask);
  491. spin_unlock_irq(&chip->reg_lock);
  492. return 0;
  493. }
  494. static int oxygen_trigger(struct snd_pcm_substream *substream, int cmd)
  495. {
  496. struct oxygen *chip = snd_pcm_substream_chip(substream);
  497. struct snd_pcm_substream *s;
  498. unsigned int mask = 0;
  499. int pausing;
  500. switch (cmd) {
  501. case SNDRV_PCM_TRIGGER_STOP:
  502. case SNDRV_PCM_TRIGGER_START:
  503. case SNDRV_PCM_TRIGGER_SUSPEND:
  504. pausing = 0;
  505. break;
  506. case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
  507. case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
  508. pausing = 1;
  509. break;
  510. default:
  511. return -EINVAL;
  512. }
  513. snd_pcm_group_for_each_entry(s, substream) {
  514. if (snd_pcm_substream_chip(s) == chip) {
  515. mask |= 1 << oxygen_substream_channel(s);
  516. snd_pcm_trigger_done(s, substream);
  517. }
  518. }
  519. spin_lock(&chip->reg_lock);
  520. if (!pausing) {
  521. if (cmd == SNDRV_PCM_TRIGGER_START)
  522. chip->pcm_running |= mask;
  523. else
  524. chip->pcm_running &= ~mask;
  525. oxygen_write8(chip, OXYGEN_DMA_STATUS, chip->pcm_running);
  526. } else {
  527. if (cmd == SNDRV_PCM_TRIGGER_PAUSE_PUSH)
  528. oxygen_set_bits8(chip, OXYGEN_DMA_PAUSE, mask);
  529. else
  530. oxygen_clear_bits8(chip, OXYGEN_DMA_PAUSE, mask);
  531. }
  532. spin_unlock(&chip->reg_lock);
  533. return 0;
  534. }
  535. static snd_pcm_uframes_t oxygen_pointer(struct snd_pcm_substream *substream)
  536. {
  537. struct oxygen *chip = snd_pcm_substream_chip(substream);
  538. struct snd_pcm_runtime *runtime = substream->runtime;
  539. unsigned int channel = oxygen_substream_channel(substream);
  540. u32 curr_addr;
  541. /* no spinlock, this read should be atomic */
  542. curr_addr = oxygen_read32(chip, channel_base_registers[channel]);
  543. return bytes_to_frames(runtime, curr_addr - (u32)runtime->dma_addr);
  544. }
  545. static struct snd_pcm_ops oxygen_rec_a_ops = {
  546. .open = oxygen_rec_a_open,
  547. .close = oxygen_close,
  548. .ioctl = snd_pcm_lib_ioctl,
  549. .hw_params = oxygen_rec_a_hw_params,
  550. .hw_free = oxygen_hw_free,
  551. .prepare = oxygen_prepare,
  552. .trigger = oxygen_trigger,
  553. .pointer = oxygen_pointer,
  554. };
  555. static struct snd_pcm_ops oxygen_rec_b_ops = {
  556. .open = oxygen_rec_b_open,
  557. .close = oxygen_close,
  558. .ioctl = snd_pcm_lib_ioctl,
  559. .hw_params = oxygen_rec_b_hw_params,
  560. .hw_free = oxygen_hw_free,
  561. .prepare = oxygen_prepare,
  562. .trigger = oxygen_trigger,
  563. .pointer = oxygen_pointer,
  564. };
  565. static struct snd_pcm_ops oxygen_rec_c_ops = {
  566. .open = oxygen_rec_c_open,
  567. .close = oxygen_close,
  568. .ioctl = snd_pcm_lib_ioctl,
  569. .hw_params = oxygen_rec_c_hw_params,
  570. .hw_free = oxygen_hw_free,
  571. .prepare = oxygen_prepare,
  572. .trigger = oxygen_trigger,
  573. .pointer = oxygen_pointer,
  574. };
  575. static struct snd_pcm_ops oxygen_spdif_ops = {
  576. .open = oxygen_spdif_open,
  577. .close = oxygen_close,
  578. .ioctl = snd_pcm_lib_ioctl,
  579. .hw_params = oxygen_spdif_hw_params,
  580. .hw_free = oxygen_spdif_hw_free,
  581. .prepare = oxygen_prepare,
  582. .trigger = oxygen_trigger,
  583. .pointer = oxygen_pointer,
  584. };
  585. static struct snd_pcm_ops oxygen_multich_ops = {
  586. .open = oxygen_multich_open,
  587. .close = oxygen_close,
  588. .ioctl = snd_pcm_lib_ioctl,
  589. .hw_params = oxygen_multich_hw_params,
  590. .hw_free = oxygen_hw_free,
  591. .prepare = oxygen_prepare,
  592. .trigger = oxygen_trigger,
  593. .pointer = oxygen_pointer,
  594. };
  595. static struct snd_pcm_ops oxygen_ac97_ops = {
  596. .open = oxygen_ac97_open,
  597. .close = oxygen_close,
  598. .ioctl = snd_pcm_lib_ioctl,
  599. .hw_params = oxygen_hw_params,
  600. .hw_free = oxygen_hw_free,
  601. .prepare = oxygen_prepare,
  602. .trigger = oxygen_trigger,
  603. .pointer = oxygen_pointer,
  604. };
  605. static void oxygen_pcm_free(struct snd_pcm *pcm)
  606. {
  607. snd_pcm_lib_preallocate_free_for_all(pcm);
  608. }
  609. int oxygen_pcm_init(struct oxygen *chip)
  610. {
  611. struct snd_pcm *pcm;
  612. int outs, ins;
  613. int err;
  614. outs = !!(chip->model.device_config & PLAYBACK_0_TO_I2S);
  615. ins = !!(chip->model.device_config & (CAPTURE_0_FROM_I2S_1 |
  616. CAPTURE_0_FROM_I2S_2));
  617. if (outs | ins) {
  618. err = snd_pcm_new(chip->card, "Multichannel",
  619. 0, outs, ins, &pcm);
  620. if (err < 0)
  621. return err;
  622. if (outs)
  623. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK,
  624. &oxygen_multich_ops);
  625. if (chip->model.device_config & CAPTURE_0_FROM_I2S_1)
  626. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE,
  627. &oxygen_rec_a_ops);
  628. else if (chip->model.device_config & CAPTURE_0_FROM_I2S_2)
  629. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE,
  630. &oxygen_rec_b_ops);
  631. pcm->private_data = chip;
  632. pcm->private_free = oxygen_pcm_free;
  633. strcpy(pcm->name, "Multichannel");
  634. if (outs)
  635. snd_pcm_lib_preallocate_pages(pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream,
  636. SNDRV_DMA_TYPE_DEV,
  637. snd_dma_pci_data(chip->pci),
  638. DEFAULT_BUFFER_BYTES_MULTICH,
  639. BUFFER_BYTES_MAX_MULTICH);
  640. if (ins)
  641. snd_pcm_lib_preallocate_pages(pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream,
  642. SNDRV_DMA_TYPE_DEV,
  643. snd_dma_pci_data(chip->pci),
  644. DEFAULT_BUFFER_BYTES,
  645. BUFFER_BYTES_MAX);
  646. }
  647. outs = !!(chip->model.device_config & PLAYBACK_1_TO_SPDIF);
  648. ins = !!(chip->model.device_config & CAPTURE_1_FROM_SPDIF);
  649. if (outs | ins) {
  650. err = snd_pcm_new(chip->card, "Digital", 1, outs, ins, &pcm);
  651. if (err < 0)
  652. return err;
  653. if (outs)
  654. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK,
  655. &oxygen_spdif_ops);
  656. if (ins)
  657. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE,
  658. &oxygen_rec_c_ops);
  659. pcm->private_data = chip;
  660. pcm->private_free = oxygen_pcm_free;
  661. strcpy(pcm->name, "Digital");
  662. snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
  663. snd_dma_pci_data(chip->pci),
  664. DEFAULT_BUFFER_BYTES,
  665. BUFFER_BYTES_MAX);
  666. }
  667. if (chip->has_ac97_1) {
  668. outs = !!(chip->model.device_config & PLAYBACK_2_TO_AC97_1);
  669. ins = !!(chip->model.device_config & CAPTURE_2_FROM_AC97_1);
  670. } else {
  671. outs = 0;
  672. ins = !!(chip->model.device_config & CAPTURE_2_FROM_I2S_2);
  673. }
  674. if (outs | ins) {
  675. err = snd_pcm_new(chip->card, outs ? "AC97" : "Analog2",
  676. 2, outs, ins, &pcm);
  677. if (err < 0)
  678. return err;
  679. if (outs) {
  680. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK,
  681. &oxygen_ac97_ops);
  682. oxygen_write8_masked(chip, OXYGEN_REC_ROUTING,
  683. OXYGEN_REC_B_ROUTE_AC97_1,
  684. OXYGEN_REC_B_ROUTE_MASK);
  685. }
  686. if (ins)
  687. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE,
  688. &oxygen_rec_b_ops);
  689. pcm->private_data = chip;
  690. pcm->private_free = oxygen_pcm_free;
  691. strcpy(pcm->name, outs ? "Front Panel" : "Analog 2");
  692. snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
  693. snd_dma_pci_data(chip->pci),
  694. DEFAULT_BUFFER_BYTES,
  695. BUFFER_BYTES_MAX);
  696. }
  697. return 0;
  698. }