lpc32xx_udc.c 85 KB

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  1. /*
  2. * USB Gadget driver for LPC32xx
  3. *
  4. * Authors:
  5. * Kevin Wells <kevin.wells@nxp.com>
  6. * Mike James
  7. * Roland Stigge <stigge@antcom.de>
  8. *
  9. * Copyright (C) 2006 Philips Semiconductors
  10. * Copyright (C) 2009 NXP Semiconductors
  11. * Copyright (C) 2012 Roland Stigge
  12. *
  13. * Note: This driver is based on original work done by Mike James for
  14. * the LPC3180.
  15. *
  16. * This program is free software; you can redistribute it and/or modify
  17. * it under the terms of the GNU General Public License as published by
  18. * the Free Software Foundation; either version 2 of the License, or
  19. * (at your option) any later version.
  20. *
  21. * This program is distributed in the hope that it will be useful,
  22. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  23. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  24. * GNU General Public License for more details.
  25. *
  26. * You should have received a copy of the GNU General Public License
  27. * along with this program; if not, write to the Free Software
  28. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  29. */
  30. #include <linux/kernel.h>
  31. #include <linux/module.h>
  32. #include <linux/platform_device.h>
  33. #include <linux/delay.h>
  34. #include <linux/ioport.h>
  35. #include <linux/slab.h>
  36. #include <linux/errno.h>
  37. #include <linux/init.h>
  38. #include <linux/list.h>
  39. #include <linux/interrupt.h>
  40. #include <linux/proc_fs.h>
  41. #include <linux/clk.h>
  42. #include <linux/usb/ch9.h>
  43. #include <linux/usb/gadget.h>
  44. #include <linux/i2c.h>
  45. #include <linux/kthread.h>
  46. #include <linux/freezer.h>
  47. #include <linux/dma-mapping.h>
  48. #include <linux/dmapool.h>
  49. #include <linux/workqueue.h>
  50. #include <linux/of.h>
  51. #include <linux/usb/isp1301.h>
  52. #include <asm/byteorder.h>
  53. #include <mach/hardware.h>
  54. #include <linux/io.h>
  55. #include <asm/irq.h>
  56. #include <mach/platform.h>
  57. #include <mach/irqs.h>
  58. #include <mach/board.h>
  59. #ifdef CONFIG_USB_GADGET_DEBUG_FILES
  60. #include <linux/debugfs.h>
  61. #include <linux/seq_file.h>
  62. #endif
  63. /*
  64. * USB device configuration structure
  65. */
  66. typedef void (*usc_chg_event)(int);
  67. struct lpc32xx_usbd_cfg {
  68. int vbus_drv_pol; /* 0=active low drive for VBUS via ISP1301 */
  69. usc_chg_event conn_chgb; /* Connection change event (optional) */
  70. usc_chg_event susp_chgb; /* Suspend/resume event (optional) */
  71. usc_chg_event rmwk_chgb; /* Enable/disable remote wakeup */
  72. };
  73. /*
  74. * controller driver data structures
  75. */
  76. /* 16 endpoints (not to be confused with 32 hardware endpoints) */
  77. #define NUM_ENDPOINTS 16
  78. /*
  79. * IRQ indices make reading the code a little easier
  80. */
  81. #define IRQ_USB_LP 0
  82. #define IRQ_USB_HP 1
  83. #define IRQ_USB_DEVDMA 2
  84. #define IRQ_USB_ATX 3
  85. #define EP_OUT 0 /* RX (from host) */
  86. #define EP_IN 1 /* TX (to host) */
  87. /* Returns the interrupt mask for the selected hardware endpoint */
  88. #define EP_MASK_SEL(ep, dir) (1 << (((ep) * 2) + dir))
  89. #define EP_INT_TYPE 0
  90. #define EP_ISO_TYPE 1
  91. #define EP_BLK_TYPE 2
  92. #define EP_CTL_TYPE 3
  93. /* EP0 states */
  94. #define WAIT_FOR_SETUP 0 /* Wait for setup packet */
  95. #define DATA_IN 1 /* Expect dev->host transfer */
  96. #define DATA_OUT 2 /* Expect host->dev transfer */
  97. /* DD (DMA Descriptor) structure, requires word alignment, this is already
  98. * defined in the LPC32XX USB device header file, but this version is slightly
  99. * modified to tag some work data with each DMA descriptor. */
  100. struct lpc32xx_usbd_dd_gad {
  101. u32 dd_next_phy;
  102. u32 dd_setup;
  103. u32 dd_buffer_addr;
  104. u32 dd_status;
  105. u32 dd_iso_ps_mem_addr;
  106. u32 this_dma;
  107. u32 iso_status[6]; /* 5 spare */
  108. u32 dd_next_v;
  109. };
  110. /*
  111. * Logical endpoint structure
  112. */
  113. struct lpc32xx_ep {
  114. struct usb_ep ep;
  115. struct list_head queue;
  116. struct lpc32xx_udc *udc;
  117. u32 hwep_num_base; /* Physical hardware EP */
  118. u32 hwep_num; /* Maps to hardware endpoint */
  119. u32 maxpacket;
  120. u32 lep;
  121. bool is_in;
  122. bool req_pending;
  123. u32 eptype;
  124. u32 totalints;
  125. bool wedge;
  126. };
  127. /*
  128. * Common UDC structure
  129. */
  130. struct lpc32xx_udc {
  131. struct usb_gadget gadget;
  132. struct usb_gadget_driver *driver;
  133. struct platform_device *pdev;
  134. struct device *dev;
  135. struct dentry *pde;
  136. spinlock_t lock;
  137. struct i2c_client *isp1301_i2c_client;
  138. /* Board and device specific */
  139. struct lpc32xx_usbd_cfg *board;
  140. u32 io_p_start;
  141. u32 io_p_size;
  142. void __iomem *udp_baseaddr;
  143. int udp_irq[4];
  144. struct clk *usb_pll_clk;
  145. struct clk *usb_slv_clk;
  146. struct clk *usb_otg_clk;
  147. /* DMA support */
  148. u32 *udca_v_base;
  149. u32 udca_p_base;
  150. struct dma_pool *dd_cache;
  151. /* Common EP and control data */
  152. u32 enabled_devints;
  153. u32 enabled_hwepints;
  154. u32 dev_status;
  155. u32 realized_eps;
  156. /* VBUS detection, pullup, and power flags */
  157. u8 vbus;
  158. u8 last_vbus;
  159. int pullup;
  160. int poweron;
  161. /* Work queues related to I2C support */
  162. struct work_struct pullup_job;
  163. struct work_struct vbus_job;
  164. struct work_struct power_job;
  165. /* USB device peripheral - various */
  166. struct lpc32xx_ep ep[NUM_ENDPOINTS];
  167. bool enabled;
  168. bool clocked;
  169. bool suspended;
  170. bool selfpowered;
  171. int ep0state;
  172. atomic_t enabled_ep_cnt;
  173. wait_queue_head_t ep_disable_wait_queue;
  174. };
  175. /*
  176. * Endpoint request
  177. */
  178. struct lpc32xx_request {
  179. struct usb_request req;
  180. struct list_head queue;
  181. struct lpc32xx_usbd_dd_gad *dd_desc_ptr;
  182. bool mapped;
  183. bool send_zlp;
  184. };
  185. static inline struct lpc32xx_udc *to_udc(struct usb_gadget *g)
  186. {
  187. return container_of(g, struct lpc32xx_udc, gadget);
  188. }
  189. #define ep_dbg(epp, fmt, arg...) \
  190. dev_dbg(epp->udc->dev, "%s: " fmt, __func__, ## arg)
  191. #define ep_err(epp, fmt, arg...) \
  192. dev_err(epp->udc->dev, "%s: " fmt, __func__, ## arg)
  193. #define ep_info(epp, fmt, arg...) \
  194. dev_info(epp->udc->dev, "%s: " fmt, __func__, ## arg)
  195. #define ep_warn(epp, fmt, arg...) \
  196. dev_warn(epp->udc->dev, "%s:" fmt, __func__, ## arg)
  197. #define UDCA_BUFF_SIZE (128)
  198. /* TODO: When the clock framework is introduced in LPC32xx, IO_ADDRESS will
  199. * be replaced with an inremap()ed pointer
  200. * */
  201. #define USB_CTRL IO_ADDRESS(LPC32XX_CLK_PM_BASE + 0x64)
  202. /* USB_CTRL bit defines */
  203. #define USB_SLAVE_HCLK_EN (1 << 24)
  204. #define USB_HOST_NEED_CLK_EN (1 << 21)
  205. #define USB_DEV_NEED_CLK_EN (1 << 22)
  206. /**********************************************************************
  207. * USB device controller register offsets
  208. **********************************************************************/
  209. #define USBD_DEVINTST(x) ((x) + 0x200)
  210. #define USBD_DEVINTEN(x) ((x) + 0x204)
  211. #define USBD_DEVINTCLR(x) ((x) + 0x208)
  212. #define USBD_DEVINTSET(x) ((x) + 0x20C)
  213. #define USBD_CMDCODE(x) ((x) + 0x210)
  214. #define USBD_CMDDATA(x) ((x) + 0x214)
  215. #define USBD_RXDATA(x) ((x) + 0x218)
  216. #define USBD_TXDATA(x) ((x) + 0x21C)
  217. #define USBD_RXPLEN(x) ((x) + 0x220)
  218. #define USBD_TXPLEN(x) ((x) + 0x224)
  219. #define USBD_CTRL(x) ((x) + 0x228)
  220. #define USBD_DEVINTPRI(x) ((x) + 0x22C)
  221. #define USBD_EPINTST(x) ((x) + 0x230)
  222. #define USBD_EPINTEN(x) ((x) + 0x234)
  223. #define USBD_EPINTCLR(x) ((x) + 0x238)
  224. #define USBD_EPINTSET(x) ((x) + 0x23C)
  225. #define USBD_EPINTPRI(x) ((x) + 0x240)
  226. #define USBD_REEP(x) ((x) + 0x244)
  227. #define USBD_EPIND(x) ((x) + 0x248)
  228. #define USBD_EPMAXPSIZE(x) ((x) + 0x24C)
  229. /* DMA support registers only below */
  230. /* Set, clear, or get enabled state of the DMA request status. If
  231. * enabled, an IN or OUT token will start a DMA transfer for the EP */
  232. #define USBD_DMARST(x) ((x) + 0x250)
  233. #define USBD_DMARCLR(x) ((x) + 0x254)
  234. #define USBD_DMARSET(x) ((x) + 0x258)
  235. /* DMA UDCA head pointer */
  236. #define USBD_UDCAH(x) ((x) + 0x280)
  237. /* EP DMA status, enable, and disable. This is used to specifically
  238. * enabled or disable DMA for a specific EP */
  239. #define USBD_EPDMAST(x) ((x) + 0x284)
  240. #define USBD_EPDMAEN(x) ((x) + 0x288)
  241. #define USBD_EPDMADIS(x) ((x) + 0x28C)
  242. /* DMA master interrupts enable and pending interrupts */
  243. #define USBD_DMAINTST(x) ((x) + 0x290)
  244. #define USBD_DMAINTEN(x) ((x) + 0x294)
  245. /* DMA end of transfer interrupt enable, disable, status */
  246. #define USBD_EOTINTST(x) ((x) + 0x2A0)
  247. #define USBD_EOTINTCLR(x) ((x) + 0x2A4)
  248. #define USBD_EOTINTSET(x) ((x) + 0x2A8)
  249. /* New DD request interrupt enable, disable, status */
  250. #define USBD_NDDRTINTST(x) ((x) + 0x2AC)
  251. #define USBD_NDDRTINTCLR(x) ((x) + 0x2B0)
  252. #define USBD_NDDRTINTSET(x) ((x) + 0x2B4)
  253. /* DMA error interrupt enable, disable, status */
  254. #define USBD_SYSERRTINTST(x) ((x) + 0x2B8)
  255. #define USBD_SYSERRTINTCLR(x) ((x) + 0x2BC)
  256. #define USBD_SYSERRTINTSET(x) ((x) + 0x2C0)
  257. /**********************************************************************
  258. * USBD_DEVINTST/USBD_DEVINTEN/USBD_DEVINTCLR/USBD_DEVINTSET/
  259. * USBD_DEVINTPRI register definitions
  260. **********************************************************************/
  261. #define USBD_ERR_INT (1 << 9)
  262. #define USBD_EP_RLZED (1 << 8)
  263. #define USBD_TXENDPKT (1 << 7)
  264. #define USBD_RXENDPKT (1 << 6)
  265. #define USBD_CDFULL (1 << 5)
  266. #define USBD_CCEMPTY (1 << 4)
  267. #define USBD_DEV_STAT (1 << 3)
  268. #define USBD_EP_SLOW (1 << 2)
  269. #define USBD_EP_FAST (1 << 1)
  270. #define USBD_FRAME (1 << 0)
  271. /**********************************************************************
  272. * USBD_EPINTST/USBD_EPINTEN/USBD_EPINTCLR/USBD_EPINTSET/
  273. * USBD_EPINTPRI register definitions
  274. **********************************************************************/
  275. /* End point selection macro (RX) */
  276. #define USBD_RX_EP_SEL(e) (1 << ((e) << 1))
  277. /* End point selection macro (TX) */
  278. #define USBD_TX_EP_SEL(e) (1 << (((e) << 1) + 1))
  279. /**********************************************************************
  280. * USBD_REEP/USBD_DMARST/USBD_DMARCLR/USBD_DMARSET/USBD_EPDMAST/
  281. * USBD_EPDMAEN/USBD_EPDMADIS/
  282. * USBD_NDDRTINTST/USBD_NDDRTINTCLR/USBD_NDDRTINTSET/
  283. * USBD_EOTINTST/USBD_EOTINTCLR/USBD_EOTINTSET/
  284. * USBD_SYSERRTINTST/USBD_SYSERRTINTCLR/USBD_SYSERRTINTSET
  285. * register definitions
  286. **********************************************************************/
  287. /* Endpoint selection macro */
  288. #define USBD_EP_SEL(e) (1 << (e))
  289. /**********************************************************************
  290. * SBD_DMAINTST/USBD_DMAINTEN
  291. **********************************************************************/
  292. #define USBD_SYS_ERR_INT (1 << 2)
  293. #define USBD_NEW_DD_INT (1 << 1)
  294. #define USBD_EOT_INT (1 << 0)
  295. /**********************************************************************
  296. * USBD_RXPLEN register definitions
  297. **********************************************************************/
  298. #define USBD_PKT_RDY (1 << 11)
  299. #define USBD_DV (1 << 10)
  300. #define USBD_PK_LEN_MASK 0x3FF
  301. /**********************************************************************
  302. * USBD_CTRL register definitions
  303. **********************************************************************/
  304. #define USBD_LOG_ENDPOINT(e) ((e) << 2)
  305. #define USBD_WR_EN (1 << 1)
  306. #define USBD_RD_EN (1 << 0)
  307. /**********************************************************************
  308. * USBD_CMDCODE register definitions
  309. **********************************************************************/
  310. #define USBD_CMD_CODE(c) ((c) << 16)
  311. #define USBD_CMD_PHASE(p) ((p) << 8)
  312. /**********************************************************************
  313. * USBD_DMARST/USBD_DMARCLR/USBD_DMARSET register definitions
  314. **********************************************************************/
  315. #define USBD_DMAEP(e) (1 << (e))
  316. /* DD (DMA Descriptor) structure, requires word alignment */
  317. struct lpc32xx_usbd_dd {
  318. u32 *dd_next;
  319. u32 dd_setup;
  320. u32 dd_buffer_addr;
  321. u32 dd_status;
  322. u32 dd_iso_ps_mem_addr;
  323. };
  324. /* dd_setup bit defines */
  325. #define DD_SETUP_ATLE_DMA_MODE 0x01
  326. #define DD_SETUP_NEXT_DD_VALID 0x04
  327. #define DD_SETUP_ISO_EP 0x10
  328. #define DD_SETUP_PACKETLEN(n) (((n) & 0x7FF) << 5)
  329. #define DD_SETUP_DMALENBYTES(n) (((n) & 0xFFFF) << 16)
  330. /* dd_status bit defines */
  331. #define DD_STATUS_DD_RETIRED 0x01
  332. #define DD_STATUS_STS_MASK 0x1E
  333. #define DD_STATUS_STS_NS 0x00 /* Not serviced */
  334. #define DD_STATUS_STS_BS 0x02 /* Being serviced */
  335. #define DD_STATUS_STS_NC 0x04 /* Normal completion */
  336. #define DD_STATUS_STS_DUR 0x06 /* Data underrun (short packet) */
  337. #define DD_STATUS_STS_DOR 0x08 /* Data overrun */
  338. #define DD_STATUS_STS_SE 0x12 /* System error */
  339. #define DD_STATUS_PKT_VAL 0x20 /* Packet valid */
  340. #define DD_STATUS_LSB_EX 0x40 /* LS byte extracted (ATLE) */
  341. #define DD_STATUS_MSB_EX 0x80 /* MS byte extracted (ATLE) */
  342. #define DD_STATUS_MLEN(n) (((n) >> 8) & 0x3F)
  343. #define DD_STATUS_CURDMACNT(n) (((n) >> 16) & 0xFFFF)
  344. /*
  345. *
  346. * Protocol engine bits below
  347. *
  348. */
  349. /* Device Interrupt Bit Definitions */
  350. #define FRAME_INT 0x00000001
  351. #define EP_FAST_INT 0x00000002
  352. #define EP_SLOW_INT 0x00000004
  353. #define DEV_STAT_INT 0x00000008
  354. #define CCEMTY_INT 0x00000010
  355. #define CDFULL_INT 0x00000020
  356. #define RxENDPKT_INT 0x00000040
  357. #define TxENDPKT_INT 0x00000080
  358. #define EP_RLZED_INT 0x00000100
  359. #define ERR_INT 0x00000200
  360. /* Rx & Tx Packet Length Definitions */
  361. #define PKT_LNGTH_MASK 0x000003FF
  362. #define PKT_DV 0x00000400
  363. #define PKT_RDY 0x00000800
  364. /* USB Control Definitions */
  365. #define CTRL_RD_EN 0x00000001
  366. #define CTRL_WR_EN 0x00000002
  367. /* Command Codes */
  368. #define CMD_SET_ADDR 0x00D00500
  369. #define CMD_CFG_DEV 0x00D80500
  370. #define CMD_SET_MODE 0x00F30500
  371. #define CMD_RD_FRAME 0x00F50500
  372. #define DAT_RD_FRAME 0x00F50200
  373. #define CMD_RD_TEST 0x00FD0500
  374. #define DAT_RD_TEST 0x00FD0200
  375. #define CMD_SET_DEV_STAT 0x00FE0500
  376. #define CMD_GET_DEV_STAT 0x00FE0500
  377. #define DAT_GET_DEV_STAT 0x00FE0200
  378. #define CMD_GET_ERR_CODE 0x00FF0500
  379. #define DAT_GET_ERR_CODE 0x00FF0200
  380. #define CMD_RD_ERR_STAT 0x00FB0500
  381. #define DAT_RD_ERR_STAT 0x00FB0200
  382. #define DAT_WR_BYTE(x) (0x00000100 | ((x) << 16))
  383. #define CMD_SEL_EP(x) (0x00000500 | ((x) << 16))
  384. #define DAT_SEL_EP(x) (0x00000200 | ((x) << 16))
  385. #define CMD_SEL_EP_CLRI(x) (0x00400500 | ((x) << 16))
  386. #define DAT_SEL_EP_CLRI(x) (0x00400200 | ((x) << 16))
  387. #define CMD_SET_EP_STAT(x) (0x00400500 | ((x) << 16))
  388. #define CMD_CLR_BUF 0x00F20500
  389. #define DAT_CLR_BUF 0x00F20200
  390. #define CMD_VALID_BUF 0x00FA0500
  391. /* Device Address Register Definitions */
  392. #define DEV_ADDR_MASK 0x7F
  393. #define DEV_EN 0x80
  394. /* Device Configure Register Definitions */
  395. #define CONF_DVICE 0x01
  396. /* Device Mode Register Definitions */
  397. #define AP_CLK 0x01
  398. #define INAK_CI 0x02
  399. #define INAK_CO 0x04
  400. #define INAK_II 0x08
  401. #define INAK_IO 0x10
  402. #define INAK_BI 0x20
  403. #define INAK_BO 0x40
  404. /* Device Status Register Definitions */
  405. #define DEV_CON 0x01
  406. #define DEV_CON_CH 0x02
  407. #define DEV_SUS 0x04
  408. #define DEV_SUS_CH 0x08
  409. #define DEV_RST 0x10
  410. /* Error Code Register Definitions */
  411. #define ERR_EC_MASK 0x0F
  412. #define ERR_EA 0x10
  413. /* Error Status Register Definitions */
  414. #define ERR_PID 0x01
  415. #define ERR_UEPKT 0x02
  416. #define ERR_DCRC 0x04
  417. #define ERR_TIMOUT 0x08
  418. #define ERR_EOP 0x10
  419. #define ERR_B_OVRN 0x20
  420. #define ERR_BTSTF 0x40
  421. #define ERR_TGL 0x80
  422. /* Endpoint Select Register Definitions */
  423. #define EP_SEL_F 0x01
  424. #define EP_SEL_ST 0x02
  425. #define EP_SEL_STP 0x04
  426. #define EP_SEL_PO 0x08
  427. #define EP_SEL_EPN 0x10
  428. #define EP_SEL_B_1_FULL 0x20
  429. #define EP_SEL_B_2_FULL 0x40
  430. /* Endpoint Status Register Definitions */
  431. #define EP_STAT_ST 0x01
  432. #define EP_STAT_DA 0x20
  433. #define EP_STAT_RF_MO 0x40
  434. #define EP_STAT_CND_ST 0x80
  435. /* Clear Buffer Register Definitions */
  436. #define CLR_BUF_PO 0x01
  437. /* DMA Interrupt Bit Definitions */
  438. #define EOT_INT 0x01
  439. #define NDD_REQ_INT 0x02
  440. #define SYS_ERR_INT 0x04
  441. #define DRIVER_VERSION "1.03"
  442. static const char driver_name[] = "lpc32xx_udc";
  443. /*
  444. *
  445. * proc interface support
  446. *
  447. */
  448. #ifdef CONFIG_USB_GADGET_DEBUG_FILES
  449. static char *epnames[] = {"INT", "ISO", "BULK", "CTRL"};
  450. static const char debug_filename[] = "driver/udc";
  451. static void proc_ep_show(struct seq_file *s, struct lpc32xx_ep *ep)
  452. {
  453. struct lpc32xx_request *req;
  454. seq_printf(s, "\n");
  455. seq_printf(s, "%12s, maxpacket %4d %3s",
  456. ep->ep.name, ep->ep.maxpacket,
  457. ep->is_in ? "in" : "out");
  458. seq_printf(s, " type %4s", epnames[ep->eptype]);
  459. seq_printf(s, " ints: %12d", ep->totalints);
  460. if (list_empty(&ep->queue))
  461. seq_printf(s, "\t(queue empty)\n");
  462. else {
  463. list_for_each_entry(req, &ep->queue, queue) {
  464. u32 length = req->req.actual;
  465. seq_printf(s, "\treq %p len %d/%d buf %p\n",
  466. &req->req, length,
  467. req->req.length, req->req.buf);
  468. }
  469. }
  470. }
  471. static int proc_udc_show(struct seq_file *s, void *unused)
  472. {
  473. struct lpc32xx_udc *udc = s->private;
  474. struct lpc32xx_ep *ep;
  475. unsigned long flags;
  476. seq_printf(s, "%s: version %s\n", driver_name, DRIVER_VERSION);
  477. spin_lock_irqsave(&udc->lock, flags);
  478. seq_printf(s, "vbus %s, pullup %s, %s powered%s, gadget %s\n\n",
  479. udc->vbus ? "present" : "off",
  480. udc->enabled ? (udc->vbus ? "active" : "enabled") :
  481. "disabled",
  482. udc->selfpowered ? "self" : "VBUS",
  483. udc->suspended ? ", suspended" : "",
  484. udc->driver ? udc->driver->driver.name : "(none)");
  485. if (udc->enabled && udc->vbus) {
  486. proc_ep_show(s, &udc->ep[0]);
  487. list_for_each_entry(ep, &udc->gadget.ep_list, ep.ep_list)
  488. proc_ep_show(s, ep);
  489. }
  490. spin_unlock_irqrestore(&udc->lock, flags);
  491. return 0;
  492. }
  493. static int proc_udc_open(struct inode *inode, struct file *file)
  494. {
  495. return single_open(file, proc_udc_show, PDE_DATA(inode));
  496. }
  497. static const struct file_operations proc_ops = {
  498. .owner = THIS_MODULE,
  499. .open = proc_udc_open,
  500. .read = seq_read,
  501. .llseek = seq_lseek,
  502. .release = single_release,
  503. };
  504. static void create_debug_file(struct lpc32xx_udc *udc)
  505. {
  506. udc->pde = debugfs_create_file(debug_filename, 0, NULL, udc, &proc_ops);
  507. }
  508. static void remove_debug_file(struct lpc32xx_udc *udc)
  509. {
  510. if (udc->pde)
  511. debugfs_remove(udc->pde);
  512. }
  513. #else
  514. static inline void create_debug_file(struct lpc32xx_udc *udc) {}
  515. static inline void remove_debug_file(struct lpc32xx_udc *udc) {}
  516. #endif
  517. /* Primary initialization sequence for the ISP1301 transceiver */
  518. static void isp1301_udc_configure(struct lpc32xx_udc *udc)
  519. {
  520. /* LPC32XX only supports DAT_SE0 USB mode */
  521. /* This sequence is important */
  522. /* Disable transparent UART mode first */
  523. i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
  524. (ISP1301_I2C_MODE_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR),
  525. MC1_UART_EN);
  526. /* Set full speed and SE0 mode */
  527. i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
  528. (ISP1301_I2C_MODE_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR), ~0);
  529. i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
  530. ISP1301_I2C_MODE_CONTROL_1, (MC1_SPEED_REG | MC1_DAT_SE0));
  531. /*
  532. * The PSW_OE enable bit state is reversed in the ISP1301 User's Guide
  533. */
  534. i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
  535. (ISP1301_I2C_MODE_CONTROL_2 | ISP1301_I2C_REG_CLEAR_ADDR), ~0);
  536. i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
  537. ISP1301_I2C_MODE_CONTROL_2, (MC2_BI_DI | MC2_SPD_SUSP_CTRL));
  538. /* Driver VBUS_DRV high or low depending on board setup */
  539. if (udc->board->vbus_drv_pol != 0)
  540. i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
  541. ISP1301_I2C_OTG_CONTROL_1, OTG1_VBUS_DRV);
  542. else
  543. i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
  544. ISP1301_I2C_OTG_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR,
  545. OTG1_VBUS_DRV);
  546. /* Bi-directional mode with suspend control
  547. * Enable both pulldowns for now - the pullup will be enable when VBUS
  548. * is detected */
  549. i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
  550. (ISP1301_I2C_OTG_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR), ~0);
  551. i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
  552. ISP1301_I2C_OTG_CONTROL_1,
  553. (0 | OTG1_DM_PULLDOWN | OTG1_DP_PULLDOWN));
  554. /* Discharge VBUS (just in case) */
  555. i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
  556. ISP1301_I2C_OTG_CONTROL_1, OTG1_VBUS_DISCHRG);
  557. msleep(1);
  558. i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
  559. (ISP1301_I2C_OTG_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR),
  560. OTG1_VBUS_DISCHRG);
  561. /* Clear and enable VBUS high edge interrupt */
  562. i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
  563. ISP1301_I2C_INTERRUPT_LATCH | ISP1301_I2C_REG_CLEAR_ADDR, ~0);
  564. i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
  565. ISP1301_I2C_INTERRUPT_FALLING | ISP1301_I2C_REG_CLEAR_ADDR, ~0);
  566. i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
  567. ISP1301_I2C_INTERRUPT_FALLING, INT_VBUS_VLD);
  568. i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
  569. ISP1301_I2C_INTERRUPT_RISING | ISP1301_I2C_REG_CLEAR_ADDR, ~0);
  570. i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
  571. ISP1301_I2C_INTERRUPT_RISING, INT_VBUS_VLD);
  572. /* Enable usb_need_clk clock after transceiver is initialized */
  573. writel((readl(USB_CTRL) | USB_DEV_NEED_CLK_EN), USB_CTRL);
  574. dev_info(udc->dev, "ISP1301 Vendor ID : 0x%04x\n",
  575. i2c_smbus_read_word_data(udc->isp1301_i2c_client, 0x00));
  576. dev_info(udc->dev, "ISP1301 Product ID : 0x%04x\n",
  577. i2c_smbus_read_word_data(udc->isp1301_i2c_client, 0x02));
  578. dev_info(udc->dev, "ISP1301 Version ID : 0x%04x\n",
  579. i2c_smbus_read_word_data(udc->isp1301_i2c_client, 0x14));
  580. }
  581. /* Enables or disables the USB device pullup via the ISP1301 transceiver */
  582. static void isp1301_pullup_set(struct lpc32xx_udc *udc)
  583. {
  584. if (udc->pullup)
  585. /* Enable pullup for bus signalling */
  586. i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
  587. ISP1301_I2C_OTG_CONTROL_1, OTG1_DP_PULLUP);
  588. else
  589. /* Enable pullup for bus signalling */
  590. i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
  591. ISP1301_I2C_OTG_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR,
  592. OTG1_DP_PULLUP);
  593. }
  594. static void pullup_work(struct work_struct *work)
  595. {
  596. struct lpc32xx_udc *udc =
  597. container_of(work, struct lpc32xx_udc, pullup_job);
  598. isp1301_pullup_set(udc);
  599. }
  600. static void isp1301_pullup_enable(struct lpc32xx_udc *udc, int en_pullup,
  601. int block)
  602. {
  603. if (en_pullup == udc->pullup)
  604. return;
  605. udc->pullup = en_pullup;
  606. if (block)
  607. isp1301_pullup_set(udc);
  608. else
  609. /* defer slow i2c pull up setting */
  610. schedule_work(&udc->pullup_job);
  611. }
  612. #ifdef CONFIG_PM
  613. /* Powers up or down the ISP1301 transceiver */
  614. static void isp1301_set_powerstate(struct lpc32xx_udc *udc, int enable)
  615. {
  616. if (enable != 0)
  617. /* Power up ISP1301 - this ISP1301 will automatically wakeup
  618. when VBUS is detected */
  619. i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
  620. ISP1301_I2C_MODE_CONTROL_2 | ISP1301_I2C_REG_CLEAR_ADDR,
  621. MC2_GLOBAL_PWR_DN);
  622. else
  623. /* Power down ISP1301 */
  624. i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
  625. ISP1301_I2C_MODE_CONTROL_2, MC2_GLOBAL_PWR_DN);
  626. }
  627. static void power_work(struct work_struct *work)
  628. {
  629. struct lpc32xx_udc *udc =
  630. container_of(work, struct lpc32xx_udc, power_job);
  631. isp1301_set_powerstate(udc, udc->poweron);
  632. }
  633. #endif
  634. /*
  635. *
  636. * USB protocol engine command/data read/write helper functions
  637. *
  638. */
  639. /* Issues a single command to the USB device state machine */
  640. static void udc_protocol_cmd_w(struct lpc32xx_udc *udc, u32 cmd)
  641. {
  642. u32 pass = 0;
  643. int to;
  644. /* EP may lock on CLRI if this read isn't done */
  645. u32 tmp = readl(USBD_DEVINTST(udc->udp_baseaddr));
  646. (void) tmp;
  647. while (pass == 0) {
  648. writel(USBD_CCEMPTY, USBD_DEVINTCLR(udc->udp_baseaddr));
  649. /* Write command code */
  650. writel(cmd, USBD_CMDCODE(udc->udp_baseaddr));
  651. to = 10000;
  652. while (((readl(USBD_DEVINTST(udc->udp_baseaddr)) &
  653. USBD_CCEMPTY) == 0) && (to > 0)) {
  654. to--;
  655. }
  656. if (to > 0)
  657. pass = 1;
  658. cpu_relax();
  659. }
  660. }
  661. /* Issues 2 commands (or command and data) to the USB device state machine */
  662. static inline void udc_protocol_cmd_data_w(struct lpc32xx_udc *udc, u32 cmd,
  663. u32 data)
  664. {
  665. udc_protocol_cmd_w(udc, cmd);
  666. udc_protocol_cmd_w(udc, data);
  667. }
  668. /* Issues a single command to the USB device state machine and reads
  669. * response data */
  670. static u32 udc_protocol_cmd_r(struct lpc32xx_udc *udc, u32 cmd)
  671. {
  672. u32 tmp;
  673. int to = 1000;
  674. /* Write a command and read data from the protocol engine */
  675. writel((USBD_CDFULL | USBD_CCEMPTY),
  676. USBD_DEVINTCLR(udc->udp_baseaddr));
  677. /* Write command code */
  678. udc_protocol_cmd_w(udc, cmd);
  679. tmp = readl(USBD_DEVINTST(udc->udp_baseaddr));
  680. while ((!(readl(USBD_DEVINTST(udc->udp_baseaddr)) & USBD_CDFULL))
  681. && (to > 0))
  682. to--;
  683. if (!to)
  684. dev_dbg(udc->dev,
  685. "Protocol engine didn't receive response (CDFULL)\n");
  686. return readl(USBD_CMDDATA(udc->udp_baseaddr));
  687. }
  688. /*
  689. *
  690. * USB device interrupt mask support functions
  691. *
  692. */
  693. /* Enable one or more USB device interrupts */
  694. static inline void uda_enable_devint(struct lpc32xx_udc *udc, u32 devmask)
  695. {
  696. udc->enabled_devints |= devmask;
  697. writel(udc->enabled_devints, USBD_DEVINTEN(udc->udp_baseaddr));
  698. }
  699. /* Disable one or more USB device interrupts */
  700. static inline void uda_disable_devint(struct lpc32xx_udc *udc, u32 mask)
  701. {
  702. udc->enabled_devints &= ~mask;
  703. writel(udc->enabled_devints, USBD_DEVINTEN(udc->udp_baseaddr));
  704. }
  705. /* Clear one or more USB device interrupts */
  706. static inline void uda_clear_devint(struct lpc32xx_udc *udc, u32 mask)
  707. {
  708. writel(mask, USBD_DEVINTCLR(udc->udp_baseaddr));
  709. }
  710. /*
  711. *
  712. * Endpoint interrupt disable/enable functions
  713. *
  714. */
  715. /* Enable one or more USB endpoint interrupts */
  716. static void uda_enable_hwepint(struct lpc32xx_udc *udc, u32 hwep)
  717. {
  718. udc->enabled_hwepints |= (1 << hwep);
  719. writel(udc->enabled_hwepints, USBD_EPINTEN(udc->udp_baseaddr));
  720. }
  721. /* Disable one or more USB endpoint interrupts */
  722. static void uda_disable_hwepint(struct lpc32xx_udc *udc, u32 hwep)
  723. {
  724. udc->enabled_hwepints &= ~(1 << hwep);
  725. writel(udc->enabled_hwepints, USBD_EPINTEN(udc->udp_baseaddr));
  726. }
  727. /* Clear one or more USB endpoint interrupts */
  728. static inline void uda_clear_hwepint(struct lpc32xx_udc *udc, u32 hwep)
  729. {
  730. writel((1 << hwep), USBD_EPINTCLR(udc->udp_baseaddr));
  731. }
  732. /* Enable DMA for the HW channel */
  733. static inline void udc_ep_dma_enable(struct lpc32xx_udc *udc, u32 hwep)
  734. {
  735. writel((1 << hwep), USBD_EPDMAEN(udc->udp_baseaddr));
  736. }
  737. /* Disable DMA for the HW channel */
  738. static inline void udc_ep_dma_disable(struct lpc32xx_udc *udc, u32 hwep)
  739. {
  740. writel((1 << hwep), USBD_EPDMADIS(udc->udp_baseaddr));
  741. }
  742. /*
  743. *
  744. * Endpoint realize/unrealize functions
  745. *
  746. */
  747. /* Before an endpoint can be used, it needs to be realized
  748. * in the USB protocol engine - this realizes the endpoint.
  749. * The interrupt (FIFO or DMA) is not enabled with this function */
  750. static void udc_realize_hwep(struct lpc32xx_udc *udc, u32 hwep,
  751. u32 maxpacket)
  752. {
  753. int to = 1000;
  754. writel(USBD_EP_RLZED, USBD_DEVINTCLR(udc->udp_baseaddr));
  755. writel(hwep, USBD_EPIND(udc->udp_baseaddr));
  756. udc->realized_eps |= (1 << hwep);
  757. writel(udc->realized_eps, USBD_REEP(udc->udp_baseaddr));
  758. writel(maxpacket, USBD_EPMAXPSIZE(udc->udp_baseaddr));
  759. /* Wait until endpoint is realized in hardware */
  760. while ((!(readl(USBD_DEVINTST(udc->udp_baseaddr)) &
  761. USBD_EP_RLZED)) && (to > 0))
  762. to--;
  763. if (!to)
  764. dev_dbg(udc->dev, "EP not correctly realized in hardware\n");
  765. writel(USBD_EP_RLZED, USBD_DEVINTCLR(udc->udp_baseaddr));
  766. }
  767. /* Unrealize an EP */
  768. static void udc_unrealize_hwep(struct lpc32xx_udc *udc, u32 hwep)
  769. {
  770. udc->realized_eps &= ~(1 << hwep);
  771. writel(udc->realized_eps, USBD_REEP(udc->udp_baseaddr));
  772. }
  773. /*
  774. *
  775. * Endpoint support functions
  776. *
  777. */
  778. /* Select and clear endpoint interrupt */
  779. static u32 udc_selep_clrint(struct lpc32xx_udc *udc, u32 hwep)
  780. {
  781. udc_protocol_cmd_w(udc, CMD_SEL_EP_CLRI(hwep));
  782. return udc_protocol_cmd_r(udc, DAT_SEL_EP_CLRI(hwep));
  783. }
  784. /* Disables the endpoint in the USB protocol engine */
  785. static void udc_disable_hwep(struct lpc32xx_udc *udc, u32 hwep)
  786. {
  787. udc_protocol_cmd_data_w(udc, CMD_SET_EP_STAT(hwep),
  788. DAT_WR_BYTE(EP_STAT_DA));
  789. }
  790. /* Stalls the endpoint - endpoint will return STALL */
  791. static void udc_stall_hwep(struct lpc32xx_udc *udc, u32 hwep)
  792. {
  793. udc_protocol_cmd_data_w(udc, CMD_SET_EP_STAT(hwep),
  794. DAT_WR_BYTE(EP_STAT_ST));
  795. }
  796. /* Clear stall or reset endpoint */
  797. static void udc_clrstall_hwep(struct lpc32xx_udc *udc, u32 hwep)
  798. {
  799. udc_protocol_cmd_data_w(udc, CMD_SET_EP_STAT(hwep),
  800. DAT_WR_BYTE(0));
  801. }
  802. /* Select an endpoint for endpoint status, clear, validate */
  803. static void udc_select_hwep(struct lpc32xx_udc *udc, u32 hwep)
  804. {
  805. udc_protocol_cmd_w(udc, CMD_SEL_EP(hwep));
  806. }
  807. /*
  808. *
  809. * Endpoint buffer management functions
  810. *
  811. */
  812. /* Clear the current endpoint's buffer */
  813. static void udc_clr_buffer_hwep(struct lpc32xx_udc *udc, u32 hwep)
  814. {
  815. udc_select_hwep(udc, hwep);
  816. udc_protocol_cmd_w(udc, CMD_CLR_BUF);
  817. }
  818. /* Validate the current endpoint's buffer */
  819. static void udc_val_buffer_hwep(struct lpc32xx_udc *udc, u32 hwep)
  820. {
  821. udc_select_hwep(udc, hwep);
  822. udc_protocol_cmd_w(udc, CMD_VALID_BUF);
  823. }
  824. static inline u32 udc_clearep_getsts(struct lpc32xx_udc *udc, u32 hwep)
  825. {
  826. /* Clear EP interrupt */
  827. uda_clear_hwepint(udc, hwep);
  828. return udc_selep_clrint(udc, hwep);
  829. }
  830. /*
  831. *
  832. * USB EP DMA support
  833. *
  834. */
  835. /* Allocate a DMA Descriptor */
  836. static struct lpc32xx_usbd_dd_gad *udc_dd_alloc(struct lpc32xx_udc *udc)
  837. {
  838. dma_addr_t dma;
  839. struct lpc32xx_usbd_dd_gad *dd;
  840. dd = (struct lpc32xx_usbd_dd_gad *) dma_pool_alloc(
  841. udc->dd_cache, (GFP_KERNEL | GFP_DMA), &dma);
  842. if (dd)
  843. dd->this_dma = dma;
  844. return dd;
  845. }
  846. /* Free a DMA Descriptor */
  847. static void udc_dd_free(struct lpc32xx_udc *udc, struct lpc32xx_usbd_dd_gad *dd)
  848. {
  849. dma_pool_free(udc->dd_cache, dd, dd->this_dma);
  850. }
  851. /*
  852. *
  853. * USB setup and shutdown functions
  854. *
  855. */
  856. /* Enables or disables most of the USB system clocks when low power mode is
  857. * needed. Clocks are typically started on a connection event, and disabled
  858. * when a cable is disconnected */
  859. static void udc_clk_set(struct lpc32xx_udc *udc, int enable)
  860. {
  861. if (enable != 0) {
  862. if (udc->clocked)
  863. return;
  864. udc->clocked = 1;
  865. /* 48MHz PLL up */
  866. clk_enable(udc->usb_pll_clk);
  867. /* Enable the USB device clock */
  868. writel(readl(USB_CTRL) | USB_DEV_NEED_CLK_EN,
  869. USB_CTRL);
  870. clk_enable(udc->usb_otg_clk);
  871. } else {
  872. if (!udc->clocked)
  873. return;
  874. udc->clocked = 0;
  875. /* Never disable the USB_HCLK during normal operation */
  876. /* 48MHz PLL dpwn */
  877. clk_disable(udc->usb_pll_clk);
  878. /* Disable the USB device clock */
  879. writel(readl(USB_CTRL) & ~USB_DEV_NEED_CLK_EN,
  880. USB_CTRL);
  881. clk_disable(udc->usb_otg_clk);
  882. }
  883. }
  884. /* Set/reset USB device address */
  885. static void udc_set_address(struct lpc32xx_udc *udc, u32 addr)
  886. {
  887. /* Address will be latched at the end of the status phase, or
  888. latched immediately if function is called twice */
  889. udc_protocol_cmd_data_w(udc, CMD_SET_ADDR,
  890. DAT_WR_BYTE(DEV_EN | addr));
  891. }
  892. /* Setup up a IN request for DMA transfer - this consists of determining the
  893. * list of DMA addresses for the transfer, allocating DMA Descriptors,
  894. * installing the DD into the UDCA, and then enabling the DMA for that EP */
  895. static int udc_ep_in_req_dma(struct lpc32xx_udc *udc, struct lpc32xx_ep *ep)
  896. {
  897. struct lpc32xx_request *req;
  898. u32 hwep = ep->hwep_num;
  899. ep->req_pending = 1;
  900. /* There will always be a request waiting here */
  901. req = list_entry(ep->queue.next, struct lpc32xx_request, queue);
  902. /* Place the DD Descriptor into the UDCA */
  903. udc->udca_v_base[hwep] = req->dd_desc_ptr->this_dma;
  904. /* Enable DMA and interrupt for the HW EP */
  905. udc_ep_dma_enable(udc, hwep);
  906. /* Clear ZLP if last packet is not of MAXP size */
  907. if (req->req.length % ep->ep.maxpacket)
  908. req->send_zlp = 0;
  909. return 0;
  910. }
  911. /* Setup up a OUT request for DMA transfer - this consists of determining the
  912. * list of DMA addresses for the transfer, allocating DMA Descriptors,
  913. * installing the DD into the UDCA, and then enabling the DMA for that EP */
  914. static int udc_ep_out_req_dma(struct lpc32xx_udc *udc, struct lpc32xx_ep *ep)
  915. {
  916. struct lpc32xx_request *req;
  917. u32 hwep = ep->hwep_num;
  918. ep->req_pending = 1;
  919. /* There will always be a request waiting here */
  920. req = list_entry(ep->queue.next, struct lpc32xx_request, queue);
  921. /* Place the DD Descriptor into the UDCA */
  922. udc->udca_v_base[hwep] = req->dd_desc_ptr->this_dma;
  923. /* Enable DMA and interrupt for the HW EP */
  924. udc_ep_dma_enable(udc, hwep);
  925. return 0;
  926. }
  927. static void udc_disable(struct lpc32xx_udc *udc)
  928. {
  929. u32 i;
  930. /* Disable device */
  931. udc_protocol_cmd_data_w(udc, CMD_CFG_DEV, DAT_WR_BYTE(0));
  932. udc_protocol_cmd_data_w(udc, CMD_SET_DEV_STAT, DAT_WR_BYTE(0));
  933. /* Disable all device interrupts (including EP0) */
  934. uda_disable_devint(udc, 0x3FF);
  935. /* Disable and reset all endpoint interrupts */
  936. for (i = 0; i < 32; i++) {
  937. uda_disable_hwepint(udc, i);
  938. uda_clear_hwepint(udc, i);
  939. udc_disable_hwep(udc, i);
  940. udc_unrealize_hwep(udc, i);
  941. udc->udca_v_base[i] = 0;
  942. /* Disable and clear all interrupts and DMA */
  943. udc_ep_dma_disable(udc, i);
  944. writel((1 << i), USBD_EOTINTCLR(udc->udp_baseaddr));
  945. writel((1 << i), USBD_NDDRTINTCLR(udc->udp_baseaddr));
  946. writel((1 << i), USBD_SYSERRTINTCLR(udc->udp_baseaddr));
  947. writel((1 << i), USBD_DMARCLR(udc->udp_baseaddr));
  948. }
  949. /* Disable DMA interrupts */
  950. writel(0, USBD_DMAINTEN(udc->udp_baseaddr));
  951. writel(0, USBD_UDCAH(udc->udp_baseaddr));
  952. }
  953. static void udc_enable(struct lpc32xx_udc *udc)
  954. {
  955. u32 i;
  956. struct lpc32xx_ep *ep = &udc->ep[0];
  957. /* Start with known state */
  958. udc_disable(udc);
  959. /* Enable device */
  960. udc_protocol_cmd_data_w(udc, CMD_SET_DEV_STAT, DAT_WR_BYTE(DEV_CON));
  961. /* EP interrupts on high priority, FRAME interrupt on low priority */
  962. writel(USBD_EP_FAST, USBD_DEVINTPRI(udc->udp_baseaddr));
  963. writel(0xFFFF, USBD_EPINTPRI(udc->udp_baseaddr));
  964. /* Clear any pending device interrupts */
  965. writel(0x3FF, USBD_DEVINTCLR(udc->udp_baseaddr));
  966. /* Setup UDCA - not yet used (DMA) */
  967. writel(udc->udca_p_base, USBD_UDCAH(udc->udp_baseaddr));
  968. /* Only enable EP0 in and out for now, EP0 only works in FIFO mode */
  969. for (i = 0; i <= 1; i++) {
  970. udc_realize_hwep(udc, i, ep->ep.maxpacket);
  971. uda_enable_hwepint(udc, i);
  972. udc_select_hwep(udc, i);
  973. udc_clrstall_hwep(udc, i);
  974. udc_clr_buffer_hwep(udc, i);
  975. }
  976. /* Device interrupt setup */
  977. uda_clear_devint(udc, (USBD_ERR_INT | USBD_DEV_STAT | USBD_EP_SLOW |
  978. USBD_EP_FAST));
  979. uda_enable_devint(udc, (USBD_ERR_INT | USBD_DEV_STAT | USBD_EP_SLOW |
  980. USBD_EP_FAST));
  981. /* Set device address to 0 - called twice to force a latch in the USB
  982. engine without the need of a setup packet status closure */
  983. udc_set_address(udc, 0);
  984. udc_set_address(udc, 0);
  985. /* Enable master DMA interrupts */
  986. writel((USBD_SYS_ERR_INT | USBD_EOT_INT),
  987. USBD_DMAINTEN(udc->udp_baseaddr));
  988. udc->dev_status = 0;
  989. }
  990. /*
  991. *
  992. * USB device board specific events handled via callbacks
  993. *
  994. */
  995. /* Connection change event - notify board function of change */
  996. static void uda_power_event(struct lpc32xx_udc *udc, u32 conn)
  997. {
  998. /* Just notify of a connection change event (optional) */
  999. if (udc->board->conn_chgb != NULL)
  1000. udc->board->conn_chgb(conn);
  1001. }
  1002. /* Suspend/resume event - notify board function of change */
  1003. static void uda_resm_susp_event(struct lpc32xx_udc *udc, u32 conn)
  1004. {
  1005. /* Just notify of a Suspend/resume change event (optional) */
  1006. if (udc->board->susp_chgb != NULL)
  1007. udc->board->susp_chgb(conn);
  1008. if (conn)
  1009. udc->suspended = 0;
  1010. else
  1011. udc->suspended = 1;
  1012. }
  1013. /* Remote wakeup enable/disable - notify board function of change */
  1014. static void uda_remwkp_cgh(struct lpc32xx_udc *udc)
  1015. {
  1016. if (udc->board->rmwk_chgb != NULL)
  1017. udc->board->rmwk_chgb(udc->dev_status &
  1018. (1 << USB_DEVICE_REMOTE_WAKEUP));
  1019. }
  1020. /* Reads data from FIFO, adjusts for alignment and data size */
  1021. static void udc_pop_fifo(struct lpc32xx_udc *udc, u8 *data, u32 bytes)
  1022. {
  1023. int n, i, bl;
  1024. u16 *p16;
  1025. u32 *p32, tmp, cbytes;
  1026. /* Use optimal data transfer method based on source address and size */
  1027. switch (((u32) data) & 0x3) {
  1028. case 0: /* 32-bit aligned */
  1029. p32 = (u32 *) data;
  1030. cbytes = (bytes & ~0x3);
  1031. /* Copy 32-bit aligned data first */
  1032. for (n = 0; n < cbytes; n += 4)
  1033. *p32++ = readl(USBD_RXDATA(udc->udp_baseaddr));
  1034. /* Handle any remaining bytes */
  1035. bl = bytes - cbytes;
  1036. if (bl) {
  1037. tmp = readl(USBD_RXDATA(udc->udp_baseaddr));
  1038. for (n = 0; n < bl; n++)
  1039. data[cbytes + n] = ((tmp >> (n * 8)) & 0xFF);
  1040. }
  1041. break;
  1042. case 1: /* 8-bit aligned */
  1043. case 3:
  1044. /* Each byte has to be handled independently */
  1045. for (n = 0; n < bytes; n += 4) {
  1046. tmp = readl(USBD_RXDATA(udc->udp_baseaddr));
  1047. bl = bytes - n;
  1048. if (bl > 3)
  1049. bl = 3;
  1050. for (i = 0; i < bl; i++)
  1051. data[n + i] = (u8) ((tmp >> (n * 8)) & 0xFF);
  1052. }
  1053. break;
  1054. case 2: /* 16-bit aligned */
  1055. p16 = (u16 *) data;
  1056. cbytes = (bytes & ~0x3);
  1057. /* Copy 32-bit sized objects first with 16-bit alignment */
  1058. for (n = 0; n < cbytes; n += 4) {
  1059. tmp = readl(USBD_RXDATA(udc->udp_baseaddr));
  1060. *p16++ = (u16)(tmp & 0xFFFF);
  1061. *p16++ = (u16)((tmp >> 16) & 0xFFFF);
  1062. }
  1063. /* Handle any remaining bytes */
  1064. bl = bytes - cbytes;
  1065. if (bl) {
  1066. tmp = readl(USBD_RXDATA(udc->udp_baseaddr));
  1067. for (n = 0; n < bl; n++)
  1068. data[cbytes + n] = ((tmp >> (n * 8)) & 0xFF);
  1069. }
  1070. break;
  1071. }
  1072. }
  1073. /* Read data from the FIFO for an endpoint. This function is for endpoints (such
  1074. * as EP0) that don't use DMA. This function should only be called if a packet
  1075. * is known to be ready to read for the endpoint. Note that the endpoint must
  1076. * be selected in the protocol engine prior to this call. */
  1077. static u32 udc_read_hwep(struct lpc32xx_udc *udc, u32 hwep, u32 *data,
  1078. u32 bytes)
  1079. {
  1080. u32 tmpv;
  1081. int to = 1000;
  1082. u32 tmp, hwrep = ((hwep & 0x1E) << 1) | CTRL_RD_EN;
  1083. /* Setup read of endpoint */
  1084. writel(hwrep, USBD_CTRL(udc->udp_baseaddr));
  1085. /* Wait until packet is ready */
  1086. while ((((tmpv = readl(USBD_RXPLEN(udc->udp_baseaddr))) &
  1087. PKT_RDY) == 0) && (to > 0))
  1088. to--;
  1089. if (!to)
  1090. dev_dbg(udc->dev, "No packet ready on FIFO EP read\n");
  1091. /* Mask out count */
  1092. tmp = tmpv & PKT_LNGTH_MASK;
  1093. if (bytes < tmp)
  1094. tmp = bytes;
  1095. if ((tmp > 0) && (data != NULL))
  1096. udc_pop_fifo(udc, (u8 *) data, tmp);
  1097. writel(((hwep & 0x1E) << 1), USBD_CTRL(udc->udp_baseaddr));
  1098. /* Clear the buffer */
  1099. udc_clr_buffer_hwep(udc, hwep);
  1100. return tmp;
  1101. }
  1102. /* Stuffs data into the FIFO, adjusts for alignment and data size */
  1103. static void udc_stuff_fifo(struct lpc32xx_udc *udc, u8 *data, u32 bytes)
  1104. {
  1105. int n, i, bl;
  1106. u16 *p16;
  1107. u32 *p32, tmp, cbytes;
  1108. /* Use optimal data transfer method based on source address and size */
  1109. switch (((u32) data) & 0x3) {
  1110. case 0: /* 32-bit aligned */
  1111. p32 = (u32 *) data;
  1112. cbytes = (bytes & ~0x3);
  1113. /* Copy 32-bit aligned data first */
  1114. for (n = 0; n < cbytes; n += 4)
  1115. writel(*p32++, USBD_TXDATA(udc->udp_baseaddr));
  1116. /* Handle any remaining bytes */
  1117. bl = bytes - cbytes;
  1118. if (bl) {
  1119. tmp = 0;
  1120. for (n = 0; n < bl; n++)
  1121. tmp |= data[cbytes + n] << (n * 8);
  1122. writel(tmp, USBD_TXDATA(udc->udp_baseaddr));
  1123. }
  1124. break;
  1125. case 1: /* 8-bit aligned */
  1126. case 3:
  1127. /* Each byte has to be handled independently */
  1128. for (n = 0; n < bytes; n += 4) {
  1129. bl = bytes - n;
  1130. if (bl > 4)
  1131. bl = 4;
  1132. tmp = 0;
  1133. for (i = 0; i < bl; i++)
  1134. tmp |= data[n + i] << (i * 8);
  1135. writel(tmp, USBD_TXDATA(udc->udp_baseaddr));
  1136. }
  1137. break;
  1138. case 2: /* 16-bit aligned */
  1139. p16 = (u16 *) data;
  1140. cbytes = (bytes & ~0x3);
  1141. /* Copy 32-bit aligned data first */
  1142. for (n = 0; n < cbytes; n += 4) {
  1143. tmp = *p16++ & 0xFFFF;
  1144. tmp |= (*p16++ & 0xFFFF) << 16;
  1145. writel(tmp, USBD_TXDATA(udc->udp_baseaddr));
  1146. }
  1147. /* Handle any remaining bytes */
  1148. bl = bytes - cbytes;
  1149. if (bl) {
  1150. tmp = 0;
  1151. for (n = 0; n < bl; n++)
  1152. tmp |= data[cbytes + n] << (n * 8);
  1153. writel(tmp, USBD_TXDATA(udc->udp_baseaddr));
  1154. }
  1155. break;
  1156. }
  1157. }
  1158. /* Write data to the FIFO for an endpoint. This function is for endpoints (such
  1159. * as EP0) that don't use DMA. Note that the endpoint must be selected in the
  1160. * protocol engine prior to this call. */
  1161. static void udc_write_hwep(struct lpc32xx_udc *udc, u32 hwep, u32 *data,
  1162. u32 bytes)
  1163. {
  1164. u32 hwwep = ((hwep & 0x1E) << 1) | CTRL_WR_EN;
  1165. if ((bytes > 0) && (data == NULL))
  1166. return;
  1167. /* Setup write of endpoint */
  1168. writel(hwwep, USBD_CTRL(udc->udp_baseaddr));
  1169. writel(bytes, USBD_TXPLEN(udc->udp_baseaddr));
  1170. /* Need at least 1 byte to trigger TX */
  1171. if (bytes == 0)
  1172. writel(0, USBD_TXDATA(udc->udp_baseaddr));
  1173. else
  1174. udc_stuff_fifo(udc, (u8 *) data, bytes);
  1175. writel(((hwep & 0x1E) << 1), USBD_CTRL(udc->udp_baseaddr));
  1176. udc_val_buffer_hwep(udc, hwep);
  1177. }
  1178. /* USB device reset - resets USB to a default state with just EP0
  1179. enabled */
  1180. static void uda_usb_reset(struct lpc32xx_udc *udc)
  1181. {
  1182. u32 i = 0;
  1183. /* Re-init device controller and EP0 */
  1184. udc_enable(udc);
  1185. udc->gadget.speed = USB_SPEED_FULL;
  1186. for (i = 1; i < NUM_ENDPOINTS; i++) {
  1187. struct lpc32xx_ep *ep = &udc->ep[i];
  1188. ep->req_pending = 0;
  1189. }
  1190. }
  1191. /* Send a ZLP on EP0 */
  1192. static void udc_ep0_send_zlp(struct lpc32xx_udc *udc)
  1193. {
  1194. udc_write_hwep(udc, EP_IN, NULL, 0);
  1195. }
  1196. /* Get current frame number */
  1197. static u16 udc_get_current_frame(struct lpc32xx_udc *udc)
  1198. {
  1199. u16 flo, fhi;
  1200. udc_protocol_cmd_w(udc, CMD_RD_FRAME);
  1201. flo = (u16) udc_protocol_cmd_r(udc, DAT_RD_FRAME);
  1202. fhi = (u16) udc_protocol_cmd_r(udc, DAT_RD_FRAME);
  1203. return (fhi << 8) | flo;
  1204. }
  1205. /* Set the device as configured - enables all endpoints */
  1206. static inline void udc_set_device_configured(struct lpc32xx_udc *udc)
  1207. {
  1208. udc_protocol_cmd_data_w(udc, CMD_CFG_DEV, DAT_WR_BYTE(CONF_DVICE));
  1209. }
  1210. /* Set the device as unconfigured - disables all endpoints */
  1211. static inline void udc_set_device_unconfigured(struct lpc32xx_udc *udc)
  1212. {
  1213. udc_protocol_cmd_data_w(udc, CMD_CFG_DEV, DAT_WR_BYTE(0));
  1214. }
  1215. /* reinit == restore initial software state */
  1216. static void udc_reinit(struct lpc32xx_udc *udc)
  1217. {
  1218. u32 i;
  1219. INIT_LIST_HEAD(&udc->gadget.ep_list);
  1220. INIT_LIST_HEAD(&udc->gadget.ep0->ep_list);
  1221. for (i = 0; i < NUM_ENDPOINTS; i++) {
  1222. struct lpc32xx_ep *ep = &udc->ep[i];
  1223. if (i != 0)
  1224. list_add_tail(&ep->ep.ep_list, &udc->gadget.ep_list);
  1225. usb_ep_set_maxpacket_limit(&ep->ep, ep->maxpacket);
  1226. INIT_LIST_HEAD(&ep->queue);
  1227. ep->req_pending = 0;
  1228. }
  1229. udc->ep0state = WAIT_FOR_SETUP;
  1230. }
  1231. /* Must be called with lock */
  1232. static void done(struct lpc32xx_ep *ep, struct lpc32xx_request *req, int status)
  1233. {
  1234. struct lpc32xx_udc *udc = ep->udc;
  1235. list_del_init(&req->queue);
  1236. if (req->req.status == -EINPROGRESS)
  1237. req->req.status = status;
  1238. else
  1239. status = req->req.status;
  1240. if (ep->lep) {
  1241. usb_gadget_unmap_request(&udc->gadget, &req->req, ep->is_in);
  1242. /* Free DDs */
  1243. udc_dd_free(udc, req->dd_desc_ptr);
  1244. }
  1245. if (status && status != -ESHUTDOWN)
  1246. ep_dbg(ep, "%s done %p, status %d\n", ep->ep.name, req, status);
  1247. ep->req_pending = 0;
  1248. spin_unlock(&udc->lock);
  1249. usb_gadget_giveback_request(&ep->ep, &req->req);
  1250. spin_lock(&udc->lock);
  1251. }
  1252. /* Must be called with lock */
  1253. static void nuke(struct lpc32xx_ep *ep, int status)
  1254. {
  1255. struct lpc32xx_request *req;
  1256. while (!list_empty(&ep->queue)) {
  1257. req = list_entry(ep->queue.next, struct lpc32xx_request, queue);
  1258. done(ep, req, status);
  1259. }
  1260. if (status == -ESHUTDOWN) {
  1261. uda_disable_hwepint(ep->udc, ep->hwep_num);
  1262. udc_disable_hwep(ep->udc, ep->hwep_num);
  1263. }
  1264. }
  1265. /* IN endpoint 0 transfer */
  1266. static int udc_ep0_in_req(struct lpc32xx_udc *udc)
  1267. {
  1268. struct lpc32xx_request *req;
  1269. struct lpc32xx_ep *ep0 = &udc->ep[0];
  1270. u32 tsend, ts = 0;
  1271. if (list_empty(&ep0->queue))
  1272. /* Nothing to send */
  1273. return 0;
  1274. else
  1275. req = list_entry(ep0->queue.next, struct lpc32xx_request,
  1276. queue);
  1277. tsend = ts = req->req.length - req->req.actual;
  1278. if (ts == 0) {
  1279. /* Send a ZLP */
  1280. udc_ep0_send_zlp(udc);
  1281. done(ep0, req, 0);
  1282. return 1;
  1283. } else if (ts > ep0->ep.maxpacket)
  1284. ts = ep0->ep.maxpacket; /* Just send what we can */
  1285. /* Write data to the EP0 FIFO and start transfer */
  1286. udc_write_hwep(udc, EP_IN, (req->req.buf + req->req.actual), ts);
  1287. /* Increment data pointer */
  1288. req->req.actual += ts;
  1289. if (tsend >= ep0->ep.maxpacket)
  1290. return 0; /* Stay in data transfer state */
  1291. /* Transfer request is complete */
  1292. udc->ep0state = WAIT_FOR_SETUP;
  1293. done(ep0, req, 0);
  1294. return 1;
  1295. }
  1296. /* OUT endpoint 0 transfer */
  1297. static int udc_ep0_out_req(struct lpc32xx_udc *udc)
  1298. {
  1299. struct lpc32xx_request *req;
  1300. struct lpc32xx_ep *ep0 = &udc->ep[0];
  1301. u32 tr, bufferspace;
  1302. if (list_empty(&ep0->queue))
  1303. return 0;
  1304. else
  1305. req = list_entry(ep0->queue.next, struct lpc32xx_request,
  1306. queue);
  1307. if (req) {
  1308. if (req->req.length == 0) {
  1309. /* Just dequeue request */
  1310. done(ep0, req, 0);
  1311. udc->ep0state = WAIT_FOR_SETUP;
  1312. return 1;
  1313. }
  1314. /* Get data from FIFO */
  1315. bufferspace = req->req.length - req->req.actual;
  1316. if (bufferspace > ep0->ep.maxpacket)
  1317. bufferspace = ep0->ep.maxpacket;
  1318. /* Copy data to buffer */
  1319. prefetchw(req->req.buf + req->req.actual);
  1320. tr = udc_read_hwep(udc, EP_OUT, req->req.buf + req->req.actual,
  1321. bufferspace);
  1322. req->req.actual += bufferspace;
  1323. if (tr < ep0->ep.maxpacket) {
  1324. /* This is the last packet */
  1325. done(ep0, req, 0);
  1326. udc->ep0state = WAIT_FOR_SETUP;
  1327. return 1;
  1328. }
  1329. }
  1330. return 0;
  1331. }
  1332. /* Must be called with lock */
  1333. static void stop_activity(struct lpc32xx_udc *udc)
  1334. {
  1335. struct usb_gadget_driver *driver = udc->driver;
  1336. int i;
  1337. if (udc->gadget.speed == USB_SPEED_UNKNOWN)
  1338. driver = NULL;
  1339. udc->gadget.speed = USB_SPEED_UNKNOWN;
  1340. udc->suspended = 0;
  1341. for (i = 0; i < NUM_ENDPOINTS; i++) {
  1342. struct lpc32xx_ep *ep = &udc->ep[i];
  1343. nuke(ep, -ESHUTDOWN);
  1344. }
  1345. if (driver) {
  1346. spin_unlock(&udc->lock);
  1347. driver->disconnect(&udc->gadget);
  1348. spin_lock(&udc->lock);
  1349. }
  1350. isp1301_pullup_enable(udc, 0, 0);
  1351. udc_disable(udc);
  1352. udc_reinit(udc);
  1353. }
  1354. /*
  1355. * Activate or kill host pullup
  1356. * Can be called with or without lock
  1357. */
  1358. static void pullup(struct lpc32xx_udc *udc, int is_on)
  1359. {
  1360. if (!udc->clocked)
  1361. return;
  1362. if (!udc->enabled || !udc->vbus)
  1363. is_on = 0;
  1364. if (is_on != udc->pullup)
  1365. isp1301_pullup_enable(udc, is_on, 0);
  1366. }
  1367. /* Must be called without lock */
  1368. static int lpc32xx_ep_disable(struct usb_ep *_ep)
  1369. {
  1370. struct lpc32xx_ep *ep = container_of(_ep, struct lpc32xx_ep, ep);
  1371. struct lpc32xx_udc *udc = ep->udc;
  1372. unsigned long flags;
  1373. if ((ep->hwep_num_base == 0) || (ep->hwep_num == 0))
  1374. return -EINVAL;
  1375. spin_lock_irqsave(&udc->lock, flags);
  1376. nuke(ep, -ESHUTDOWN);
  1377. /* Clear all DMA statuses for this EP */
  1378. udc_ep_dma_disable(udc, ep->hwep_num);
  1379. writel(1 << ep->hwep_num, USBD_EOTINTCLR(udc->udp_baseaddr));
  1380. writel(1 << ep->hwep_num, USBD_NDDRTINTCLR(udc->udp_baseaddr));
  1381. writel(1 << ep->hwep_num, USBD_SYSERRTINTCLR(udc->udp_baseaddr));
  1382. writel(1 << ep->hwep_num, USBD_DMARCLR(udc->udp_baseaddr));
  1383. /* Remove the DD pointer in the UDCA */
  1384. udc->udca_v_base[ep->hwep_num] = 0;
  1385. /* Disable and reset endpoint and interrupt */
  1386. uda_clear_hwepint(udc, ep->hwep_num);
  1387. udc_unrealize_hwep(udc, ep->hwep_num);
  1388. ep->hwep_num = 0;
  1389. spin_unlock_irqrestore(&udc->lock, flags);
  1390. atomic_dec(&udc->enabled_ep_cnt);
  1391. wake_up(&udc->ep_disable_wait_queue);
  1392. return 0;
  1393. }
  1394. /* Must be called without lock */
  1395. static int lpc32xx_ep_enable(struct usb_ep *_ep,
  1396. const struct usb_endpoint_descriptor *desc)
  1397. {
  1398. struct lpc32xx_ep *ep = container_of(_ep, struct lpc32xx_ep, ep);
  1399. struct lpc32xx_udc *udc = ep->udc;
  1400. u16 maxpacket;
  1401. u32 tmp;
  1402. unsigned long flags;
  1403. /* Verify EP data */
  1404. if ((!_ep) || (!ep) || (!desc) ||
  1405. (desc->bDescriptorType != USB_DT_ENDPOINT)) {
  1406. dev_dbg(udc->dev, "bad ep or descriptor\n");
  1407. return -EINVAL;
  1408. }
  1409. maxpacket = usb_endpoint_maxp(desc);
  1410. if ((maxpacket == 0) || (maxpacket > ep->maxpacket)) {
  1411. dev_dbg(udc->dev, "bad ep descriptor's packet size\n");
  1412. return -EINVAL;
  1413. }
  1414. /* Don't touch EP0 */
  1415. if (ep->hwep_num_base == 0) {
  1416. dev_dbg(udc->dev, "Can't re-enable EP0!!!\n");
  1417. return -EINVAL;
  1418. }
  1419. /* Is driver ready? */
  1420. if ((!udc->driver) || (udc->gadget.speed == USB_SPEED_UNKNOWN)) {
  1421. dev_dbg(udc->dev, "bogus device state\n");
  1422. return -ESHUTDOWN;
  1423. }
  1424. tmp = desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK;
  1425. switch (tmp) {
  1426. case USB_ENDPOINT_XFER_CONTROL:
  1427. return -EINVAL;
  1428. case USB_ENDPOINT_XFER_INT:
  1429. if (maxpacket > ep->maxpacket) {
  1430. dev_dbg(udc->dev,
  1431. "Bad INT endpoint maxpacket %d\n", maxpacket);
  1432. return -EINVAL;
  1433. }
  1434. break;
  1435. case USB_ENDPOINT_XFER_BULK:
  1436. switch (maxpacket) {
  1437. case 8:
  1438. case 16:
  1439. case 32:
  1440. case 64:
  1441. break;
  1442. default:
  1443. dev_dbg(udc->dev,
  1444. "Bad BULK endpoint maxpacket %d\n", maxpacket);
  1445. return -EINVAL;
  1446. }
  1447. break;
  1448. case USB_ENDPOINT_XFER_ISOC:
  1449. break;
  1450. }
  1451. spin_lock_irqsave(&udc->lock, flags);
  1452. /* Initialize endpoint to match the selected descriptor */
  1453. ep->is_in = (desc->bEndpointAddress & USB_DIR_IN) != 0;
  1454. ep->ep.maxpacket = maxpacket;
  1455. /* Map hardware endpoint from base and direction */
  1456. if (ep->is_in)
  1457. /* IN endpoints are offset 1 from the OUT endpoint */
  1458. ep->hwep_num = ep->hwep_num_base + EP_IN;
  1459. else
  1460. ep->hwep_num = ep->hwep_num_base;
  1461. ep_dbg(ep, "EP enabled: %s, HW:%d, MP:%d IN:%d\n", ep->ep.name,
  1462. ep->hwep_num, maxpacket, (ep->is_in == 1));
  1463. /* Realize the endpoint, interrupt is enabled later when
  1464. * buffers are queued, IN EPs will NAK until buffers are ready */
  1465. udc_realize_hwep(udc, ep->hwep_num, ep->ep.maxpacket);
  1466. udc_clr_buffer_hwep(udc, ep->hwep_num);
  1467. uda_disable_hwepint(udc, ep->hwep_num);
  1468. udc_clrstall_hwep(udc, ep->hwep_num);
  1469. /* Clear all DMA statuses for this EP */
  1470. udc_ep_dma_disable(udc, ep->hwep_num);
  1471. writel(1 << ep->hwep_num, USBD_EOTINTCLR(udc->udp_baseaddr));
  1472. writel(1 << ep->hwep_num, USBD_NDDRTINTCLR(udc->udp_baseaddr));
  1473. writel(1 << ep->hwep_num, USBD_SYSERRTINTCLR(udc->udp_baseaddr));
  1474. writel(1 << ep->hwep_num, USBD_DMARCLR(udc->udp_baseaddr));
  1475. spin_unlock_irqrestore(&udc->lock, flags);
  1476. atomic_inc(&udc->enabled_ep_cnt);
  1477. return 0;
  1478. }
  1479. /*
  1480. * Allocate a USB request list
  1481. * Can be called with or without lock
  1482. */
  1483. static struct usb_request *lpc32xx_ep_alloc_request(struct usb_ep *_ep,
  1484. gfp_t gfp_flags)
  1485. {
  1486. struct lpc32xx_request *req;
  1487. req = kzalloc(sizeof(struct lpc32xx_request), gfp_flags);
  1488. if (!req)
  1489. return NULL;
  1490. INIT_LIST_HEAD(&req->queue);
  1491. return &req->req;
  1492. }
  1493. /*
  1494. * De-allocate a USB request list
  1495. * Can be called with or without lock
  1496. */
  1497. static void lpc32xx_ep_free_request(struct usb_ep *_ep,
  1498. struct usb_request *_req)
  1499. {
  1500. struct lpc32xx_request *req;
  1501. req = container_of(_req, struct lpc32xx_request, req);
  1502. BUG_ON(!list_empty(&req->queue));
  1503. kfree(req);
  1504. }
  1505. /* Must be called without lock */
  1506. static int lpc32xx_ep_queue(struct usb_ep *_ep,
  1507. struct usb_request *_req, gfp_t gfp_flags)
  1508. {
  1509. struct lpc32xx_request *req;
  1510. struct lpc32xx_ep *ep;
  1511. struct lpc32xx_udc *udc;
  1512. unsigned long flags;
  1513. int status = 0;
  1514. req = container_of(_req, struct lpc32xx_request, req);
  1515. ep = container_of(_ep, struct lpc32xx_ep, ep);
  1516. if (!_req || !_req->complete || !_req->buf ||
  1517. !list_empty(&req->queue))
  1518. return -EINVAL;
  1519. udc = ep->udc;
  1520. if (!_ep) {
  1521. dev_dbg(udc->dev, "invalid ep\n");
  1522. return -EINVAL;
  1523. }
  1524. if ((!udc) || (!udc->driver) ||
  1525. (udc->gadget.speed == USB_SPEED_UNKNOWN)) {
  1526. dev_dbg(udc->dev, "invalid device\n");
  1527. return -EINVAL;
  1528. }
  1529. if (ep->lep) {
  1530. struct lpc32xx_usbd_dd_gad *dd;
  1531. status = usb_gadget_map_request(&udc->gadget, _req, ep->is_in);
  1532. if (status)
  1533. return status;
  1534. /* For the request, build a list of DDs */
  1535. dd = udc_dd_alloc(udc);
  1536. if (!dd) {
  1537. /* Error allocating DD */
  1538. return -ENOMEM;
  1539. }
  1540. req->dd_desc_ptr = dd;
  1541. /* Setup the DMA descriptor */
  1542. dd->dd_next_phy = dd->dd_next_v = 0;
  1543. dd->dd_buffer_addr = req->req.dma;
  1544. dd->dd_status = 0;
  1545. /* Special handling for ISO EPs */
  1546. if (ep->eptype == EP_ISO_TYPE) {
  1547. dd->dd_setup = DD_SETUP_ISO_EP |
  1548. DD_SETUP_PACKETLEN(0) |
  1549. DD_SETUP_DMALENBYTES(1);
  1550. dd->dd_iso_ps_mem_addr = dd->this_dma + 24;
  1551. if (ep->is_in)
  1552. dd->iso_status[0] = req->req.length;
  1553. else
  1554. dd->iso_status[0] = 0;
  1555. } else
  1556. dd->dd_setup = DD_SETUP_PACKETLEN(ep->ep.maxpacket) |
  1557. DD_SETUP_DMALENBYTES(req->req.length);
  1558. }
  1559. ep_dbg(ep, "%s queue req %p len %d buf %p (in=%d) z=%d\n", _ep->name,
  1560. _req, _req->length, _req->buf, ep->is_in, _req->zero);
  1561. spin_lock_irqsave(&udc->lock, flags);
  1562. _req->status = -EINPROGRESS;
  1563. _req->actual = 0;
  1564. req->send_zlp = _req->zero;
  1565. /* Kickstart empty queues */
  1566. if (list_empty(&ep->queue)) {
  1567. list_add_tail(&req->queue, &ep->queue);
  1568. if (ep->hwep_num_base == 0) {
  1569. /* Handle expected data direction */
  1570. if (ep->is_in) {
  1571. /* IN packet to host */
  1572. udc->ep0state = DATA_IN;
  1573. status = udc_ep0_in_req(udc);
  1574. } else {
  1575. /* OUT packet from host */
  1576. udc->ep0state = DATA_OUT;
  1577. status = udc_ep0_out_req(udc);
  1578. }
  1579. } else if (ep->is_in) {
  1580. /* IN packet to host and kick off transfer */
  1581. if (!ep->req_pending)
  1582. udc_ep_in_req_dma(udc, ep);
  1583. } else
  1584. /* OUT packet from host and kick off list */
  1585. if (!ep->req_pending)
  1586. udc_ep_out_req_dma(udc, ep);
  1587. } else
  1588. list_add_tail(&req->queue, &ep->queue);
  1589. spin_unlock_irqrestore(&udc->lock, flags);
  1590. return (status < 0) ? status : 0;
  1591. }
  1592. /* Must be called without lock */
  1593. static int lpc32xx_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
  1594. {
  1595. struct lpc32xx_ep *ep;
  1596. struct lpc32xx_request *req;
  1597. unsigned long flags;
  1598. ep = container_of(_ep, struct lpc32xx_ep, ep);
  1599. if (!_ep || ep->hwep_num_base == 0)
  1600. return -EINVAL;
  1601. spin_lock_irqsave(&ep->udc->lock, flags);
  1602. /* make sure it's actually queued on this endpoint */
  1603. list_for_each_entry(req, &ep->queue, queue) {
  1604. if (&req->req == _req)
  1605. break;
  1606. }
  1607. if (&req->req != _req) {
  1608. spin_unlock_irqrestore(&ep->udc->lock, flags);
  1609. return -EINVAL;
  1610. }
  1611. done(ep, req, -ECONNRESET);
  1612. spin_unlock_irqrestore(&ep->udc->lock, flags);
  1613. return 0;
  1614. }
  1615. /* Must be called without lock */
  1616. static int lpc32xx_ep_set_halt(struct usb_ep *_ep, int value)
  1617. {
  1618. struct lpc32xx_ep *ep = container_of(_ep, struct lpc32xx_ep, ep);
  1619. struct lpc32xx_udc *udc = ep->udc;
  1620. unsigned long flags;
  1621. if ((!ep) || (ep->hwep_num <= 1))
  1622. return -EINVAL;
  1623. /* Don't halt an IN EP */
  1624. if (ep->is_in)
  1625. return -EAGAIN;
  1626. spin_lock_irqsave(&udc->lock, flags);
  1627. if (value == 1) {
  1628. /* stall */
  1629. udc_protocol_cmd_data_w(udc, CMD_SET_EP_STAT(ep->hwep_num),
  1630. DAT_WR_BYTE(EP_STAT_ST));
  1631. } else {
  1632. /* End stall */
  1633. ep->wedge = 0;
  1634. udc_protocol_cmd_data_w(udc, CMD_SET_EP_STAT(ep->hwep_num),
  1635. DAT_WR_BYTE(0));
  1636. }
  1637. spin_unlock_irqrestore(&udc->lock, flags);
  1638. return 0;
  1639. }
  1640. /* set the halt feature and ignores clear requests */
  1641. static int lpc32xx_ep_set_wedge(struct usb_ep *_ep)
  1642. {
  1643. struct lpc32xx_ep *ep = container_of(_ep, struct lpc32xx_ep, ep);
  1644. if (!_ep || !ep->udc)
  1645. return -EINVAL;
  1646. ep->wedge = 1;
  1647. return usb_ep_set_halt(_ep);
  1648. }
  1649. static const struct usb_ep_ops lpc32xx_ep_ops = {
  1650. .enable = lpc32xx_ep_enable,
  1651. .disable = lpc32xx_ep_disable,
  1652. .alloc_request = lpc32xx_ep_alloc_request,
  1653. .free_request = lpc32xx_ep_free_request,
  1654. .queue = lpc32xx_ep_queue,
  1655. .dequeue = lpc32xx_ep_dequeue,
  1656. .set_halt = lpc32xx_ep_set_halt,
  1657. .set_wedge = lpc32xx_ep_set_wedge,
  1658. };
  1659. /* Send a ZLP on a non-0 IN EP */
  1660. void udc_send_in_zlp(struct lpc32xx_udc *udc, struct lpc32xx_ep *ep)
  1661. {
  1662. /* Clear EP status */
  1663. udc_clearep_getsts(udc, ep->hwep_num);
  1664. /* Send ZLP via FIFO mechanism */
  1665. udc_write_hwep(udc, ep->hwep_num, NULL, 0);
  1666. }
  1667. /*
  1668. * Handle EP completion for ZLP
  1669. * This function will only be called when a delayed ZLP needs to be sent out
  1670. * after a DMA transfer has filled both buffers.
  1671. */
  1672. void udc_handle_eps(struct lpc32xx_udc *udc, struct lpc32xx_ep *ep)
  1673. {
  1674. u32 epstatus;
  1675. struct lpc32xx_request *req;
  1676. if (ep->hwep_num <= 0)
  1677. return;
  1678. uda_clear_hwepint(udc, ep->hwep_num);
  1679. /* If this interrupt isn't enabled, return now */
  1680. if (!(udc->enabled_hwepints & (1 << ep->hwep_num)))
  1681. return;
  1682. /* Get endpoint status */
  1683. epstatus = udc_clearep_getsts(udc, ep->hwep_num);
  1684. /*
  1685. * This should never happen, but protect against writing to the
  1686. * buffer when full.
  1687. */
  1688. if (epstatus & EP_SEL_F)
  1689. return;
  1690. if (ep->is_in) {
  1691. udc_send_in_zlp(udc, ep);
  1692. uda_disable_hwepint(udc, ep->hwep_num);
  1693. } else
  1694. return;
  1695. /* If there isn't a request waiting, something went wrong */
  1696. req = list_entry(ep->queue.next, struct lpc32xx_request, queue);
  1697. if (req) {
  1698. done(ep, req, 0);
  1699. /* Start another request if ready */
  1700. if (!list_empty(&ep->queue)) {
  1701. if (ep->is_in)
  1702. udc_ep_in_req_dma(udc, ep);
  1703. else
  1704. udc_ep_out_req_dma(udc, ep);
  1705. } else
  1706. ep->req_pending = 0;
  1707. }
  1708. }
  1709. /* DMA end of transfer completion */
  1710. static void udc_handle_dma_ep(struct lpc32xx_udc *udc, struct lpc32xx_ep *ep)
  1711. {
  1712. u32 status, epstatus;
  1713. struct lpc32xx_request *req;
  1714. struct lpc32xx_usbd_dd_gad *dd;
  1715. #ifdef CONFIG_USB_GADGET_DEBUG_FILES
  1716. ep->totalints++;
  1717. #endif
  1718. req = list_entry(ep->queue.next, struct lpc32xx_request, queue);
  1719. if (!req) {
  1720. ep_err(ep, "DMA interrupt on no req!\n");
  1721. return;
  1722. }
  1723. dd = req->dd_desc_ptr;
  1724. /* DMA descriptor should always be retired for this call */
  1725. if (!(dd->dd_status & DD_STATUS_DD_RETIRED))
  1726. ep_warn(ep, "DMA descriptor did not retire\n");
  1727. /* Disable DMA */
  1728. udc_ep_dma_disable(udc, ep->hwep_num);
  1729. writel((1 << ep->hwep_num), USBD_EOTINTCLR(udc->udp_baseaddr));
  1730. writel((1 << ep->hwep_num), USBD_NDDRTINTCLR(udc->udp_baseaddr));
  1731. /* System error? */
  1732. if (readl(USBD_SYSERRTINTST(udc->udp_baseaddr)) &
  1733. (1 << ep->hwep_num)) {
  1734. writel((1 << ep->hwep_num),
  1735. USBD_SYSERRTINTCLR(udc->udp_baseaddr));
  1736. ep_err(ep, "AHB critical error!\n");
  1737. ep->req_pending = 0;
  1738. /* The error could have occurred on a packet of a multipacket
  1739. * transfer, so recovering the transfer is not possible. Close
  1740. * the request with an error */
  1741. done(ep, req, -ECONNABORTED);
  1742. return;
  1743. }
  1744. /* Handle the current DD's status */
  1745. status = dd->dd_status;
  1746. switch (status & DD_STATUS_STS_MASK) {
  1747. case DD_STATUS_STS_NS:
  1748. /* DD not serviced? This shouldn't happen! */
  1749. ep->req_pending = 0;
  1750. ep_err(ep, "DMA critical EP error: DD not serviced (0x%x)!\n",
  1751. status);
  1752. done(ep, req, -ECONNABORTED);
  1753. return;
  1754. case DD_STATUS_STS_BS:
  1755. /* Interrupt only fires on EOT - This shouldn't happen! */
  1756. ep->req_pending = 0;
  1757. ep_err(ep, "DMA critical EP error: EOT prior to service completion (0x%x)!\n",
  1758. status);
  1759. done(ep, req, -ECONNABORTED);
  1760. return;
  1761. case DD_STATUS_STS_NC:
  1762. case DD_STATUS_STS_DUR:
  1763. /* Really just a short packet, not an underrun */
  1764. /* This is a good status and what we expect */
  1765. break;
  1766. default:
  1767. /* Data overrun, system error, or unknown */
  1768. ep->req_pending = 0;
  1769. ep_err(ep, "DMA critical EP error: System error (0x%x)!\n",
  1770. status);
  1771. done(ep, req, -ECONNABORTED);
  1772. return;
  1773. }
  1774. /* ISO endpoints are handled differently */
  1775. if (ep->eptype == EP_ISO_TYPE) {
  1776. if (ep->is_in)
  1777. req->req.actual = req->req.length;
  1778. else
  1779. req->req.actual = dd->iso_status[0] & 0xFFFF;
  1780. } else
  1781. req->req.actual += DD_STATUS_CURDMACNT(status);
  1782. /* Send a ZLP if necessary. This will be done for non-int
  1783. * packets which have a size that is a divisor of MAXP */
  1784. if (req->send_zlp) {
  1785. /*
  1786. * If at least 1 buffer is available, send the ZLP now.
  1787. * Otherwise, the ZLP send needs to be deferred until a
  1788. * buffer is available.
  1789. */
  1790. if (udc_clearep_getsts(udc, ep->hwep_num) & EP_SEL_F) {
  1791. udc_clearep_getsts(udc, ep->hwep_num);
  1792. uda_enable_hwepint(udc, ep->hwep_num);
  1793. epstatus = udc_clearep_getsts(udc, ep->hwep_num);
  1794. /* Let the EP interrupt handle the ZLP */
  1795. return;
  1796. } else
  1797. udc_send_in_zlp(udc, ep);
  1798. }
  1799. /* Transfer request is complete */
  1800. done(ep, req, 0);
  1801. /* Start another request if ready */
  1802. udc_clearep_getsts(udc, ep->hwep_num);
  1803. if (!list_empty((&ep->queue))) {
  1804. if (ep->is_in)
  1805. udc_ep_in_req_dma(udc, ep);
  1806. else
  1807. udc_ep_out_req_dma(udc, ep);
  1808. } else
  1809. ep->req_pending = 0;
  1810. }
  1811. /*
  1812. *
  1813. * Endpoint 0 functions
  1814. *
  1815. */
  1816. static void udc_handle_dev(struct lpc32xx_udc *udc)
  1817. {
  1818. u32 tmp;
  1819. udc_protocol_cmd_w(udc, CMD_GET_DEV_STAT);
  1820. tmp = udc_protocol_cmd_r(udc, DAT_GET_DEV_STAT);
  1821. if (tmp & DEV_RST)
  1822. uda_usb_reset(udc);
  1823. else if (tmp & DEV_CON_CH)
  1824. uda_power_event(udc, (tmp & DEV_CON));
  1825. else if (tmp & DEV_SUS_CH) {
  1826. if (tmp & DEV_SUS) {
  1827. if (udc->vbus == 0)
  1828. stop_activity(udc);
  1829. else if ((udc->gadget.speed != USB_SPEED_UNKNOWN) &&
  1830. udc->driver) {
  1831. /* Power down transceiver */
  1832. udc->poweron = 0;
  1833. schedule_work(&udc->pullup_job);
  1834. uda_resm_susp_event(udc, 1);
  1835. }
  1836. } else if ((udc->gadget.speed != USB_SPEED_UNKNOWN) &&
  1837. udc->driver && udc->vbus) {
  1838. uda_resm_susp_event(udc, 0);
  1839. /* Power up transceiver */
  1840. udc->poweron = 1;
  1841. schedule_work(&udc->pullup_job);
  1842. }
  1843. }
  1844. }
  1845. static int udc_get_status(struct lpc32xx_udc *udc, u16 reqtype, u16 wIndex)
  1846. {
  1847. struct lpc32xx_ep *ep;
  1848. u32 ep0buff = 0, tmp;
  1849. switch (reqtype & USB_RECIP_MASK) {
  1850. case USB_RECIP_INTERFACE:
  1851. break; /* Not supported */
  1852. case USB_RECIP_DEVICE:
  1853. ep0buff = (udc->selfpowered << USB_DEVICE_SELF_POWERED);
  1854. if (udc->dev_status & (1 << USB_DEVICE_REMOTE_WAKEUP))
  1855. ep0buff |= (1 << USB_DEVICE_REMOTE_WAKEUP);
  1856. break;
  1857. case USB_RECIP_ENDPOINT:
  1858. tmp = wIndex & USB_ENDPOINT_NUMBER_MASK;
  1859. ep = &udc->ep[tmp];
  1860. if ((tmp == 0) || (tmp >= NUM_ENDPOINTS))
  1861. return -EOPNOTSUPP;
  1862. if (wIndex & USB_DIR_IN) {
  1863. if (!ep->is_in)
  1864. return -EOPNOTSUPP; /* Something's wrong */
  1865. } else if (ep->is_in)
  1866. return -EOPNOTSUPP; /* Not an IN endpoint */
  1867. /* Get status of the endpoint */
  1868. udc_protocol_cmd_w(udc, CMD_SEL_EP(ep->hwep_num));
  1869. tmp = udc_protocol_cmd_r(udc, DAT_SEL_EP(ep->hwep_num));
  1870. if (tmp & EP_SEL_ST)
  1871. ep0buff = (1 << USB_ENDPOINT_HALT);
  1872. else
  1873. ep0buff = 0;
  1874. break;
  1875. default:
  1876. break;
  1877. }
  1878. /* Return data */
  1879. udc_write_hwep(udc, EP_IN, &ep0buff, 2);
  1880. return 0;
  1881. }
  1882. static void udc_handle_ep0_setup(struct lpc32xx_udc *udc)
  1883. {
  1884. struct lpc32xx_ep *ep, *ep0 = &udc->ep[0];
  1885. struct usb_ctrlrequest ctrlpkt;
  1886. int i, bytes;
  1887. u16 wIndex, wValue, wLength, reqtype, req, tmp;
  1888. /* Nuke previous transfers */
  1889. nuke(ep0, -EPROTO);
  1890. /* Get setup packet */
  1891. bytes = udc_read_hwep(udc, EP_OUT, (u32 *) &ctrlpkt, 8);
  1892. if (bytes != 8) {
  1893. ep_warn(ep0, "Incorrectly sized setup packet (s/b 8, is %d)!\n",
  1894. bytes);
  1895. return;
  1896. }
  1897. /* Native endianness */
  1898. wIndex = le16_to_cpu(ctrlpkt.wIndex);
  1899. wValue = le16_to_cpu(ctrlpkt.wValue);
  1900. wLength = le16_to_cpu(ctrlpkt.wLength);
  1901. reqtype = le16_to_cpu(ctrlpkt.bRequestType);
  1902. /* Set direction of EP0 */
  1903. if (likely(reqtype & USB_DIR_IN))
  1904. ep0->is_in = 1;
  1905. else
  1906. ep0->is_in = 0;
  1907. /* Handle SETUP packet */
  1908. req = le16_to_cpu(ctrlpkt.bRequest);
  1909. switch (req) {
  1910. case USB_REQ_CLEAR_FEATURE:
  1911. case USB_REQ_SET_FEATURE:
  1912. switch (reqtype) {
  1913. case (USB_TYPE_STANDARD | USB_RECIP_DEVICE):
  1914. if (wValue != USB_DEVICE_REMOTE_WAKEUP)
  1915. goto stall; /* Nothing else handled */
  1916. /* Tell board about event */
  1917. if (req == USB_REQ_CLEAR_FEATURE)
  1918. udc->dev_status &=
  1919. ~(1 << USB_DEVICE_REMOTE_WAKEUP);
  1920. else
  1921. udc->dev_status |=
  1922. (1 << USB_DEVICE_REMOTE_WAKEUP);
  1923. uda_remwkp_cgh(udc);
  1924. goto zlp_send;
  1925. case (USB_TYPE_STANDARD | USB_RECIP_ENDPOINT):
  1926. tmp = wIndex & USB_ENDPOINT_NUMBER_MASK;
  1927. if ((wValue != USB_ENDPOINT_HALT) ||
  1928. (tmp >= NUM_ENDPOINTS))
  1929. break;
  1930. /* Find hardware endpoint from logical endpoint */
  1931. ep = &udc->ep[tmp];
  1932. tmp = ep->hwep_num;
  1933. if (tmp == 0)
  1934. break;
  1935. if (req == USB_REQ_SET_FEATURE)
  1936. udc_stall_hwep(udc, tmp);
  1937. else if (!ep->wedge)
  1938. udc_clrstall_hwep(udc, tmp);
  1939. goto zlp_send;
  1940. default:
  1941. break;
  1942. }
  1943. case USB_REQ_SET_ADDRESS:
  1944. if (reqtype == (USB_TYPE_STANDARD | USB_RECIP_DEVICE)) {
  1945. udc_set_address(udc, wValue);
  1946. goto zlp_send;
  1947. }
  1948. break;
  1949. case USB_REQ_GET_STATUS:
  1950. udc_get_status(udc, reqtype, wIndex);
  1951. return;
  1952. default:
  1953. break; /* Let GadgetFS handle the descriptor instead */
  1954. }
  1955. if (likely(udc->driver)) {
  1956. /* device-2-host (IN) or no data setup command, process
  1957. * immediately */
  1958. spin_unlock(&udc->lock);
  1959. i = udc->driver->setup(&udc->gadget, &ctrlpkt);
  1960. spin_lock(&udc->lock);
  1961. if (req == USB_REQ_SET_CONFIGURATION) {
  1962. /* Configuration is set after endpoints are realized */
  1963. if (wValue) {
  1964. /* Set configuration */
  1965. udc_set_device_configured(udc);
  1966. udc_protocol_cmd_data_w(udc, CMD_SET_MODE,
  1967. DAT_WR_BYTE(AP_CLK |
  1968. INAK_BI | INAK_II));
  1969. } else {
  1970. /* Clear configuration */
  1971. udc_set_device_unconfigured(udc);
  1972. /* Disable NAK interrupts */
  1973. udc_protocol_cmd_data_w(udc, CMD_SET_MODE,
  1974. DAT_WR_BYTE(AP_CLK));
  1975. }
  1976. }
  1977. if (i < 0) {
  1978. /* setup processing failed, force stall */
  1979. dev_dbg(udc->dev,
  1980. "req %02x.%02x protocol STALL; stat %d\n",
  1981. reqtype, req, i);
  1982. udc->ep0state = WAIT_FOR_SETUP;
  1983. goto stall;
  1984. }
  1985. }
  1986. if (!ep0->is_in)
  1987. udc_ep0_send_zlp(udc); /* ZLP IN packet on data phase */
  1988. return;
  1989. stall:
  1990. udc_stall_hwep(udc, EP_IN);
  1991. return;
  1992. zlp_send:
  1993. udc_ep0_send_zlp(udc);
  1994. return;
  1995. }
  1996. /* IN endpoint 0 transfer */
  1997. static void udc_handle_ep0_in(struct lpc32xx_udc *udc)
  1998. {
  1999. struct lpc32xx_ep *ep0 = &udc->ep[0];
  2000. u32 epstatus;
  2001. /* Clear EP interrupt */
  2002. epstatus = udc_clearep_getsts(udc, EP_IN);
  2003. #ifdef CONFIG_USB_GADGET_DEBUG_FILES
  2004. ep0->totalints++;
  2005. #endif
  2006. /* Stalled? Clear stall and reset buffers */
  2007. if (epstatus & EP_SEL_ST) {
  2008. udc_clrstall_hwep(udc, EP_IN);
  2009. nuke(ep0, -ECONNABORTED);
  2010. udc->ep0state = WAIT_FOR_SETUP;
  2011. return;
  2012. }
  2013. /* Is a buffer available? */
  2014. if (!(epstatus & EP_SEL_F)) {
  2015. /* Handle based on current state */
  2016. if (udc->ep0state == DATA_IN)
  2017. udc_ep0_in_req(udc);
  2018. else {
  2019. /* Unknown state for EP0 oe end of DATA IN phase */
  2020. nuke(ep0, -ECONNABORTED);
  2021. udc->ep0state = WAIT_FOR_SETUP;
  2022. }
  2023. }
  2024. }
  2025. /* OUT endpoint 0 transfer */
  2026. static void udc_handle_ep0_out(struct lpc32xx_udc *udc)
  2027. {
  2028. struct lpc32xx_ep *ep0 = &udc->ep[0];
  2029. u32 epstatus;
  2030. /* Clear EP interrupt */
  2031. epstatus = udc_clearep_getsts(udc, EP_OUT);
  2032. #ifdef CONFIG_USB_GADGET_DEBUG_FILES
  2033. ep0->totalints++;
  2034. #endif
  2035. /* Stalled? */
  2036. if (epstatus & EP_SEL_ST) {
  2037. udc_clrstall_hwep(udc, EP_OUT);
  2038. nuke(ep0, -ECONNABORTED);
  2039. udc->ep0state = WAIT_FOR_SETUP;
  2040. return;
  2041. }
  2042. /* A NAK may occur if a packet couldn't be received yet */
  2043. if (epstatus & EP_SEL_EPN)
  2044. return;
  2045. /* Setup packet incoming? */
  2046. if (epstatus & EP_SEL_STP) {
  2047. nuke(ep0, 0);
  2048. udc->ep0state = WAIT_FOR_SETUP;
  2049. }
  2050. /* Data available? */
  2051. if (epstatus & EP_SEL_F)
  2052. /* Handle based on current state */
  2053. switch (udc->ep0state) {
  2054. case WAIT_FOR_SETUP:
  2055. udc_handle_ep0_setup(udc);
  2056. break;
  2057. case DATA_OUT:
  2058. udc_ep0_out_req(udc);
  2059. break;
  2060. default:
  2061. /* Unknown state for EP0 */
  2062. nuke(ep0, -ECONNABORTED);
  2063. udc->ep0state = WAIT_FOR_SETUP;
  2064. }
  2065. }
  2066. /* Must be called without lock */
  2067. static int lpc32xx_get_frame(struct usb_gadget *gadget)
  2068. {
  2069. int frame;
  2070. unsigned long flags;
  2071. struct lpc32xx_udc *udc = to_udc(gadget);
  2072. if (!udc->clocked)
  2073. return -EINVAL;
  2074. spin_lock_irqsave(&udc->lock, flags);
  2075. frame = (int) udc_get_current_frame(udc);
  2076. spin_unlock_irqrestore(&udc->lock, flags);
  2077. return frame;
  2078. }
  2079. static int lpc32xx_wakeup(struct usb_gadget *gadget)
  2080. {
  2081. return -ENOTSUPP;
  2082. }
  2083. static int lpc32xx_set_selfpowered(struct usb_gadget *gadget, int is_on)
  2084. {
  2085. struct lpc32xx_udc *udc = to_udc(gadget);
  2086. /* Always self-powered */
  2087. udc->selfpowered = (is_on != 0);
  2088. return 0;
  2089. }
  2090. /*
  2091. * vbus is here! turn everything on that's ready
  2092. * Must be called without lock
  2093. */
  2094. static int lpc32xx_vbus_session(struct usb_gadget *gadget, int is_active)
  2095. {
  2096. unsigned long flags;
  2097. struct lpc32xx_udc *udc = to_udc(gadget);
  2098. spin_lock_irqsave(&udc->lock, flags);
  2099. /* Doesn't need lock */
  2100. if (udc->driver) {
  2101. udc_clk_set(udc, 1);
  2102. udc_enable(udc);
  2103. pullup(udc, is_active);
  2104. } else {
  2105. stop_activity(udc);
  2106. pullup(udc, 0);
  2107. spin_unlock_irqrestore(&udc->lock, flags);
  2108. /*
  2109. * Wait for all the endpoints to disable,
  2110. * before disabling clocks. Don't wait if
  2111. * endpoints are not enabled.
  2112. */
  2113. if (atomic_read(&udc->enabled_ep_cnt))
  2114. wait_event_interruptible(udc->ep_disable_wait_queue,
  2115. (atomic_read(&udc->enabled_ep_cnt) == 0));
  2116. spin_lock_irqsave(&udc->lock, flags);
  2117. udc_clk_set(udc, 0);
  2118. }
  2119. spin_unlock_irqrestore(&udc->lock, flags);
  2120. return 0;
  2121. }
  2122. /* Can be called with or without lock */
  2123. static int lpc32xx_pullup(struct usb_gadget *gadget, int is_on)
  2124. {
  2125. struct lpc32xx_udc *udc = to_udc(gadget);
  2126. /* Doesn't need lock */
  2127. pullup(udc, is_on);
  2128. return 0;
  2129. }
  2130. static int lpc32xx_start(struct usb_gadget *, struct usb_gadget_driver *);
  2131. static int lpc32xx_stop(struct usb_gadget *, struct usb_gadget_driver *);
  2132. static const struct usb_gadget_ops lpc32xx_udc_ops = {
  2133. .get_frame = lpc32xx_get_frame,
  2134. .wakeup = lpc32xx_wakeup,
  2135. .set_selfpowered = lpc32xx_set_selfpowered,
  2136. .vbus_session = lpc32xx_vbus_session,
  2137. .pullup = lpc32xx_pullup,
  2138. .udc_start = lpc32xx_start,
  2139. .udc_stop = lpc32xx_stop,
  2140. };
  2141. static void nop_release(struct device *dev)
  2142. {
  2143. /* nothing to free */
  2144. }
  2145. static const struct lpc32xx_udc controller_template = {
  2146. .gadget = {
  2147. .ops = &lpc32xx_udc_ops,
  2148. .name = driver_name,
  2149. .dev = {
  2150. .init_name = "gadget",
  2151. .release = nop_release,
  2152. }
  2153. },
  2154. .ep[0] = {
  2155. .ep = {
  2156. .name = "ep0",
  2157. .ops = &lpc32xx_ep_ops,
  2158. },
  2159. .maxpacket = 64,
  2160. .hwep_num_base = 0,
  2161. .hwep_num = 0, /* Can be 0 or 1, has special handling */
  2162. .lep = 0,
  2163. .eptype = EP_CTL_TYPE,
  2164. },
  2165. .ep[1] = {
  2166. .ep = {
  2167. .name = "ep1-int",
  2168. .ops = &lpc32xx_ep_ops,
  2169. },
  2170. .maxpacket = 64,
  2171. .hwep_num_base = 2,
  2172. .hwep_num = 0, /* 2 or 3, will be set later */
  2173. .lep = 1,
  2174. .eptype = EP_INT_TYPE,
  2175. },
  2176. .ep[2] = {
  2177. .ep = {
  2178. .name = "ep2-bulk",
  2179. .ops = &lpc32xx_ep_ops,
  2180. },
  2181. .maxpacket = 64,
  2182. .hwep_num_base = 4,
  2183. .hwep_num = 0, /* 4 or 5, will be set later */
  2184. .lep = 2,
  2185. .eptype = EP_BLK_TYPE,
  2186. },
  2187. .ep[3] = {
  2188. .ep = {
  2189. .name = "ep3-iso",
  2190. .ops = &lpc32xx_ep_ops,
  2191. },
  2192. .maxpacket = 1023,
  2193. .hwep_num_base = 6,
  2194. .hwep_num = 0, /* 6 or 7, will be set later */
  2195. .lep = 3,
  2196. .eptype = EP_ISO_TYPE,
  2197. },
  2198. .ep[4] = {
  2199. .ep = {
  2200. .name = "ep4-int",
  2201. .ops = &lpc32xx_ep_ops,
  2202. },
  2203. .maxpacket = 64,
  2204. .hwep_num_base = 8,
  2205. .hwep_num = 0, /* 8 or 9, will be set later */
  2206. .lep = 4,
  2207. .eptype = EP_INT_TYPE,
  2208. },
  2209. .ep[5] = {
  2210. .ep = {
  2211. .name = "ep5-bulk",
  2212. .ops = &lpc32xx_ep_ops,
  2213. },
  2214. .maxpacket = 64,
  2215. .hwep_num_base = 10,
  2216. .hwep_num = 0, /* 10 or 11, will be set later */
  2217. .lep = 5,
  2218. .eptype = EP_BLK_TYPE,
  2219. },
  2220. .ep[6] = {
  2221. .ep = {
  2222. .name = "ep6-iso",
  2223. .ops = &lpc32xx_ep_ops,
  2224. },
  2225. .maxpacket = 1023,
  2226. .hwep_num_base = 12,
  2227. .hwep_num = 0, /* 12 or 13, will be set later */
  2228. .lep = 6,
  2229. .eptype = EP_ISO_TYPE,
  2230. },
  2231. .ep[7] = {
  2232. .ep = {
  2233. .name = "ep7-int",
  2234. .ops = &lpc32xx_ep_ops,
  2235. },
  2236. .maxpacket = 64,
  2237. .hwep_num_base = 14,
  2238. .hwep_num = 0,
  2239. .lep = 7,
  2240. .eptype = EP_INT_TYPE,
  2241. },
  2242. .ep[8] = {
  2243. .ep = {
  2244. .name = "ep8-bulk",
  2245. .ops = &lpc32xx_ep_ops,
  2246. },
  2247. .maxpacket = 64,
  2248. .hwep_num_base = 16,
  2249. .hwep_num = 0,
  2250. .lep = 8,
  2251. .eptype = EP_BLK_TYPE,
  2252. },
  2253. .ep[9] = {
  2254. .ep = {
  2255. .name = "ep9-iso",
  2256. .ops = &lpc32xx_ep_ops,
  2257. },
  2258. .maxpacket = 1023,
  2259. .hwep_num_base = 18,
  2260. .hwep_num = 0,
  2261. .lep = 9,
  2262. .eptype = EP_ISO_TYPE,
  2263. },
  2264. .ep[10] = {
  2265. .ep = {
  2266. .name = "ep10-int",
  2267. .ops = &lpc32xx_ep_ops,
  2268. },
  2269. .maxpacket = 64,
  2270. .hwep_num_base = 20,
  2271. .hwep_num = 0,
  2272. .lep = 10,
  2273. .eptype = EP_INT_TYPE,
  2274. },
  2275. .ep[11] = {
  2276. .ep = {
  2277. .name = "ep11-bulk",
  2278. .ops = &lpc32xx_ep_ops,
  2279. },
  2280. .maxpacket = 64,
  2281. .hwep_num_base = 22,
  2282. .hwep_num = 0,
  2283. .lep = 11,
  2284. .eptype = EP_BLK_TYPE,
  2285. },
  2286. .ep[12] = {
  2287. .ep = {
  2288. .name = "ep12-iso",
  2289. .ops = &lpc32xx_ep_ops,
  2290. },
  2291. .maxpacket = 1023,
  2292. .hwep_num_base = 24,
  2293. .hwep_num = 0,
  2294. .lep = 12,
  2295. .eptype = EP_ISO_TYPE,
  2296. },
  2297. .ep[13] = {
  2298. .ep = {
  2299. .name = "ep13-int",
  2300. .ops = &lpc32xx_ep_ops,
  2301. },
  2302. .maxpacket = 64,
  2303. .hwep_num_base = 26,
  2304. .hwep_num = 0,
  2305. .lep = 13,
  2306. .eptype = EP_INT_TYPE,
  2307. },
  2308. .ep[14] = {
  2309. .ep = {
  2310. .name = "ep14-bulk",
  2311. .ops = &lpc32xx_ep_ops,
  2312. },
  2313. .maxpacket = 64,
  2314. .hwep_num_base = 28,
  2315. .hwep_num = 0,
  2316. .lep = 14,
  2317. .eptype = EP_BLK_TYPE,
  2318. },
  2319. .ep[15] = {
  2320. .ep = {
  2321. .name = "ep15-bulk",
  2322. .ops = &lpc32xx_ep_ops,
  2323. },
  2324. .maxpacket = 1023,
  2325. .hwep_num_base = 30,
  2326. .hwep_num = 0,
  2327. .lep = 15,
  2328. .eptype = EP_BLK_TYPE,
  2329. },
  2330. };
  2331. /* ISO and status interrupts */
  2332. static irqreturn_t lpc32xx_usb_lp_irq(int irq, void *_udc)
  2333. {
  2334. u32 tmp, devstat;
  2335. struct lpc32xx_udc *udc = _udc;
  2336. spin_lock(&udc->lock);
  2337. /* Read the device status register */
  2338. devstat = readl(USBD_DEVINTST(udc->udp_baseaddr));
  2339. devstat &= ~USBD_EP_FAST;
  2340. writel(devstat, USBD_DEVINTCLR(udc->udp_baseaddr));
  2341. devstat = devstat & udc->enabled_devints;
  2342. /* Device specific handling needed? */
  2343. if (devstat & USBD_DEV_STAT)
  2344. udc_handle_dev(udc);
  2345. /* Start of frame? (devstat & FRAME_INT):
  2346. * The frame interrupt isn't really needed for ISO support,
  2347. * as the driver will queue the necessary packets */
  2348. /* Error? */
  2349. if (devstat & ERR_INT) {
  2350. /* All types of errors, from cable removal during transfer to
  2351. * misc protocol and bit errors. These are mostly for just info,
  2352. * as the USB hardware will work around these. If these errors
  2353. * happen alot, something is wrong. */
  2354. udc_protocol_cmd_w(udc, CMD_RD_ERR_STAT);
  2355. tmp = udc_protocol_cmd_r(udc, DAT_RD_ERR_STAT);
  2356. dev_dbg(udc->dev, "Device error (0x%x)!\n", tmp);
  2357. }
  2358. spin_unlock(&udc->lock);
  2359. return IRQ_HANDLED;
  2360. }
  2361. /* EP interrupts */
  2362. static irqreturn_t lpc32xx_usb_hp_irq(int irq, void *_udc)
  2363. {
  2364. u32 tmp;
  2365. struct lpc32xx_udc *udc = _udc;
  2366. spin_lock(&udc->lock);
  2367. /* Read the device status register */
  2368. writel(USBD_EP_FAST, USBD_DEVINTCLR(udc->udp_baseaddr));
  2369. /* Endpoints */
  2370. tmp = readl(USBD_EPINTST(udc->udp_baseaddr));
  2371. /* Special handling for EP0 */
  2372. if (tmp & (EP_MASK_SEL(0, EP_OUT) | EP_MASK_SEL(0, EP_IN))) {
  2373. /* Handle EP0 IN */
  2374. if (tmp & (EP_MASK_SEL(0, EP_IN)))
  2375. udc_handle_ep0_in(udc);
  2376. /* Handle EP0 OUT */
  2377. if (tmp & (EP_MASK_SEL(0, EP_OUT)))
  2378. udc_handle_ep0_out(udc);
  2379. }
  2380. /* All other EPs */
  2381. if (tmp & ~(EP_MASK_SEL(0, EP_OUT) | EP_MASK_SEL(0, EP_IN))) {
  2382. int i;
  2383. /* Handle other EP interrupts */
  2384. for (i = 1; i < NUM_ENDPOINTS; i++) {
  2385. if (tmp & (1 << udc->ep[i].hwep_num))
  2386. udc_handle_eps(udc, &udc->ep[i]);
  2387. }
  2388. }
  2389. spin_unlock(&udc->lock);
  2390. return IRQ_HANDLED;
  2391. }
  2392. static irqreturn_t lpc32xx_usb_devdma_irq(int irq, void *_udc)
  2393. {
  2394. struct lpc32xx_udc *udc = _udc;
  2395. int i;
  2396. u32 tmp;
  2397. spin_lock(&udc->lock);
  2398. /* Handle EP DMA EOT interrupts */
  2399. tmp = readl(USBD_EOTINTST(udc->udp_baseaddr)) |
  2400. (readl(USBD_EPDMAST(udc->udp_baseaddr)) &
  2401. readl(USBD_NDDRTINTST(udc->udp_baseaddr))) |
  2402. readl(USBD_SYSERRTINTST(udc->udp_baseaddr));
  2403. for (i = 1; i < NUM_ENDPOINTS; i++) {
  2404. if (tmp & (1 << udc->ep[i].hwep_num))
  2405. udc_handle_dma_ep(udc, &udc->ep[i]);
  2406. }
  2407. spin_unlock(&udc->lock);
  2408. return IRQ_HANDLED;
  2409. }
  2410. /*
  2411. *
  2412. * VBUS detection, pullup handler, and Gadget cable state notification
  2413. *
  2414. */
  2415. static void vbus_work(struct work_struct *work)
  2416. {
  2417. u8 value;
  2418. struct lpc32xx_udc *udc = container_of(work, struct lpc32xx_udc,
  2419. vbus_job);
  2420. if (udc->enabled != 0) {
  2421. /* Discharge VBUS real quick */
  2422. i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
  2423. ISP1301_I2C_OTG_CONTROL_1, OTG1_VBUS_DISCHRG);
  2424. /* Give VBUS some time (100mS) to discharge */
  2425. msleep(100);
  2426. /* Disable VBUS discharge resistor */
  2427. i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
  2428. ISP1301_I2C_OTG_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR,
  2429. OTG1_VBUS_DISCHRG);
  2430. /* Clear interrupt */
  2431. i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
  2432. ISP1301_I2C_INTERRUPT_LATCH |
  2433. ISP1301_I2C_REG_CLEAR_ADDR, ~0);
  2434. /* Get the VBUS status from the transceiver */
  2435. value = i2c_smbus_read_byte_data(udc->isp1301_i2c_client,
  2436. ISP1301_I2C_INTERRUPT_SOURCE);
  2437. /* VBUS on or off? */
  2438. if (value & INT_SESS_VLD)
  2439. udc->vbus = 1;
  2440. else
  2441. udc->vbus = 0;
  2442. /* VBUS changed? */
  2443. if (udc->last_vbus != udc->vbus) {
  2444. udc->last_vbus = udc->vbus;
  2445. lpc32xx_vbus_session(&udc->gadget, udc->vbus);
  2446. }
  2447. }
  2448. /* Re-enable after completion */
  2449. enable_irq(udc->udp_irq[IRQ_USB_ATX]);
  2450. }
  2451. static irqreturn_t lpc32xx_usb_vbus_irq(int irq, void *_udc)
  2452. {
  2453. struct lpc32xx_udc *udc = _udc;
  2454. /* Defer handling of VBUS IRQ to work queue */
  2455. disable_irq_nosync(udc->udp_irq[IRQ_USB_ATX]);
  2456. schedule_work(&udc->vbus_job);
  2457. return IRQ_HANDLED;
  2458. }
  2459. static int lpc32xx_start(struct usb_gadget *gadget,
  2460. struct usb_gadget_driver *driver)
  2461. {
  2462. struct lpc32xx_udc *udc = to_udc(gadget);
  2463. int i;
  2464. if (!driver || driver->max_speed < USB_SPEED_FULL || !driver->setup) {
  2465. dev_err(udc->dev, "bad parameter.\n");
  2466. return -EINVAL;
  2467. }
  2468. if (udc->driver) {
  2469. dev_err(udc->dev, "UDC already has a gadget driver\n");
  2470. return -EBUSY;
  2471. }
  2472. udc->driver = driver;
  2473. udc->gadget.dev.of_node = udc->dev->of_node;
  2474. udc->enabled = 1;
  2475. udc->selfpowered = 1;
  2476. udc->vbus = 0;
  2477. /* Force VBUS process once to check for cable insertion */
  2478. udc->last_vbus = udc->vbus = 0;
  2479. schedule_work(&udc->vbus_job);
  2480. /* Do not re-enable ATX IRQ (3) */
  2481. for (i = IRQ_USB_LP; i < IRQ_USB_ATX; i++)
  2482. enable_irq(udc->udp_irq[i]);
  2483. return 0;
  2484. }
  2485. static int lpc32xx_stop(struct usb_gadget *gadget,
  2486. struct usb_gadget_driver *driver)
  2487. {
  2488. int i;
  2489. struct lpc32xx_udc *udc = to_udc(gadget);
  2490. if (!driver || driver != udc->driver)
  2491. return -EINVAL;
  2492. for (i = IRQ_USB_LP; i <= IRQ_USB_ATX; i++)
  2493. disable_irq(udc->udp_irq[i]);
  2494. if (udc->clocked) {
  2495. spin_lock(&udc->lock);
  2496. stop_activity(udc);
  2497. spin_unlock(&udc->lock);
  2498. /*
  2499. * Wait for all the endpoints to disable,
  2500. * before disabling clocks. Don't wait if
  2501. * endpoints are not enabled.
  2502. */
  2503. if (atomic_read(&udc->enabled_ep_cnt))
  2504. wait_event_interruptible(udc->ep_disable_wait_queue,
  2505. (atomic_read(&udc->enabled_ep_cnt) == 0));
  2506. spin_lock(&udc->lock);
  2507. udc_clk_set(udc, 0);
  2508. spin_unlock(&udc->lock);
  2509. }
  2510. udc->enabled = 0;
  2511. udc->driver = NULL;
  2512. return 0;
  2513. }
  2514. static void lpc32xx_udc_shutdown(struct platform_device *dev)
  2515. {
  2516. /* Force disconnect on reboot */
  2517. struct lpc32xx_udc *udc = platform_get_drvdata(dev);
  2518. pullup(udc, 0);
  2519. }
  2520. /*
  2521. * Callbacks to be overridden by options passed via OF (TODO)
  2522. */
  2523. static void lpc32xx_usbd_conn_chg(int conn)
  2524. {
  2525. /* Do nothing, it might be nice to enable an LED
  2526. * based on conn state being !0 */
  2527. }
  2528. static void lpc32xx_usbd_susp_chg(int susp)
  2529. {
  2530. /* Device suspend if susp != 0 */
  2531. }
  2532. static void lpc32xx_rmwkup_chg(int remote_wakup_enable)
  2533. {
  2534. /* Enable or disable USB remote wakeup */
  2535. }
  2536. struct lpc32xx_usbd_cfg lpc32xx_usbddata = {
  2537. .vbus_drv_pol = 0,
  2538. .conn_chgb = &lpc32xx_usbd_conn_chg,
  2539. .susp_chgb = &lpc32xx_usbd_susp_chg,
  2540. .rmwk_chgb = &lpc32xx_rmwkup_chg,
  2541. };
  2542. static u64 lpc32xx_usbd_dmamask = ~(u32) 0x7F;
  2543. static int lpc32xx_udc_probe(struct platform_device *pdev)
  2544. {
  2545. struct device *dev = &pdev->dev;
  2546. struct lpc32xx_udc *udc;
  2547. int retval, i;
  2548. struct resource *res;
  2549. dma_addr_t dma_handle;
  2550. struct device_node *isp1301_node;
  2551. udc = kmemdup(&controller_template, sizeof(*udc), GFP_KERNEL);
  2552. if (!udc)
  2553. return -ENOMEM;
  2554. for (i = 0; i <= 15; i++)
  2555. udc->ep[i].udc = udc;
  2556. udc->gadget.ep0 = &udc->ep[0].ep;
  2557. /* init software state */
  2558. udc->gadget.dev.parent = dev;
  2559. udc->pdev = pdev;
  2560. udc->dev = &pdev->dev;
  2561. udc->enabled = 0;
  2562. if (pdev->dev.of_node) {
  2563. isp1301_node = of_parse_phandle(pdev->dev.of_node,
  2564. "transceiver", 0);
  2565. } else {
  2566. isp1301_node = NULL;
  2567. }
  2568. udc->isp1301_i2c_client = isp1301_get_client(isp1301_node);
  2569. if (!udc->isp1301_i2c_client) {
  2570. retval = -EPROBE_DEFER;
  2571. goto phy_fail;
  2572. }
  2573. dev_info(udc->dev, "ISP1301 I2C device at address 0x%x\n",
  2574. udc->isp1301_i2c_client->addr);
  2575. pdev->dev.dma_mask = &lpc32xx_usbd_dmamask;
  2576. retval = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
  2577. if (retval)
  2578. goto resource_fail;
  2579. udc->board = &lpc32xx_usbddata;
  2580. /*
  2581. * Resources are mapped as follows:
  2582. * IORESOURCE_MEM, base address and size of USB space
  2583. * IORESOURCE_IRQ, USB device low priority interrupt number
  2584. * IORESOURCE_IRQ, USB device high priority interrupt number
  2585. * IORESOURCE_IRQ, USB device interrupt number
  2586. * IORESOURCE_IRQ, USB transceiver interrupt number
  2587. */
  2588. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  2589. if (!res) {
  2590. retval = -ENXIO;
  2591. goto resource_fail;
  2592. }
  2593. spin_lock_init(&udc->lock);
  2594. /* Get IRQs */
  2595. for (i = 0; i < 4; i++) {
  2596. udc->udp_irq[i] = platform_get_irq(pdev, i);
  2597. if (udc->udp_irq[i] < 0) {
  2598. dev_err(udc->dev,
  2599. "irq resource %d not available!\n", i);
  2600. retval = udc->udp_irq[i];
  2601. goto irq_fail;
  2602. }
  2603. }
  2604. udc->io_p_start = res->start;
  2605. udc->io_p_size = resource_size(res);
  2606. if (!request_mem_region(udc->io_p_start, udc->io_p_size, driver_name)) {
  2607. dev_err(udc->dev, "someone's using UDC memory\n");
  2608. retval = -EBUSY;
  2609. goto request_mem_region_fail;
  2610. }
  2611. udc->udp_baseaddr = ioremap(udc->io_p_start, udc->io_p_size);
  2612. if (!udc->udp_baseaddr) {
  2613. retval = -ENOMEM;
  2614. dev_err(udc->dev, "IO map failure\n");
  2615. goto io_map_fail;
  2616. }
  2617. /* Enable AHB slave USB clock, needed for further USB clock control */
  2618. writel(USB_SLAVE_HCLK_EN | (1 << 19), USB_CTRL);
  2619. /* Get required clocks */
  2620. udc->usb_pll_clk = clk_get(&pdev->dev, "ck_pll5");
  2621. if (IS_ERR(udc->usb_pll_clk)) {
  2622. dev_err(udc->dev, "failed to acquire USB PLL\n");
  2623. retval = PTR_ERR(udc->usb_pll_clk);
  2624. goto pll_get_fail;
  2625. }
  2626. udc->usb_slv_clk = clk_get(&pdev->dev, "ck_usbd");
  2627. if (IS_ERR(udc->usb_slv_clk)) {
  2628. dev_err(udc->dev, "failed to acquire USB device clock\n");
  2629. retval = PTR_ERR(udc->usb_slv_clk);
  2630. goto usb_clk_get_fail;
  2631. }
  2632. udc->usb_otg_clk = clk_get(&pdev->dev, "ck_usb_otg");
  2633. if (IS_ERR(udc->usb_otg_clk)) {
  2634. dev_err(udc->dev, "failed to acquire USB otg clock\n");
  2635. retval = PTR_ERR(udc->usb_otg_clk);
  2636. goto usb_otg_clk_get_fail;
  2637. }
  2638. /* Setup PLL clock to 48MHz */
  2639. retval = clk_enable(udc->usb_pll_clk);
  2640. if (retval < 0) {
  2641. dev_err(udc->dev, "failed to start USB PLL\n");
  2642. goto pll_enable_fail;
  2643. }
  2644. retval = clk_set_rate(udc->usb_pll_clk, 48000);
  2645. if (retval < 0) {
  2646. dev_err(udc->dev, "failed to set USB clock rate\n");
  2647. goto pll_set_fail;
  2648. }
  2649. writel(readl(USB_CTRL) | USB_DEV_NEED_CLK_EN, USB_CTRL);
  2650. /* Enable USB device clock */
  2651. retval = clk_enable(udc->usb_slv_clk);
  2652. if (retval < 0) {
  2653. dev_err(udc->dev, "failed to start USB device clock\n");
  2654. goto usb_clk_enable_fail;
  2655. }
  2656. /* Enable USB OTG clock */
  2657. retval = clk_enable(udc->usb_otg_clk);
  2658. if (retval < 0) {
  2659. dev_err(udc->dev, "failed to start USB otg clock\n");
  2660. goto usb_otg_clk_enable_fail;
  2661. }
  2662. /* Setup deferred workqueue data */
  2663. udc->poweron = udc->pullup = 0;
  2664. INIT_WORK(&udc->pullup_job, pullup_work);
  2665. INIT_WORK(&udc->vbus_job, vbus_work);
  2666. #ifdef CONFIG_PM
  2667. INIT_WORK(&udc->power_job, power_work);
  2668. #endif
  2669. /* All clocks are now on */
  2670. udc->clocked = 1;
  2671. isp1301_udc_configure(udc);
  2672. /* Allocate memory for the UDCA */
  2673. udc->udca_v_base = dma_alloc_coherent(&pdev->dev, UDCA_BUFF_SIZE,
  2674. &dma_handle,
  2675. (GFP_KERNEL | GFP_DMA));
  2676. if (!udc->udca_v_base) {
  2677. dev_err(udc->dev, "error getting UDCA region\n");
  2678. retval = -ENOMEM;
  2679. goto i2c_fail;
  2680. }
  2681. udc->udca_p_base = dma_handle;
  2682. dev_dbg(udc->dev, "DMA buffer(0x%x bytes), P:0x%08x, V:0x%p\n",
  2683. UDCA_BUFF_SIZE, udc->udca_p_base, udc->udca_v_base);
  2684. /* Setup the DD DMA memory pool */
  2685. udc->dd_cache = dma_pool_create("udc_dd", udc->dev,
  2686. sizeof(struct lpc32xx_usbd_dd_gad),
  2687. sizeof(u32), 0);
  2688. if (!udc->dd_cache) {
  2689. dev_err(udc->dev, "error getting DD DMA region\n");
  2690. retval = -ENOMEM;
  2691. goto dma_alloc_fail;
  2692. }
  2693. /* Clear USB peripheral and initialize gadget endpoints */
  2694. udc_disable(udc);
  2695. udc_reinit(udc);
  2696. /* Request IRQs - low and high priority USB device IRQs are routed to
  2697. * the same handler, while the DMA interrupt is routed elsewhere */
  2698. retval = request_irq(udc->udp_irq[IRQ_USB_LP], lpc32xx_usb_lp_irq,
  2699. 0, "udc_lp", udc);
  2700. if (retval < 0) {
  2701. dev_err(udc->dev, "LP request irq %d failed\n",
  2702. udc->udp_irq[IRQ_USB_LP]);
  2703. goto irq_lp_fail;
  2704. }
  2705. retval = request_irq(udc->udp_irq[IRQ_USB_HP], lpc32xx_usb_hp_irq,
  2706. 0, "udc_hp", udc);
  2707. if (retval < 0) {
  2708. dev_err(udc->dev, "HP request irq %d failed\n",
  2709. udc->udp_irq[IRQ_USB_HP]);
  2710. goto irq_hp_fail;
  2711. }
  2712. retval = request_irq(udc->udp_irq[IRQ_USB_DEVDMA],
  2713. lpc32xx_usb_devdma_irq, 0, "udc_dma", udc);
  2714. if (retval < 0) {
  2715. dev_err(udc->dev, "DEV request irq %d failed\n",
  2716. udc->udp_irq[IRQ_USB_DEVDMA]);
  2717. goto irq_dev_fail;
  2718. }
  2719. /* The transceiver interrupt is used for VBUS detection and will
  2720. kick off the VBUS handler function */
  2721. retval = request_irq(udc->udp_irq[IRQ_USB_ATX], lpc32xx_usb_vbus_irq,
  2722. 0, "udc_otg", udc);
  2723. if (retval < 0) {
  2724. dev_err(udc->dev, "VBUS request irq %d failed\n",
  2725. udc->udp_irq[IRQ_USB_ATX]);
  2726. goto irq_xcvr_fail;
  2727. }
  2728. /* Initialize wait queue */
  2729. init_waitqueue_head(&udc->ep_disable_wait_queue);
  2730. atomic_set(&udc->enabled_ep_cnt, 0);
  2731. /* Keep all IRQs disabled until GadgetFS starts up */
  2732. for (i = IRQ_USB_LP; i <= IRQ_USB_ATX; i++)
  2733. disable_irq(udc->udp_irq[i]);
  2734. retval = usb_add_gadget_udc(dev, &udc->gadget);
  2735. if (retval < 0)
  2736. goto add_gadget_fail;
  2737. dev_set_drvdata(dev, udc);
  2738. device_init_wakeup(dev, 1);
  2739. create_debug_file(udc);
  2740. /* Disable clocks for now */
  2741. udc_clk_set(udc, 0);
  2742. dev_info(udc->dev, "%s version %s\n", driver_name, DRIVER_VERSION);
  2743. return 0;
  2744. add_gadget_fail:
  2745. free_irq(udc->udp_irq[IRQ_USB_ATX], udc);
  2746. irq_xcvr_fail:
  2747. free_irq(udc->udp_irq[IRQ_USB_DEVDMA], udc);
  2748. irq_dev_fail:
  2749. free_irq(udc->udp_irq[IRQ_USB_HP], udc);
  2750. irq_hp_fail:
  2751. free_irq(udc->udp_irq[IRQ_USB_LP], udc);
  2752. irq_lp_fail:
  2753. dma_pool_destroy(udc->dd_cache);
  2754. dma_alloc_fail:
  2755. dma_free_coherent(&pdev->dev, UDCA_BUFF_SIZE,
  2756. udc->udca_v_base, udc->udca_p_base);
  2757. i2c_fail:
  2758. clk_disable(udc->usb_otg_clk);
  2759. usb_otg_clk_enable_fail:
  2760. clk_disable(udc->usb_slv_clk);
  2761. usb_clk_enable_fail:
  2762. pll_set_fail:
  2763. clk_disable(udc->usb_pll_clk);
  2764. pll_enable_fail:
  2765. clk_put(udc->usb_otg_clk);
  2766. usb_otg_clk_get_fail:
  2767. clk_put(udc->usb_slv_clk);
  2768. usb_clk_get_fail:
  2769. clk_put(udc->usb_pll_clk);
  2770. pll_get_fail:
  2771. iounmap(udc->udp_baseaddr);
  2772. io_map_fail:
  2773. release_mem_region(udc->io_p_start, udc->io_p_size);
  2774. dev_err(udc->dev, "%s probe failed, %d\n", driver_name, retval);
  2775. request_mem_region_fail:
  2776. irq_fail:
  2777. resource_fail:
  2778. phy_fail:
  2779. kfree(udc);
  2780. return retval;
  2781. }
  2782. static int lpc32xx_udc_remove(struct platform_device *pdev)
  2783. {
  2784. struct lpc32xx_udc *udc = platform_get_drvdata(pdev);
  2785. usb_del_gadget_udc(&udc->gadget);
  2786. if (udc->driver)
  2787. return -EBUSY;
  2788. udc_clk_set(udc, 1);
  2789. udc_disable(udc);
  2790. pullup(udc, 0);
  2791. free_irq(udc->udp_irq[IRQ_USB_ATX], udc);
  2792. device_init_wakeup(&pdev->dev, 0);
  2793. remove_debug_file(udc);
  2794. dma_pool_destroy(udc->dd_cache);
  2795. dma_free_coherent(&pdev->dev, UDCA_BUFF_SIZE,
  2796. udc->udca_v_base, udc->udca_p_base);
  2797. free_irq(udc->udp_irq[IRQ_USB_DEVDMA], udc);
  2798. free_irq(udc->udp_irq[IRQ_USB_HP], udc);
  2799. free_irq(udc->udp_irq[IRQ_USB_LP], udc);
  2800. clk_disable(udc->usb_otg_clk);
  2801. clk_put(udc->usb_otg_clk);
  2802. clk_disable(udc->usb_slv_clk);
  2803. clk_put(udc->usb_slv_clk);
  2804. clk_disable(udc->usb_pll_clk);
  2805. clk_put(udc->usb_pll_clk);
  2806. iounmap(udc->udp_baseaddr);
  2807. release_mem_region(udc->io_p_start, udc->io_p_size);
  2808. kfree(udc);
  2809. return 0;
  2810. }
  2811. #ifdef CONFIG_PM
  2812. static int lpc32xx_udc_suspend(struct platform_device *pdev, pm_message_t mesg)
  2813. {
  2814. struct lpc32xx_udc *udc = platform_get_drvdata(pdev);
  2815. if (udc->clocked) {
  2816. /* Power down ISP */
  2817. udc->poweron = 0;
  2818. isp1301_set_powerstate(udc, 0);
  2819. /* Disable clocking */
  2820. udc_clk_set(udc, 0);
  2821. /* Keep clock flag on, so we know to re-enable clocks
  2822. on resume */
  2823. udc->clocked = 1;
  2824. /* Kill global USB clock */
  2825. clk_disable(udc->usb_slv_clk);
  2826. }
  2827. return 0;
  2828. }
  2829. static int lpc32xx_udc_resume(struct platform_device *pdev)
  2830. {
  2831. struct lpc32xx_udc *udc = platform_get_drvdata(pdev);
  2832. if (udc->clocked) {
  2833. /* Enable global USB clock */
  2834. clk_enable(udc->usb_slv_clk);
  2835. /* Enable clocking */
  2836. udc_clk_set(udc, 1);
  2837. /* ISP back to normal power mode */
  2838. udc->poweron = 1;
  2839. isp1301_set_powerstate(udc, 1);
  2840. }
  2841. return 0;
  2842. }
  2843. #else
  2844. #define lpc32xx_udc_suspend NULL
  2845. #define lpc32xx_udc_resume NULL
  2846. #endif
  2847. #ifdef CONFIG_OF
  2848. static const struct of_device_id lpc32xx_udc_of_match[] = {
  2849. { .compatible = "nxp,lpc3220-udc", },
  2850. { },
  2851. };
  2852. MODULE_DEVICE_TABLE(of, lpc32xx_udc_of_match);
  2853. #endif
  2854. static struct platform_driver lpc32xx_udc_driver = {
  2855. .remove = lpc32xx_udc_remove,
  2856. .shutdown = lpc32xx_udc_shutdown,
  2857. .suspend = lpc32xx_udc_suspend,
  2858. .resume = lpc32xx_udc_resume,
  2859. .driver = {
  2860. .name = (char *) driver_name,
  2861. .owner = THIS_MODULE,
  2862. .of_match_table = of_match_ptr(lpc32xx_udc_of_match),
  2863. },
  2864. };
  2865. module_platform_driver_probe(lpc32xx_udc_driver, lpc32xx_udc_probe);
  2866. MODULE_DESCRIPTION("LPC32XX udc driver");
  2867. MODULE_AUTHOR("Kevin Wells <kevin.wells@nxp.com>");
  2868. MODULE_AUTHOR("Roland Stigge <stigge@antcom.de>");
  2869. MODULE_LICENSE("GPL");
  2870. MODULE_ALIAS("platform:lpc32xx_udc");