rtc-ds1307.c 33 KB

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  1. /*
  2. * rtc-ds1307.c - RTC driver for some mostly-compatible I2C chips.
  3. *
  4. * Copyright (C) 2005 James Chapman (ds1337 core)
  5. * Copyright (C) 2006 David Brownell
  6. * Copyright (C) 2009 Matthias Fuchs (rx8025 support)
  7. * Copyright (C) 2012 Bertrand Achard (nvram access fixes)
  8. *
  9. * This program is free software; you can redistribute it and/or modify
  10. * it under the terms of the GNU General Public License version 2 as
  11. * published by the Free Software Foundation.
  12. */
  13. #include <linux/module.h>
  14. #include <linux/init.h>
  15. #include <linux/slab.h>
  16. #include <linux/i2c.h>
  17. #include <linux/string.h>
  18. #include <linux/rtc.h>
  19. #include <linux/bcd.h>
  20. #include <linux/rtc/ds1307.h>
  21. /*
  22. * We can't determine type by probing, but if we expect pre-Linux code
  23. * to have set the chip up as a clock (turning on the oscillator and
  24. * setting the date and time), Linux can ignore the non-clock features.
  25. * That's a natural job for a factory or repair bench.
  26. */
  27. enum ds_type {
  28. ds_1307,
  29. ds_1337,
  30. ds_1338,
  31. ds_1339,
  32. ds_1340,
  33. ds_1388,
  34. ds_3231,
  35. m41t00,
  36. mcp7941x,
  37. rx_8025,
  38. last_ds_type /* always last */
  39. /* rs5c372 too? different address... */
  40. };
  41. /* RTC registers don't differ much, except for the century flag */
  42. #define DS1307_REG_SECS 0x00 /* 00-59 */
  43. # define DS1307_BIT_CH 0x80
  44. # define DS1340_BIT_nEOSC 0x80
  45. # define MCP7941X_BIT_ST 0x80
  46. #define DS1307_REG_MIN 0x01 /* 00-59 */
  47. #define DS1307_REG_HOUR 0x02 /* 00-23, or 1-12{am,pm} */
  48. # define DS1307_BIT_12HR 0x40 /* in REG_HOUR */
  49. # define DS1307_BIT_PM 0x20 /* in REG_HOUR */
  50. # define DS1340_BIT_CENTURY_EN 0x80 /* in REG_HOUR */
  51. # define DS1340_BIT_CENTURY 0x40 /* in REG_HOUR */
  52. #define DS1307_REG_WDAY 0x03 /* 01-07 */
  53. # define MCP7941X_BIT_VBATEN 0x08
  54. #define DS1307_REG_MDAY 0x04 /* 01-31 */
  55. #define DS1307_REG_MONTH 0x05 /* 01-12 */
  56. # define DS1337_BIT_CENTURY 0x80 /* in REG_MONTH */
  57. #define DS1307_REG_YEAR 0x06 /* 00-99 */
  58. /*
  59. * Other registers (control, status, alarms, trickle charge, NVRAM, etc)
  60. * start at 7, and they differ a LOT. Only control and status matter for
  61. * basic RTC date and time functionality; be careful using them.
  62. */
  63. #define DS1307_REG_CONTROL 0x07 /* or ds1338 */
  64. # define DS1307_BIT_OUT 0x80
  65. # define DS1338_BIT_OSF 0x20
  66. # define DS1307_BIT_SQWE 0x10
  67. # define DS1307_BIT_RS1 0x02
  68. # define DS1307_BIT_RS0 0x01
  69. #define DS1337_REG_CONTROL 0x0e
  70. # define DS1337_BIT_nEOSC 0x80
  71. # define DS1339_BIT_BBSQI 0x20
  72. # define DS3231_BIT_BBSQW 0x40 /* same as BBSQI */
  73. # define DS1337_BIT_RS2 0x10
  74. # define DS1337_BIT_RS1 0x08
  75. # define DS1337_BIT_INTCN 0x04
  76. # define DS1337_BIT_A2IE 0x02
  77. # define DS1337_BIT_A1IE 0x01
  78. #define DS1340_REG_CONTROL 0x07
  79. # define DS1340_BIT_OUT 0x80
  80. # define DS1340_BIT_FT 0x40
  81. # define DS1340_BIT_CALIB_SIGN 0x20
  82. # define DS1340_M_CALIBRATION 0x1f
  83. #define DS1340_REG_FLAG 0x09
  84. # define DS1340_BIT_OSF 0x80
  85. #define DS1337_REG_STATUS 0x0f
  86. # define DS1337_BIT_OSF 0x80
  87. # define DS1337_BIT_A2I 0x02
  88. # define DS1337_BIT_A1I 0x01
  89. #define DS1339_REG_ALARM1_SECS 0x07
  90. #define DS13XX_TRICKLE_CHARGER_MAGIC 0xa0
  91. #define RX8025_REG_CTRL1 0x0e
  92. # define RX8025_BIT_2412 0x20
  93. #define RX8025_REG_CTRL2 0x0f
  94. # define RX8025_BIT_PON 0x10
  95. # define RX8025_BIT_VDET 0x40
  96. # define RX8025_BIT_XST 0x20
  97. struct ds1307 {
  98. u8 offset; /* register's offset */
  99. u8 regs[11];
  100. u16 nvram_offset;
  101. struct bin_attribute *nvram;
  102. enum ds_type type;
  103. unsigned long flags;
  104. #define HAS_NVRAM 0 /* bit 0 == sysfs file active */
  105. #define HAS_ALARM 1 /* bit 1 == irq claimed */
  106. struct i2c_client *client;
  107. struct rtc_device *rtc;
  108. struct work_struct work;
  109. s32 (*read_block_data)(const struct i2c_client *client, u8 command,
  110. u8 length, u8 *values);
  111. s32 (*write_block_data)(const struct i2c_client *client, u8 command,
  112. u8 length, const u8 *values);
  113. };
  114. struct chip_desc {
  115. unsigned alarm:1;
  116. u16 nvram_offset;
  117. u16 nvram_size;
  118. u16 trickle_charger_reg;
  119. u8 trickle_charger_setup;
  120. u8 (*do_trickle_setup)(struct i2c_client *, uint32_t, bool);
  121. };
  122. static u8 do_trickle_setup_ds1339(struct i2c_client *,
  123. uint32_t ohms, bool diode);
  124. static struct chip_desc chips[last_ds_type] = {
  125. [ds_1307] = {
  126. .nvram_offset = 8,
  127. .nvram_size = 56,
  128. },
  129. [ds_1337] = {
  130. .alarm = 1,
  131. },
  132. [ds_1338] = {
  133. .nvram_offset = 8,
  134. .nvram_size = 56,
  135. },
  136. [ds_1339] = {
  137. .alarm = 1,
  138. .trickle_charger_reg = 0x10,
  139. .do_trickle_setup = &do_trickle_setup_ds1339,
  140. },
  141. [ds_1340] = {
  142. .trickle_charger_reg = 0x08,
  143. },
  144. [ds_1388] = {
  145. .trickle_charger_reg = 0x0a,
  146. },
  147. [ds_3231] = {
  148. .alarm = 1,
  149. },
  150. [mcp7941x] = {
  151. .alarm = 1,
  152. /* this is battery backed SRAM */
  153. .nvram_offset = 0x20,
  154. .nvram_size = 0x40,
  155. },
  156. };
  157. static const struct i2c_device_id ds1307_id[] = {
  158. { "ds1307", ds_1307 },
  159. { "ds1337", ds_1337 },
  160. { "ds1338", ds_1338 },
  161. { "ds1339", ds_1339 },
  162. { "ds1388", ds_1388 },
  163. { "ds1340", ds_1340 },
  164. { "ds3231", ds_3231 },
  165. { "m41t00", m41t00 },
  166. { "mcp7941x", mcp7941x },
  167. { "pt7c4338", ds_1307 },
  168. { "rx8025", rx_8025 },
  169. { }
  170. };
  171. MODULE_DEVICE_TABLE(i2c, ds1307_id);
  172. /*----------------------------------------------------------------------*/
  173. #define BLOCK_DATA_MAX_TRIES 10
  174. static s32 ds1307_read_block_data_once(const struct i2c_client *client,
  175. u8 command, u8 length, u8 *values)
  176. {
  177. s32 i, data;
  178. for (i = 0; i < length; i++) {
  179. data = i2c_smbus_read_byte_data(client, command + i);
  180. if (data < 0)
  181. return data;
  182. values[i] = data;
  183. }
  184. return i;
  185. }
  186. static s32 ds1307_read_block_data(const struct i2c_client *client, u8 command,
  187. u8 length, u8 *values)
  188. {
  189. u8 oldvalues[255];
  190. s32 ret;
  191. int tries = 0;
  192. dev_dbg(&client->dev, "ds1307_read_block_data (length=%d)\n", length);
  193. ret = ds1307_read_block_data_once(client, command, length, values);
  194. if (ret < 0)
  195. return ret;
  196. do {
  197. if (++tries > BLOCK_DATA_MAX_TRIES) {
  198. dev_err(&client->dev,
  199. "ds1307_read_block_data failed\n");
  200. return -EIO;
  201. }
  202. memcpy(oldvalues, values, length);
  203. ret = ds1307_read_block_data_once(client, command, length,
  204. values);
  205. if (ret < 0)
  206. return ret;
  207. } while (memcmp(oldvalues, values, length));
  208. return length;
  209. }
  210. static s32 ds1307_write_block_data(const struct i2c_client *client, u8 command,
  211. u8 length, const u8 *values)
  212. {
  213. u8 currvalues[255];
  214. int tries = 0;
  215. dev_dbg(&client->dev, "ds1307_write_block_data (length=%d)\n", length);
  216. do {
  217. s32 i, ret;
  218. if (++tries > BLOCK_DATA_MAX_TRIES) {
  219. dev_err(&client->dev,
  220. "ds1307_write_block_data failed\n");
  221. return -EIO;
  222. }
  223. for (i = 0; i < length; i++) {
  224. ret = i2c_smbus_write_byte_data(client, command + i,
  225. values[i]);
  226. if (ret < 0)
  227. return ret;
  228. }
  229. ret = ds1307_read_block_data_once(client, command, length,
  230. currvalues);
  231. if (ret < 0)
  232. return ret;
  233. } while (memcmp(currvalues, values, length));
  234. return length;
  235. }
  236. /*----------------------------------------------------------------------*/
  237. /* These RTC devices are not designed to be connected to a SMbus adapter.
  238. SMbus limits block operations length to 32 bytes, whereas it's not
  239. limited on I2C buses. As a result, accesses may exceed 32 bytes;
  240. in that case, split them into smaller blocks */
  241. static s32 ds1307_native_smbus_write_block_data(const struct i2c_client *client,
  242. u8 command, u8 length, const u8 *values)
  243. {
  244. u8 suboffset = 0;
  245. if (length <= I2C_SMBUS_BLOCK_MAX)
  246. return i2c_smbus_write_i2c_block_data(client,
  247. command, length, values);
  248. while (suboffset < length) {
  249. s32 retval = i2c_smbus_write_i2c_block_data(client,
  250. command + suboffset,
  251. min(I2C_SMBUS_BLOCK_MAX, length - suboffset),
  252. values + suboffset);
  253. if (retval < 0)
  254. return retval;
  255. suboffset += I2C_SMBUS_BLOCK_MAX;
  256. }
  257. return length;
  258. }
  259. static s32 ds1307_native_smbus_read_block_data(const struct i2c_client *client,
  260. u8 command, u8 length, u8 *values)
  261. {
  262. u8 suboffset = 0;
  263. if (length <= I2C_SMBUS_BLOCK_MAX)
  264. return i2c_smbus_read_i2c_block_data(client,
  265. command, length, values);
  266. while (suboffset < length) {
  267. s32 retval = i2c_smbus_read_i2c_block_data(client,
  268. command + suboffset,
  269. min(I2C_SMBUS_BLOCK_MAX, length - suboffset),
  270. values + suboffset);
  271. if (retval < 0)
  272. return retval;
  273. suboffset += I2C_SMBUS_BLOCK_MAX;
  274. }
  275. return length;
  276. }
  277. /*----------------------------------------------------------------------*/
  278. /*
  279. * The IRQ logic includes a "real" handler running in IRQ context just
  280. * long enough to schedule this workqueue entry. We need a task context
  281. * to talk to the RTC, since I2C I/O calls require that; and disable the
  282. * IRQ until we clear its status on the chip, so that this handler can
  283. * work with any type of triggering (not just falling edge).
  284. *
  285. * The ds1337 and ds1339 both have two alarms, but we only use the first
  286. * one (with a "seconds" field). For ds1337 we expect nINTA is our alarm
  287. * signal; ds1339 chips have only one alarm signal.
  288. */
  289. static void ds1307_work(struct work_struct *work)
  290. {
  291. struct ds1307 *ds1307;
  292. struct i2c_client *client;
  293. struct mutex *lock;
  294. int stat, control;
  295. ds1307 = container_of(work, struct ds1307, work);
  296. client = ds1307->client;
  297. lock = &ds1307->rtc->ops_lock;
  298. mutex_lock(lock);
  299. stat = i2c_smbus_read_byte_data(client, DS1337_REG_STATUS);
  300. if (stat < 0)
  301. goto out;
  302. if (stat & DS1337_BIT_A1I) {
  303. stat &= ~DS1337_BIT_A1I;
  304. i2c_smbus_write_byte_data(client, DS1337_REG_STATUS, stat);
  305. control = i2c_smbus_read_byte_data(client, DS1337_REG_CONTROL);
  306. if (control < 0)
  307. goto out;
  308. control &= ~DS1337_BIT_A1IE;
  309. i2c_smbus_write_byte_data(client, DS1337_REG_CONTROL, control);
  310. rtc_update_irq(ds1307->rtc, 1, RTC_AF | RTC_IRQF);
  311. }
  312. out:
  313. if (test_bit(HAS_ALARM, &ds1307->flags))
  314. enable_irq(client->irq);
  315. mutex_unlock(lock);
  316. }
  317. static irqreturn_t ds1307_irq(int irq, void *dev_id)
  318. {
  319. struct i2c_client *client = dev_id;
  320. struct ds1307 *ds1307 = i2c_get_clientdata(client);
  321. disable_irq_nosync(irq);
  322. schedule_work(&ds1307->work);
  323. return IRQ_HANDLED;
  324. }
  325. /*----------------------------------------------------------------------*/
  326. static int ds1307_get_time(struct device *dev, struct rtc_time *t)
  327. {
  328. struct ds1307 *ds1307 = dev_get_drvdata(dev);
  329. int tmp;
  330. /* read the RTC date and time registers all at once */
  331. tmp = ds1307->read_block_data(ds1307->client,
  332. ds1307->offset, 7, ds1307->regs);
  333. if (tmp != 7) {
  334. dev_err(dev, "%s error %d\n", "read", tmp);
  335. return -EIO;
  336. }
  337. dev_dbg(dev, "%s: %7ph\n", "read", ds1307->regs);
  338. t->tm_sec = bcd2bin(ds1307->regs[DS1307_REG_SECS] & 0x7f);
  339. t->tm_min = bcd2bin(ds1307->regs[DS1307_REG_MIN] & 0x7f);
  340. tmp = ds1307->regs[DS1307_REG_HOUR] & 0x3f;
  341. t->tm_hour = bcd2bin(tmp);
  342. t->tm_wday = bcd2bin(ds1307->regs[DS1307_REG_WDAY] & 0x07) - 1;
  343. t->tm_mday = bcd2bin(ds1307->regs[DS1307_REG_MDAY] & 0x3f);
  344. tmp = ds1307->regs[DS1307_REG_MONTH] & 0x1f;
  345. t->tm_mon = bcd2bin(tmp) - 1;
  346. /* assume 20YY not 19YY, and ignore DS1337_BIT_CENTURY */
  347. t->tm_year = bcd2bin(ds1307->regs[DS1307_REG_YEAR]) + 100;
  348. dev_dbg(dev, "%s secs=%d, mins=%d, "
  349. "hours=%d, mday=%d, mon=%d, year=%d, wday=%d\n",
  350. "read", t->tm_sec, t->tm_min,
  351. t->tm_hour, t->tm_mday,
  352. t->tm_mon, t->tm_year, t->tm_wday);
  353. /* initial clock setting can be undefined */
  354. return rtc_valid_tm(t);
  355. }
  356. static int ds1307_set_time(struct device *dev, struct rtc_time *t)
  357. {
  358. struct ds1307 *ds1307 = dev_get_drvdata(dev);
  359. int result;
  360. int tmp;
  361. u8 *buf = ds1307->regs;
  362. dev_dbg(dev, "%s secs=%d, mins=%d, "
  363. "hours=%d, mday=%d, mon=%d, year=%d, wday=%d\n",
  364. "write", t->tm_sec, t->tm_min,
  365. t->tm_hour, t->tm_mday,
  366. t->tm_mon, t->tm_year, t->tm_wday);
  367. buf[DS1307_REG_SECS] = bin2bcd(t->tm_sec);
  368. buf[DS1307_REG_MIN] = bin2bcd(t->tm_min);
  369. buf[DS1307_REG_HOUR] = bin2bcd(t->tm_hour);
  370. buf[DS1307_REG_WDAY] = bin2bcd(t->tm_wday + 1);
  371. buf[DS1307_REG_MDAY] = bin2bcd(t->tm_mday);
  372. buf[DS1307_REG_MONTH] = bin2bcd(t->tm_mon + 1);
  373. /* assume 20YY not 19YY */
  374. tmp = t->tm_year - 100;
  375. buf[DS1307_REG_YEAR] = bin2bcd(tmp);
  376. switch (ds1307->type) {
  377. case ds_1337:
  378. case ds_1339:
  379. case ds_3231:
  380. buf[DS1307_REG_MONTH] |= DS1337_BIT_CENTURY;
  381. break;
  382. case ds_1340:
  383. buf[DS1307_REG_HOUR] |= DS1340_BIT_CENTURY_EN
  384. | DS1340_BIT_CENTURY;
  385. break;
  386. case mcp7941x:
  387. /*
  388. * these bits were cleared when preparing the date/time
  389. * values and need to be set again before writing the
  390. * buffer out to the device.
  391. */
  392. buf[DS1307_REG_SECS] |= MCP7941X_BIT_ST;
  393. buf[DS1307_REG_WDAY] |= MCP7941X_BIT_VBATEN;
  394. break;
  395. default:
  396. break;
  397. }
  398. dev_dbg(dev, "%s: %7ph\n", "write", buf);
  399. result = ds1307->write_block_data(ds1307->client,
  400. ds1307->offset, 7, buf);
  401. if (result < 0) {
  402. dev_err(dev, "%s error %d\n", "write", result);
  403. return result;
  404. }
  405. return 0;
  406. }
  407. static int ds1337_read_alarm(struct device *dev, struct rtc_wkalrm *t)
  408. {
  409. struct i2c_client *client = to_i2c_client(dev);
  410. struct ds1307 *ds1307 = i2c_get_clientdata(client);
  411. int ret;
  412. if (!test_bit(HAS_ALARM, &ds1307->flags))
  413. return -EINVAL;
  414. /* read all ALARM1, ALARM2, and status registers at once */
  415. ret = ds1307->read_block_data(client,
  416. DS1339_REG_ALARM1_SECS, 9, ds1307->regs);
  417. if (ret != 9) {
  418. dev_err(dev, "%s error %d\n", "alarm read", ret);
  419. return -EIO;
  420. }
  421. dev_dbg(dev, "%s: %02x %02x %02x %02x, %02x %02x %02x, %02x %02x\n",
  422. "alarm read",
  423. ds1307->regs[0], ds1307->regs[1],
  424. ds1307->regs[2], ds1307->regs[3],
  425. ds1307->regs[4], ds1307->regs[5],
  426. ds1307->regs[6], ds1307->regs[7],
  427. ds1307->regs[8]);
  428. /*
  429. * report alarm time (ALARM1); assume 24 hour and day-of-month modes,
  430. * and that all four fields are checked matches
  431. */
  432. t->time.tm_sec = bcd2bin(ds1307->regs[0] & 0x7f);
  433. t->time.tm_min = bcd2bin(ds1307->regs[1] & 0x7f);
  434. t->time.tm_hour = bcd2bin(ds1307->regs[2] & 0x3f);
  435. t->time.tm_mday = bcd2bin(ds1307->regs[3] & 0x3f);
  436. t->time.tm_mon = -1;
  437. t->time.tm_year = -1;
  438. t->time.tm_wday = -1;
  439. t->time.tm_yday = -1;
  440. t->time.tm_isdst = -1;
  441. /* ... and status */
  442. t->enabled = !!(ds1307->regs[7] & DS1337_BIT_A1IE);
  443. t->pending = !!(ds1307->regs[8] & DS1337_BIT_A1I);
  444. dev_dbg(dev, "%s secs=%d, mins=%d, "
  445. "hours=%d, mday=%d, enabled=%d, pending=%d\n",
  446. "alarm read", t->time.tm_sec, t->time.tm_min,
  447. t->time.tm_hour, t->time.tm_mday,
  448. t->enabled, t->pending);
  449. return 0;
  450. }
  451. static int ds1337_set_alarm(struct device *dev, struct rtc_wkalrm *t)
  452. {
  453. struct i2c_client *client = to_i2c_client(dev);
  454. struct ds1307 *ds1307 = i2c_get_clientdata(client);
  455. unsigned char *buf = ds1307->regs;
  456. u8 control, status;
  457. int ret;
  458. if (!test_bit(HAS_ALARM, &ds1307->flags))
  459. return -EINVAL;
  460. dev_dbg(dev, "%s secs=%d, mins=%d, "
  461. "hours=%d, mday=%d, enabled=%d, pending=%d\n",
  462. "alarm set", t->time.tm_sec, t->time.tm_min,
  463. t->time.tm_hour, t->time.tm_mday,
  464. t->enabled, t->pending);
  465. /* read current status of both alarms and the chip */
  466. ret = ds1307->read_block_data(client,
  467. DS1339_REG_ALARM1_SECS, 9, buf);
  468. if (ret != 9) {
  469. dev_err(dev, "%s error %d\n", "alarm write", ret);
  470. return -EIO;
  471. }
  472. control = ds1307->regs[7];
  473. status = ds1307->regs[8];
  474. dev_dbg(dev, "%s: %02x %02x %02x %02x, %02x %02x %02x, %02x %02x\n",
  475. "alarm set (old status)",
  476. ds1307->regs[0], ds1307->regs[1],
  477. ds1307->regs[2], ds1307->regs[3],
  478. ds1307->regs[4], ds1307->regs[5],
  479. ds1307->regs[6], control, status);
  480. /* set ALARM1, using 24 hour and day-of-month modes */
  481. buf[0] = bin2bcd(t->time.tm_sec);
  482. buf[1] = bin2bcd(t->time.tm_min);
  483. buf[2] = bin2bcd(t->time.tm_hour);
  484. buf[3] = bin2bcd(t->time.tm_mday);
  485. /* set ALARM2 to non-garbage */
  486. buf[4] = 0;
  487. buf[5] = 0;
  488. buf[6] = 0;
  489. /* optionally enable ALARM1 */
  490. buf[7] = control & ~(DS1337_BIT_A1IE | DS1337_BIT_A2IE);
  491. if (t->enabled) {
  492. dev_dbg(dev, "alarm IRQ armed\n");
  493. buf[7] |= DS1337_BIT_A1IE; /* only ALARM1 is used */
  494. }
  495. buf[8] = status & ~(DS1337_BIT_A1I | DS1337_BIT_A2I);
  496. ret = ds1307->write_block_data(client,
  497. DS1339_REG_ALARM1_SECS, 9, buf);
  498. if (ret < 0) {
  499. dev_err(dev, "can't set alarm time\n");
  500. return ret;
  501. }
  502. return 0;
  503. }
  504. static int ds1307_alarm_irq_enable(struct device *dev, unsigned int enabled)
  505. {
  506. struct i2c_client *client = to_i2c_client(dev);
  507. struct ds1307 *ds1307 = i2c_get_clientdata(client);
  508. int ret;
  509. if (!test_bit(HAS_ALARM, &ds1307->flags))
  510. return -ENOTTY;
  511. ret = i2c_smbus_read_byte_data(client, DS1337_REG_CONTROL);
  512. if (ret < 0)
  513. return ret;
  514. if (enabled)
  515. ret |= DS1337_BIT_A1IE;
  516. else
  517. ret &= ~DS1337_BIT_A1IE;
  518. ret = i2c_smbus_write_byte_data(client, DS1337_REG_CONTROL, ret);
  519. if (ret < 0)
  520. return ret;
  521. return 0;
  522. }
  523. static const struct rtc_class_ops ds13xx_rtc_ops = {
  524. .read_time = ds1307_get_time,
  525. .set_time = ds1307_set_time,
  526. .read_alarm = ds1337_read_alarm,
  527. .set_alarm = ds1337_set_alarm,
  528. .alarm_irq_enable = ds1307_alarm_irq_enable,
  529. };
  530. /*----------------------------------------------------------------------*/
  531. /*
  532. * Alarm support for mcp7941x devices.
  533. */
  534. #define MCP7941X_REG_CONTROL 0x07
  535. # define MCP7941X_BIT_ALM0_EN 0x10
  536. # define MCP7941X_BIT_ALM1_EN 0x20
  537. #define MCP7941X_REG_ALARM0_BASE 0x0a
  538. #define MCP7941X_REG_ALARM0_CTRL 0x0d
  539. #define MCP7941X_REG_ALARM1_BASE 0x11
  540. #define MCP7941X_REG_ALARM1_CTRL 0x14
  541. # define MCP7941X_BIT_ALMX_IF (1 << 3)
  542. # define MCP7941X_BIT_ALMX_C0 (1 << 4)
  543. # define MCP7941X_BIT_ALMX_C1 (1 << 5)
  544. # define MCP7941X_BIT_ALMX_C2 (1 << 6)
  545. # define MCP7941X_BIT_ALMX_POL (1 << 7)
  546. # define MCP7941X_MSK_ALMX_MATCH (MCP7941X_BIT_ALMX_C0 | \
  547. MCP7941X_BIT_ALMX_C1 | \
  548. MCP7941X_BIT_ALMX_C2)
  549. static void mcp7941x_work(struct work_struct *work)
  550. {
  551. struct ds1307 *ds1307 = container_of(work, struct ds1307, work);
  552. struct i2c_client *client = ds1307->client;
  553. int reg, ret;
  554. mutex_lock(&ds1307->rtc->ops_lock);
  555. /* Check and clear alarm 0 interrupt flag. */
  556. reg = i2c_smbus_read_byte_data(client, MCP7941X_REG_ALARM0_CTRL);
  557. if (reg < 0)
  558. goto out;
  559. if (!(reg & MCP7941X_BIT_ALMX_IF))
  560. goto out;
  561. reg &= ~MCP7941X_BIT_ALMX_IF;
  562. ret = i2c_smbus_write_byte_data(client, MCP7941X_REG_ALARM0_CTRL, reg);
  563. if (ret < 0)
  564. goto out;
  565. /* Disable alarm 0. */
  566. reg = i2c_smbus_read_byte_data(client, MCP7941X_REG_CONTROL);
  567. if (reg < 0)
  568. goto out;
  569. reg &= ~MCP7941X_BIT_ALM0_EN;
  570. ret = i2c_smbus_write_byte_data(client, MCP7941X_REG_CONTROL, reg);
  571. if (ret < 0)
  572. goto out;
  573. rtc_update_irq(ds1307->rtc, 1, RTC_AF | RTC_IRQF);
  574. out:
  575. if (test_bit(HAS_ALARM, &ds1307->flags))
  576. enable_irq(client->irq);
  577. mutex_unlock(&ds1307->rtc->ops_lock);
  578. }
  579. static int mcp7941x_read_alarm(struct device *dev, struct rtc_wkalrm *t)
  580. {
  581. struct i2c_client *client = to_i2c_client(dev);
  582. struct ds1307 *ds1307 = i2c_get_clientdata(client);
  583. u8 *regs = ds1307->regs;
  584. int ret;
  585. if (!test_bit(HAS_ALARM, &ds1307->flags))
  586. return -EINVAL;
  587. /* Read control and alarm 0 registers. */
  588. ret = ds1307->read_block_data(client, MCP7941X_REG_CONTROL, 10, regs);
  589. if (ret < 0)
  590. return ret;
  591. t->enabled = !!(regs[0] & MCP7941X_BIT_ALM0_EN);
  592. /* Report alarm 0 time assuming 24-hour and day-of-month modes. */
  593. t->time.tm_sec = bcd2bin(ds1307->regs[3] & 0x7f);
  594. t->time.tm_min = bcd2bin(ds1307->regs[4] & 0x7f);
  595. t->time.tm_hour = bcd2bin(ds1307->regs[5] & 0x3f);
  596. t->time.tm_wday = bcd2bin(ds1307->regs[6] & 0x7) - 1;
  597. t->time.tm_mday = bcd2bin(ds1307->regs[7] & 0x3f);
  598. t->time.tm_mon = bcd2bin(ds1307->regs[8] & 0x1f) - 1;
  599. t->time.tm_year = -1;
  600. t->time.tm_yday = -1;
  601. t->time.tm_isdst = -1;
  602. dev_dbg(dev, "%s, sec=%d min=%d hour=%d wday=%d mday=%d mon=%d "
  603. "enabled=%d polarity=%d irq=%d match=%d\n", __func__,
  604. t->time.tm_sec, t->time.tm_min, t->time.tm_hour,
  605. t->time.tm_wday, t->time.tm_mday, t->time.tm_mon, t->enabled,
  606. !!(ds1307->regs[6] & MCP7941X_BIT_ALMX_POL),
  607. !!(ds1307->regs[6] & MCP7941X_BIT_ALMX_IF),
  608. (ds1307->regs[6] & MCP7941X_MSK_ALMX_MATCH) >> 4);
  609. return 0;
  610. }
  611. static int mcp7941x_set_alarm(struct device *dev, struct rtc_wkalrm *t)
  612. {
  613. struct i2c_client *client = to_i2c_client(dev);
  614. struct ds1307 *ds1307 = i2c_get_clientdata(client);
  615. unsigned char *regs = ds1307->regs;
  616. int ret;
  617. if (!test_bit(HAS_ALARM, &ds1307->flags))
  618. return -EINVAL;
  619. dev_dbg(dev, "%s, sec=%d min=%d hour=%d wday=%d mday=%d mon=%d "
  620. "enabled=%d pending=%d\n", __func__,
  621. t->time.tm_sec, t->time.tm_min, t->time.tm_hour,
  622. t->time.tm_wday, t->time.tm_mday, t->time.tm_mon,
  623. t->enabled, t->pending);
  624. /* Read control and alarm 0 registers. */
  625. ret = ds1307->read_block_data(client, MCP7941X_REG_CONTROL, 10, regs);
  626. if (ret < 0)
  627. return ret;
  628. /* Set alarm 0, using 24-hour and day-of-month modes. */
  629. regs[3] = bin2bcd(t->time.tm_sec);
  630. regs[4] = bin2bcd(t->time.tm_min);
  631. regs[5] = bin2bcd(t->time.tm_hour);
  632. regs[6] = bin2bcd(t->time.tm_wday) + 1;
  633. regs[7] = bin2bcd(t->time.tm_mday);
  634. regs[8] = bin2bcd(t->time.tm_mon) + 1;
  635. /* Clear the alarm 0 interrupt flag. */
  636. regs[6] &= ~MCP7941X_BIT_ALMX_IF;
  637. /* Set alarm match: second, minute, hour, day, date, month. */
  638. regs[6] |= MCP7941X_MSK_ALMX_MATCH;
  639. if (t->enabled)
  640. regs[0] |= MCP7941X_BIT_ALM0_EN;
  641. else
  642. regs[0] &= ~MCP7941X_BIT_ALM0_EN;
  643. ret = ds1307->write_block_data(client, MCP7941X_REG_CONTROL, 10, regs);
  644. if (ret < 0)
  645. return ret;
  646. return 0;
  647. }
  648. static int mcp7941x_alarm_irq_enable(struct device *dev, unsigned int enabled)
  649. {
  650. struct i2c_client *client = to_i2c_client(dev);
  651. struct ds1307 *ds1307 = i2c_get_clientdata(client);
  652. int reg;
  653. if (!test_bit(HAS_ALARM, &ds1307->flags))
  654. return -EINVAL;
  655. reg = i2c_smbus_read_byte_data(client, MCP7941X_REG_CONTROL);
  656. if (reg < 0)
  657. return reg;
  658. if (enabled)
  659. reg |= MCP7941X_BIT_ALM0_EN;
  660. else
  661. reg &= ~MCP7941X_BIT_ALM0_EN;
  662. return i2c_smbus_write_byte_data(client, MCP7941X_REG_CONTROL, reg);
  663. }
  664. static const struct rtc_class_ops mcp7941x_rtc_ops = {
  665. .read_time = ds1307_get_time,
  666. .set_time = ds1307_set_time,
  667. .read_alarm = mcp7941x_read_alarm,
  668. .set_alarm = mcp7941x_set_alarm,
  669. .alarm_irq_enable = mcp7941x_alarm_irq_enable,
  670. };
  671. /*----------------------------------------------------------------------*/
  672. static ssize_t
  673. ds1307_nvram_read(struct file *filp, struct kobject *kobj,
  674. struct bin_attribute *attr,
  675. char *buf, loff_t off, size_t count)
  676. {
  677. struct i2c_client *client;
  678. struct ds1307 *ds1307;
  679. int result;
  680. client = kobj_to_i2c_client(kobj);
  681. ds1307 = i2c_get_clientdata(client);
  682. if (unlikely(off >= ds1307->nvram->size))
  683. return 0;
  684. if ((off + count) > ds1307->nvram->size)
  685. count = ds1307->nvram->size - off;
  686. if (unlikely(!count))
  687. return count;
  688. result = ds1307->read_block_data(client, ds1307->nvram_offset + off,
  689. count, buf);
  690. if (result < 0)
  691. dev_err(&client->dev, "%s error %d\n", "nvram read", result);
  692. return result;
  693. }
  694. static ssize_t
  695. ds1307_nvram_write(struct file *filp, struct kobject *kobj,
  696. struct bin_attribute *attr,
  697. char *buf, loff_t off, size_t count)
  698. {
  699. struct i2c_client *client;
  700. struct ds1307 *ds1307;
  701. int result;
  702. client = kobj_to_i2c_client(kobj);
  703. ds1307 = i2c_get_clientdata(client);
  704. if (unlikely(off >= ds1307->nvram->size))
  705. return -EFBIG;
  706. if ((off + count) > ds1307->nvram->size)
  707. count = ds1307->nvram->size - off;
  708. if (unlikely(!count))
  709. return count;
  710. result = ds1307->write_block_data(client, ds1307->nvram_offset + off,
  711. count, buf);
  712. if (result < 0) {
  713. dev_err(&client->dev, "%s error %d\n", "nvram write", result);
  714. return result;
  715. }
  716. return count;
  717. }
  718. /*----------------------------------------------------------------------*/
  719. static u8 do_trickle_setup_ds1339(struct i2c_client *client,
  720. uint32_t ohms, bool diode)
  721. {
  722. u8 setup = (diode) ? DS1307_TRICKLE_CHARGER_DIODE :
  723. DS1307_TRICKLE_CHARGER_NO_DIODE;
  724. switch (ohms) {
  725. case 250:
  726. setup |= DS1307_TRICKLE_CHARGER_250_OHM;
  727. break;
  728. case 2000:
  729. setup |= DS1307_TRICKLE_CHARGER_2K_OHM;
  730. break;
  731. case 4000:
  732. setup |= DS1307_TRICKLE_CHARGER_4K_OHM;
  733. break;
  734. default:
  735. dev_warn(&client->dev,
  736. "Unsupported ohm value %u in dt\n", ohms);
  737. return 0;
  738. }
  739. return setup;
  740. }
  741. static void ds1307_trickle_of_init(struct i2c_client *client,
  742. struct chip_desc *chip)
  743. {
  744. uint32_t ohms = 0;
  745. bool diode = true;
  746. if (!chip->do_trickle_setup)
  747. goto out;
  748. if (of_property_read_u32(client->dev.of_node, "trickle-resistor-ohms" , &ohms))
  749. goto out;
  750. if (of_property_read_bool(client->dev.of_node, "trickle-diode-disable"))
  751. diode = false;
  752. chip->trickle_charger_setup = chip->do_trickle_setup(client,
  753. ohms, diode);
  754. out:
  755. return;
  756. }
  757. static int ds1307_probe(struct i2c_client *client,
  758. const struct i2c_device_id *id)
  759. {
  760. struct ds1307 *ds1307;
  761. int err = -ENODEV;
  762. int tmp;
  763. struct chip_desc *chip = &chips[id->driver_data];
  764. struct i2c_adapter *adapter = to_i2c_adapter(client->dev.parent);
  765. bool want_irq = false;
  766. unsigned char *buf;
  767. struct ds1307_platform_data *pdata = dev_get_platdata(&client->dev);
  768. static const int bbsqi_bitpos[] = {
  769. [ds_1337] = 0,
  770. [ds_1339] = DS1339_BIT_BBSQI,
  771. [ds_3231] = DS3231_BIT_BBSQW,
  772. };
  773. const struct rtc_class_ops *rtc_ops = &ds13xx_rtc_ops;
  774. if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA)
  775. && !i2c_check_functionality(adapter, I2C_FUNC_SMBUS_I2C_BLOCK))
  776. return -EIO;
  777. ds1307 = devm_kzalloc(&client->dev, sizeof(struct ds1307), GFP_KERNEL);
  778. if (!ds1307)
  779. return -ENOMEM;
  780. i2c_set_clientdata(client, ds1307);
  781. ds1307->client = client;
  782. ds1307->type = id->driver_data;
  783. if (!pdata && client->dev.of_node)
  784. ds1307_trickle_of_init(client, chip);
  785. else if (pdata && pdata->trickle_charger_setup)
  786. chip->trickle_charger_setup = pdata->trickle_charger_setup;
  787. if (chip->trickle_charger_setup && chip->trickle_charger_reg) {
  788. dev_dbg(&client->dev, "writing trickle charger info 0x%x to 0x%x\n",
  789. DS13XX_TRICKLE_CHARGER_MAGIC | chip->trickle_charger_setup,
  790. chip->trickle_charger_reg);
  791. i2c_smbus_write_byte_data(client, chip->trickle_charger_reg,
  792. DS13XX_TRICKLE_CHARGER_MAGIC |
  793. chip->trickle_charger_setup);
  794. }
  795. buf = ds1307->regs;
  796. if (i2c_check_functionality(adapter, I2C_FUNC_SMBUS_I2C_BLOCK)) {
  797. ds1307->read_block_data = ds1307_native_smbus_read_block_data;
  798. ds1307->write_block_data = ds1307_native_smbus_write_block_data;
  799. } else {
  800. ds1307->read_block_data = ds1307_read_block_data;
  801. ds1307->write_block_data = ds1307_write_block_data;
  802. }
  803. switch (ds1307->type) {
  804. case ds_1337:
  805. case ds_1339:
  806. case ds_3231:
  807. /* get registers that the "rtc" read below won't read... */
  808. tmp = ds1307->read_block_data(ds1307->client,
  809. DS1337_REG_CONTROL, 2, buf);
  810. if (tmp != 2) {
  811. dev_dbg(&client->dev, "read error %d\n", tmp);
  812. err = -EIO;
  813. goto exit;
  814. }
  815. /* oscillator off? turn it on, so clock can tick. */
  816. if (ds1307->regs[0] & DS1337_BIT_nEOSC)
  817. ds1307->regs[0] &= ~DS1337_BIT_nEOSC;
  818. /*
  819. * Using IRQ? Disable the square wave and both alarms.
  820. * For some variants, be sure alarms can trigger when we're
  821. * running on Vbackup (BBSQI/BBSQW)
  822. */
  823. if (ds1307->client->irq > 0 && chip->alarm) {
  824. INIT_WORK(&ds1307->work, ds1307_work);
  825. ds1307->regs[0] |= DS1337_BIT_INTCN
  826. | bbsqi_bitpos[ds1307->type];
  827. ds1307->regs[0] &= ~(DS1337_BIT_A2IE | DS1337_BIT_A1IE);
  828. want_irq = true;
  829. }
  830. i2c_smbus_write_byte_data(client, DS1337_REG_CONTROL,
  831. ds1307->regs[0]);
  832. /* oscillator fault? clear flag, and warn */
  833. if (ds1307->regs[1] & DS1337_BIT_OSF) {
  834. i2c_smbus_write_byte_data(client, DS1337_REG_STATUS,
  835. ds1307->regs[1] & ~DS1337_BIT_OSF);
  836. dev_warn(&client->dev, "SET TIME!\n");
  837. }
  838. break;
  839. case rx_8025:
  840. tmp = i2c_smbus_read_i2c_block_data(ds1307->client,
  841. RX8025_REG_CTRL1 << 4 | 0x08, 2, buf);
  842. if (tmp != 2) {
  843. dev_dbg(&client->dev, "read error %d\n", tmp);
  844. err = -EIO;
  845. goto exit;
  846. }
  847. /* oscillator off? turn it on, so clock can tick. */
  848. if (!(ds1307->regs[1] & RX8025_BIT_XST)) {
  849. ds1307->regs[1] |= RX8025_BIT_XST;
  850. i2c_smbus_write_byte_data(client,
  851. RX8025_REG_CTRL2 << 4 | 0x08,
  852. ds1307->regs[1]);
  853. dev_warn(&client->dev,
  854. "oscillator stop detected - SET TIME!\n");
  855. }
  856. if (ds1307->regs[1] & RX8025_BIT_PON) {
  857. ds1307->regs[1] &= ~RX8025_BIT_PON;
  858. i2c_smbus_write_byte_data(client,
  859. RX8025_REG_CTRL2 << 4 | 0x08,
  860. ds1307->regs[1]);
  861. dev_warn(&client->dev, "power-on detected\n");
  862. }
  863. if (ds1307->regs[1] & RX8025_BIT_VDET) {
  864. ds1307->regs[1] &= ~RX8025_BIT_VDET;
  865. i2c_smbus_write_byte_data(client,
  866. RX8025_REG_CTRL2 << 4 | 0x08,
  867. ds1307->regs[1]);
  868. dev_warn(&client->dev, "voltage drop detected\n");
  869. }
  870. /* make sure we are running in 24hour mode */
  871. if (!(ds1307->regs[0] & RX8025_BIT_2412)) {
  872. u8 hour;
  873. /* switch to 24 hour mode */
  874. i2c_smbus_write_byte_data(client,
  875. RX8025_REG_CTRL1 << 4 | 0x08,
  876. ds1307->regs[0] |
  877. RX8025_BIT_2412);
  878. tmp = i2c_smbus_read_i2c_block_data(ds1307->client,
  879. RX8025_REG_CTRL1 << 4 | 0x08, 2, buf);
  880. if (tmp != 2) {
  881. dev_dbg(&client->dev, "read error %d\n", tmp);
  882. err = -EIO;
  883. goto exit;
  884. }
  885. /* correct hour */
  886. hour = bcd2bin(ds1307->regs[DS1307_REG_HOUR]);
  887. if (hour == 12)
  888. hour = 0;
  889. if (ds1307->regs[DS1307_REG_HOUR] & DS1307_BIT_PM)
  890. hour += 12;
  891. i2c_smbus_write_byte_data(client,
  892. DS1307_REG_HOUR << 4 | 0x08,
  893. hour);
  894. }
  895. break;
  896. case ds_1388:
  897. ds1307->offset = 1; /* Seconds starts at 1 */
  898. break;
  899. case mcp7941x:
  900. rtc_ops = &mcp7941x_rtc_ops;
  901. if (ds1307->client->irq > 0 && chip->alarm) {
  902. INIT_WORK(&ds1307->work, mcp7941x_work);
  903. want_irq = true;
  904. }
  905. break;
  906. default:
  907. break;
  908. }
  909. read_rtc:
  910. /* read RTC registers */
  911. tmp = ds1307->read_block_data(ds1307->client, ds1307->offset, 8, buf);
  912. if (tmp != 8) {
  913. dev_dbg(&client->dev, "read error %d\n", tmp);
  914. err = -EIO;
  915. goto exit;
  916. }
  917. /*
  918. * minimal sanity checking; some chips (like DS1340) don't
  919. * specify the extra bits as must-be-zero, but there are
  920. * still a few values that are clearly out-of-range.
  921. */
  922. tmp = ds1307->regs[DS1307_REG_SECS];
  923. switch (ds1307->type) {
  924. case ds_1307:
  925. case m41t00:
  926. /* clock halted? turn it on, so clock can tick. */
  927. if (tmp & DS1307_BIT_CH) {
  928. i2c_smbus_write_byte_data(client, DS1307_REG_SECS, 0);
  929. dev_warn(&client->dev, "SET TIME!\n");
  930. goto read_rtc;
  931. }
  932. break;
  933. case ds_1338:
  934. /* clock halted? turn it on, so clock can tick. */
  935. if (tmp & DS1307_BIT_CH)
  936. i2c_smbus_write_byte_data(client, DS1307_REG_SECS, 0);
  937. /* oscillator fault? clear flag, and warn */
  938. if (ds1307->regs[DS1307_REG_CONTROL] & DS1338_BIT_OSF) {
  939. i2c_smbus_write_byte_data(client, DS1307_REG_CONTROL,
  940. ds1307->regs[DS1307_REG_CONTROL]
  941. & ~DS1338_BIT_OSF);
  942. dev_warn(&client->dev, "SET TIME!\n");
  943. goto read_rtc;
  944. }
  945. break;
  946. case ds_1340:
  947. /* clock halted? turn it on, so clock can tick. */
  948. if (tmp & DS1340_BIT_nEOSC)
  949. i2c_smbus_write_byte_data(client, DS1307_REG_SECS, 0);
  950. tmp = i2c_smbus_read_byte_data(client, DS1340_REG_FLAG);
  951. if (tmp < 0) {
  952. dev_dbg(&client->dev, "read error %d\n", tmp);
  953. err = -EIO;
  954. goto exit;
  955. }
  956. /* oscillator fault? clear flag, and warn */
  957. if (tmp & DS1340_BIT_OSF) {
  958. i2c_smbus_write_byte_data(client, DS1340_REG_FLAG, 0);
  959. dev_warn(&client->dev, "SET TIME!\n");
  960. }
  961. break;
  962. case mcp7941x:
  963. /* make sure that the backup battery is enabled */
  964. if (!(ds1307->regs[DS1307_REG_WDAY] & MCP7941X_BIT_VBATEN)) {
  965. i2c_smbus_write_byte_data(client, DS1307_REG_WDAY,
  966. ds1307->regs[DS1307_REG_WDAY]
  967. | MCP7941X_BIT_VBATEN);
  968. }
  969. /* clock halted? turn it on, so clock can tick. */
  970. if (!(tmp & MCP7941X_BIT_ST)) {
  971. i2c_smbus_write_byte_data(client, DS1307_REG_SECS,
  972. MCP7941X_BIT_ST);
  973. dev_warn(&client->dev, "SET TIME!\n");
  974. goto read_rtc;
  975. }
  976. break;
  977. default:
  978. break;
  979. }
  980. tmp = ds1307->regs[DS1307_REG_HOUR];
  981. switch (ds1307->type) {
  982. case ds_1340:
  983. case m41t00:
  984. /*
  985. * NOTE: ignores century bits; fix before deploying
  986. * systems that will run through year 2100.
  987. */
  988. break;
  989. case rx_8025:
  990. break;
  991. default:
  992. if (!(tmp & DS1307_BIT_12HR))
  993. break;
  994. /*
  995. * Be sure we're in 24 hour mode. Multi-master systems
  996. * take note...
  997. */
  998. tmp = bcd2bin(tmp & 0x1f);
  999. if (tmp == 12)
  1000. tmp = 0;
  1001. if (ds1307->regs[DS1307_REG_HOUR] & DS1307_BIT_PM)
  1002. tmp += 12;
  1003. i2c_smbus_write_byte_data(client,
  1004. ds1307->offset + DS1307_REG_HOUR,
  1005. bin2bcd(tmp));
  1006. }
  1007. device_set_wakeup_capable(&client->dev, want_irq);
  1008. ds1307->rtc = devm_rtc_device_register(&client->dev, client->name,
  1009. rtc_ops, THIS_MODULE);
  1010. if (IS_ERR(ds1307->rtc)) {
  1011. return PTR_ERR(ds1307->rtc);
  1012. }
  1013. if (want_irq) {
  1014. err = request_irq(client->irq, ds1307_irq, IRQF_SHARED,
  1015. ds1307->rtc->name, client);
  1016. if (err) {
  1017. client->irq = 0;
  1018. dev_err(&client->dev, "unable to request IRQ!\n");
  1019. } else {
  1020. set_bit(HAS_ALARM, &ds1307->flags);
  1021. dev_dbg(&client->dev, "got IRQ %d\n", client->irq);
  1022. }
  1023. }
  1024. if (chip->nvram_size) {
  1025. ds1307->nvram = devm_kzalloc(&client->dev,
  1026. sizeof(struct bin_attribute),
  1027. GFP_KERNEL);
  1028. if (!ds1307->nvram) {
  1029. dev_err(&client->dev, "cannot allocate memory for nvram sysfs\n");
  1030. } else {
  1031. ds1307->nvram->attr.name = "nvram";
  1032. ds1307->nvram->attr.mode = S_IRUGO | S_IWUSR;
  1033. sysfs_bin_attr_init(ds1307->nvram);
  1034. ds1307->nvram->read = ds1307_nvram_read;
  1035. ds1307->nvram->write = ds1307_nvram_write;
  1036. ds1307->nvram->size = chip->nvram_size;
  1037. ds1307->nvram_offset = chip->nvram_offset;
  1038. err = sysfs_create_bin_file(&client->dev.kobj,
  1039. ds1307->nvram);
  1040. if (err) {
  1041. dev_err(&client->dev,
  1042. "unable to create sysfs file: %s\n",
  1043. ds1307->nvram->attr.name);
  1044. } else {
  1045. set_bit(HAS_NVRAM, &ds1307->flags);
  1046. dev_info(&client->dev, "%zu bytes nvram\n",
  1047. ds1307->nvram->size);
  1048. }
  1049. }
  1050. }
  1051. return 0;
  1052. exit:
  1053. return err;
  1054. }
  1055. static int ds1307_remove(struct i2c_client *client)
  1056. {
  1057. struct ds1307 *ds1307 = i2c_get_clientdata(client);
  1058. if (test_and_clear_bit(HAS_ALARM, &ds1307->flags)) {
  1059. free_irq(client->irq, client);
  1060. cancel_work_sync(&ds1307->work);
  1061. }
  1062. if (test_and_clear_bit(HAS_NVRAM, &ds1307->flags))
  1063. sysfs_remove_bin_file(&client->dev.kobj, ds1307->nvram);
  1064. return 0;
  1065. }
  1066. static struct i2c_driver ds1307_driver = {
  1067. .driver = {
  1068. .name = "rtc-ds1307",
  1069. .owner = THIS_MODULE,
  1070. },
  1071. .probe = ds1307_probe,
  1072. .remove = ds1307_remove,
  1073. .id_table = ds1307_id,
  1074. };
  1075. module_i2c_driver(ds1307_driver);
  1076. MODULE_DESCRIPTION("RTC driver for DS1307 and similar chips");
  1077. MODULE_LICENSE("GPL");