phy-exynos-mipi-video.c 4.6 KB

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  1. /*
  2. * Samsung S5P/EXYNOS SoC series MIPI CSIS/DSIM DPHY driver
  3. *
  4. * Copyright (C) 2013 Samsung Electronics Co., Ltd.
  5. * Author: Sylwester Nawrocki <s.nawrocki@samsung.com>
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License version 2 as
  9. * published by the Free Software Foundation.
  10. */
  11. #include <linux/err.h>
  12. #include <linux/io.h>
  13. #include <linux/kernel.h>
  14. #include <linux/module.h>
  15. #include <linux/of.h>
  16. #include <linux/of_address.h>
  17. #include <linux/phy/phy.h>
  18. #include <linux/platform_device.h>
  19. #include <linux/spinlock.h>
  20. /* MIPI_PHYn_CONTROL register offset: n = 0..1 */
  21. #define EXYNOS_MIPI_PHY_CONTROL(n) ((n) * 4)
  22. #define EXYNOS_MIPI_PHY_ENABLE (1 << 0)
  23. #define EXYNOS_MIPI_PHY_SRESETN (1 << 1)
  24. #define EXYNOS_MIPI_PHY_MRESETN (1 << 2)
  25. #define EXYNOS_MIPI_PHY_RESET_MASK (3 << 1)
  26. enum exynos_mipi_phy_id {
  27. EXYNOS_MIPI_PHY_ID_CSIS0,
  28. EXYNOS_MIPI_PHY_ID_DSIM0,
  29. EXYNOS_MIPI_PHY_ID_CSIS1,
  30. EXYNOS_MIPI_PHY_ID_DSIM1,
  31. EXYNOS_MIPI_PHYS_NUM
  32. };
  33. #define is_mipi_dsim_phy_id(id) \
  34. ((id) == EXYNOS_MIPI_PHY_ID_DSIM0 || (id) == EXYNOS_MIPI_PHY_ID_DSIM1)
  35. struct exynos_mipi_video_phy {
  36. spinlock_t slock;
  37. struct video_phy_desc {
  38. struct phy *phy;
  39. unsigned int index;
  40. } phys[EXYNOS_MIPI_PHYS_NUM];
  41. void __iomem *regs;
  42. };
  43. static int __set_phy_state(struct exynos_mipi_video_phy *state,
  44. enum exynos_mipi_phy_id id, unsigned int on)
  45. {
  46. void __iomem *addr;
  47. u32 reg, reset;
  48. addr = state->regs + EXYNOS_MIPI_PHY_CONTROL(id / 2);
  49. if (is_mipi_dsim_phy_id(id))
  50. reset = EXYNOS_MIPI_PHY_MRESETN;
  51. else
  52. reset = EXYNOS_MIPI_PHY_SRESETN;
  53. spin_lock(&state->slock);
  54. reg = readl(addr);
  55. if (on)
  56. reg |= reset;
  57. else
  58. reg &= ~reset;
  59. writel(reg, addr);
  60. /* Clear ENABLE bit only if MRESETN, SRESETN bits are not set. */
  61. if (on)
  62. reg |= EXYNOS_MIPI_PHY_ENABLE;
  63. else if (!(reg & EXYNOS_MIPI_PHY_RESET_MASK))
  64. reg &= ~EXYNOS_MIPI_PHY_ENABLE;
  65. writel(reg, addr);
  66. spin_unlock(&state->slock);
  67. return 0;
  68. }
  69. #define to_mipi_video_phy(desc) \
  70. container_of((desc), struct exynos_mipi_video_phy, phys[(desc)->index]);
  71. static int exynos_mipi_video_phy_power_on(struct phy *phy)
  72. {
  73. struct video_phy_desc *phy_desc = phy_get_drvdata(phy);
  74. struct exynos_mipi_video_phy *state = to_mipi_video_phy(phy_desc);
  75. return __set_phy_state(state, phy_desc->index, 1);
  76. }
  77. static int exynos_mipi_video_phy_power_off(struct phy *phy)
  78. {
  79. struct video_phy_desc *phy_desc = phy_get_drvdata(phy);
  80. struct exynos_mipi_video_phy *state = to_mipi_video_phy(phy_desc);
  81. return __set_phy_state(state, phy_desc->index, 0);
  82. }
  83. static struct phy *exynos_mipi_video_phy_xlate(struct device *dev,
  84. struct of_phandle_args *args)
  85. {
  86. struct exynos_mipi_video_phy *state = dev_get_drvdata(dev);
  87. if (WARN_ON(args->args[0] >= EXYNOS_MIPI_PHYS_NUM))
  88. return ERR_PTR(-ENODEV);
  89. return state->phys[args->args[0]].phy;
  90. }
  91. static struct phy_ops exynos_mipi_video_phy_ops = {
  92. .power_on = exynos_mipi_video_phy_power_on,
  93. .power_off = exynos_mipi_video_phy_power_off,
  94. .owner = THIS_MODULE,
  95. };
  96. static int exynos_mipi_video_phy_probe(struct platform_device *pdev)
  97. {
  98. struct exynos_mipi_video_phy *state;
  99. struct device *dev = &pdev->dev;
  100. struct resource *res;
  101. struct phy_provider *phy_provider;
  102. unsigned int i;
  103. state = devm_kzalloc(dev, sizeof(*state), GFP_KERNEL);
  104. if (!state)
  105. return -ENOMEM;
  106. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  107. state->regs = devm_ioremap_resource(dev, res);
  108. if (IS_ERR(state->regs))
  109. return PTR_ERR(state->regs);
  110. dev_set_drvdata(dev, state);
  111. spin_lock_init(&state->slock);
  112. for (i = 0; i < EXYNOS_MIPI_PHYS_NUM; i++) {
  113. struct phy *phy = devm_phy_create(dev, NULL,
  114. &exynos_mipi_video_phy_ops, NULL);
  115. if (IS_ERR(phy)) {
  116. dev_err(dev, "failed to create PHY %d\n", i);
  117. return PTR_ERR(phy);
  118. }
  119. state->phys[i].phy = phy;
  120. state->phys[i].index = i;
  121. phy_set_drvdata(phy, &state->phys[i]);
  122. }
  123. phy_provider = devm_of_phy_provider_register(dev,
  124. exynos_mipi_video_phy_xlate);
  125. return PTR_ERR_OR_ZERO(phy_provider);
  126. }
  127. static const struct of_device_id exynos_mipi_video_phy_of_match[] = {
  128. { .compatible = "samsung,s5pv210-mipi-video-phy" },
  129. { },
  130. };
  131. MODULE_DEVICE_TABLE(of, exynos_mipi_video_phy_of_match);
  132. static struct platform_driver exynos_mipi_video_phy_driver = {
  133. .probe = exynos_mipi_video_phy_probe,
  134. .driver = {
  135. .of_match_table = exynos_mipi_video_phy_of_match,
  136. .name = "exynos-mipi-video-phy",
  137. }
  138. };
  139. module_platform_driver(exynos_mipi_video_phy_driver);
  140. MODULE_DESCRIPTION("Samsung S5P/EXYNOS SoC MIPI CSI-2/DSI PHY driver");
  141. MODULE_AUTHOR("Sylwester Nawrocki <s.nawrocki@samsung.com>");
  142. MODULE_LICENSE("GPL v2");