iwl-nvm-parse.c 21 KB

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  1. /******************************************************************************
  2. *
  3. * This file is provided under a dual BSD/GPLv2 license. When using or
  4. * redistributing this file, you may do so under either license.
  5. *
  6. * GPL LICENSE SUMMARY
  7. *
  8. * Copyright(c) 2008 - 2014 Intel Corporation. All rights reserved.
  9. * Copyright(c) 2013 - 2014 Intel Mobile Communications GmbH
  10. *
  11. * This program is free software; you can redistribute it and/or modify
  12. * it under the terms of version 2 of the GNU General Public License as
  13. * published by the Free Software Foundation.
  14. *
  15. * This program is distributed in the hope that it will be useful, but
  16. * WITHOUT ANY WARRANTY; without even the implied warranty of
  17. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  18. * General Public License for more details.
  19. *
  20. * You should have received a copy of the GNU General Public License
  21. * along with this program; if not, write to the Free Software
  22. * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
  23. * USA
  24. *
  25. * The full GNU General Public License is included in this distribution
  26. * in the file called COPYING.
  27. *
  28. * Contact Information:
  29. * Intel Linux Wireless <ilw@linux.intel.com>
  30. * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  31. *
  32. * BSD LICENSE
  33. *
  34. * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved.
  35. * Copyright(c) 2013 - 2014 Intel Mobile Communications GmbH
  36. * All rights reserved.
  37. *
  38. * Redistribution and use in source and binary forms, with or without
  39. * modification, are permitted provided that the following conditions
  40. * are met:
  41. *
  42. * * Redistributions of source code must retain the above copyright
  43. * notice, this list of conditions and the following disclaimer.
  44. * * Redistributions in binary form must reproduce the above copyright
  45. * notice, this list of conditions and the following disclaimer in
  46. * the documentation and/or other materials provided with the
  47. * distribution.
  48. * * Neither the name Intel Corporation nor the names of its
  49. * contributors may be used to endorse or promote products derived
  50. * from this software without specific prior written permission.
  51. *
  52. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  53. * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  54. * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  55. * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  56. * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  57. * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  58. * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  59. * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  60. * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  61. * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  62. * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  63. *****************************************************************************/
  64. #include <linux/types.h>
  65. #include <linux/slab.h>
  66. #include <linux/export.h>
  67. #include <linux/etherdevice.h>
  68. #include <linux/pci.h>
  69. #include "iwl-drv.h"
  70. #include "iwl-modparams.h"
  71. #include "iwl-nvm-parse.h"
  72. /* NVM offsets (in words) definitions */
  73. enum wkp_nvm_offsets {
  74. /* NVM HW-Section offset (in words) definitions */
  75. HW_ADDR = 0x15,
  76. /* NVM SW-Section offset (in words) definitions */
  77. NVM_SW_SECTION = 0x1C0,
  78. NVM_VERSION = 0,
  79. RADIO_CFG = 1,
  80. SKU = 2,
  81. N_HW_ADDRS = 3,
  82. NVM_CHANNELS = 0x1E0 - NVM_SW_SECTION,
  83. /* NVM calibration section offset (in words) definitions */
  84. NVM_CALIB_SECTION = 0x2B8,
  85. XTAL_CALIB = 0x316 - NVM_CALIB_SECTION
  86. };
  87. enum family_8000_nvm_offsets {
  88. /* NVM HW-Section offset (in words) definitions */
  89. HW_ADDR0_WFPM_FAMILY_8000 = 0x12,
  90. HW_ADDR1_WFPM_FAMILY_8000 = 0x16,
  91. HW_ADDR0_PCIE_FAMILY_8000 = 0x8A,
  92. HW_ADDR1_PCIE_FAMILY_8000 = 0x8E,
  93. MAC_ADDRESS_OVERRIDE_FAMILY_8000 = 1,
  94. /* NVM SW-Section offset (in words) definitions */
  95. NVM_SW_SECTION_FAMILY_8000 = 0x1C0,
  96. NVM_VERSION_FAMILY_8000 = 0,
  97. RADIO_CFG_FAMILY_8000 = 2,
  98. SKU_FAMILY_8000 = 4,
  99. N_HW_ADDRS_FAMILY_8000 = 5,
  100. /* NVM REGULATORY -Section offset (in words) definitions */
  101. NVM_CHANNELS_FAMILY_8000 = 0,
  102. /* NVM calibration section offset (in words) definitions */
  103. NVM_CALIB_SECTION_FAMILY_8000 = 0x2B8,
  104. XTAL_CALIB_FAMILY_8000 = 0x316 - NVM_CALIB_SECTION_FAMILY_8000
  105. };
  106. /* SKU Capabilities (actual values from NVM definition) */
  107. enum nvm_sku_bits {
  108. NVM_SKU_CAP_BAND_24GHZ = BIT(0),
  109. NVM_SKU_CAP_BAND_52GHZ = BIT(1),
  110. NVM_SKU_CAP_11N_ENABLE = BIT(2),
  111. NVM_SKU_CAP_11AC_ENABLE = BIT(3),
  112. };
  113. /*
  114. * These are the channel numbers in the order that they are stored in the NVM
  115. */
  116. static const u8 iwl_nvm_channels[] = {
  117. /* 2.4 GHz */
  118. 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,
  119. /* 5 GHz */
  120. 36, 40, 44 , 48, 52, 56, 60, 64,
  121. 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 144,
  122. 149, 153, 157, 161, 165
  123. };
  124. static const u8 iwl_nvm_channels_family_8000[] = {
  125. /* 2.4 GHz */
  126. 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,
  127. /* 5 GHz */
  128. 36, 40, 44, 48, 52, 56, 60, 64, 68, 72, 76, 80, 84, 88, 92,
  129. 96, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 144,
  130. 149, 153, 157, 161, 165, 169, 173, 177, 181
  131. };
  132. #define IWL_NUM_CHANNELS ARRAY_SIZE(iwl_nvm_channels)
  133. #define IWL_NUM_CHANNELS_FAMILY_8000 ARRAY_SIZE(iwl_nvm_channels_family_8000)
  134. #define NUM_2GHZ_CHANNELS 14
  135. #define NUM_2GHZ_CHANNELS_FAMILY_8000 14
  136. #define FIRST_2GHZ_HT_MINUS 5
  137. #define LAST_2GHZ_HT_PLUS 9
  138. #define LAST_5GHZ_HT 161
  139. /* rate data (static) */
  140. static struct ieee80211_rate iwl_cfg80211_rates[] = {
  141. { .bitrate = 1 * 10, .hw_value = 0, .hw_value_short = 0, },
  142. { .bitrate = 2 * 10, .hw_value = 1, .hw_value_short = 1,
  143. .flags = IEEE80211_RATE_SHORT_PREAMBLE, },
  144. { .bitrate = 5.5 * 10, .hw_value = 2, .hw_value_short = 2,
  145. .flags = IEEE80211_RATE_SHORT_PREAMBLE, },
  146. { .bitrate = 11 * 10, .hw_value = 3, .hw_value_short = 3,
  147. .flags = IEEE80211_RATE_SHORT_PREAMBLE, },
  148. { .bitrate = 6 * 10, .hw_value = 4, .hw_value_short = 4, },
  149. { .bitrate = 9 * 10, .hw_value = 5, .hw_value_short = 5, },
  150. { .bitrate = 12 * 10, .hw_value = 6, .hw_value_short = 6, },
  151. { .bitrate = 18 * 10, .hw_value = 7, .hw_value_short = 7, },
  152. { .bitrate = 24 * 10, .hw_value = 8, .hw_value_short = 8, },
  153. { .bitrate = 36 * 10, .hw_value = 9, .hw_value_short = 9, },
  154. { .bitrate = 48 * 10, .hw_value = 10, .hw_value_short = 10, },
  155. { .bitrate = 54 * 10, .hw_value = 11, .hw_value_short = 11, },
  156. };
  157. #define RATES_24_OFFS 0
  158. #define N_RATES_24 ARRAY_SIZE(iwl_cfg80211_rates)
  159. #define RATES_52_OFFS 4
  160. #define N_RATES_52 (N_RATES_24 - RATES_52_OFFS)
  161. /**
  162. * enum iwl_nvm_channel_flags - channel flags in NVM
  163. * @NVM_CHANNEL_VALID: channel is usable for this SKU/geo
  164. * @NVM_CHANNEL_IBSS: usable as an IBSS channel
  165. * @NVM_CHANNEL_ACTIVE: active scanning allowed
  166. * @NVM_CHANNEL_RADAR: radar detection required
  167. * @NVM_CHANNEL_INDOOR_ONLY: only indoor use is allowed
  168. * @NVM_CHANNEL_GO_CONCURRENT: GO operation is allowed when connected to BSS
  169. * on same channel on 2.4 or same UNII band on 5.2
  170. * @NVM_CHANNEL_WIDE: 20 MHz channel okay (?)
  171. * @NVM_CHANNEL_40MHZ: 40 MHz channel okay (?)
  172. * @NVM_CHANNEL_80MHZ: 80 MHz channel okay (?)
  173. * @NVM_CHANNEL_160MHZ: 160 MHz channel okay (?)
  174. */
  175. enum iwl_nvm_channel_flags {
  176. NVM_CHANNEL_VALID = BIT(0),
  177. NVM_CHANNEL_IBSS = BIT(1),
  178. NVM_CHANNEL_ACTIVE = BIT(3),
  179. NVM_CHANNEL_RADAR = BIT(4),
  180. NVM_CHANNEL_INDOOR_ONLY = BIT(5),
  181. NVM_CHANNEL_GO_CONCURRENT = BIT(6),
  182. NVM_CHANNEL_WIDE = BIT(8),
  183. NVM_CHANNEL_40MHZ = BIT(9),
  184. NVM_CHANNEL_80MHZ = BIT(10),
  185. NVM_CHANNEL_160MHZ = BIT(11),
  186. };
  187. #define CHECK_AND_PRINT_I(x) \
  188. ((ch_flags & NVM_CHANNEL_##x) ? # x " " : "")
  189. static int iwl_init_channel_map(struct device *dev, const struct iwl_cfg *cfg,
  190. struct iwl_nvm_data *data,
  191. const __le16 * const nvm_ch_flags)
  192. {
  193. int ch_idx;
  194. int n_channels = 0;
  195. struct ieee80211_channel *channel;
  196. u16 ch_flags;
  197. bool is_5ghz;
  198. int num_of_ch, num_2ghz_channels;
  199. const u8 *nvm_chan;
  200. if (cfg->device_family != IWL_DEVICE_FAMILY_8000) {
  201. num_of_ch = IWL_NUM_CHANNELS;
  202. nvm_chan = &iwl_nvm_channels[0];
  203. num_2ghz_channels = NUM_2GHZ_CHANNELS;
  204. } else {
  205. num_of_ch = IWL_NUM_CHANNELS_FAMILY_8000;
  206. nvm_chan = &iwl_nvm_channels_family_8000[0];
  207. num_2ghz_channels = NUM_2GHZ_CHANNELS_FAMILY_8000;
  208. }
  209. for (ch_idx = 0; ch_idx < num_of_ch; ch_idx++) {
  210. ch_flags = __le16_to_cpup(nvm_ch_flags + ch_idx);
  211. if (ch_idx >= num_2ghz_channels &&
  212. !data->sku_cap_band_52GHz_enable)
  213. ch_flags &= ~NVM_CHANNEL_VALID;
  214. if (!(ch_flags & NVM_CHANNEL_VALID)) {
  215. IWL_DEBUG_EEPROM(dev,
  216. "Ch. %d Flags %x [%sGHz] - No traffic\n",
  217. nvm_chan[ch_idx],
  218. ch_flags,
  219. (ch_idx >= num_2ghz_channels) ?
  220. "5.2" : "2.4");
  221. continue;
  222. }
  223. channel = &data->channels[n_channels];
  224. n_channels++;
  225. channel->hw_value = nvm_chan[ch_idx];
  226. channel->band = (ch_idx < num_2ghz_channels) ?
  227. IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
  228. channel->center_freq =
  229. ieee80211_channel_to_frequency(
  230. channel->hw_value, channel->band);
  231. /* TODO: Need to be dependent to the NVM */
  232. channel->flags = IEEE80211_CHAN_NO_HT40;
  233. if (ch_idx < num_2ghz_channels &&
  234. (ch_flags & NVM_CHANNEL_40MHZ)) {
  235. if (nvm_chan[ch_idx] <= LAST_2GHZ_HT_PLUS)
  236. channel->flags &= ~IEEE80211_CHAN_NO_HT40PLUS;
  237. if (nvm_chan[ch_idx] >= FIRST_2GHZ_HT_MINUS)
  238. channel->flags &= ~IEEE80211_CHAN_NO_HT40MINUS;
  239. } else if (nvm_chan[ch_idx] <= LAST_5GHZ_HT &&
  240. (ch_flags & NVM_CHANNEL_40MHZ)) {
  241. if ((ch_idx - num_2ghz_channels) % 2 == 0)
  242. channel->flags &= ~IEEE80211_CHAN_NO_HT40PLUS;
  243. else
  244. channel->flags &= ~IEEE80211_CHAN_NO_HT40MINUS;
  245. }
  246. if (!(ch_flags & NVM_CHANNEL_80MHZ))
  247. channel->flags |= IEEE80211_CHAN_NO_80MHZ;
  248. if (!(ch_flags & NVM_CHANNEL_160MHZ))
  249. channel->flags |= IEEE80211_CHAN_NO_160MHZ;
  250. if (!(ch_flags & NVM_CHANNEL_IBSS))
  251. channel->flags |= IEEE80211_CHAN_NO_IR;
  252. if (!(ch_flags & NVM_CHANNEL_ACTIVE))
  253. channel->flags |= IEEE80211_CHAN_NO_IR;
  254. if (ch_flags & NVM_CHANNEL_RADAR)
  255. channel->flags |= IEEE80211_CHAN_RADAR;
  256. if (ch_flags & NVM_CHANNEL_INDOOR_ONLY)
  257. channel->flags |= IEEE80211_CHAN_INDOOR_ONLY;
  258. /* Set the GO concurrent flag only in case that NO_IR is set.
  259. * Otherwise it is meaningless
  260. */
  261. if ((ch_flags & NVM_CHANNEL_GO_CONCURRENT) &&
  262. (channel->flags & IEEE80211_CHAN_NO_IR))
  263. channel->flags |= IEEE80211_CHAN_GO_CONCURRENT;
  264. /* Initialize regulatory-based run-time data */
  265. /*
  266. * Default value - highest tx power value. max_power
  267. * is not used in mvm, and is used for backwards compatibility
  268. */
  269. channel->max_power = IWL_DEFAULT_MAX_TX_POWER;
  270. is_5ghz = channel->band == IEEE80211_BAND_5GHZ;
  271. IWL_DEBUG_EEPROM(dev,
  272. "Ch. %d [%sGHz] %s%s%s%s%s%s%s(0x%02x %ddBm): Ad-Hoc %ssupported\n",
  273. channel->hw_value,
  274. is_5ghz ? "5.2" : "2.4",
  275. CHECK_AND_PRINT_I(VALID),
  276. CHECK_AND_PRINT_I(IBSS),
  277. CHECK_AND_PRINT_I(ACTIVE),
  278. CHECK_AND_PRINT_I(RADAR),
  279. CHECK_AND_PRINT_I(WIDE),
  280. CHECK_AND_PRINT_I(INDOOR_ONLY),
  281. CHECK_AND_PRINT_I(GO_CONCURRENT),
  282. ch_flags,
  283. channel->max_power,
  284. ((ch_flags & NVM_CHANNEL_IBSS) &&
  285. !(ch_flags & NVM_CHANNEL_RADAR))
  286. ? "" : "not ");
  287. }
  288. return n_channels;
  289. }
  290. static void iwl_init_vht_hw_capab(const struct iwl_cfg *cfg,
  291. struct iwl_nvm_data *data,
  292. struct ieee80211_sta_vht_cap *vht_cap,
  293. u8 tx_chains, u8 rx_chains)
  294. {
  295. int num_rx_ants = num_of_ant(rx_chains);
  296. int num_tx_ants = num_of_ant(tx_chains);
  297. vht_cap->vht_supported = true;
  298. vht_cap->cap = IEEE80211_VHT_CAP_SHORT_GI_80 |
  299. IEEE80211_VHT_CAP_RXSTBC_1 |
  300. IEEE80211_VHT_CAP_SU_BEAMFORMEE_CAPABLE |
  301. 3 << IEEE80211_VHT_CAP_BEAMFORMEE_STS_SHIFT |
  302. 7 << IEEE80211_VHT_CAP_MAX_A_MPDU_LENGTH_EXPONENT_SHIFT;
  303. if (cfg->ht_params->ldpc)
  304. vht_cap->cap |= IEEE80211_VHT_CAP_RXLDPC;
  305. if (num_tx_ants > 1)
  306. vht_cap->cap |= IEEE80211_VHT_CAP_TXSTBC;
  307. else
  308. vht_cap->cap |= IEEE80211_VHT_CAP_TX_ANTENNA_PATTERN;
  309. if (iwlwifi_mod_params.amsdu_size_8K)
  310. vht_cap->cap |= IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_7991;
  311. vht_cap->vht_mcs.rx_mcs_map =
  312. cpu_to_le16(IEEE80211_VHT_MCS_SUPPORT_0_9 << 0 |
  313. IEEE80211_VHT_MCS_SUPPORT_0_9 << 2 |
  314. IEEE80211_VHT_MCS_NOT_SUPPORTED << 4 |
  315. IEEE80211_VHT_MCS_NOT_SUPPORTED << 6 |
  316. IEEE80211_VHT_MCS_NOT_SUPPORTED << 8 |
  317. IEEE80211_VHT_MCS_NOT_SUPPORTED << 10 |
  318. IEEE80211_VHT_MCS_NOT_SUPPORTED << 12 |
  319. IEEE80211_VHT_MCS_NOT_SUPPORTED << 14);
  320. if (num_rx_ants == 1 || cfg->rx_with_siso_diversity) {
  321. vht_cap->cap |= IEEE80211_VHT_CAP_RX_ANTENNA_PATTERN;
  322. /* this works because NOT_SUPPORTED == 3 */
  323. vht_cap->vht_mcs.rx_mcs_map |=
  324. cpu_to_le16(IEEE80211_VHT_MCS_NOT_SUPPORTED << 2);
  325. }
  326. vht_cap->vht_mcs.tx_mcs_map = vht_cap->vht_mcs.rx_mcs_map;
  327. }
  328. static void iwl_init_sbands(struct device *dev, const struct iwl_cfg *cfg,
  329. struct iwl_nvm_data *data,
  330. const __le16 *ch_section, bool enable_vht,
  331. u8 tx_chains, u8 rx_chains)
  332. {
  333. int n_channels;
  334. int n_used = 0;
  335. struct ieee80211_supported_band *sband;
  336. if (cfg->device_family != IWL_DEVICE_FAMILY_8000)
  337. n_channels = iwl_init_channel_map(
  338. dev, cfg, data,
  339. &ch_section[NVM_CHANNELS]);
  340. else
  341. n_channels = iwl_init_channel_map(
  342. dev, cfg, data,
  343. &ch_section[NVM_CHANNELS_FAMILY_8000]);
  344. sband = &data->bands[IEEE80211_BAND_2GHZ];
  345. sband->band = IEEE80211_BAND_2GHZ;
  346. sband->bitrates = &iwl_cfg80211_rates[RATES_24_OFFS];
  347. sband->n_bitrates = N_RATES_24;
  348. n_used += iwl_init_sband_channels(data, sband, n_channels,
  349. IEEE80211_BAND_2GHZ);
  350. iwl_init_ht_hw_capab(cfg, data, &sband->ht_cap, IEEE80211_BAND_2GHZ,
  351. tx_chains, rx_chains);
  352. sband = &data->bands[IEEE80211_BAND_5GHZ];
  353. sband->band = IEEE80211_BAND_5GHZ;
  354. sband->bitrates = &iwl_cfg80211_rates[RATES_52_OFFS];
  355. sband->n_bitrates = N_RATES_52;
  356. n_used += iwl_init_sband_channels(data, sband, n_channels,
  357. IEEE80211_BAND_5GHZ);
  358. iwl_init_ht_hw_capab(cfg, data, &sband->ht_cap, IEEE80211_BAND_5GHZ,
  359. tx_chains, rx_chains);
  360. if (enable_vht)
  361. iwl_init_vht_hw_capab(cfg, data, &sband->vht_cap,
  362. tx_chains, rx_chains);
  363. if (n_channels != n_used)
  364. IWL_ERR_DEV(dev, "NVM: used only %d of %d channels\n",
  365. n_used, n_channels);
  366. }
  367. static int iwl_get_sku(const struct iwl_cfg *cfg,
  368. const __le16 *nvm_sw)
  369. {
  370. if (cfg->device_family != IWL_DEVICE_FAMILY_8000)
  371. return le16_to_cpup(nvm_sw + SKU);
  372. else
  373. return le32_to_cpup((__le32 *)(nvm_sw + SKU_FAMILY_8000));
  374. }
  375. static int iwl_get_nvm_version(const struct iwl_cfg *cfg,
  376. const __le16 *nvm_sw)
  377. {
  378. if (cfg->device_family != IWL_DEVICE_FAMILY_8000)
  379. return le16_to_cpup(nvm_sw + NVM_VERSION);
  380. else
  381. return le32_to_cpup((__le32 *)(nvm_sw +
  382. NVM_VERSION_FAMILY_8000));
  383. }
  384. static int iwl_get_radio_cfg(const struct iwl_cfg *cfg,
  385. const __le16 *nvm_sw)
  386. {
  387. if (cfg->device_family != IWL_DEVICE_FAMILY_8000)
  388. return le16_to_cpup(nvm_sw + RADIO_CFG);
  389. else
  390. return le32_to_cpup((__le32 *)(nvm_sw + RADIO_CFG_FAMILY_8000));
  391. }
  392. #define N_HW_ADDRS_MASK_FAMILY_8000 0xF
  393. static int iwl_get_n_hw_addrs(const struct iwl_cfg *cfg,
  394. const __le16 *nvm_sw)
  395. {
  396. if (cfg->device_family != IWL_DEVICE_FAMILY_8000)
  397. return le16_to_cpup(nvm_sw + N_HW_ADDRS);
  398. else
  399. return le32_to_cpup((__le32 *)(nvm_sw + N_HW_ADDRS_FAMILY_8000))
  400. & N_HW_ADDRS_MASK_FAMILY_8000;
  401. }
  402. static void iwl_set_radio_cfg(const struct iwl_cfg *cfg,
  403. struct iwl_nvm_data *data,
  404. u32 radio_cfg)
  405. {
  406. if (cfg->device_family != IWL_DEVICE_FAMILY_8000) {
  407. data->radio_cfg_type = NVM_RF_CFG_TYPE_MSK(radio_cfg);
  408. data->radio_cfg_step = NVM_RF_CFG_STEP_MSK(radio_cfg);
  409. data->radio_cfg_dash = NVM_RF_CFG_DASH_MSK(radio_cfg);
  410. data->radio_cfg_pnum = NVM_RF_CFG_PNUM_MSK(radio_cfg);
  411. return;
  412. }
  413. /* set the radio configuration for family 8000 */
  414. data->radio_cfg_type = NVM_RF_CFG_TYPE_MSK_FAMILY_8000(radio_cfg);
  415. data->radio_cfg_step = NVM_RF_CFG_STEP_MSK_FAMILY_8000(radio_cfg);
  416. data->radio_cfg_dash = NVM_RF_CFG_DASH_MSK_FAMILY_8000(radio_cfg);
  417. data->radio_cfg_pnum = NVM_RF_CFG_FLAVOR_MSK_FAMILY_8000(radio_cfg);
  418. }
  419. static void iwl_set_hw_address(const struct iwl_cfg *cfg,
  420. struct iwl_nvm_data *data,
  421. const __le16 *nvm_sec)
  422. {
  423. const u8 *hw_addr = (const u8 *)(nvm_sec + HW_ADDR);
  424. /* The byte order is little endian 16 bit, meaning 214365 */
  425. data->hw_addr[0] = hw_addr[1];
  426. data->hw_addr[1] = hw_addr[0];
  427. data->hw_addr[2] = hw_addr[3];
  428. data->hw_addr[3] = hw_addr[2];
  429. data->hw_addr[4] = hw_addr[5];
  430. data->hw_addr[5] = hw_addr[4];
  431. }
  432. static void iwl_set_hw_address_family_8000(struct device *dev,
  433. const struct iwl_cfg *cfg,
  434. struct iwl_nvm_data *data,
  435. const __le16 *mac_override,
  436. const __le16 *nvm_hw)
  437. {
  438. const u8 *hw_addr;
  439. if (mac_override) {
  440. hw_addr = (const u8 *)(mac_override +
  441. MAC_ADDRESS_OVERRIDE_FAMILY_8000);
  442. /* The byte order is little endian 16 bit, meaning 214365 */
  443. data->hw_addr[0] = hw_addr[1];
  444. data->hw_addr[1] = hw_addr[0];
  445. data->hw_addr[2] = hw_addr[3];
  446. data->hw_addr[3] = hw_addr[2];
  447. data->hw_addr[4] = hw_addr[5];
  448. data->hw_addr[5] = hw_addr[4];
  449. if (is_valid_ether_addr(data->hw_addr))
  450. return;
  451. IWL_ERR_DEV(dev,
  452. "mac address from nvm override section is not valid\n");
  453. }
  454. if (nvm_hw) {
  455. /* read the MAC address from OTP */
  456. if (!dev_is_pci(dev) || (data->nvm_version < 0xE08)) {
  457. /* read the mac address from the WFPM location */
  458. hw_addr = (const u8 *)(nvm_hw +
  459. HW_ADDR0_WFPM_FAMILY_8000);
  460. data->hw_addr[0] = hw_addr[3];
  461. data->hw_addr[1] = hw_addr[2];
  462. data->hw_addr[2] = hw_addr[1];
  463. data->hw_addr[3] = hw_addr[0];
  464. hw_addr = (const u8 *)(nvm_hw +
  465. HW_ADDR1_WFPM_FAMILY_8000);
  466. data->hw_addr[4] = hw_addr[1];
  467. data->hw_addr[5] = hw_addr[0];
  468. } else if ((data->nvm_version >= 0xE08) &&
  469. (data->nvm_version < 0xE0B)) {
  470. /* read "reverse order" from the PCIe location */
  471. hw_addr = (const u8 *)(nvm_hw +
  472. HW_ADDR0_PCIE_FAMILY_8000);
  473. data->hw_addr[5] = hw_addr[2];
  474. data->hw_addr[4] = hw_addr[1];
  475. data->hw_addr[3] = hw_addr[0];
  476. hw_addr = (const u8 *)(nvm_hw +
  477. HW_ADDR1_PCIE_FAMILY_8000);
  478. data->hw_addr[2] = hw_addr[3];
  479. data->hw_addr[1] = hw_addr[2];
  480. data->hw_addr[0] = hw_addr[1];
  481. } else {
  482. /* read from the PCIe location */
  483. hw_addr = (const u8 *)(nvm_hw +
  484. HW_ADDR0_PCIE_FAMILY_8000);
  485. data->hw_addr[5] = hw_addr[0];
  486. data->hw_addr[4] = hw_addr[1];
  487. data->hw_addr[3] = hw_addr[2];
  488. hw_addr = (const u8 *)(nvm_hw +
  489. HW_ADDR1_PCIE_FAMILY_8000);
  490. data->hw_addr[2] = hw_addr[1];
  491. data->hw_addr[1] = hw_addr[2];
  492. data->hw_addr[0] = hw_addr[3];
  493. }
  494. if (!is_valid_ether_addr(data->hw_addr))
  495. IWL_ERR_DEV(dev,
  496. "mac address from hw section is not valid\n");
  497. return;
  498. }
  499. IWL_ERR_DEV(dev, "mac address is not found\n");
  500. }
  501. struct iwl_nvm_data *
  502. iwl_parse_nvm_data(struct device *dev, const struct iwl_cfg *cfg,
  503. const __le16 *nvm_hw, const __le16 *nvm_sw,
  504. const __le16 *nvm_calib, const __le16 *regulatory,
  505. const __le16 *mac_override, u8 tx_chains, u8 rx_chains)
  506. {
  507. struct iwl_nvm_data *data;
  508. u32 sku;
  509. u32 radio_cfg;
  510. if (cfg->device_family != IWL_DEVICE_FAMILY_8000)
  511. data = kzalloc(sizeof(*data) +
  512. sizeof(struct ieee80211_channel) *
  513. IWL_NUM_CHANNELS,
  514. GFP_KERNEL);
  515. else
  516. data = kzalloc(sizeof(*data) +
  517. sizeof(struct ieee80211_channel) *
  518. IWL_NUM_CHANNELS_FAMILY_8000,
  519. GFP_KERNEL);
  520. if (!data)
  521. return NULL;
  522. data->nvm_version = iwl_get_nvm_version(cfg, nvm_sw);
  523. radio_cfg = iwl_get_radio_cfg(cfg, nvm_sw);
  524. iwl_set_radio_cfg(cfg, data, radio_cfg);
  525. sku = iwl_get_sku(cfg, nvm_sw);
  526. data->sku_cap_band_24GHz_enable = sku & NVM_SKU_CAP_BAND_24GHZ;
  527. data->sku_cap_band_52GHz_enable = sku & NVM_SKU_CAP_BAND_52GHZ;
  528. data->sku_cap_11n_enable = sku & NVM_SKU_CAP_11N_ENABLE;
  529. data->sku_cap_11ac_enable = sku & NVM_SKU_CAP_11AC_ENABLE;
  530. if (iwlwifi_mod_params.disable_11n & IWL_DISABLE_HT_ALL)
  531. data->sku_cap_11n_enable = false;
  532. data->n_hw_addrs = iwl_get_n_hw_addrs(cfg, nvm_sw);
  533. if (cfg->device_family != IWL_DEVICE_FAMILY_8000) {
  534. /* Checking for required sections */
  535. if (!nvm_calib) {
  536. IWL_ERR_DEV(dev,
  537. "Can't parse empty Calib NVM sections\n");
  538. kfree(data);
  539. return NULL;
  540. }
  541. /* in family 8000 Xtal calibration values moved to OTP */
  542. data->xtal_calib[0] = *(nvm_calib + XTAL_CALIB);
  543. data->xtal_calib[1] = *(nvm_calib + XTAL_CALIB + 1);
  544. }
  545. if (cfg->device_family != IWL_DEVICE_FAMILY_8000) {
  546. iwl_set_hw_address(cfg, data, nvm_hw);
  547. iwl_init_sbands(dev, cfg, data, nvm_sw,
  548. sku & NVM_SKU_CAP_11AC_ENABLE, tx_chains,
  549. rx_chains);
  550. } else {
  551. /* MAC address in family 8000 */
  552. iwl_set_hw_address_family_8000(dev, cfg, data, mac_override,
  553. nvm_hw);
  554. iwl_init_sbands(dev, cfg, data, regulatory,
  555. sku & NVM_SKU_CAP_11AC_ENABLE, tx_chains,
  556. rx_chains);
  557. }
  558. data->calib_version = 255;
  559. return data;
  560. }
  561. IWL_EXPORT_SYMBOL(iwl_parse_nvm_data);