cpsw-phy-sel.c 5.0 KB

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  1. /* Texas Instruments Ethernet Switch Driver
  2. *
  3. * Copyright (C) 2013 Texas Instruments
  4. *
  5. * This program is free software; you can redistribute it and/or
  6. * modify it under the terms of the GNU General Public License
  7. * version 2 as published by the Free Software Foundation.
  8. *
  9. * This program is distributed "as is" WITHOUT ANY WARRANTY of any
  10. * kind, whether express or implied; without even the implied warranty
  11. * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  12. * GNU General Public License for more details.
  13. */
  14. #include <linux/platform_device.h>
  15. #include <linux/module.h>
  16. #include <linux/netdevice.h>
  17. #include <linux/phy.h>
  18. #include <linux/of.h>
  19. #include <linux/of_device.h>
  20. #include "cpsw.h"
  21. /* AM33xx SoC specific definitions for the CONTROL port */
  22. #define AM33XX_GMII_SEL_MODE_MII 0
  23. #define AM33XX_GMII_SEL_MODE_RMII 1
  24. #define AM33XX_GMII_SEL_MODE_RGMII 2
  25. #define AM33XX_GMII_SEL_RMII2_IO_CLK_EN BIT(7)
  26. #define AM33XX_GMII_SEL_RMII1_IO_CLK_EN BIT(6)
  27. #define GMII_SEL_MODE_MASK 0x3
  28. struct cpsw_phy_sel_priv {
  29. struct device *dev;
  30. u32 __iomem *gmii_sel;
  31. bool rmii_clock_external;
  32. void (*cpsw_phy_sel)(struct cpsw_phy_sel_priv *priv,
  33. phy_interface_t phy_mode, int slave);
  34. };
  35. static void cpsw_gmii_sel_am3352(struct cpsw_phy_sel_priv *priv,
  36. phy_interface_t phy_mode, int slave)
  37. {
  38. u32 reg;
  39. u32 mask;
  40. u32 mode = 0;
  41. reg = readl(priv->gmii_sel);
  42. switch (phy_mode) {
  43. case PHY_INTERFACE_MODE_RMII:
  44. mode = AM33XX_GMII_SEL_MODE_RMII;
  45. break;
  46. case PHY_INTERFACE_MODE_RGMII:
  47. case PHY_INTERFACE_MODE_RGMII_ID:
  48. case PHY_INTERFACE_MODE_RGMII_RXID:
  49. case PHY_INTERFACE_MODE_RGMII_TXID:
  50. mode = AM33XX_GMII_SEL_MODE_RGMII;
  51. break;
  52. case PHY_INTERFACE_MODE_MII:
  53. default:
  54. mode = AM33XX_GMII_SEL_MODE_MII;
  55. break;
  56. };
  57. mask = GMII_SEL_MODE_MASK << (slave * 2) | BIT(slave + 6);
  58. mode <<= slave * 2;
  59. if (priv->rmii_clock_external) {
  60. if (slave == 0)
  61. mode |= AM33XX_GMII_SEL_RMII1_IO_CLK_EN;
  62. else
  63. mode |= AM33XX_GMII_SEL_RMII2_IO_CLK_EN;
  64. }
  65. reg &= ~mask;
  66. reg |= mode;
  67. writel(reg, priv->gmii_sel);
  68. }
  69. static void cpsw_gmii_sel_dra7xx(struct cpsw_phy_sel_priv *priv,
  70. phy_interface_t phy_mode, int slave)
  71. {
  72. u32 reg;
  73. u32 mask;
  74. u32 mode = 0;
  75. reg = readl(priv->gmii_sel);
  76. switch (phy_mode) {
  77. case PHY_INTERFACE_MODE_RMII:
  78. mode = AM33XX_GMII_SEL_MODE_RMII;
  79. break;
  80. case PHY_INTERFACE_MODE_RGMII:
  81. case PHY_INTERFACE_MODE_RGMII_ID:
  82. case PHY_INTERFACE_MODE_RGMII_RXID:
  83. case PHY_INTERFACE_MODE_RGMII_TXID:
  84. mode = AM33XX_GMII_SEL_MODE_RGMII;
  85. break;
  86. case PHY_INTERFACE_MODE_MII:
  87. default:
  88. mode = AM33XX_GMII_SEL_MODE_MII;
  89. break;
  90. };
  91. switch (slave) {
  92. case 0:
  93. mask = GMII_SEL_MODE_MASK;
  94. break;
  95. case 1:
  96. mask = GMII_SEL_MODE_MASK << 4;
  97. mode <<= 4;
  98. break;
  99. default:
  100. dev_err(priv->dev, "invalid slave number...\n");
  101. return;
  102. }
  103. if (priv->rmii_clock_external)
  104. dev_err(priv->dev, "RMII External clock is not supported\n");
  105. reg &= ~mask;
  106. reg |= mode;
  107. writel(reg, priv->gmii_sel);
  108. }
  109. static struct platform_driver cpsw_phy_sel_driver;
  110. static int match(struct device *dev, void *data)
  111. {
  112. struct device_node *node = (struct device_node *)data;
  113. return dev->of_node == node &&
  114. dev->driver == &cpsw_phy_sel_driver.driver;
  115. }
  116. void cpsw_phy_sel(struct device *dev, phy_interface_t phy_mode, int slave)
  117. {
  118. struct device_node *node;
  119. struct cpsw_phy_sel_priv *priv;
  120. node = of_get_child_by_name(dev->of_node, "cpsw-phy-sel");
  121. if (!node) {
  122. dev_err(dev, "Phy mode driver DT not found\n");
  123. return;
  124. }
  125. dev = bus_find_device(&platform_bus_type, NULL, node, match);
  126. priv = dev_get_drvdata(dev);
  127. priv->cpsw_phy_sel(priv, phy_mode, slave);
  128. }
  129. EXPORT_SYMBOL_GPL(cpsw_phy_sel);
  130. static const struct of_device_id cpsw_phy_sel_id_table[] = {
  131. {
  132. .compatible = "ti,am3352-cpsw-phy-sel",
  133. .data = &cpsw_gmii_sel_am3352,
  134. },
  135. {
  136. .compatible = "ti,dra7xx-cpsw-phy-sel",
  137. .data = &cpsw_gmii_sel_dra7xx,
  138. },
  139. {
  140. .compatible = "ti,am43xx-cpsw-phy-sel",
  141. .data = &cpsw_gmii_sel_am3352,
  142. },
  143. {}
  144. };
  145. MODULE_DEVICE_TABLE(of, cpsw_phy_sel_id_table);
  146. static int cpsw_phy_sel_probe(struct platform_device *pdev)
  147. {
  148. struct resource *res;
  149. const struct of_device_id *of_id;
  150. struct cpsw_phy_sel_priv *priv;
  151. of_id = of_match_node(cpsw_phy_sel_id_table, pdev->dev.of_node);
  152. if (!of_id)
  153. return -EINVAL;
  154. priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
  155. if (!priv) {
  156. dev_err(&pdev->dev, "unable to alloc memory for cpsw phy sel\n");
  157. return -ENOMEM;
  158. }
  159. priv->dev = &pdev->dev;
  160. priv->cpsw_phy_sel = of_id->data;
  161. res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "gmii-sel");
  162. priv->gmii_sel = devm_ioremap_resource(&pdev->dev, res);
  163. if (IS_ERR(priv->gmii_sel))
  164. return PTR_ERR(priv->gmii_sel);
  165. if (of_find_property(pdev->dev.of_node, "rmii-clock-ext", NULL))
  166. priv->rmii_clock_external = true;
  167. dev_set_drvdata(&pdev->dev, priv);
  168. return 0;
  169. }
  170. static struct platform_driver cpsw_phy_sel_driver = {
  171. .probe = cpsw_phy_sel_probe,
  172. .driver = {
  173. .name = "cpsw-phy-sel",
  174. .of_match_table = cpsw_phy_sel_id_table,
  175. },
  176. };
  177. module_platform_driver(cpsw_phy_sel_driver);
  178. MODULE_AUTHOR("Mugunthan V N <mugunthanvnm@ti.com>");
  179. MODULE_LICENSE("GPL v2");