carma-fpga-program.c 27 KB

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  1. /*
  2. * CARMA Board DATA-FPGA Programmer
  3. *
  4. * Copyright (c) 2009-2011 Ira W. Snyder <iws@ovro.caltech.edu>
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms of the GNU General Public License as published by the
  8. * Free Software Foundation; either version 2 of the License, or (at your
  9. * option) any later version.
  10. */
  11. #include <linux/dma-mapping.h>
  12. #include <linux/of_address.h>
  13. #include <linux/of_irq.h>
  14. #include <linux/of_platform.h>
  15. #include <linux/completion.h>
  16. #include <linux/miscdevice.h>
  17. #include <linux/dmaengine.h>
  18. #include <linux/fsldma.h>
  19. #include <linux/interrupt.h>
  20. #include <linux/highmem.h>
  21. #include <linux/kernel.h>
  22. #include <linux/module.h>
  23. #include <linux/mutex.h>
  24. #include <linux/delay.h>
  25. #include <linux/init.h>
  26. #include <linux/leds.h>
  27. #include <linux/slab.h>
  28. #include <linux/kref.h>
  29. #include <linux/fs.h>
  30. #include <linux/io.h>
  31. #include <media/videobuf-dma-sg.h>
  32. /* MPC8349EMDS specific get_immrbase() */
  33. #include <sysdev/fsl_soc.h>
  34. static const char drv_name[] = "carma-fpga-program";
  35. /*
  36. * Firmware images are always this exact size
  37. *
  38. * 12849552 bytes for a CARMA Digitizer Board (EP2S90 FPGAs)
  39. * 18662880 bytes for a CARMA Correlator Board (EP2S130 FPGAs)
  40. */
  41. #define FW_SIZE_EP2S90 12849552
  42. #define FW_SIZE_EP2S130 18662880
  43. struct fpga_dev {
  44. struct miscdevice miscdev;
  45. /* Reference count */
  46. struct kref ref;
  47. /* Device Registers */
  48. struct device *dev;
  49. void __iomem *regs;
  50. void __iomem *immr;
  51. /* Freescale DMA Device */
  52. struct dma_chan *chan;
  53. /* Interrupts */
  54. int irq, status;
  55. struct completion completion;
  56. /* FPGA Bitfile */
  57. struct mutex lock;
  58. struct videobuf_dmabuf vb;
  59. bool vb_allocated;
  60. /* max size and written bytes */
  61. size_t fw_size;
  62. size_t bytes;
  63. };
  64. /*
  65. * FPGA Bitfile Helpers
  66. */
  67. /**
  68. * fpga_drop_firmware_data() - drop the bitfile image from memory
  69. * @priv: the driver's private data structure
  70. *
  71. * LOCKING: must hold priv->lock
  72. */
  73. static void fpga_drop_firmware_data(struct fpga_dev *priv)
  74. {
  75. videobuf_dma_free(&priv->vb);
  76. priv->vb_allocated = false;
  77. priv->bytes = 0;
  78. }
  79. /*
  80. * Private Data Reference Count
  81. */
  82. static void fpga_dev_remove(struct kref *ref)
  83. {
  84. struct fpga_dev *priv = container_of(ref, struct fpga_dev, ref);
  85. /* free any firmware image that was not programmed */
  86. fpga_drop_firmware_data(priv);
  87. mutex_destroy(&priv->lock);
  88. kfree(priv);
  89. }
  90. /*
  91. * LED Trigger (could be a seperate module)
  92. */
  93. /*
  94. * NOTE: this whole thing does have the problem that whenever the led's are
  95. * NOTE: first set to use the fpga trigger, they could be in the wrong state
  96. */
  97. DEFINE_LED_TRIGGER(ledtrig_fpga);
  98. static void ledtrig_fpga_programmed(bool enabled)
  99. {
  100. if (enabled)
  101. led_trigger_event(ledtrig_fpga, LED_FULL);
  102. else
  103. led_trigger_event(ledtrig_fpga, LED_OFF);
  104. }
  105. /*
  106. * FPGA Register Helpers
  107. */
  108. /* Register Definitions */
  109. #define FPGA_CONFIG_CONTROL 0x40
  110. #define FPGA_CONFIG_STATUS 0x44
  111. #define FPGA_CONFIG_FIFO_SIZE 0x48
  112. #define FPGA_CONFIG_FIFO_USED 0x4C
  113. #define FPGA_CONFIG_TOTAL_BYTE_COUNT 0x50
  114. #define FPGA_CONFIG_CUR_BYTE_COUNT 0x54
  115. #define FPGA_FIFO_ADDRESS 0x3000
  116. static int fpga_fifo_size(void __iomem *regs)
  117. {
  118. return ioread32be(regs + FPGA_CONFIG_FIFO_SIZE);
  119. }
  120. #define CFG_STATUS_ERR_MASK 0xfffe
  121. static int fpga_config_error(void __iomem *regs)
  122. {
  123. return ioread32be(regs + FPGA_CONFIG_STATUS) & CFG_STATUS_ERR_MASK;
  124. }
  125. static int fpga_fifo_empty(void __iomem *regs)
  126. {
  127. return ioread32be(regs + FPGA_CONFIG_FIFO_USED) == 0;
  128. }
  129. static void fpga_fifo_write(void __iomem *regs, u32 val)
  130. {
  131. iowrite32be(val, regs + FPGA_FIFO_ADDRESS);
  132. }
  133. static void fpga_set_byte_count(void __iomem *regs, u32 count)
  134. {
  135. iowrite32be(count, regs + FPGA_CONFIG_TOTAL_BYTE_COUNT);
  136. }
  137. #define CFG_CTL_ENABLE (1 << 0)
  138. #define CFG_CTL_RESET (1 << 1)
  139. #define CFG_CTL_DMA (1 << 2)
  140. static void fpga_programmer_enable(struct fpga_dev *priv, bool dma)
  141. {
  142. u32 val;
  143. val = (dma) ? (CFG_CTL_ENABLE | CFG_CTL_DMA) : CFG_CTL_ENABLE;
  144. iowrite32be(val, priv->regs + FPGA_CONFIG_CONTROL);
  145. }
  146. static void fpga_programmer_disable(struct fpga_dev *priv)
  147. {
  148. iowrite32be(0x0, priv->regs + FPGA_CONFIG_CONTROL);
  149. }
  150. static void fpga_dump_registers(struct fpga_dev *priv)
  151. {
  152. u32 control, status, size, used, total, curr;
  153. /* good status: do nothing */
  154. if (priv->status == 0)
  155. return;
  156. /* Dump all status registers */
  157. control = ioread32be(priv->regs + FPGA_CONFIG_CONTROL);
  158. status = ioread32be(priv->regs + FPGA_CONFIG_STATUS);
  159. size = ioread32be(priv->regs + FPGA_CONFIG_FIFO_SIZE);
  160. used = ioread32be(priv->regs + FPGA_CONFIG_FIFO_USED);
  161. total = ioread32be(priv->regs + FPGA_CONFIG_TOTAL_BYTE_COUNT);
  162. curr = ioread32be(priv->regs + FPGA_CONFIG_CUR_BYTE_COUNT);
  163. dev_err(priv->dev, "Configuration failed, dumping status registers\n");
  164. dev_err(priv->dev, "Control: 0x%.8x\n", control);
  165. dev_err(priv->dev, "Status: 0x%.8x\n", status);
  166. dev_err(priv->dev, "FIFO Size: 0x%.8x\n", size);
  167. dev_err(priv->dev, "FIFO Used: 0x%.8x\n", used);
  168. dev_err(priv->dev, "FIFO Total: 0x%.8x\n", total);
  169. dev_err(priv->dev, "FIFO Curr: 0x%.8x\n", curr);
  170. }
  171. /*
  172. * FPGA Power Supply Code
  173. */
  174. #define CTL_PWR_CONTROL 0x2006
  175. #define CTL_PWR_STATUS 0x200A
  176. #define CTL_PWR_FAIL 0x200B
  177. #define PWR_CONTROL_ENABLE 0x01
  178. #define PWR_STATUS_ERROR_MASK 0x10
  179. #define PWR_STATUS_GOOD 0x0f
  180. /*
  181. * Determine if the FPGA power is good for all supplies
  182. */
  183. static bool fpga_power_good(struct fpga_dev *priv)
  184. {
  185. u8 val;
  186. val = ioread8(priv->regs + CTL_PWR_STATUS);
  187. if (val & PWR_STATUS_ERROR_MASK)
  188. return false;
  189. return val == PWR_STATUS_GOOD;
  190. }
  191. /*
  192. * Disable the FPGA power supplies
  193. */
  194. static void fpga_disable_power_supplies(struct fpga_dev *priv)
  195. {
  196. unsigned long start;
  197. u8 val;
  198. iowrite8(0x0, priv->regs + CTL_PWR_CONTROL);
  199. /*
  200. * Wait 500ms for the power rails to discharge
  201. *
  202. * Without this delay, the CTL-CPLD state machine can get into a
  203. * state where it is waiting for the power-goods to assert, but they
  204. * never do. This only happens when enabling and disabling the
  205. * power sequencer very rapidly.
  206. *
  207. * The loop below will also wait for the power goods to de-assert,
  208. * but testing has shown that they are always disabled by the time
  209. * the sleep completes. However, omitting the sleep and only waiting
  210. * for the power-goods to de-assert was not sufficient to ensure
  211. * that the power sequencer would not wedge itself.
  212. */
  213. msleep(500);
  214. start = jiffies;
  215. while (time_before(jiffies, start + HZ)) {
  216. val = ioread8(priv->regs + CTL_PWR_STATUS);
  217. if (!(val & PWR_STATUS_GOOD))
  218. break;
  219. usleep_range(5000, 10000);
  220. }
  221. val = ioread8(priv->regs + CTL_PWR_STATUS);
  222. if (val & PWR_STATUS_GOOD) {
  223. dev_err(priv->dev, "power disable failed: "
  224. "power goods: status 0x%.2x\n", val);
  225. }
  226. if (val & PWR_STATUS_ERROR_MASK) {
  227. dev_err(priv->dev, "power disable failed: "
  228. "alarm bit set: status 0x%.2x\n", val);
  229. }
  230. }
  231. /**
  232. * fpga_enable_power_supplies() - enable the DATA-FPGA power supplies
  233. * @priv: the driver's private data structure
  234. *
  235. * Enable the DATA-FPGA power supplies, waiting up to 1 second for
  236. * them to enable successfully.
  237. *
  238. * Returns 0 on success, -ERRNO otherwise
  239. */
  240. static int fpga_enable_power_supplies(struct fpga_dev *priv)
  241. {
  242. unsigned long start = jiffies;
  243. if (fpga_power_good(priv)) {
  244. dev_dbg(priv->dev, "power was already good\n");
  245. return 0;
  246. }
  247. iowrite8(PWR_CONTROL_ENABLE, priv->regs + CTL_PWR_CONTROL);
  248. while (time_before(jiffies, start + HZ)) {
  249. if (fpga_power_good(priv))
  250. return 0;
  251. usleep_range(5000, 10000);
  252. }
  253. return fpga_power_good(priv) ? 0 : -ETIMEDOUT;
  254. }
  255. /*
  256. * Determine if the FPGA power supplies are all enabled
  257. */
  258. static bool fpga_power_enabled(struct fpga_dev *priv)
  259. {
  260. u8 val;
  261. val = ioread8(priv->regs + CTL_PWR_CONTROL);
  262. if (val & PWR_CONTROL_ENABLE)
  263. return true;
  264. return false;
  265. }
  266. /*
  267. * Determine if the FPGA's are programmed and running correctly
  268. */
  269. static bool fpga_running(struct fpga_dev *priv)
  270. {
  271. if (!fpga_power_good(priv))
  272. return false;
  273. /* Check the config done bit */
  274. return ioread32be(priv->regs + FPGA_CONFIG_STATUS) & (1 << 18);
  275. }
  276. /*
  277. * FPGA Programming Code
  278. */
  279. /**
  280. * fpga_program_block() - put a block of data into the programmer's FIFO
  281. * @priv: the driver's private data structure
  282. * @buf: the data to program
  283. * @count: the length of data to program (must be a multiple of 4 bytes)
  284. *
  285. * Returns 0 on success, -ERRNO otherwise
  286. */
  287. static int fpga_program_block(struct fpga_dev *priv, void *buf, size_t count)
  288. {
  289. u32 *data = buf;
  290. int size = fpga_fifo_size(priv->regs);
  291. int i, len;
  292. unsigned long timeout;
  293. /* enforce correct data length for the FIFO */
  294. BUG_ON(count % 4 != 0);
  295. while (count > 0) {
  296. /* Get the size of the block to write (maximum is FIFO_SIZE) */
  297. len = min_t(size_t, count, size);
  298. timeout = jiffies + HZ / 4;
  299. /* Write the block */
  300. for (i = 0; i < len / 4; i++)
  301. fpga_fifo_write(priv->regs, data[i]);
  302. /* Update the amounts left */
  303. count -= len;
  304. data += len / 4;
  305. /* Wait for the fifo to empty */
  306. while (true) {
  307. if (fpga_fifo_empty(priv->regs)) {
  308. break;
  309. } else {
  310. dev_dbg(priv->dev, "Fifo not empty\n");
  311. cpu_relax();
  312. }
  313. if (fpga_config_error(priv->regs)) {
  314. dev_err(priv->dev, "Error detected\n");
  315. return -EIO;
  316. }
  317. if (time_after(jiffies, timeout)) {
  318. dev_err(priv->dev, "Fifo drain timeout\n");
  319. return -ETIMEDOUT;
  320. }
  321. usleep_range(5000, 10000);
  322. }
  323. }
  324. return 0;
  325. }
  326. /**
  327. * fpga_program_cpu() - program the DATA-FPGA's using the CPU
  328. * @priv: the driver's private data structure
  329. *
  330. * This is useful when the DMA programming method fails. It is possible to
  331. * wedge the Freescale DMA controller such that the DMA programming method
  332. * always fails. This method has always succeeded.
  333. *
  334. * Returns 0 on success, -ERRNO otherwise
  335. */
  336. static noinline int fpga_program_cpu(struct fpga_dev *priv)
  337. {
  338. int ret;
  339. /* Disable the programmer */
  340. fpga_programmer_disable(priv);
  341. /* Set the total byte count */
  342. fpga_set_byte_count(priv->regs, priv->bytes);
  343. dev_dbg(priv->dev, "total byte count %u bytes\n", priv->bytes);
  344. /* Enable the controller for programming */
  345. fpga_programmer_enable(priv, false);
  346. dev_dbg(priv->dev, "enabled the controller\n");
  347. /* Write each chunk of the FPGA bitfile to FPGA programmer */
  348. ret = fpga_program_block(priv, priv->vb.vaddr, priv->bytes);
  349. if (ret)
  350. goto out_disable_controller;
  351. /* Wait for the interrupt handler to signal that programming finished */
  352. ret = wait_for_completion_timeout(&priv->completion, 2 * HZ);
  353. if (!ret) {
  354. dev_err(priv->dev, "Timed out waiting for completion\n");
  355. ret = -ETIMEDOUT;
  356. goto out_disable_controller;
  357. }
  358. /* Retrieve the status from the interrupt handler */
  359. ret = priv->status;
  360. out_disable_controller:
  361. fpga_programmer_disable(priv);
  362. return ret;
  363. }
  364. #define FIFO_DMA_ADDRESS 0xf0003000
  365. #define FIFO_MAX_LEN 4096
  366. /**
  367. * fpga_program_dma() - program the DATA-FPGA's using the DMA engine
  368. * @priv: the driver's private data structure
  369. *
  370. * Program the DATA-FPGA's using the Freescale DMA engine. This requires that
  371. * the engine is programmed such that the hardware DMA request lines can
  372. * control the entire DMA transaction. The system controller FPGA then
  373. * completely offloads the programming from the CPU.
  374. *
  375. * Returns 0 on success, -ERRNO otherwise
  376. */
  377. static noinline int fpga_program_dma(struct fpga_dev *priv)
  378. {
  379. struct videobuf_dmabuf *vb = &priv->vb;
  380. struct dma_chan *chan = priv->chan;
  381. struct dma_async_tx_descriptor *tx;
  382. size_t num_pages, len, avail = 0;
  383. struct dma_slave_config config;
  384. struct scatterlist *sg;
  385. struct sg_table table;
  386. dma_cookie_t cookie;
  387. int ret, i;
  388. /* Disable the programmer */
  389. fpga_programmer_disable(priv);
  390. /* Allocate a scatterlist for the DMA destination */
  391. num_pages = DIV_ROUND_UP(priv->bytes, FIFO_MAX_LEN);
  392. ret = sg_alloc_table(&table, num_pages, GFP_KERNEL);
  393. if (ret) {
  394. dev_err(priv->dev, "Unable to allocate dst scatterlist\n");
  395. ret = -ENOMEM;
  396. goto out_return;
  397. }
  398. /*
  399. * This is an ugly hack
  400. *
  401. * We fill in a scatterlist as if it were mapped for DMA. This is
  402. * necessary because there exists no better structure for this
  403. * inside the kernel code.
  404. *
  405. * As an added bonus, we can use the DMAEngine API for all of this,
  406. * rather than inventing another extremely similar API.
  407. */
  408. avail = priv->bytes;
  409. for_each_sg(table.sgl, sg, num_pages, i) {
  410. len = min_t(size_t, avail, FIFO_MAX_LEN);
  411. sg_dma_address(sg) = FIFO_DMA_ADDRESS;
  412. sg_dma_len(sg) = len;
  413. avail -= len;
  414. }
  415. /* Map the buffer for DMA */
  416. ret = videobuf_dma_map(priv->dev, &priv->vb);
  417. if (ret) {
  418. dev_err(priv->dev, "Unable to map buffer for DMA\n");
  419. goto out_free_table;
  420. }
  421. /*
  422. * Configure the DMA channel to transfer FIFO_SIZE / 2 bytes per
  423. * transaction, and then put it under external control
  424. */
  425. memset(&config, 0, sizeof(config));
  426. config.direction = DMA_MEM_TO_DEV;
  427. config.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
  428. config.dst_maxburst = fpga_fifo_size(priv->regs) / 2 / 4;
  429. ret = dmaengine_slave_config(chan, &config);
  430. if (ret) {
  431. dev_err(priv->dev, "DMA slave configuration failed\n");
  432. goto out_dma_unmap;
  433. }
  434. ret = fsl_dma_external_start(chan, 1)
  435. if (ret) {
  436. dev_err(priv->dev, "DMA external control setup failed\n");
  437. goto out_dma_unmap;
  438. }
  439. /* setup and submit the DMA transaction */
  440. tx = dmaengine_prep_dma_sg(chan, table.sgl, num_pages,
  441. vb->sglist, vb->sglen, 0);
  442. if (!tx) {
  443. dev_err(priv->dev, "Unable to prep DMA transaction\n");
  444. ret = -ENOMEM;
  445. goto out_dma_unmap;
  446. }
  447. cookie = tx->tx_submit(tx);
  448. if (dma_submit_error(cookie)) {
  449. dev_err(priv->dev, "Unable to submit DMA transaction\n");
  450. ret = -ENOMEM;
  451. goto out_dma_unmap;
  452. }
  453. dma_async_issue_pending(chan);
  454. /* Set the total byte count */
  455. fpga_set_byte_count(priv->regs, priv->bytes);
  456. dev_dbg(priv->dev, "total byte count %u bytes\n", priv->bytes);
  457. /* Enable the controller for DMA programming */
  458. fpga_programmer_enable(priv, true);
  459. dev_dbg(priv->dev, "enabled the controller\n");
  460. /* Wait for the interrupt handler to signal that programming finished */
  461. ret = wait_for_completion_timeout(&priv->completion, 2 * HZ);
  462. if (!ret) {
  463. dev_err(priv->dev, "Timed out waiting for completion\n");
  464. ret = -ETIMEDOUT;
  465. goto out_disable_controller;
  466. }
  467. /* Retrieve the status from the interrupt handler */
  468. ret = priv->status;
  469. out_disable_controller:
  470. fpga_programmer_disable(priv);
  471. out_dma_unmap:
  472. videobuf_dma_unmap(priv->dev, vb);
  473. out_free_table:
  474. sg_free_table(&table);
  475. out_return:
  476. return ret;
  477. }
  478. /*
  479. * Interrupt Handling
  480. */
  481. static irqreturn_t fpga_irq(int irq, void *dev_id)
  482. {
  483. struct fpga_dev *priv = dev_id;
  484. /* Save the status */
  485. priv->status = fpga_config_error(priv->regs) ? -EIO : 0;
  486. dev_dbg(priv->dev, "INTERRUPT status %d\n", priv->status);
  487. fpga_dump_registers(priv);
  488. /* Disabling the programmer clears the interrupt */
  489. fpga_programmer_disable(priv);
  490. /* Notify any waiters */
  491. complete(&priv->completion);
  492. return IRQ_HANDLED;
  493. }
  494. /*
  495. * SYSFS Helpers
  496. */
  497. /**
  498. * fpga_do_stop() - deconfigure (reset) the DATA-FPGA's
  499. * @priv: the driver's private data structure
  500. *
  501. * LOCKING: must hold priv->lock
  502. */
  503. static int fpga_do_stop(struct fpga_dev *priv)
  504. {
  505. u32 val;
  506. /* Set the led to unprogrammed */
  507. ledtrig_fpga_programmed(false);
  508. /* Pulse the config line to reset the FPGA's */
  509. val = CFG_CTL_ENABLE | CFG_CTL_RESET;
  510. iowrite32be(val, priv->regs + FPGA_CONFIG_CONTROL);
  511. iowrite32be(0x0, priv->regs + FPGA_CONFIG_CONTROL);
  512. return 0;
  513. }
  514. static noinline int fpga_do_program(struct fpga_dev *priv)
  515. {
  516. int ret;
  517. if (priv->bytes != priv->fw_size) {
  518. dev_err(priv->dev, "Incorrect bitfile size: got %zu bytes, "
  519. "should be %zu bytes\n",
  520. priv->bytes, priv->fw_size);
  521. return -EINVAL;
  522. }
  523. if (!fpga_power_enabled(priv)) {
  524. dev_err(priv->dev, "Power not enabled\n");
  525. return -EINVAL;
  526. }
  527. if (!fpga_power_good(priv)) {
  528. dev_err(priv->dev, "Power not good\n");
  529. return -EINVAL;
  530. }
  531. /* Set the LED to unprogrammed */
  532. ledtrig_fpga_programmed(false);
  533. /* Try to program the FPGA's using DMA */
  534. ret = fpga_program_dma(priv);
  535. /* If DMA failed or doesn't exist, try with CPU */
  536. if (ret) {
  537. dev_warn(priv->dev, "Falling back to CPU programming\n");
  538. ret = fpga_program_cpu(priv);
  539. }
  540. if (ret) {
  541. dev_err(priv->dev, "Unable to program FPGA's\n");
  542. return ret;
  543. }
  544. /* Drop the firmware bitfile from memory */
  545. fpga_drop_firmware_data(priv);
  546. dev_dbg(priv->dev, "FPGA programming successful\n");
  547. ledtrig_fpga_programmed(true);
  548. return 0;
  549. }
  550. /*
  551. * File Operations
  552. */
  553. static int fpga_open(struct inode *inode, struct file *filp)
  554. {
  555. /*
  556. * The miscdevice layer puts our struct miscdevice into the
  557. * filp->private_data field. We use this to find our private
  558. * data and then overwrite it with our own private structure.
  559. */
  560. struct fpga_dev *priv = container_of(filp->private_data,
  561. struct fpga_dev, miscdev);
  562. unsigned int nr_pages;
  563. int ret;
  564. /* We only allow one process at a time */
  565. ret = mutex_lock_interruptible(&priv->lock);
  566. if (ret)
  567. return ret;
  568. filp->private_data = priv;
  569. kref_get(&priv->ref);
  570. /* Truncation: drop any existing data */
  571. if (filp->f_flags & O_TRUNC)
  572. priv->bytes = 0;
  573. /* Check if we have already allocated a buffer */
  574. if (priv->vb_allocated)
  575. return 0;
  576. /* Allocate a buffer to hold enough data for the bitfile */
  577. nr_pages = DIV_ROUND_UP(priv->fw_size, PAGE_SIZE);
  578. ret = videobuf_dma_init_kernel(&priv->vb, DMA_TO_DEVICE, nr_pages);
  579. if (ret) {
  580. dev_err(priv->dev, "unable to allocate data buffer\n");
  581. mutex_unlock(&priv->lock);
  582. kref_put(&priv->ref, fpga_dev_remove);
  583. return ret;
  584. }
  585. priv->vb_allocated = true;
  586. return 0;
  587. }
  588. static int fpga_release(struct inode *inode, struct file *filp)
  589. {
  590. struct fpga_dev *priv = filp->private_data;
  591. mutex_unlock(&priv->lock);
  592. kref_put(&priv->ref, fpga_dev_remove);
  593. return 0;
  594. }
  595. static ssize_t fpga_write(struct file *filp, const char __user *buf,
  596. size_t count, loff_t *f_pos)
  597. {
  598. struct fpga_dev *priv = filp->private_data;
  599. /* FPGA bitfiles have an exact size: disallow anything else */
  600. if (priv->bytes >= priv->fw_size)
  601. return -ENOSPC;
  602. count = min_t(size_t, priv->fw_size - priv->bytes, count);
  603. if (copy_from_user(priv->vb.vaddr + priv->bytes, buf, count))
  604. return -EFAULT;
  605. priv->bytes += count;
  606. return count;
  607. }
  608. static ssize_t fpga_read(struct file *filp, char __user *buf, size_t count,
  609. loff_t *f_pos)
  610. {
  611. struct fpga_dev *priv = filp->private_data;
  612. return simple_read_from_buffer(buf, count, ppos,
  613. priv->vb.vaddr, priv->bytes);
  614. }
  615. static loff_t fpga_llseek(struct file *filp, loff_t offset, int origin)
  616. {
  617. struct fpga_dev *priv = filp->private_data;
  618. loff_t newpos;
  619. /* only read-only opens are allowed to seek */
  620. if ((filp->f_flags & O_ACCMODE) != O_RDONLY)
  621. return -EINVAL;
  622. return fixed_size_llseek(file, offset, origin, priv->fw_size);
  623. }
  624. static const struct file_operations fpga_fops = {
  625. .open = fpga_open,
  626. .release = fpga_release,
  627. .write = fpga_write,
  628. .read = fpga_read,
  629. .llseek = fpga_llseek,
  630. };
  631. /*
  632. * Device Attributes
  633. */
  634. static ssize_t pfail_show(struct device *dev, struct device_attribute *attr,
  635. char *buf)
  636. {
  637. struct fpga_dev *priv = dev_get_drvdata(dev);
  638. u8 val;
  639. val = ioread8(priv->regs + CTL_PWR_FAIL);
  640. return snprintf(buf, PAGE_SIZE, "0x%.2x\n", val);
  641. }
  642. static ssize_t pgood_show(struct device *dev, struct device_attribute *attr,
  643. char *buf)
  644. {
  645. struct fpga_dev *priv = dev_get_drvdata(dev);
  646. return snprintf(buf, PAGE_SIZE, "%d\n", fpga_power_good(priv));
  647. }
  648. static ssize_t penable_show(struct device *dev, struct device_attribute *attr,
  649. char *buf)
  650. {
  651. struct fpga_dev *priv = dev_get_drvdata(dev);
  652. return snprintf(buf, PAGE_SIZE, "%d\n", fpga_power_enabled(priv));
  653. }
  654. static ssize_t penable_store(struct device *dev, struct device_attribute *attr,
  655. const char *buf, size_t count)
  656. {
  657. struct fpga_dev *priv = dev_get_drvdata(dev);
  658. unsigned long val;
  659. int ret;
  660. ret = kstrtoul(buf, 0, &val);
  661. if (ret)
  662. return ret;
  663. if (val) {
  664. ret = fpga_enable_power_supplies(priv);
  665. if (ret)
  666. return ret;
  667. } else {
  668. fpga_do_stop(priv);
  669. fpga_disable_power_supplies(priv);
  670. }
  671. return count;
  672. }
  673. static ssize_t program_show(struct device *dev, struct device_attribute *attr,
  674. char *buf)
  675. {
  676. struct fpga_dev *priv = dev_get_drvdata(dev);
  677. return snprintf(buf, PAGE_SIZE, "%d\n", fpga_running(priv));
  678. }
  679. static ssize_t program_store(struct device *dev, struct device_attribute *attr,
  680. const char *buf, size_t count)
  681. {
  682. struct fpga_dev *priv = dev_get_drvdata(dev);
  683. unsigned long val;
  684. int ret;
  685. ret = kstrtoul(buf, 0, &val);
  686. if (ret)
  687. return ret;
  688. /* We can't have an image writer and be programming simultaneously */
  689. if (mutex_lock_interruptible(&priv->lock))
  690. return -ERESTARTSYS;
  691. /* Program or Reset the FPGA's */
  692. ret = val ? fpga_do_program(priv) : fpga_do_stop(priv);
  693. if (ret)
  694. goto out_unlock;
  695. /* Success */
  696. ret = count;
  697. out_unlock:
  698. mutex_unlock(&priv->lock);
  699. return ret;
  700. }
  701. static DEVICE_ATTR(power_fail, S_IRUGO, pfail_show, NULL);
  702. static DEVICE_ATTR(power_good, S_IRUGO, pgood_show, NULL);
  703. static DEVICE_ATTR(power_enable, S_IRUGO | S_IWUSR,
  704. penable_show, penable_store);
  705. static DEVICE_ATTR(program, S_IRUGO | S_IWUSR,
  706. program_show, program_store);
  707. static struct attribute *fpga_attributes[] = {
  708. &dev_attr_power_fail.attr,
  709. &dev_attr_power_good.attr,
  710. &dev_attr_power_enable.attr,
  711. &dev_attr_program.attr,
  712. NULL,
  713. };
  714. static const struct attribute_group fpga_attr_group = {
  715. .attrs = fpga_attributes,
  716. };
  717. /*
  718. * OpenFirmware Device Subsystem
  719. */
  720. #define SYS_REG_VERSION 0x00
  721. #define SYS_REG_GEOGRAPHIC 0x10
  722. static bool dma_filter(struct dma_chan *chan, void *data)
  723. {
  724. /*
  725. * DMA Channel #0 is the only acceptable device
  726. *
  727. * This probably won't survive an unload/load cycle of the Freescale
  728. * DMAEngine driver, but that won't be a problem
  729. */
  730. return chan->chan_id == 0 && chan->device->dev_id == 0;
  731. }
  732. static int fpga_of_remove(struct platform_device *op)
  733. {
  734. struct fpga_dev *priv = platform_get_drvdata(op);
  735. struct device *this_device = priv->miscdev.this_device;
  736. sysfs_remove_group(&this_device->kobj, &fpga_attr_group);
  737. misc_deregister(&priv->miscdev);
  738. free_irq(priv->irq, priv);
  739. irq_dispose_mapping(priv->irq);
  740. /* make sure the power supplies are off */
  741. fpga_disable_power_supplies(priv);
  742. /* unmap registers */
  743. iounmap(priv->immr);
  744. iounmap(priv->regs);
  745. dma_release_channel(priv->chan);
  746. /* drop our reference to the private data structure */
  747. kref_put(&priv->ref, fpga_dev_remove);
  748. return 0;
  749. }
  750. /* CTL-CPLD Version Register */
  751. #define CTL_CPLD_VERSION 0x2000
  752. static int fpga_of_probe(struct platform_device *op)
  753. {
  754. struct device_node *of_node = op->dev.of_node;
  755. struct device *this_device;
  756. struct fpga_dev *priv;
  757. dma_cap_mask_t mask;
  758. u32 ver;
  759. int ret;
  760. /* Allocate private data */
  761. priv = kzalloc(sizeof(*priv), GFP_KERNEL);
  762. if (!priv) {
  763. dev_err(&op->dev, "Unable to allocate private data\n");
  764. ret = -ENOMEM;
  765. goto out_return;
  766. }
  767. /* Setup the miscdevice */
  768. priv->miscdev.minor = MISC_DYNAMIC_MINOR;
  769. priv->miscdev.name = drv_name;
  770. priv->miscdev.fops = &fpga_fops;
  771. kref_init(&priv->ref);
  772. platform_set_drvdata(op, priv);
  773. priv->dev = &op->dev;
  774. mutex_init(&priv->lock);
  775. init_completion(&priv->completion);
  776. videobuf_dma_init(&priv->vb);
  777. dev_set_drvdata(priv->dev, priv);
  778. dma_cap_zero(mask);
  779. dma_cap_set(DMA_MEMCPY, mask);
  780. dma_cap_set(DMA_SLAVE, mask);
  781. dma_cap_set(DMA_SG, mask);
  782. /* Get control of DMA channel #0 */
  783. priv->chan = dma_request_channel(mask, dma_filter, NULL);
  784. if (!priv->chan) {
  785. dev_err(&op->dev, "Unable to acquire DMA channel #0\n");
  786. ret = -ENODEV;
  787. goto out_free_priv;
  788. }
  789. /* Remap the registers for use */
  790. priv->regs = of_iomap(of_node, 0);
  791. if (!priv->regs) {
  792. dev_err(&op->dev, "Unable to ioremap registers\n");
  793. ret = -ENOMEM;
  794. goto out_dma_release_channel;
  795. }
  796. /* Remap the IMMR for use */
  797. priv->immr = ioremap(get_immrbase(), 0x100000);
  798. if (!priv->immr) {
  799. dev_err(&op->dev, "Unable to ioremap IMMR\n");
  800. ret = -ENOMEM;
  801. goto out_unmap_regs;
  802. }
  803. /*
  804. * Check that external DMA is configured
  805. *
  806. * U-Boot does this for us, but we should check it and bail out if
  807. * there is a problem. Failing to have this register setup correctly
  808. * will cause the DMA controller to transfer a single cacheline
  809. * worth of data, then wedge itself.
  810. */
  811. if ((ioread32be(priv->immr + 0x114) & 0xE00) != 0xE00) {
  812. dev_err(&op->dev, "External DMA control not configured\n");
  813. ret = -ENODEV;
  814. goto out_unmap_immr;
  815. }
  816. /*
  817. * Check the CTL-CPLD version
  818. *
  819. * This driver uses the CTL-CPLD DATA-FPGA power sequencer, and we
  820. * don't want to run on any version of the CTL-CPLD that does not use
  821. * a compatible register layout.
  822. *
  823. * v2: changed register layout, added power sequencer
  824. * v3: added glitch filter on the i2c overcurrent/overtemp outputs
  825. */
  826. ver = ioread8(priv->regs + CTL_CPLD_VERSION);
  827. if (ver != 0x02 && ver != 0x03) {
  828. dev_err(&op->dev, "CTL-CPLD is not version 0x02 or 0x03!\n");
  829. ret = -ENODEV;
  830. goto out_unmap_immr;
  831. }
  832. /* Set the exact size that the firmware image should be */
  833. ver = ioread32be(priv->regs + SYS_REG_VERSION);
  834. priv->fw_size = (ver & (1 << 18)) ? FW_SIZE_EP2S130 : FW_SIZE_EP2S90;
  835. /* Find the correct IRQ number */
  836. priv->irq = irq_of_parse_and_map(of_node, 0);
  837. if (priv->irq == NO_IRQ) {
  838. dev_err(&op->dev, "Unable to find IRQ line\n");
  839. ret = -ENODEV;
  840. goto out_unmap_immr;
  841. }
  842. /* Request the IRQ */
  843. ret = request_irq(priv->irq, fpga_irq, IRQF_SHARED, drv_name, priv);
  844. if (ret) {
  845. dev_err(&op->dev, "Unable to request IRQ %d\n", priv->irq);
  846. ret = -ENODEV;
  847. goto out_irq_dispose_mapping;
  848. }
  849. /* Reset and stop the FPGA's, just in case */
  850. fpga_do_stop(priv);
  851. /* Register the miscdevice */
  852. ret = misc_register(&priv->miscdev);
  853. if (ret) {
  854. dev_err(&op->dev, "Unable to register miscdevice\n");
  855. goto out_free_irq;
  856. }
  857. /* Create the sysfs files */
  858. this_device = priv->miscdev.this_device;
  859. dev_set_drvdata(this_device, priv);
  860. ret = sysfs_create_group(&this_device->kobj, &fpga_attr_group);
  861. if (ret) {
  862. dev_err(&op->dev, "Unable to create sysfs files\n");
  863. goto out_misc_deregister;
  864. }
  865. dev_info(priv->dev, "CARMA FPGA Programmer: %s rev%s with %s FPGAs\n",
  866. (ver & (1 << 17)) ? "Correlator" : "Digitizer",
  867. (ver & (1 << 16)) ? "B" : "A",
  868. (ver & (1 << 18)) ? "EP2S130" : "EP2S90");
  869. return 0;
  870. out_misc_deregister:
  871. misc_deregister(&priv->miscdev);
  872. out_free_irq:
  873. free_irq(priv->irq, priv);
  874. out_irq_dispose_mapping:
  875. irq_dispose_mapping(priv->irq);
  876. out_unmap_immr:
  877. iounmap(priv->immr);
  878. out_unmap_regs:
  879. iounmap(priv->regs);
  880. out_dma_release_channel:
  881. dma_release_channel(priv->chan);
  882. out_free_priv:
  883. kref_put(&priv->ref, fpga_dev_remove);
  884. out_return:
  885. return ret;
  886. }
  887. static struct of_device_id fpga_of_match[] = {
  888. { .compatible = "carma,fpga-programmer", },
  889. {},
  890. };
  891. static struct platform_driver fpga_of_driver = {
  892. .probe = fpga_of_probe,
  893. .remove = fpga_of_remove,
  894. .driver = {
  895. .name = drv_name,
  896. .of_match_table = fpga_of_match,
  897. .owner = THIS_MODULE,
  898. },
  899. };
  900. /*
  901. * Module Init / Exit
  902. */
  903. static int __init fpga_init(void)
  904. {
  905. led_trigger_register_simple("fpga", &ledtrig_fpga);
  906. return platform_driver_register(&fpga_of_driver);
  907. }
  908. static void __exit fpga_exit(void)
  909. {
  910. platform_driver_unregister(&fpga_of_driver);
  911. led_trigger_unregister_simple(ledtrig_fpga);
  912. }
  913. MODULE_AUTHOR("Ira W. Snyder <iws@ovro.caltech.edu>");
  914. MODULE_DESCRIPTION("CARMA Board DATA-FPGA Programmer");
  915. MODULE_LICENSE("GPL");
  916. module_init(fpga_init);
  917. module_exit(fpga_exit);