coda-bit.c 53 KB

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  1. /*
  2. * Coda multi-standard codec IP - BIT processor functions
  3. *
  4. * Copyright (C) 2012 Vista Silicon S.L.
  5. * Javier Martin, <javier.martin@vista-silicon.com>
  6. * Xavier Duret
  7. * Copyright (C) 2012-2014 Philipp Zabel, Pengutronix
  8. *
  9. * This program is free software; you can redistribute it and/or modify
  10. * it under the terms of the GNU General Public License as published by
  11. * the Free Software Foundation; either version 2 of the License, or
  12. * (at your option) any later version.
  13. */
  14. #include <linux/clk.h>
  15. #include <linux/irqreturn.h>
  16. #include <linux/kernel.h>
  17. #include <linux/platform_device.h>
  18. #include <linux/reset.h>
  19. #include <linux/slab.h>
  20. #include <linux/videodev2.h>
  21. #include <media/v4l2-common.h>
  22. #include <media/v4l2-ctrls.h>
  23. #include <media/v4l2-fh.h>
  24. #include <media/v4l2-mem2mem.h>
  25. #include <media/videobuf2-core.h>
  26. #include <media/videobuf2-dma-contig.h>
  27. #include <media/videobuf2-vmalloc.h>
  28. #include "coda.h"
  29. #define CODA7_PS_BUF_SIZE 0x28000
  30. #define CODA9_PS_SAVE_SIZE (512 * 1024)
  31. #define CODA_DEFAULT_GAMMA 4096
  32. #define CODA9_DEFAULT_GAMMA 24576 /* 0.75 * 32768 */
  33. static inline int coda_is_initialized(struct coda_dev *dev)
  34. {
  35. return coda_read(dev, CODA_REG_BIT_CUR_PC) != 0;
  36. }
  37. static inline unsigned long coda_isbusy(struct coda_dev *dev)
  38. {
  39. return coda_read(dev, CODA_REG_BIT_BUSY);
  40. }
  41. static int coda_wait_timeout(struct coda_dev *dev)
  42. {
  43. unsigned long timeout = jiffies + msecs_to_jiffies(1000);
  44. while (coda_isbusy(dev)) {
  45. if (time_after(jiffies, timeout))
  46. return -ETIMEDOUT;
  47. }
  48. return 0;
  49. }
  50. static void coda_command_async(struct coda_ctx *ctx, int cmd)
  51. {
  52. struct coda_dev *dev = ctx->dev;
  53. if (dev->devtype->product == CODA_960 ||
  54. dev->devtype->product == CODA_7541) {
  55. /* Restore context related registers to CODA */
  56. coda_write(dev, ctx->bit_stream_param,
  57. CODA_REG_BIT_BIT_STREAM_PARAM);
  58. coda_write(dev, ctx->frm_dis_flg,
  59. CODA_REG_BIT_FRM_DIS_FLG(ctx->reg_idx));
  60. coda_write(dev, ctx->frame_mem_ctrl,
  61. CODA_REG_BIT_FRAME_MEM_CTRL);
  62. coda_write(dev, ctx->workbuf.paddr, CODA_REG_BIT_WORK_BUF_ADDR);
  63. }
  64. if (dev->devtype->product == CODA_960) {
  65. coda_write(dev, 1, CODA9_GDI_WPROT_ERR_CLR);
  66. coda_write(dev, 0, CODA9_GDI_WPROT_RGN_EN);
  67. }
  68. coda_write(dev, CODA_REG_BIT_BUSY_FLAG, CODA_REG_BIT_BUSY);
  69. coda_write(dev, ctx->idx, CODA_REG_BIT_RUN_INDEX);
  70. coda_write(dev, ctx->params.codec_mode, CODA_REG_BIT_RUN_COD_STD);
  71. coda_write(dev, ctx->params.codec_mode_aux, CODA7_REG_BIT_RUN_AUX_STD);
  72. coda_write(dev, cmd, CODA_REG_BIT_RUN_COMMAND);
  73. }
  74. static int coda_command_sync(struct coda_ctx *ctx, int cmd)
  75. {
  76. struct coda_dev *dev = ctx->dev;
  77. coda_command_async(ctx, cmd);
  78. return coda_wait_timeout(dev);
  79. }
  80. int coda_hw_reset(struct coda_ctx *ctx)
  81. {
  82. struct coda_dev *dev = ctx->dev;
  83. unsigned long timeout;
  84. unsigned int idx;
  85. int ret;
  86. if (!dev->rstc)
  87. return -ENOENT;
  88. idx = coda_read(dev, CODA_REG_BIT_RUN_INDEX);
  89. if (dev->devtype->product == CODA_960) {
  90. timeout = jiffies + msecs_to_jiffies(100);
  91. coda_write(dev, 0x11, CODA9_GDI_BUS_CTRL);
  92. while (coda_read(dev, CODA9_GDI_BUS_STATUS) != 0x77) {
  93. if (time_after(jiffies, timeout))
  94. return -ETIME;
  95. cpu_relax();
  96. }
  97. }
  98. ret = reset_control_reset(dev->rstc);
  99. if (ret < 0)
  100. return ret;
  101. if (dev->devtype->product == CODA_960)
  102. coda_write(dev, 0x00, CODA9_GDI_BUS_CTRL);
  103. coda_write(dev, CODA_REG_BIT_BUSY_FLAG, CODA_REG_BIT_BUSY);
  104. coda_write(dev, CODA_REG_RUN_ENABLE, CODA_REG_BIT_CODE_RUN);
  105. ret = coda_wait_timeout(dev);
  106. coda_write(dev, idx, CODA_REG_BIT_RUN_INDEX);
  107. return ret;
  108. }
  109. static void coda_kfifo_sync_from_device(struct coda_ctx *ctx)
  110. {
  111. struct __kfifo *kfifo = &ctx->bitstream_fifo.kfifo;
  112. struct coda_dev *dev = ctx->dev;
  113. u32 rd_ptr;
  114. rd_ptr = coda_read(dev, CODA_REG_BIT_RD_PTR(ctx->reg_idx));
  115. kfifo->out = (kfifo->in & ~kfifo->mask) |
  116. (rd_ptr - ctx->bitstream.paddr);
  117. if (kfifo->out > kfifo->in)
  118. kfifo->out -= kfifo->mask + 1;
  119. }
  120. static void coda_kfifo_sync_to_device_full(struct coda_ctx *ctx)
  121. {
  122. struct __kfifo *kfifo = &ctx->bitstream_fifo.kfifo;
  123. struct coda_dev *dev = ctx->dev;
  124. u32 rd_ptr, wr_ptr;
  125. rd_ptr = ctx->bitstream.paddr + (kfifo->out & kfifo->mask);
  126. coda_write(dev, rd_ptr, CODA_REG_BIT_RD_PTR(ctx->reg_idx));
  127. wr_ptr = ctx->bitstream.paddr + (kfifo->in & kfifo->mask);
  128. coda_write(dev, wr_ptr, CODA_REG_BIT_WR_PTR(ctx->reg_idx));
  129. }
  130. static void coda_kfifo_sync_to_device_write(struct coda_ctx *ctx)
  131. {
  132. struct __kfifo *kfifo = &ctx->bitstream_fifo.kfifo;
  133. struct coda_dev *dev = ctx->dev;
  134. u32 wr_ptr;
  135. wr_ptr = ctx->bitstream.paddr + (kfifo->in & kfifo->mask);
  136. coda_write(dev, wr_ptr, CODA_REG_BIT_WR_PTR(ctx->reg_idx));
  137. }
  138. static int coda_bitstream_queue(struct coda_ctx *ctx,
  139. struct vb2_buffer *src_buf)
  140. {
  141. u32 src_size = vb2_get_plane_payload(src_buf, 0);
  142. u32 n;
  143. n = kfifo_in(&ctx->bitstream_fifo, vb2_plane_vaddr(src_buf, 0),
  144. src_size);
  145. if (n < src_size)
  146. return -ENOSPC;
  147. dma_sync_single_for_device(&ctx->dev->plat_dev->dev,
  148. ctx->bitstream.paddr, ctx->bitstream.size,
  149. DMA_TO_DEVICE);
  150. src_buf->v4l2_buf.sequence = ctx->qsequence++;
  151. return 0;
  152. }
  153. static bool coda_bitstream_try_queue(struct coda_ctx *ctx,
  154. struct vb2_buffer *src_buf)
  155. {
  156. int ret;
  157. if (coda_get_bitstream_payload(ctx) +
  158. vb2_get_plane_payload(src_buf, 0) + 512 >= ctx->bitstream.size)
  159. return false;
  160. if (vb2_plane_vaddr(src_buf, 0) == NULL) {
  161. v4l2_err(&ctx->dev->v4l2_dev, "trying to queue empty buffer\n");
  162. return true;
  163. }
  164. ret = coda_bitstream_queue(ctx, src_buf);
  165. if (ret < 0) {
  166. v4l2_err(&ctx->dev->v4l2_dev, "bitstream buffer overflow\n");
  167. return false;
  168. }
  169. /* Sync read pointer to device */
  170. if (ctx == v4l2_m2m_get_curr_priv(ctx->dev->m2m_dev))
  171. coda_kfifo_sync_to_device_write(ctx);
  172. ctx->hold = false;
  173. return true;
  174. }
  175. void coda_fill_bitstream(struct coda_ctx *ctx)
  176. {
  177. struct vb2_buffer *src_buf;
  178. struct coda_timestamp *ts;
  179. while (v4l2_m2m_num_src_bufs_ready(ctx->fh.m2m_ctx) > 0) {
  180. src_buf = v4l2_m2m_next_src_buf(ctx->fh.m2m_ctx);
  181. if (coda_bitstream_try_queue(ctx, src_buf)) {
  182. /*
  183. * Source buffer is queued in the bitstream ringbuffer;
  184. * queue the timestamp and mark source buffer as done
  185. */
  186. src_buf = v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx);
  187. ts = kmalloc(sizeof(*ts), GFP_KERNEL);
  188. if (ts) {
  189. ts->sequence = src_buf->v4l2_buf.sequence;
  190. ts->timecode = src_buf->v4l2_buf.timecode;
  191. ts->timestamp = src_buf->v4l2_buf.timestamp;
  192. list_add_tail(&ts->list, &ctx->timestamp_list);
  193. }
  194. v4l2_m2m_buf_done(src_buf, VB2_BUF_STATE_DONE);
  195. } else {
  196. break;
  197. }
  198. }
  199. }
  200. void coda_bit_stream_end_flag(struct coda_ctx *ctx)
  201. {
  202. struct coda_dev *dev = ctx->dev;
  203. ctx->bit_stream_param |= CODA_BIT_STREAM_END_FLAG;
  204. /* If this context is currently running, update the hardware flag */
  205. if ((dev->devtype->product == CODA_960) &&
  206. coda_isbusy(dev) &&
  207. (ctx->idx == coda_read(dev, CODA_REG_BIT_RUN_INDEX))) {
  208. coda_write(dev, ctx->bit_stream_param,
  209. CODA_REG_BIT_BIT_STREAM_PARAM);
  210. }
  211. }
  212. static void coda_parabuf_write(struct coda_ctx *ctx, int index, u32 value)
  213. {
  214. struct coda_dev *dev = ctx->dev;
  215. u32 *p = ctx->parabuf.vaddr;
  216. if (dev->devtype->product == CODA_DX6)
  217. p[index] = value;
  218. else
  219. p[index ^ 1] = value;
  220. }
  221. static void coda_free_framebuffers(struct coda_ctx *ctx)
  222. {
  223. int i;
  224. for (i = 0; i < CODA_MAX_FRAMEBUFFERS; i++)
  225. coda_free_aux_buf(ctx->dev, &ctx->internal_frames[i]);
  226. }
  227. static int coda_alloc_framebuffers(struct coda_ctx *ctx,
  228. struct coda_q_data *q_data, u32 fourcc)
  229. {
  230. struct coda_dev *dev = ctx->dev;
  231. int width, height;
  232. dma_addr_t paddr;
  233. int ysize;
  234. int ret;
  235. int i;
  236. if (ctx->codec && (ctx->codec->src_fourcc == V4L2_PIX_FMT_H264 ||
  237. ctx->codec->dst_fourcc == V4L2_PIX_FMT_H264)) {
  238. width = round_up(q_data->width, 16);
  239. height = round_up(q_data->height, 16);
  240. } else {
  241. width = round_up(q_data->width, 8);
  242. height = q_data->height;
  243. }
  244. ysize = width * height;
  245. /* Allocate frame buffers */
  246. for (i = 0; i < ctx->num_internal_frames; i++) {
  247. size_t size;
  248. char *name;
  249. size = ysize + ysize / 2;
  250. if (ctx->codec->src_fourcc == V4L2_PIX_FMT_H264 &&
  251. dev->devtype->product != CODA_DX6)
  252. size += ysize / 4;
  253. name = kasprintf(GFP_KERNEL, "fb%d", i);
  254. ret = coda_alloc_context_buf(ctx, &ctx->internal_frames[i],
  255. size, name);
  256. kfree(name);
  257. if (ret < 0) {
  258. coda_free_framebuffers(ctx);
  259. return ret;
  260. }
  261. }
  262. /* Register frame buffers in the parameter buffer */
  263. for (i = 0; i < ctx->num_internal_frames; i++) {
  264. paddr = ctx->internal_frames[i].paddr;
  265. /* Start addresses of Y, Cb, Cr planes */
  266. coda_parabuf_write(ctx, i * 3 + 0, paddr);
  267. coda_parabuf_write(ctx, i * 3 + 1, paddr + ysize);
  268. coda_parabuf_write(ctx, i * 3 + 2, paddr + ysize + ysize / 4);
  269. /* mvcol buffer for h.264 */
  270. if (ctx->codec->src_fourcc == V4L2_PIX_FMT_H264 &&
  271. dev->devtype->product != CODA_DX6)
  272. coda_parabuf_write(ctx, 96 + i,
  273. ctx->internal_frames[i].paddr +
  274. ysize + ysize/4 + ysize/4);
  275. }
  276. /* mvcol buffer for mpeg4 */
  277. if ((dev->devtype->product != CODA_DX6) &&
  278. (ctx->codec->src_fourcc == V4L2_PIX_FMT_MPEG4))
  279. coda_parabuf_write(ctx, 97, ctx->internal_frames[i].paddr +
  280. ysize + ysize/4 + ysize/4);
  281. return 0;
  282. }
  283. static void coda_free_context_buffers(struct coda_ctx *ctx)
  284. {
  285. struct coda_dev *dev = ctx->dev;
  286. coda_free_aux_buf(dev, &ctx->slicebuf);
  287. coda_free_aux_buf(dev, &ctx->psbuf);
  288. if (dev->devtype->product != CODA_DX6)
  289. coda_free_aux_buf(dev, &ctx->workbuf);
  290. }
  291. static int coda_alloc_context_buffers(struct coda_ctx *ctx,
  292. struct coda_q_data *q_data)
  293. {
  294. struct coda_dev *dev = ctx->dev;
  295. size_t size;
  296. int ret;
  297. if (dev->devtype->product == CODA_DX6)
  298. return 0;
  299. if (ctx->psbuf.vaddr) {
  300. v4l2_err(&dev->v4l2_dev, "psmembuf still allocated\n");
  301. return -EBUSY;
  302. }
  303. if (ctx->slicebuf.vaddr) {
  304. v4l2_err(&dev->v4l2_dev, "slicebuf still allocated\n");
  305. return -EBUSY;
  306. }
  307. if (ctx->workbuf.vaddr) {
  308. v4l2_err(&dev->v4l2_dev, "context buffer still allocated\n");
  309. ret = -EBUSY;
  310. return -ENOMEM;
  311. }
  312. if (q_data->fourcc == V4L2_PIX_FMT_H264) {
  313. /* worst case slice size */
  314. size = (DIV_ROUND_UP(q_data->width, 16) *
  315. DIV_ROUND_UP(q_data->height, 16)) * 3200 / 8 + 512;
  316. ret = coda_alloc_context_buf(ctx, &ctx->slicebuf, size,
  317. "slicebuf");
  318. if (ret < 0) {
  319. v4l2_err(&dev->v4l2_dev,
  320. "failed to allocate %d byte slice buffer",
  321. ctx->slicebuf.size);
  322. return ret;
  323. }
  324. }
  325. if (dev->devtype->product == CODA_7541) {
  326. ret = coda_alloc_context_buf(ctx, &ctx->psbuf,
  327. CODA7_PS_BUF_SIZE, "psbuf");
  328. if (ret < 0) {
  329. v4l2_err(&dev->v4l2_dev,
  330. "failed to allocate psmem buffer");
  331. goto err;
  332. }
  333. }
  334. size = dev->devtype->workbuf_size;
  335. if (dev->devtype->product == CODA_960 &&
  336. q_data->fourcc == V4L2_PIX_FMT_H264)
  337. size += CODA9_PS_SAVE_SIZE;
  338. ret = coda_alloc_context_buf(ctx, &ctx->workbuf, size, "workbuf");
  339. if (ret < 0) {
  340. v4l2_err(&dev->v4l2_dev,
  341. "failed to allocate %d byte context buffer",
  342. ctx->workbuf.size);
  343. goto err;
  344. }
  345. return 0;
  346. err:
  347. coda_free_context_buffers(ctx);
  348. return ret;
  349. }
  350. static int coda_encode_header(struct coda_ctx *ctx, struct vb2_buffer *buf,
  351. int header_code, u8 *header, int *size)
  352. {
  353. struct coda_dev *dev = ctx->dev;
  354. size_t bufsize;
  355. int ret;
  356. int i;
  357. if (dev->devtype->product == CODA_960)
  358. memset(vb2_plane_vaddr(buf, 0), 0, 64);
  359. coda_write(dev, vb2_dma_contig_plane_dma_addr(buf, 0),
  360. CODA_CMD_ENC_HEADER_BB_START);
  361. bufsize = vb2_plane_size(buf, 0);
  362. if (dev->devtype->product == CODA_960)
  363. bufsize /= 1024;
  364. coda_write(dev, bufsize, CODA_CMD_ENC_HEADER_BB_SIZE);
  365. coda_write(dev, header_code, CODA_CMD_ENC_HEADER_CODE);
  366. ret = coda_command_sync(ctx, CODA_COMMAND_ENCODE_HEADER);
  367. if (ret < 0) {
  368. v4l2_err(&dev->v4l2_dev, "CODA_COMMAND_ENCODE_HEADER timeout\n");
  369. return ret;
  370. }
  371. if (dev->devtype->product == CODA_960) {
  372. for (i = 63; i > 0; i--)
  373. if (((char *)vb2_plane_vaddr(buf, 0))[i] != 0)
  374. break;
  375. *size = i + 1;
  376. } else {
  377. *size = coda_read(dev, CODA_REG_BIT_WR_PTR(ctx->reg_idx)) -
  378. coda_read(dev, CODA_CMD_ENC_HEADER_BB_START);
  379. }
  380. memcpy(header, vb2_plane_vaddr(buf, 0), *size);
  381. return 0;
  382. }
  383. static phys_addr_t coda_iram_alloc(struct coda_iram_info *iram, size_t size)
  384. {
  385. phys_addr_t ret;
  386. size = round_up(size, 1024);
  387. if (size > iram->remaining)
  388. return 0;
  389. iram->remaining -= size;
  390. ret = iram->next_paddr;
  391. iram->next_paddr += size;
  392. return ret;
  393. }
  394. static void coda_setup_iram(struct coda_ctx *ctx)
  395. {
  396. struct coda_iram_info *iram_info = &ctx->iram_info;
  397. struct coda_dev *dev = ctx->dev;
  398. int w64, w128;
  399. int mb_width;
  400. int dbk_bits;
  401. int bit_bits;
  402. int ip_bits;
  403. memset(iram_info, 0, sizeof(*iram_info));
  404. iram_info->next_paddr = dev->iram.paddr;
  405. iram_info->remaining = dev->iram.size;
  406. if (!dev->iram.vaddr)
  407. return;
  408. switch (dev->devtype->product) {
  409. case CODA_7541:
  410. dbk_bits = CODA7_USE_HOST_DBK_ENABLE | CODA7_USE_DBK_ENABLE;
  411. bit_bits = CODA7_USE_HOST_BIT_ENABLE | CODA7_USE_BIT_ENABLE;
  412. ip_bits = CODA7_USE_HOST_IP_ENABLE | CODA7_USE_IP_ENABLE;
  413. break;
  414. case CODA_960:
  415. dbk_bits = CODA9_USE_HOST_DBK_ENABLE | CODA9_USE_DBK_ENABLE;
  416. bit_bits = CODA9_USE_HOST_BIT_ENABLE | CODA7_USE_BIT_ENABLE;
  417. ip_bits = CODA9_USE_HOST_IP_ENABLE | CODA7_USE_IP_ENABLE;
  418. break;
  419. default: /* CODA_DX6 */
  420. return;
  421. }
  422. if (ctx->inst_type == CODA_INST_ENCODER) {
  423. struct coda_q_data *q_data_src;
  424. q_data_src = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT);
  425. mb_width = DIV_ROUND_UP(q_data_src->width, 16);
  426. w128 = mb_width * 128;
  427. w64 = mb_width * 64;
  428. /* Prioritize in case IRAM is too small for everything */
  429. if (dev->devtype->product == CODA_7541) {
  430. iram_info->search_ram_size = round_up(mb_width * 16 *
  431. 36 + 2048, 1024);
  432. iram_info->search_ram_paddr = coda_iram_alloc(iram_info,
  433. iram_info->search_ram_size);
  434. if (!iram_info->search_ram_paddr) {
  435. pr_err("IRAM is smaller than the search ram size\n");
  436. goto out;
  437. }
  438. iram_info->axi_sram_use |= CODA7_USE_HOST_ME_ENABLE |
  439. CODA7_USE_ME_ENABLE;
  440. }
  441. /* Only H.264BP and H.263P3 are considered */
  442. iram_info->buf_dbk_y_use = coda_iram_alloc(iram_info, w64);
  443. iram_info->buf_dbk_c_use = coda_iram_alloc(iram_info, w64);
  444. if (!iram_info->buf_dbk_c_use)
  445. goto out;
  446. iram_info->axi_sram_use |= dbk_bits;
  447. iram_info->buf_bit_use = coda_iram_alloc(iram_info, w128);
  448. if (!iram_info->buf_bit_use)
  449. goto out;
  450. iram_info->axi_sram_use |= bit_bits;
  451. iram_info->buf_ip_ac_dc_use = coda_iram_alloc(iram_info, w128);
  452. if (!iram_info->buf_ip_ac_dc_use)
  453. goto out;
  454. iram_info->axi_sram_use |= ip_bits;
  455. /* OVL and BTP disabled for encoder */
  456. } else if (ctx->inst_type == CODA_INST_DECODER) {
  457. struct coda_q_data *q_data_dst;
  458. q_data_dst = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE);
  459. mb_width = DIV_ROUND_UP(q_data_dst->width, 16);
  460. w128 = mb_width * 128;
  461. iram_info->buf_dbk_y_use = coda_iram_alloc(iram_info, w128);
  462. iram_info->buf_dbk_c_use = coda_iram_alloc(iram_info, w128);
  463. if (!iram_info->buf_dbk_c_use)
  464. goto out;
  465. iram_info->axi_sram_use |= dbk_bits;
  466. iram_info->buf_bit_use = coda_iram_alloc(iram_info, w128);
  467. if (!iram_info->buf_bit_use)
  468. goto out;
  469. iram_info->axi_sram_use |= bit_bits;
  470. iram_info->buf_ip_ac_dc_use = coda_iram_alloc(iram_info, w128);
  471. if (!iram_info->buf_ip_ac_dc_use)
  472. goto out;
  473. iram_info->axi_sram_use |= ip_bits;
  474. /* OVL and BTP unused as there is no VC1 support yet */
  475. }
  476. out:
  477. if (!(iram_info->axi_sram_use & CODA7_USE_HOST_IP_ENABLE))
  478. v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev,
  479. "IRAM smaller than needed\n");
  480. if (dev->devtype->product == CODA_7541) {
  481. /* TODO - Enabling these causes picture errors on CODA7541 */
  482. if (ctx->inst_type == CODA_INST_DECODER) {
  483. /* fw 1.4.50 */
  484. iram_info->axi_sram_use &= ~(CODA7_USE_HOST_IP_ENABLE |
  485. CODA7_USE_IP_ENABLE);
  486. } else {
  487. /* fw 13.4.29 */
  488. iram_info->axi_sram_use &= ~(CODA7_USE_HOST_IP_ENABLE |
  489. CODA7_USE_HOST_DBK_ENABLE |
  490. CODA7_USE_IP_ENABLE |
  491. CODA7_USE_DBK_ENABLE);
  492. }
  493. }
  494. }
  495. static u32 coda_supported_firmwares[] = {
  496. CODA_FIRMWARE_VERNUM(CODA_DX6, 2, 2, 5),
  497. CODA_FIRMWARE_VERNUM(CODA_7541, 1, 4, 50),
  498. CODA_FIRMWARE_VERNUM(CODA_960, 2, 1, 5),
  499. };
  500. static bool coda_firmware_supported(u32 vernum)
  501. {
  502. int i;
  503. for (i = 0; i < ARRAY_SIZE(coda_supported_firmwares); i++)
  504. if (vernum == coda_supported_firmwares[i])
  505. return true;
  506. return false;
  507. }
  508. int coda_check_firmware(struct coda_dev *dev)
  509. {
  510. u16 product, major, minor, release;
  511. u32 data;
  512. int ret;
  513. ret = clk_prepare_enable(dev->clk_per);
  514. if (ret)
  515. goto err_clk_per;
  516. ret = clk_prepare_enable(dev->clk_ahb);
  517. if (ret)
  518. goto err_clk_ahb;
  519. coda_write(dev, 0, CODA_CMD_FIRMWARE_VERNUM);
  520. coda_write(dev, CODA_REG_BIT_BUSY_FLAG, CODA_REG_BIT_BUSY);
  521. coda_write(dev, 0, CODA_REG_BIT_RUN_INDEX);
  522. coda_write(dev, 0, CODA_REG_BIT_RUN_COD_STD);
  523. coda_write(dev, CODA_COMMAND_FIRMWARE_GET, CODA_REG_BIT_RUN_COMMAND);
  524. if (coda_wait_timeout(dev)) {
  525. v4l2_err(&dev->v4l2_dev, "firmware get command error\n");
  526. ret = -EIO;
  527. goto err_run_cmd;
  528. }
  529. if (dev->devtype->product == CODA_960) {
  530. data = coda_read(dev, CODA9_CMD_FIRMWARE_CODE_REV);
  531. v4l2_info(&dev->v4l2_dev, "Firmware code revision: %d\n",
  532. data);
  533. }
  534. /* Check we are compatible with the loaded firmware */
  535. data = coda_read(dev, CODA_CMD_FIRMWARE_VERNUM);
  536. product = CODA_FIRMWARE_PRODUCT(data);
  537. major = CODA_FIRMWARE_MAJOR(data);
  538. minor = CODA_FIRMWARE_MINOR(data);
  539. release = CODA_FIRMWARE_RELEASE(data);
  540. clk_disable_unprepare(dev->clk_per);
  541. clk_disable_unprepare(dev->clk_ahb);
  542. if (product != dev->devtype->product) {
  543. v4l2_err(&dev->v4l2_dev,
  544. "Wrong firmware. Hw: %s, Fw: %s, Version: %u.%u.%u\n",
  545. coda_product_name(dev->devtype->product),
  546. coda_product_name(product), major, minor, release);
  547. return -EINVAL;
  548. }
  549. v4l2_info(&dev->v4l2_dev, "Initialized %s.\n",
  550. coda_product_name(product));
  551. if (coda_firmware_supported(data)) {
  552. v4l2_info(&dev->v4l2_dev, "Firmware version: %u.%u.%u\n",
  553. major, minor, release);
  554. } else {
  555. v4l2_warn(&dev->v4l2_dev,
  556. "Unsupported firmware version: %u.%u.%u\n",
  557. major, minor, release);
  558. }
  559. return 0;
  560. err_run_cmd:
  561. clk_disable_unprepare(dev->clk_ahb);
  562. err_clk_ahb:
  563. clk_disable_unprepare(dev->clk_per);
  564. err_clk_per:
  565. return ret;
  566. }
  567. /*
  568. * Encoder context operations
  569. */
  570. static int coda_start_encoding(struct coda_ctx *ctx)
  571. {
  572. struct coda_dev *dev = ctx->dev;
  573. struct v4l2_device *v4l2_dev = &dev->v4l2_dev;
  574. struct coda_q_data *q_data_src, *q_data_dst;
  575. u32 bitstream_buf, bitstream_size;
  576. struct vb2_buffer *buf;
  577. int gamma, ret, value;
  578. u32 dst_fourcc;
  579. q_data_src = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT);
  580. q_data_dst = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE);
  581. dst_fourcc = q_data_dst->fourcc;
  582. /* Allocate per-instance buffers */
  583. ret = coda_alloc_context_buffers(ctx, q_data_src);
  584. if (ret < 0)
  585. return ret;
  586. buf = v4l2_m2m_next_dst_buf(ctx->fh.m2m_ctx);
  587. bitstream_buf = vb2_dma_contig_plane_dma_addr(buf, 0);
  588. bitstream_size = q_data_dst->sizeimage;
  589. if (!coda_is_initialized(dev)) {
  590. v4l2_err(v4l2_dev, "coda is not initialized.\n");
  591. return -EFAULT;
  592. }
  593. mutex_lock(&dev->coda_mutex);
  594. coda_write(dev, ctx->parabuf.paddr, CODA_REG_BIT_PARA_BUF_ADDR);
  595. coda_write(dev, bitstream_buf, CODA_REG_BIT_RD_PTR(ctx->reg_idx));
  596. coda_write(dev, bitstream_buf, CODA_REG_BIT_WR_PTR(ctx->reg_idx));
  597. switch (dev->devtype->product) {
  598. case CODA_DX6:
  599. coda_write(dev, CODADX6_STREAM_BUF_DYNALLOC_EN |
  600. CODADX6_STREAM_BUF_PIC_RESET, CODA_REG_BIT_STREAM_CTRL);
  601. break;
  602. case CODA_960:
  603. coda_write(dev, 0, CODA9_GDI_WPROT_RGN_EN);
  604. /* fallthrough */
  605. case CODA_7541:
  606. coda_write(dev, CODA7_STREAM_BUF_DYNALLOC_EN |
  607. CODA7_STREAM_BUF_PIC_RESET, CODA_REG_BIT_STREAM_CTRL);
  608. break;
  609. }
  610. value = coda_read(dev, CODA_REG_BIT_FRAME_MEM_CTRL);
  611. value &= ~(1 << 2 | 0x7 << 9);
  612. ctx->frame_mem_ctrl = value;
  613. coda_write(dev, value, CODA_REG_BIT_FRAME_MEM_CTRL);
  614. if (dev->devtype->product == CODA_DX6) {
  615. /* Configure the coda */
  616. coda_write(dev, dev->iram.paddr,
  617. CODADX6_REG_BIT_SEARCH_RAM_BASE_ADDR);
  618. }
  619. /* Could set rotation here if needed */
  620. switch (dev->devtype->product) {
  621. case CODA_DX6:
  622. value = (q_data_src->width & CODADX6_PICWIDTH_MASK)
  623. << CODADX6_PICWIDTH_OFFSET;
  624. value |= (q_data_src->height & CODADX6_PICHEIGHT_MASK)
  625. << CODA_PICHEIGHT_OFFSET;
  626. break;
  627. case CODA_7541:
  628. if (dst_fourcc == V4L2_PIX_FMT_H264) {
  629. value = (round_up(q_data_src->width, 16) &
  630. CODA7_PICWIDTH_MASK) << CODA7_PICWIDTH_OFFSET;
  631. value |= (round_up(q_data_src->height, 16) &
  632. CODA7_PICHEIGHT_MASK) << CODA_PICHEIGHT_OFFSET;
  633. break;
  634. }
  635. /* fallthrough */
  636. case CODA_960:
  637. value = (q_data_src->width & CODA7_PICWIDTH_MASK)
  638. << CODA7_PICWIDTH_OFFSET;
  639. value |= (q_data_src->height & CODA7_PICHEIGHT_MASK)
  640. << CODA_PICHEIGHT_OFFSET;
  641. }
  642. coda_write(dev, value, CODA_CMD_ENC_SEQ_SRC_SIZE);
  643. coda_write(dev, ctx->params.framerate,
  644. CODA_CMD_ENC_SEQ_SRC_F_RATE);
  645. ctx->params.codec_mode = ctx->codec->mode;
  646. switch (dst_fourcc) {
  647. case V4L2_PIX_FMT_MPEG4:
  648. if (dev->devtype->product == CODA_960)
  649. coda_write(dev, CODA9_STD_MPEG4,
  650. CODA_CMD_ENC_SEQ_COD_STD);
  651. else
  652. coda_write(dev, CODA_STD_MPEG4,
  653. CODA_CMD_ENC_SEQ_COD_STD);
  654. coda_write(dev, 0, CODA_CMD_ENC_SEQ_MP4_PARA);
  655. break;
  656. case V4L2_PIX_FMT_H264:
  657. if (dev->devtype->product == CODA_960)
  658. coda_write(dev, CODA9_STD_H264,
  659. CODA_CMD_ENC_SEQ_COD_STD);
  660. else
  661. coda_write(dev, CODA_STD_H264,
  662. CODA_CMD_ENC_SEQ_COD_STD);
  663. if (ctx->params.h264_deblk_enabled) {
  664. value = ((ctx->params.h264_deblk_alpha &
  665. CODA_264PARAM_DEBLKFILTEROFFSETALPHA_MASK) <<
  666. CODA_264PARAM_DEBLKFILTEROFFSETALPHA_OFFSET) |
  667. ((ctx->params.h264_deblk_beta &
  668. CODA_264PARAM_DEBLKFILTEROFFSETBETA_MASK) <<
  669. CODA_264PARAM_DEBLKFILTEROFFSETBETA_OFFSET);
  670. } else {
  671. value = 1 << CODA_264PARAM_DISABLEDEBLK_OFFSET;
  672. }
  673. coda_write(dev, value, CODA_CMD_ENC_SEQ_264_PARA);
  674. break;
  675. default:
  676. v4l2_err(v4l2_dev,
  677. "dst format (0x%08x) invalid.\n", dst_fourcc);
  678. ret = -EINVAL;
  679. goto out;
  680. }
  681. switch (ctx->params.slice_mode) {
  682. case V4L2_MPEG_VIDEO_MULTI_SLICE_MODE_SINGLE:
  683. value = 0;
  684. break;
  685. case V4L2_MPEG_VIDEO_MULTI_SICE_MODE_MAX_MB:
  686. value = (ctx->params.slice_max_mb & CODA_SLICING_SIZE_MASK)
  687. << CODA_SLICING_SIZE_OFFSET;
  688. value |= (1 & CODA_SLICING_UNIT_MASK)
  689. << CODA_SLICING_UNIT_OFFSET;
  690. value |= 1 & CODA_SLICING_MODE_MASK;
  691. break;
  692. case V4L2_MPEG_VIDEO_MULTI_SICE_MODE_MAX_BYTES:
  693. value = (ctx->params.slice_max_bits & CODA_SLICING_SIZE_MASK)
  694. << CODA_SLICING_SIZE_OFFSET;
  695. value |= (0 & CODA_SLICING_UNIT_MASK)
  696. << CODA_SLICING_UNIT_OFFSET;
  697. value |= 1 & CODA_SLICING_MODE_MASK;
  698. break;
  699. }
  700. coda_write(dev, value, CODA_CMD_ENC_SEQ_SLICE_MODE);
  701. value = ctx->params.gop_size & CODA_GOP_SIZE_MASK;
  702. coda_write(dev, value, CODA_CMD_ENC_SEQ_GOP_SIZE);
  703. if (ctx->params.bitrate) {
  704. /* Rate control enabled */
  705. value = (ctx->params.bitrate & CODA_RATECONTROL_BITRATE_MASK)
  706. << CODA_RATECONTROL_BITRATE_OFFSET;
  707. value |= 1 & CODA_RATECONTROL_ENABLE_MASK;
  708. if (dev->devtype->product == CODA_960)
  709. value |= BIT(31); /* disable autoskip */
  710. } else {
  711. value = 0;
  712. }
  713. coda_write(dev, value, CODA_CMD_ENC_SEQ_RC_PARA);
  714. coda_write(dev, 0, CODA_CMD_ENC_SEQ_RC_BUF_SIZE);
  715. coda_write(dev, ctx->params.intra_refresh,
  716. CODA_CMD_ENC_SEQ_INTRA_REFRESH);
  717. coda_write(dev, bitstream_buf, CODA_CMD_ENC_SEQ_BB_START);
  718. coda_write(dev, bitstream_size / 1024, CODA_CMD_ENC_SEQ_BB_SIZE);
  719. value = 0;
  720. if (dev->devtype->product == CODA_960)
  721. gamma = CODA9_DEFAULT_GAMMA;
  722. else
  723. gamma = CODA_DEFAULT_GAMMA;
  724. if (gamma > 0) {
  725. coda_write(dev, (gamma & CODA_GAMMA_MASK) << CODA_GAMMA_OFFSET,
  726. CODA_CMD_ENC_SEQ_RC_GAMMA);
  727. }
  728. if (ctx->params.h264_min_qp || ctx->params.h264_max_qp) {
  729. coda_write(dev,
  730. ctx->params.h264_min_qp << CODA_QPMIN_OFFSET |
  731. ctx->params.h264_max_qp << CODA_QPMAX_OFFSET,
  732. CODA_CMD_ENC_SEQ_RC_QP_MIN_MAX);
  733. }
  734. if (dev->devtype->product == CODA_960) {
  735. if (ctx->params.h264_max_qp)
  736. value |= 1 << CODA9_OPTION_RCQPMAX_OFFSET;
  737. if (CODA_DEFAULT_GAMMA > 0)
  738. value |= 1 << CODA9_OPTION_GAMMA_OFFSET;
  739. } else {
  740. if (CODA_DEFAULT_GAMMA > 0) {
  741. if (dev->devtype->product == CODA_DX6)
  742. value |= 1 << CODADX6_OPTION_GAMMA_OFFSET;
  743. else
  744. value |= 1 << CODA7_OPTION_GAMMA_OFFSET;
  745. }
  746. if (ctx->params.h264_min_qp)
  747. value |= 1 << CODA7_OPTION_RCQPMIN_OFFSET;
  748. if (ctx->params.h264_max_qp)
  749. value |= 1 << CODA7_OPTION_RCQPMAX_OFFSET;
  750. }
  751. coda_write(dev, value, CODA_CMD_ENC_SEQ_OPTION);
  752. coda_write(dev, 0, CODA_CMD_ENC_SEQ_RC_INTERVAL_MODE);
  753. coda_setup_iram(ctx);
  754. if (dst_fourcc == V4L2_PIX_FMT_H264) {
  755. switch (dev->devtype->product) {
  756. case CODA_DX6:
  757. value = FMO_SLICE_SAVE_BUF_SIZE << 7;
  758. coda_write(dev, value, CODADX6_CMD_ENC_SEQ_FMO);
  759. break;
  760. case CODA_7541:
  761. coda_write(dev, ctx->iram_info.search_ram_paddr,
  762. CODA7_CMD_ENC_SEQ_SEARCH_BASE);
  763. coda_write(dev, ctx->iram_info.search_ram_size,
  764. CODA7_CMD_ENC_SEQ_SEARCH_SIZE);
  765. break;
  766. case CODA_960:
  767. coda_write(dev, 0, CODA9_CMD_ENC_SEQ_ME_OPTION);
  768. coda_write(dev, 0, CODA9_CMD_ENC_SEQ_INTRA_WEIGHT);
  769. }
  770. }
  771. ret = coda_command_sync(ctx, CODA_COMMAND_SEQ_INIT);
  772. if (ret < 0) {
  773. v4l2_err(v4l2_dev, "CODA_COMMAND_SEQ_INIT timeout\n");
  774. goto out;
  775. }
  776. if (coda_read(dev, CODA_RET_ENC_SEQ_SUCCESS) == 0) {
  777. v4l2_err(v4l2_dev, "CODA_COMMAND_SEQ_INIT failed\n");
  778. ret = -EFAULT;
  779. goto out;
  780. }
  781. if (dev->devtype->product == CODA_960)
  782. ctx->num_internal_frames = 4;
  783. else
  784. ctx->num_internal_frames = 2;
  785. ret = coda_alloc_framebuffers(ctx, q_data_src, dst_fourcc);
  786. if (ret < 0) {
  787. v4l2_err(v4l2_dev, "failed to allocate framebuffers\n");
  788. goto out;
  789. }
  790. coda_write(dev, ctx->num_internal_frames, CODA_CMD_SET_FRAME_BUF_NUM);
  791. coda_write(dev, q_data_src->bytesperline,
  792. CODA_CMD_SET_FRAME_BUF_STRIDE);
  793. if (dev->devtype->product == CODA_7541) {
  794. coda_write(dev, q_data_src->bytesperline,
  795. CODA7_CMD_SET_FRAME_SOURCE_BUF_STRIDE);
  796. }
  797. if (dev->devtype->product != CODA_DX6) {
  798. coda_write(dev, ctx->iram_info.buf_bit_use,
  799. CODA7_CMD_SET_FRAME_AXI_BIT_ADDR);
  800. coda_write(dev, ctx->iram_info.buf_ip_ac_dc_use,
  801. CODA7_CMD_SET_FRAME_AXI_IPACDC_ADDR);
  802. coda_write(dev, ctx->iram_info.buf_dbk_y_use,
  803. CODA7_CMD_SET_FRAME_AXI_DBKY_ADDR);
  804. coda_write(dev, ctx->iram_info.buf_dbk_c_use,
  805. CODA7_CMD_SET_FRAME_AXI_DBKC_ADDR);
  806. coda_write(dev, ctx->iram_info.buf_ovl_use,
  807. CODA7_CMD_SET_FRAME_AXI_OVL_ADDR);
  808. if (dev->devtype->product == CODA_960) {
  809. coda_write(dev, ctx->iram_info.buf_btp_use,
  810. CODA9_CMD_SET_FRAME_AXI_BTP_ADDR);
  811. /* FIXME */
  812. coda_write(dev, ctx->internal_frames[2].paddr,
  813. CODA9_CMD_SET_FRAME_SUBSAMP_A);
  814. coda_write(dev, ctx->internal_frames[3].paddr,
  815. CODA9_CMD_SET_FRAME_SUBSAMP_B);
  816. }
  817. }
  818. ret = coda_command_sync(ctx, CODA_COMMAND_SET_FRAME_BUF);
  819. if (ret < 0) {
  820. v4l2_err(v4l2_dev, "CODA_COMMAND_SET_FRAME_BUF timeout\n");
  821. goto out;
  822. }
  823. /* Save stream headers */
  824. buf = v4l2_m2m_next_dst_buf(ctx->fh.m2m_ctx);
  825. switch (dst_fourcc) {
  826. case V4L2_PIX_FMT_H264:
  827. /*
  828. * Get SPS in the first frame and copy it to an
  829. * intermediate buffer.
  830. */
  831. ret = coda_encode_header(ctx, buf, CODA_HEADER_H264_SPS,
  832. &ctx->vpu_header[0][0],
  833. &ctx->vpu_header_size[0]);
  834. if (ret < 0)
  835. goto out;
  836. /*
  837. * Get PPS in the first frame and copy it to an
  838. * intermediate buffer.
  839. */
  840. ret = coda_encode_header(ctx, buf, CODA_HEADER_H264_PPS,
  841. &ctx->vpu_header[1][0],
  842. &ctx->vpu_header_size[1]);
  843. if (ret < 0)
  844. goto out;
  845. /*
  846. * Length of H.264 headers is variable and thus it might not be
  847. * aligned for the coda to append the encoded frame. In that is
  848. * the case a filler NAL must be added to header 2.
  849. */
  850. ctx->vpu_header_size[2] = coda_h264_padding(
  851. (ctx->vpu_header_size[0] +
  852. ctx->vpu_header_size[1]),
  853. ctx->vpu_header[2]);
  854. break;
  855. case V4L2_PIX_FMT_MPEG4:
  856. /*
  857. * Get VOS in the first frame and copy it to an
  858. * intermediate buffer
  859. */
  860. ret = coda_encode_header(ctx, buf, CODA_HEADER_MP4V_VOS,
  861. &ctx->vpu_header[0][0],
  862. &ctx->vpu_header_size[0]);
  863. if (ret < 0)
  864. goto out;
  865. ret = coda_encode_header(ctx, buf, CODA_HEADER_MP4V_VIS,
  866. &ctx->vpu_header[1][0],
  867. &ctx->vpu_header_size[1]);
  868. if (ret < 0)
  869. goto out;
  870. ret = coda_encode_header(ctx, buf, CODA_HEADER_MP4V_VOL,
  871. &ctx->vpu_header[2][0],
  872. &ctx->vpu_header_size[2]);
  873. if (ret < 0)
  874. goto out;
  875. break;
  876. default:
  877. /* No more formats need to save headers at the moment */
  878. break;
  879. }
  880. out:
  881. mutex_unlock(&dev->coda_mutex);
  882. return ret;
  883. }
  884. static int coda_prepare_encode(struct coda_ctx *ctx)
  885. {
  886. struct coda_q_data *q_data_src, *q_data_dst;
  887. struct vb2_buffer *src_buf, *dst_buf;
  888. struct coda_dev *dev = ctx->dev;
  889. int force_ipicture;
  890. int quant_param = 0;
  891. u32 picture_y, picture_cb, picture_cr;
  892. u32 pic_stream_buffer_addr, pic_stream_buffer_size;
  893. u32 dst_fourcc;
  894. src_buf = v4l2_m2m_next_src_buf(ctx->fh.m2m_ctx);
  895. dst_buf = v4l2_m2m_next_dst_buf(ctx->fh.m2m_ctx);
  896. q_data_src = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT);
  897. q_data_dst = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE);
  898. dst_fourcc = q_data_dst->fourcc;
  899. src_buf->v4l2_buf.sequence = ctx->osequence;
  900. dst_buf->v4l2_buf.sequence = ctx->osequence;
  901. ctx->osequence++;
  902. /*
  903. * Workaround coda firmware BUG that only marks the first
  904. * frame as IDR. This is a problem for some decoders that can't
  905. * recover when a frame is lost.
  906. */
  907. if (src_buf->v4l2_buf.sequence % ctx->params.gop_size) {
  908. src_buf->v4l2_buf.flags |= V4L2_BUF_FLAG_PFRAME;
  909. src_buf->v4l2_buf.flags &= ~V4L2_BUF_FLAG_KEYFRAME;
  910. } else {
  911. src_buf->v4l2_buf.flags |= V4L2_BUF_FLAG_KEYFRAME;
  912. src_buf->v4l2_buf.flags &= ~V4L2_BUF_FLAG_PFRAME;
  913. }
  914. if (dev->devtype->product == CODA_960)
  915. coda_set_gdi_regs(ctx);
  916. /*
  917. * Copy headers at the beginning of the first frame for H.264 only.
  918. * In MPEG4 they are already copied by the coda.
  919. */
  920. if (src_buf->v4l2_buf.sequence == 0) {
  921. pic_stream_buffer_addr =
  922. vb2_dma_contig_plane_dma_addr(dst_buf, 0) +
  923. ctx->vpu_header_size[0] +
  924. ctx->vpu_header_size[1] +
  925. ctx->vpu_header_size[2];
  926. pic_stream_buffer_size = CODA_MAX_FRAME_SIZE -
  927. ctx->vpu_header_size[0] -
  928. ctx->vpu_header_size[1] -
  929. ctx->vpu_header_size[2];
  930. memcpy(vb2_plane_vaddr(dst_buf, 0),
  931. &ctx->vpu_header[0][0], ctx->vpu_header_size[0]);
  932. memcpy(vb2_plane_vaddr(dst_buf, 0) + ctx->vpu_header_size[0],
  933. &ctx->vpu_header[1][0], ctx->vpu_header_size[1]);
  934. memcpy(vb2_plane_vaddr(dst_buf, 0) + ctx->vpu_header_size[0] +
  935. ctx->vpu_header_size[1], &ctx->vpu_header[2][0],
  936. ctx->vpu_header_size[2]);
  937. } else {
  938. pic_stream_buffer_addr =
  939. vb2_dma_contig_plane_dma_addr(dst_buf, 0);
  940. pic_stream_buffer_size = CODA_MAX_FRAME_SIZE;
  941. }
  942. if (src_buf->v4l2_buf.flags & V4L2_BUF_FLAG_KEYFRAME) {
  943. force_ipicture = 1;
  944. switch (dst_fourcc) {
  945. case V4L2_PIX_FMT_H264:
  946. quant_param = ctx->params.h264_intra_qp;
  947. break;
  948. case V4L2_PIX_FMT_MPEG4:
  949. quant_param = ctx->params.mpeg4_intra_qp;
  950. break;
  951. default:
  952. v4l2_warn(&ctx->dev->v4l2_dev,
  953. "cannot set intra qp, fmt not supported\n");
  954. break;
  955. }
  956. } else {
  957. force_ipicture = 0;
  958. switch (dst_fourcc) {
  959. case V4L2_PIX_FMT_H264:
  960. quant_param = ctx->params.h264_inter_qp;
  961. break;
  962. case V4L2_PIX_FMT_MPEG4:
  963. quant_param = ctx->params.mpeg4_inter_qp;
  964. break;
  965. default:
  966. v4l2_warn(&ctx->dev->v4l2_dev,
  967. "cannot set inter qp, fmt not supported\n");
  968. break;
  969. }
  970. }
  971. /* submit */
  972. coda_write(dev, CODA_ROT_MIR_ENABLE | ctx->params.rot_mode,
  973. CODA_CMD_ENC_PIC_ROT_MODE);
  974. coda_write(dev, quant_param, CODA_CMD_ENC_PIC_QS);
  975. picture_y = vb2_dma_contig_plane_dma_addr(src_buf, 0);
  976. switch (q_data_src->fourcc) {
  977. case V4L2_PIX_FMT_YVU420:
  978. /* Switch Cb and Cr for YVU420 format */
  979. picture_cr = picture_y + q_data_src->bytesperline *
  980. q_data_src->height;
  981. picture_cb = picture_cr + q_data_src->bytesperline / 2 *
  982. q_data_src->height / 2;
  983. break;
  984. case V4L2_PIX_FMT_YUV420:
  985. default:
  986. picture_cb = picture_y + q_data_src->bytesperline *
  987. q_data_src->height;
  988. picture_cr = picture_cb + q_data_src->bytesperline / 2 *
  989. q_data_src->height / 2;
  990. break;
  991. }
  992. if (dev->devtype->product == CODA_960) {
  993. coda_write(dev, 4/*FIXME: 0*/, CODA9_CMD_ENC_PIC_SRC_INDEX);
  994. coda_write(dev, q_data_src->width, CODA9_CMD_ENC_PIC_SRC_STRIDE);
  995. coda_write(dev, 0, CODA9_CMD_ENC_PIC_SUB_FRAME_SYNC);
  996. coda_write(dev, picture_y, CODA9_CMD_ENC_PIC_SRC_ADDR_Y);
  997. coda_write(dev, picture_cb, CODA9_CMD_ENC_PIC_SRC_ADDR_CB);
  998. coda_write(dev, picture_cr, CODA9_CMD_ENC_PIC_SRC_ADDR_CR);
  999. } else {
  1000. coda_write(dev, picture_y, CODA_CMD_ENC_PIC_SRC_ADDR_Y);
  1001. coda_write(dev, picture_cb, CODA_CMD_ENC_PIC_SRC_ADDR_CB);
  1002. coda_write(dev, picture_cr, CODA_CMD_ENC_PIC_SRC_ADDR_CR);
  1003. }
  1004. coda_write(dev, force_ipicture << 1 & 0x2,
  1005. CODA_CMD_ENC_PIC_OPTION);
  1006. coda_write(dev, pic_stream_buffer_addr, CODA_CMD_ENC_PIC_BB_START);
  1007. coda_write(dev, pic_stream_buffer_size / 1024,
  1008. CODA_CMD_ENC_PIC_BB_SIZE);
  1009. if (!ctx->streamon_out) {
  1010. /* After streamoff on the output side, set stream end flag */
  1011. ctx->bit_stream_param |= CODA_BIT_STREAM_END_FLAG;
  1012. coda_write(dev, ctx->bit_stream_param,
  1013. CODA_REG_BIT_BIT_STREAM_PARAM);
  1014. }
  1015. if (dev->devtype->product != CODA_DX6)
  1016. coda_write(dev, ctx->iram_info.axi_sram_use,
  1017. CODA7_REG_BIT_AXI_SRAM_USE);
  1018. coda_command_async(ctx, CODA_COMMAND_PIC_RUN);
  1019. return 0;
  1020. }
  1021. static void coda_finish_encode(struct coda_ctx *ctx)
  1022. {
  1023. struct vb2_buffer *src_buf, *dst_buf;
  1024. struct coda_dev *dev = ctx->dev;
  1025. u32 wr_ptr, start_ptr;
  1026. src_buf = v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx);
  1027. dst_buf = v4l2_m2m_next_dst_buf(ctx->fh.m2m_ctx);
  1028. /* Get results from the coda */
  1029. start_ptr = coda_read(dev, CODA_CMD_ENC_PIC_BB_START);
  1030. wr_ptr = coda_read(dev, CODA_REG_BIT_WR_PTR(ctx->reg_idx));
  1031. /* Calculate bytesused field */
  1032. if (dst_buf->v4l2_buf.sequence == 0) {
  1033. vb2_set_plane_payload(dst_buf, 0, wr_ptr - start_ptr +
  1034. ctx->vpu_header_size[0] +
  1035. ctx->vpu_header_size[1] +
  1036. ctx->vpu_header_size[2]);
  1037. } else {
  1038. vb2_set_plane_payload(dst_buf, 0, wr_ptr - start_ptr);
  1039. }
  1040. v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev, "frame size = %u\n",
  1041. wr_ptr - start_ptr);
  1042. coda_read(dev, CODA_RET_ENC_PIC_SLICE_NUM);
  1043. coda_read(dev, CODA_RET_ENC_PIC_FLAG);
  1044. if (coda_read(dev, CODA_RET_ENC_PIC_TYPE) == 0) {
  1045. dst_buf->v4l2_buf.flags |= V4L2_BUF_FLAG_KEYFRAME;
  1046. dst_buf->v4l2_buf.flags &= ~V4L2_BUF_FLAG_PFRAME;
  1047. } else {
  1048. dst_buf->v4l2_buf.flags |= V4L2_BUF_FLAG_PFRAME;
  1049. dst_buf->v4l2_buf.flags &= ~V4L2_BUF_FLAG_KEYFRAME;
  1050. }
  1051. dst_buf->v4l2_buf.timestamp = src_buf->v4l2_buf.timestamp;
  1052. dst_buf->v4l2_buf.flags &= ~V4L2_BUF_FLAG_TSTAMP_SRC_MASK;
  1053. dst_buf->v4l2_buf.flags |=
  1054. src_buf->v4l2_buf.flags & V4L2_BUF_FLAG_TSTAMP_SRC_MASK;
  1055. dst_buf->v4l2_buf.timecode = src_buf->v4l2_buf.timecode;
  1056. v4l2_m2m_buf_done(src_buf, VB2_BUF_STATE_DONE);
  1057. dst_buf = v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx);
  1058. v4l2_m2m_buf_done(dst_buf, VB2_BUF_STATE_DONE);
  1059. ctx->gopcounter--;
  1060. if (ctx->gopcounter < 0)
  1061. ctx->gopcounter = ctx->params.gop_size - 1;
  1062. v4l2_dbg(1, coda_debug, &dev->v4l2_dev,
  1063. "job finished: encoding frame (%d) (%s)\n",
  1064. dst_buf->v4l2_buf.sequence,
  1065. (dst_buf->v4l2_buf.flags & V4L2_BUF_FLAG_KEYFRAME) ?
  1066. "KEYFRAME" : "PFRAME");
  1067. }
  1068. static void coda_seq_end_work(struct work_struct *work)
  1069. {
  1070. struct coda_ctx *ctx = container_of(work, struct coda_ctx, seq_end_work);
  1071. struct coda_dev *dev = ctx->dev;
  1072. mutex_lock(&ctx->buffer_mutex);
  1073. mutex_lock(&dev->coda_mutex);
  1074. v4l2_dbg(1, coda_debug, &dev->v4l2_dev,
  1075. "%d: %s: sent command 'SEQ_END' to coda\n", ctx->idx,
  1076. __func__);
  1077. if (coda_command_sync(ctx, CODA_COMMAND_SEQ_END)) {
  1078. v4l2_err(&dev->v4l2_dev,
  1079. "CODA_COMMAND_SEQ_END failed\n");
  1080. }
  1081. kfifo_init(&ctx->bitstream_fifo,
  1082. ctx->bitstream.vaddr, ctx->bitstream.size);
  1083. coda_free_framebuffers(ctx);
  1084. coda_free_context_buffers(ctx);
  1085. mutex_unlock(&dev->coda_mutex);
  1086. mutex_unlock(&ctx->buffer_mutex);
  1087. }
  1088. static void coda_bit_release(struct coda_ctx *ctx)
  1089. {
  1090. coda_free_framebuffers(ctx);
  1091. coda_free_context_buffers(ctx);
  1092. }
  1093. const struct coda_context_ops coda_bit_encode_ops = {
  1094. .queue_init = coda_encoder_queue_init,
  1095. .start_streaming = coda_start_encoding,
  1096. .prepare_run = coda_prepare_encode,
  1097. .finish_run = coda_finish_encode,
  1098. .seq_end_work = coda_seq_end_work,
  1099. .release = coda_bit_release,
  1100. };
  1101. /*
  1102. * Decoder context operations
  1103. */
  1104. static int __coda_start_decoding(struct coda_ctx *ctx)
  1105. {
  1106. struct coda_q_data *q_data_src, *q_data_dst;
  1107. u32 bitstream_buf, bitstream_size;
  1108. struct coda_dev *dev = ctx->dev;
  1109. int width, height;
  1110. u32 src_fourcc;
  1111. u32 val;
  1112. int ret;
  1113. /* Start decoding */
  1114. q_data_src = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT);
  1115. q_data_dst = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE);
  1116. bitstream_buf = ctx->bitstream.paddr;
  1117. bitstream_size = ctx->bitstream.size;
  1118. src_fourcc = q_data_src->fourcc;
  1119. /* Allocate per-instance buffers */
  1120. ret = coda_alloc_context_buffers(ctx, q_data_src);
  1121. if (ret < 0)
  1122. return ret;
  1123. coda_write(dev, ctx->parabuf.paddr, CODA_REG_BIT_PARA_BUF_ADDR);
  1124. /* Update coda bitstream read and write pointers from kfifo */
  1125. coda_kfifo_sync_to_device_full(ctx);
  1126. ctx->display_idx = -1;
  1127. ctx->frm_dis_flg = 0;
  1128. coda_write(dev, 0, CODA_REG_BIT_FRM_DIS_FLG(ctx->reg_idx));
  1129. coda_write(dev, CODA_BIT_DEC_SEQ_INIT_ESCAPE,
  1130. CODA_REG_BIT_BIT_STREAM_PARAM);
  1131. coda_write(dev, bitstream_buf, CODA_CMD_DEC_SEQ_BB_START);
  1132. coda_write(dev, bitstream_size / 1024, CODA_CMD_DEC_SEQ_BB_SIZE);
  1133. val = 0;
  1134. if ((dev->devtype->product == CODA_7541) ||
  1135. (dev->devtype->product == CODA_960))
  1136. val |= CODA_REORDER_ENABLE;
  1137. coda_write(dev, val, CODA_CMD_DEC_SEQ_OPTION);
  1138. ctx->params.codec_mode = ctx->codec->mode;
  1139. if (dev->devtype->product == CODA_960 &&
  1140. src_fourcc == V4L2_PIX_FMT_MPEG4)
  1141. ctx->params.codec_mode_aux = CODA_MP4_AUX_MPEG4;
  1142. else
  1143. ctx->params.codec_mode_aux = 0;
  1144. if (src_fourcc == V4L2_PIX_FMT_H264) {
  1145. if (dev->devtype->product == CODA_7541) {
  1146. coda_write(dev, ctx->psbuf.paddr,
  1147. CODA_CMD_DEC_SEQ_PS_BB_START);
  1148. coda_write(dev, (CODA7_PS_BUF_SIZE / 1024),
  1149. CODA_CMD_DEC_SEQ_PS_BB_SIZE);
  1150. }
  1151. if (dev->devtype->product == CODA_960) {
  1152. coda_write(dev, 0, CODA_CMD_DEC_SEQ_X264_MV_EN);
  1153. coda_write(dev, 512, CODA_CMD_DEC_SEQ_SPP_CHUNK_SIZE);
  1154. }
  1155. }
  1156. if (dev->devtype->product != CODA_960)
  1157. coda_write(dev, 0, CODA_CMD_DEC_SEQ_SRC_SIZE);
  1158. if (coda_command_sync(ctx, CODA_COMMAND_SEQ_INIT)) {
  1159. v4l2_err(&dev->v4l2_dev, "CODA_COMMAND_SEQ_INIT timeout\n");
  1160. coda_write(dev, 0, CODA_REG_BIT_BIT_STREAM_PARAM);
  1161. return -ETIMEDOUT;
  1162. }
  1163. /* Update kfifo out pointer from coda bitstream read pointer */
  1164. coda_kfifo_sync_from_device(ctx);
  1165. coda_write(dev, 0, CODA_REG_BIT_BIT_STREAM_PARAM);
  1166. if (coda_read(dev, CODA_RET_DEC_SEQ_SUCCESS) == 0) {
  1167. v4l2_err(&dev->v4l2_dev,
  1168. "CODA_COMMAND_SEQ_INIT failed, error code = %d\n",
  1169. coda_read(dev, CODA_RET_DEC_SEQ_ERR_REASON));
  1170. return -EAGAIN;
  1171. }
  1172. val = coda_read(dev, CODA_RET_DEC_SEQ_SRC_SIZE);
  1173. if (dev->devtype->product == CODA_DX6) {
  1174. width = (val >> CODADX6_PICWIDTH_OFFSET) & CODADX6_PICWIDTH_MASK;
  1175. height = val & CODADX6_PICHEIGHT_MASK;
  1176. } else {
  1177. width = (val >> CODA7_PICWIDTH_OFFSET) & CODA7_PICWIDTH_MASK;
  1178. height = val & CODA7_PICHEIGHT_MASK;
  1179. }
  1180. if (width > q_data_dst->width || height > q_data_dst->height) {
  1181. v4l2_err(&dev->v4l2_dev, "stream is %dx%d, not %dx%d\n",
  1182. width, height, q_data_dst->width, q_data_dst->height);
  1183. return -EINVAL;
  1184. }
  1185. width = round_up(width, 16);
  1186. height = round_up(height, 16);
  1187. v4l2_dbg(1, coda_debug, &dev->v4l2_dev, "%s instance %d now: %dx%d\n",
  1188. __func__, ctx->idx, width, height);
  1189. ctx->num_internal_frames = coda_read(dev, CODA_RET_DEC_SEQ_FRAME_NEED);
  1190. if (ctx->num_internal_frames > CODA_MAX_FRAMEBUFFERS) {
  1191. v4l2_err(&dev->v4l2_dev,
  1192. "not enough framebuffers to decode (%d < %d)\n",
  1193. CODA_MAX_FRAMEBUFFERS, ctx->num_internal_frames);
  1194. return -EINVAL;
  1195. }
  1196. if (src_fourcc == V4L2_PIX_FMT_H264) {
  1197. u32 left_right;
  1198. u32 top_bottom;
  1199. left_right = coda_read(dev, CODA_RET_DEC_SEQ_CROP_LEFT_RIGHT);
  1200. top_bottom = coda_read(dev, CODA_RET_DEC_SEQ_CROP_TOP_BOTTOM);
  1201. q_data_dst->rect.left = (left_right >> 10) & 0x3ff;
  1202. q_data_dst->rect.top = (top_bottom >> 10) & 0x3ff;
  1203. q_data_dst->rect.width = width - q_data_dst->rect.left -
  1204. (left_right & 0x3ff);
  1205. q_data_dst->rect.height = height - q_data_dst->rect.top -
  1206. (top_bottom & 0x3ff);
  1207. }
  1208. ret = coda_alloc_framebuffers(ctx, q_data_dst, src_fourcc);
  1209. if (ret < 0) {
  1210. v4l2_err(&dev->v4l2_dev, "failed to allocate framebuffers\n");
  1211. return ret;
  1212. }
  1213. /* Tell the decoder how many frame buffers we allocated. */
  1214. coda_write(dev, ctx->num_internal_frames, CODA_CMD_SET_FRAME_BUF_NUM);
  1215. coda_write(dev, width, CODA_CMD_SET_FRAME_BUF_STRIDE);
  1216. if (dev->devtype->product != CODA_DX6) {
  1217. /* Set secondary AXI IRAM */
  1218. coda_setup_iram(ctx);
  1219. coda_write(dev, ctx->iram_info.buf_bit_use,
  1220. CODA7_CMD_SET_FRAME_AXI_BIT_ADDR);
  1221. coda_write(dev, ctx->iram_info.buf_ip_ac_dc_use,
  1222. CODA7_CMD_SET_FRAME_AXI_IPACDC_ADDR);
  1223. coda_write(dev, ctx->iram_info.buf_dbk_y_use,
  1224. CODA7_CMD_SET_FRAME_AXI_DBKY_ADDR);
  1225. coda_write(dev, ctx->iram_info.buf_dbk_c_use,
  1226. CODA7_CMD_SET_FRAME_AXI_DBKC_ADDR);
  1227. coda_write(dev, ctx->iram_info.buf_ovl_use,
  1228. CODA7_CMD_SET_FRAME_AXI_OVL_ADDR);
  1229. if (dev->devtype->product == CODA_960)
  1230. coda_write(dev, ctx->iram_info.buf_btp_use,
  1231. CODA9_CMD_SET_FRAME_AXI_BTP_ADDR);
  1232. }
  1233. if (dev->devtype->product == CODA_960) {
  1234. coda_write(dev, -1, CODA9_CMD_SET_FRAME_DELAY);
  1235. coda_write(dev, 0x20262024, CODA9_CMD_SET_FRAME_CACHE_SIZE);
  1236. coda_write(dev, 2 << CODA9_CACHE_PAGEMERGE_OFFSET |
  1237. 32 << CODA9_CACHE_LUMA_BUFFER_SIZE_OFFSET |
  1238. 8 << CODA9_CACHE_CB_BUFFER_SIZE_OFFSET |
  1239. 8 << CODA9_CACHE_CR_BUFFER_SIZE_OFFSET,
  1240. CODA9_CMD_SET_FRAME_CACHE_CONFIG);
  1241. }
  1242. if (src_fourcc == V4L2_PIX_FMT_H264) {
  1243. coda_write(dev, ctx->slicebuf.paddr,
  1244. CODA_CMD_SET_FRAME_SLICE_BB_START);
  1245. coda_write(dev, ctx->slicebuf.size / 1024,
  1246. CODA_CMD_SET_FRAME_SLICE_BB_SIZE);
  1247. }
  1248. if (dev->devtype->product == CODA_7541) {
  1249. int max_mb_x = 1920 / 16;
  1250. int max_mb_y = 1088 / 16;
  1251. int max_mb_num = max_mb_x * max_mb_y;
  1252. coda_write(dev, max_mb_num << 16 | max_mb_x << 8 | max_mb_y,
  1253. CODA7_CMD_SET_FRAME_MAX_DEC_SIZE);
  1254. } else if (dev->devtype->product == CODA_960) {
  1255. int max_mb_x = 1920 / 16;
  1256. int max_mb_y = 1088 / 16;
  1257. int max_mb_num = max_mb_x * max_mb_y;
  1258. coda_write(dev, max_mb_num << 16 | max_mb_x << 8 | max_mb_y,
  1259. CODA9_CMD_SET_FRAME_MAX_DEC_SIZE);
  1260. }
  1261. if (coda_command_sync(ctx, CODA_COMMAND_SET_FRAME_BUF)) {
  1262. v4l2_err(&ctx->dev->v4l2_dev,
  1263. "CODA_COMMAND_SET_FRAME_BUF timeout\n");
  1264. return -ETIMEDOUT;
  1265. }
  1266. return 0;
  1267. }
  1268. static int coda_start_decoding(struct coda_ctx *ctx)
  1269. {
  1270. struct coda_dev *dev = ctx->dev;
  1271. int ret;
  1272. mutex_lock(&dev->coda_mutex);
  1273. ret = __coda_start_decoding(ctx);
  1274. mutex_unlock(&dev->coda_mutex);
  1275. return ret;
  1276. }
  1277. static int coda_prepare_decode(struct coda_ctx *ctx)
  1278. {
  1279. struct vb2_buffer *dst_buf;
  1280. struct coda_dev *dev = ctx->dev;
  1281. struct coda_q_data *q_data_dst;
  1282. u32 stridey, height;
  1283. u32 picture_y, picture_cb, picture_cr;
  1284. dst_buf = v4l2_m2m_next_dst_buf(ctx->fh.m2m_ctx);
  1285. q_data_dst = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE);
  1286. if (ctx->params.rot_mode & CODA_ROT_90) {
  1287. stridey = q_data_dst->height;
  1288. height = q_data_dst->width;
  1289. } else {
  1290. stridey = q_data_dst->width;
  1291. height = q_data_dst->height;
  1292. }
  1293. /* Try to copy source buffer contents into the bitstream ringbuffer */
  1294. mutex_lock(&ctx->bitstream_mutex);
  1295. coda_fill_bitstream(ctx);
  1296. mutex_unlock(&ctx->bitstream_mutex);
  1297. if (coda_get_bitstream_payload(ctx) < 512 &&
  1298. (!(ctx->bit_stream_param & CODA_BIT_STREAM_END_FLAG))) {
  1299. v4l2_dbg(1, coda_debug, &dev->v4l2_dev,
  1300. "bitstream payload: %d, skipping\n",
  1301. coda_get_bitstream_payload(ctx));
  1302. v4l2_m2m_job_finish(ctx->dev->m2m_dev, ctx->fh.m2m_ctx);
  1303. return -EAGAIN;
  1304. }
  1305. /* Run coda_start_decoding (again) if not yet initialized */
  1306. if (!ctx->initialized) {
  1307. int ret = __coda_start_decoding(ctx);
  1308. if (ret < 0) {
  1309. v4l2_err(&dev->v4l2_dev, "failed to start decoding\n");
  1310. v4l2_m2m_job_finish(ctx->dev->m2m_dev, ctx->fh.m2m_ctx);
  1311. return -EAGAIN;
  1312. } else {
  1313. ctx->initialized = 1;
  1314. }
  1315. }
  1316. if (dev->devtype->product == CODA_960)
  1317. coda_set_gdi_regs(ctx);
  1318. /* Set rotator output */
  1319. picture_y = vb2_dma_contig_plane_dma_addr(dst_buf, 0);
  1320. if (q_data_dst->fourcc == V4L2_PIX_FMT_YVU420) {
  1321. /* Switch Cr and Cb for YVU420 format */
  1322. picture_cr = picture_y + stridey * height;
  1323. picture_cb = picture_cr + stridey / 2 * height / 2;
  1324. } else {
  1325. picture_cb = picture_y + stridey * height;
  1326. picture_cr = picture_cb + stridey / 2 * height / 2;
  1327. }
  1328. if (dev->devtype->product == CODA_960) {
  1329. /*
  1330. * The CODA960 seems to have an internal list of buffers with
  1331. * 64 entries that includes the registered frame buffers as
  1332. * well as the rotator buffer output.
  1333. * ROT_INDEX needs to be < 0x40, but > ctx->num_internal_frames.
  1334. */
  1335. coda_write(dev, CODA_MAX_FRAMEBUFFERS + dst_buf->v4l2_buf.index,
  1336. CODA9_CMD_DEC_PIC_ROT_INDEX);
  1337. coda_write(dev, picture_y, CODA9_CMD_DEC_PIC_ROT_ADDR_Y);
  1338. coda_write(dev, picture_cb, CODA9_CMD_DEC_PIC_ROT_ADDR_CB);
  1339. coda_write(dev, picture_cr, CODA9_CMD_DEC_PIC_ROT_ADDR_CR);
  1340. coda_write(dev, stridey, CODA9_CMD_DEC_PIC_ROT_STRIDE);
  1341. } else {
  1342. coda_write(dev, picture_y, CODA_CMD_DEC_PIC_ROT_ADDR_Y);
  1343. coda_write(dev, picture_cb, CODA_CMD_DEC_PIC_ROT_ADDR_CB);
  1344. coda_write(dev, picture_cr, CODA_CMD_DEC_PIC_ROT_ADDR_CR);
  1345. coda_write(dev, stridey, CODA_CMD_DEC_PIC_ROT_STRIDE);
  1346. }
  1347. coda_write(dev, CODA_ROT_MIR_ENABLE | ctx->params.rot_mode,
  1348. CODA_CMD_DEC_PIC_ROT_MODE);
  1349. switch (dev->devtype->product) {
  1350. case CODA_DX6:
  1351. /* TBD */
  1352. case CODA_7541:
  1353. coda_write(dev, CODA_PRE_SCAN_EN, CODA_CMD_DEC_PIC_OPTION);
  1354. break;
  1355. case CODA_960:
  1356. /* 'hardcode to use interrupt disable mode'? */
  1357. coda_write(dev, (1 << 10), CODA_CMD_DEC_PIC_OPTION);
  1358. break;
  1359. }
  1360. coda_write(dev, 0, CODA_CMD_DEC_PIC_SKIP_NUM);
  1361. coda_write(dev, 0, CODA_CMD_DEC_PIC_BB_START);
  1362. coda_write(dev, 0, CODA_CMD_DEC_PIC_START_BYTE);
  1363. if (dev->devtype->product != CODA_DX6)
  1364. coda_write(dev, ctx->iram_info.axi_sram_use,
  1365. CODA7_REG_BIT_AXI_SRAM_USE);
  1366. coda_kfifo_sync_to_device_full(ctx);
  1367. coda_command_async(ctx, CODA_COMMAND_PIC_RUN);
  1368. return 0;
  1369. }
  1370. static void coda_finish_decode(struct coda_ctx *ctx)
  1371. {
  1372. struct coda_dev *dev = ctx->dev;
  1373. struct coda_q_data *q_data_src;
  1374. struct coda_q_data *q_data_dst;
  1375. struct vb2_buffer *dst_buf;
  1376. struct coda_timestamp *ts;
  1377. int width, height;
  1378. int decoded_idx;
  1379. int display_idx;
  1380. u32 src_fourcc;
  1381. int success;
  1382. u32 err_mb;
  1383. u32 val;
  1384. /* Update kfifo out pointer from coda bitstream read pointer */
  1385. coda_kfifo_sync_from_device(ctx);
  1386. /*
  1387. * in stream-end mode, the read pointer can overshoot the write pointer
  1388. * by up to 512 bytes
  1389. */
  1390. if (ctx->bit_stream_param & CODA_BIT_STREAM_END_FLAG) {
  1391. if (coda_get_bitstream_payload(ctx) >= CODA_MAX_FRAME_SIZE - 512)
  1392. kfifo_init(&ctx->bitstream_fifo,
  1393. ctx->bitstream.vaddr, ctx->bitstream.size);
  1394. }
  1395. q_data_src = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT);
  1396. src_fourcc = q_data_src->fourcc;
  1397. val = coda_read(dev, CODA_RET_DEC_PIC_SUCCESS);
  1398. if (val != 1)
  1399. pr_err("DEC_PIC_SUCCESS = %d\n", val);
  1400. success = val & 0x1;
  1401. if (!success)
  1402. v4l2_err(&dev->v4l2_dev, "decode failed\n");
  1403. if (src_fourcc == V4L2_PIX_FMT_H264) {
  1404. if (val & (1 << 3))
  1405. v4l2_err(&dev->v4l2_dev,
  1406. "insufficient PS buffer space (%d bytes)\n",
  1407. ctx->psbuf.size);
  1408. if (val & (1 << 2))
  1409. v4l2_err(&dev->v4l2_dev,
  1410. "insufficient slice buffer space (%d bytes)\n",
  1411. ctx->slicebuf.size);
  1412. }
  1413. val = coda_read(dev, CODA_RET_DEC_PIC_SIZE);
  1414. width = (val >> 16) & 0xffff;
  1415. height = val & 0xffff;
  1416. q_data_dst = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE);
  1417. /* frame crop information */
  1418. if (src_fourcc == V4L2_PIX_FMT_H264) {
  1419. u32 left_right;
  1420. u32 top_bottom;
  1421. left_right = coda_read(dev, CODA_RET_DEC_PIC_CROP_LEFT_RIGHT);
  1422. top_bottom = coda_read(dev, CODA_RET_DEC_PIC_CROP_TOP_BOTTOM);
  1423. if (left_right == 0xffffffff && top_bottom == 0xffffffff) {
  1424. /* Keep current crop information */
  1425. } else {
  1426. struct v4l2_rect *rect = &q_data_dst->rect;
  1427. rect->left = left_right >> 16 & 0xffff;
  1428. rect->top = top_bottom >> 16 & 0xffff;
  1429. rect->width = width - rect->left -
  1430. (left_right & 0xffff);
  1431. rect->height = height - rect->top -
  1432. (top_bottom & 0xffff);
  1433. }
  1434. } else {
  1435. /* no cropping */
  1436. }
  1437. err_mb = coda_read(dev, CODA_RET_DEC_PIC_ERR_MB);
  1438. if (err_mb > 0)
  1439. v4l2_err(&dev->v4l2_dev,
  1440. "errors in %d macroblocks\n", err_mb);
  1441. if (dev->devtype->product == CODA_7541) {
  1442. val = coda_read(dev, CODA_RET_DEC_PIC_OPTION);
  1443. if (val == 0) {
  1444. /* not enough bitstream data */
  1445. v4l2_dbg(1, coda_debug, &dev->v4l2_dev,
  1446. "prescan failed: %d\n", val);
  1447. ctx->hold = true;
  1448. return;
  1449. }
  1450. }
  1451. ctx->frm_dis_flg = coda_read(dev,
  1452. CODA_REG_BIT_FRM_DIS_FLG(ctx->reg_idx));
  1453. /*
  1454. * The previous display frame was copied out by the rotator,
  1455. * now it can be overwritten again
  1456. */
  1457. if (ctx->display_idx >= 0 &&
  1458. ctx->display_idx < ctx->num_internal_frames) {
  1459. ctx->frm_dis_flg &= ~(1 << ctx->display_idx);
  1460. coda_write(dev, ctx->frm_dis_flg,
  1461. CODA_REG_BIT_FRM_DIS_FLG(ctx->reg_idx));
  1462. }
  1463. /*
  1464. * The index of the last decoded frame, not necessarily in
  1465. * display order, and the index of the next display frame.
  1466. * The latter could have been decoded in a previous run.
  1467. */
  1468. decoded_idx = coda_read(dev, CODA_RET_DEC_PIC_CUR_IDX);
  1469. display_idx = coda_read(dev, CODA_RET_DEC_PIC_FRAME_IDX);
  1470. if (decoded_idx == -1) {
  1471. /* no frame was decoded, but we might have a display frame */
  1472. if (display_idx >= 0 && display_idx < ctx->num_internal_frames)
  1473. ctx->sequence_offset++;
  1474. else if (ctx->display_idx < 0)
  1475. ctx->hold = true;
  1476. } else if (decoded_idx == -2) {
  1477. /* no frame was decoded, we still return remaining buffers */
  1478. } else if (decoded_idx < 0 || decoded_idx >= ctx->num_internal_frames) {
  1479. v4l2_err(&dev->v4l2_dev,
  1480. "decoded frame index out of range: %d\n", decoded_idx);
  1481. } else {
  1482. val = coda_read(dev, CODA_RET_DEC_PIC_FRAME_NUM) - 1;
  1483. val -= ctx->sequence_offset;
  1484. mutex_lock(&ctx->bitstream_mutex);
  1485. if (!list_empty(&ctx->timestamp_list)) {
  1486. ts = list_first_entry(&ctx->timestamp_list,
  1487. struct coda_timestamp, list);
  1488. list_del(&ts->list);
  1489. if (val != (ts->sequence & 0xffff)) {
  1490. v4l2_err(&dev->v4l2_dev,
  1491. "sequence number mismatch (%d(%d) != %d)\n",
  1492. val, ctx->sequence_offset,
  1493. ts->sequence);
  1494. }
  1495. ctx->frame_timestamps[decoded_idx] = *ts;
  1496. kfree(ts);
  1497. } else {
  1498. v4l2_err(&dev->v4l2_dev, "empty timestamp list!\n");
  1499. memset(&ctx->frame_timestamps[decoded_idx], 0,
  1500. sizeof(struct coda_timestamp));
  1501. ctx->frame_timestamps[decoded_idx].sequence = val;
  1502. }
  1503. mutex_unlock(&ctx->bitstream_mutex);
  1504. val = coda_read(dev, CODA_RET_DEC_PIC_TYPE) & 0x7;
  1505. if (val == 0)
  1506. ctx->frame_types[decoded_idx] = V4L2_BUF_FLAG_KEYFRAME;
  1507. else if (val == 1)
  1508. ctx->frame_types[decoded_idx] = V4L2_BUF_FLAG_PFRAME;
  1509. else
  1510. ctx->frame_types[decoded_idx] = V4L2_BUF_FLAG_BFRAME;
  1511. ctx->frame_errors[decoded_idx] = err_mb;
  1512. }
  1513. if (display_idx == -1) {
  1514. /*
  1515. * no more frames to be decoded, but there could still
  1516. * be rotator output to dequeue
  1517. */
  1518. ctx->hold = true;
  1519. } else if (display_idx == -3) {
  1520. /* possibly prescan failure */
  1521. } else if (display_idx < 0 || display_idx >= ctx->num_internal_frames) {
  1522. v4l2_err(&dev->v4l2_dev,
  1523. "presentation frame index out of range: %d\n",
  1524. display_idx);
  1525. }
  1526. /* If a frame was copied out, return it */
  1527. if (ctx->display_idx >= 0 &&
  1528. ctx->display_idx < ctx->num_internal_frames) {
  1529. dst_buf = v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx);
  1530. dst_buf->v4l2_buf.sequence = ctx->osequence++;
  1531. dst_buf->v4l2_buf.flags &= ~(V4L2_BUF_FLAG_KEYFRAME |
  1532. V4L2_BUF_FLAG_PFRAME |
  1533. V4L2_BUF_FLAG_BFRAME);
  1534. dst_buf->v4l2_buf.flags |= ctx->frame_types[ctx->display_idx];
  1535. ts = &ctx->frame_timestamps[ctx->display_idx];
  1536. dst_buf->v4l2_buf.timecode = ts->timecode;
  1537. dst_buf->v4l2_buf.timestamp = ts->timestamp;
  1538. vb2_set_plane_payload(dst_buf, 0, width * height * 3 / 2);
  1539. v4l2_m2m_buf_done(dst_buf, ctx->frame_errors[display_idx] ?
  1540. VB2_BUF_STATE_ERROR : VB2_BUF_STATE_DONE);
  1541. v4l2_dbg(1, coda_debug, &dev->v4l2_dev,
  1542. "job finished: decoding frame (%d) (%s)\n",
  1543. dst_buf->v4l2_buf.sequence,
  1544. (dst_buf->v4l2_buf.flags & V4L2_BUF_FLAG_KEYFRAME) ?
  1545. "KEYFRAME" : "PFRAME");
  1546. } else {
  1547. v4l2_dbg(1, coda_debug, &dev->v4l2_dev,
  1548. "job finished: no frame decoded\n");
  1549. }
  1550. /* The rotator will copy the current display frame next time */
  1551. ctx->display_idx = display_idx;
  1552. }
  1553. const struct coda_context_ops coda_bit_decode_ops = {
  1554. .queue_init = coda_decoder_queue_init,
  1555. .start_streaming = coda_start_decoding,
  1556. .prepare_run = coda_prepare_decode,
  1557. .finish_run = coda_finish_decode,
  1558. .seq_end_work = coda_seq_end_work,
  1559. .release = coda_bit_release,
  1560. };
  1561. irqreturn_t coda_irq_handler(int irq, void *data)
  1562. {
  1563. struct coda_dev *dev = data;
  1564. struct coda_ctx *ctx;
  1565. /* read status register to attend the IRQ */
  1566. coda_read(dev, CODA_REG_BIT_INT_STATUS);
  1567. coda_write(dev, CODA_REG_BIT_INT_CLEAR_SET,
  1568. CODA_REG_BIT_INT_CLEAR);
  1569. ctx = v4l2_m2m_get_curr_priv(dev->m2m_dev);
  1570. if (ctx == NULL) {
  1571. v4l2_err(&dev->v4l2_dev,
  1572. "Instance released before the end of transaction\n");
  1573. mutex_unlock(&dev->coda_mutex);
  1574. return IRQ_HANDLED;
  1575. }
  1576. if (ctx->aborting) {
  1577. v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev,
  1578. "task has been aborted\n");
  1579. }
  1580. if (coda_isbusy(ctx->dev)) {
  1581. v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev,
  1582. "coda is still busy!!!!\n");
  1583. return IRQ_NONE;
  1584. }
  1585. complete(&ctx->completion);
  1586. return IRQ_HANDLED;
  1587. }