kxcjk-1013.c 33 KB

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  1. /*
  2. * KXCJK-1013 3-axis accelerometer driver
  3. * Copyright (c) 2014, Intel Corporation.
  4. *
  5. * This program is free software; you can redistribute it and/or modify it
  6. * under the terms and conditions of the GNU General Public License,
  7. * version 2, as published by the Free Software Foundation.
  8. *
  9. * This program is distributed in the hope it will be useful, but WITHOUT
  10. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12. * more details.
  13. */
  14. #include <linux/module.h>
  15. #include <linux/i2c.h>
  16. #include <linux/interrupt.h>
  17. #include <linux/delay.h>
  18. #include <linux/bitops.h>
  19. #include <linux/slab.h>
  20. #include <linux/string.h>
  21. #include <linux/acpi.h>
  22. #include <linux/gpio/consumer.h>
  23. #include <linux/pm.h>
  24. #include <linux/pm_runtime.h>
  25. #include <linux/iio/iio.h>
  26. #include <linux/iio/sysfs.h>
  27. #include <linux/iio/buffer.h>
  28. #include <linux/iio/trigger.h>
  29. #include <linux/iio/events.h>
  30. #include <linux/iio/trigger_consumer.h>
  31. #include <linux/iio/triggered_buffer.h>
  32. #include <linux/iio/accel/kxcjk_1013.h>
  33. #define KXCJK1013_DRV_NAME "kxcjk1013"
  34. #define KXCJK1013_IRQ_NAME "kxcjk1013_event"
  35. #define KXCJK1013_REG_XOUT_L 0x06
  36. /*
  37. * From low byte X axis register, all the other addresses of Y and Z can be
  38. * obtained by just applying axis offset. The following axis defines are just
  39. * provide clarity, but not used.
  40. */
  41. #define KXCJK1013_REG_XOUT_H 0x07
  42. #define KXCJK1013_REG_YOUT_L 0x08
  43. #define KXCJK1013_REG_YOUT_H 0x09
  44. #define KXCJK1013_REG_ZOUT_L 0x0A
  45. #define KXCJK1013_REG_ZOUT_H 0x0B
  46. #define KXCJK1013_REG_DCST_RESP 0x0C
  47. #define KXCJK1013_REG_WHO_AM_I 0x0F
  48. #define KXCJK1013_REG_INT_SRC1 0x16
  49. #define KXCJK1013_REG_INT_SRC2 0x17
  50. #define KXCJK1013_REG_STATUS_REG 0x18
  51. #define KXCJK1013_REG_INT_REL 0x1A
  52. #define KXCJK1013_REG_CTRL1 0x1B
  53. #define KXCJK1013_REG_CTRL2 0x1D
  54. #define KXCJK1013_REG_INT_CTRL1 0x1E
  55. #define KXCJK1013_REG_INT_CTRL2 0x1F
  56. #define KXCJK1013_REG_DATA_CTRL 0x21
  57. #define KXCJK1013_REG_WAKE_TIMER 0x29
  58. #define KXCJK1013_REG_SELF_TEST 0x3A
  59. #define KXCJK1013_REG_WAKE_THRES 0x6A
  60. #define KXCJK1013_REG_CTRL1_BIT_PC1 BIT(7)
  61. #define KXCJK1013_REG_CTRL1_BIT_RES BIT(6)
  62. #define KXCJK1013_REG_CTRL1_BIT_DRDY BIT(5)
  63. #define KXCJK1013_REG_CTRL1_BIT_GSEL1 BIT(4)
  64. #define KXCJK1013_REG_CTRL1_BIT_GSEL0 BIT(3)
  65. #define KXCJK1013_REG_CTRL1_BIT_WUFE BIT(1)
  66. #define KXCJK1013_REG_INT_REG1_BIT_IEA BIT(4)
  67. #define KXCJK1013_REG_INT_REG1_BIT_IEN BIT(5)
  68. #define KXCJK1013_DATA_MASK_12_BIT 0x0FFF
  69. #define KXCJK1013_MAX_STARTUP_TIME_US 100000
  70. #define KXCJK1013_SLEEP_DELAY_MS 2000
  71. #define KXCJK1013_REG_INT_SRC2_BIT_ZP BIT(0)
  72. #define KXCJK1013_REG_INT_SRC2_BIT_ZN BIT(1)
  73. #define KXCJK1013_REG_INT_SRC2_BIT_YP BIT(2)
  74. #define KXCJK1013_REG_INT_SRC2_BIT_YN BIT(3)
  75. #define KXCJK1013_REG_INT_SRC2_BIT_XP BIT(4)
  76. #define KXCJK1013_REG_INT_SRC2_BIT_XN BIT(5)
  77. #define KXCJK1013_DEFAULT_WAKE_THRES 1
  78. enum kx_chipset {
  79. KXCJK1013,
  80. KXCJ91008,
  81. KXTJ21009,
  82. KX_MAX_CHIPS /* this must be last */
  83. };
  84. struct kxcjk1013_data {
  85. struct i2c_client *client;
  86. struct iio_trigger *dready_trig;
  87. struct iio_trigger *motion_trig;
  88. struct mutex mutex;
  89. s16 buffer[8];
  90. u8 odr_bits;
  91. u8 range;
  92. int wake_thres;
  93. int wake_dur;
  94. bool active_high_intr;
  95. bool dready_trigger_on;
  96. int ev_enable_state;
  97. bool motion_trigger_on;
  98. int64_t timestamp;
  99. enum kx_chipset chipset;
  100. };
  101. enum kxcjk1013_axis {
  102. AXIS_X,
  103. AXIS_Y,
  104. AXIS_Z,
  105. };
  106. enum kxcjk1013_mode {
  107. STANDBY,
  108. OPERATION,
  109. };
  110. enum kxcjk1013_range {
  111. KXCJK1013_RANGE_2G,
  112. KXCJK1013_RANGE_4G,
  113. KXCJK1013_RANGE_8G,
  114. };
  115. static const struct {
  116. int val;
  117. int val2;
  118. int odr_bits;
  119. } samp_freq_table[] = { {0, 781000, 0x08}, {1, 563000, 0x09},
  120. {3, 125000, 0x0A}, {6, 250000, 0x0B}, {12, 500000, 0},
  121. {25, 0, 0x01}, {50, 0, 0x02}, {100, 0, 0x03},
  122. {200, 0, 0x04}, {400, 0, 0x05}, {800, 0, 0x06},
  123. {1600, 0, 0x07} };
  124. /* Refer to section 4 of the specification */
  125. static const struct {
  126. int odr_bits;
  127. int usec;
  128. } odr_start_up_times[KX_MAX_CHIPS][12] = {
  129. /* KXCJK-1013 */
  130. {
  131. {0x08, 100000},
  132. {0x09, 100000},
  133. {0x0A, 100000},
  134. {0x0B, 100000},
  135. {0, 80000},
  136. {0x01, 41000},
  137. {0x02, 21000},
  138. {0x03, 11000},
  139. {0x04, 6400},
  140. {0x05, 3900},
  141. {0x06, 2700},
  142. {0x07, 2100},
  143. },
  144. /* KXCJ9-1008 */
  145. {
  146. {0x08, 100000},
  147. {0x09, 100000},
  148. {0x0A, 100000},
  149. {0x0B, 100000},
  150. {0, 80000},
  151. {0x01, 41000},
  152. {0x02, 21000},
  153. {0x03, 11000},
  154. {0x04, 6400},
  155. {0x05, 3900},
  156. {0x06, 2700},
  157. {0x07, 2100},
  158. },
  159. /* KXCTJ2-1009 */
  160. {
  161. {0x08, 1240000},
  162. {0x09, 621000},
  163. {0x0A, 309000},
  164. {0x0B, 151000},
  165. {0, 80000},
  166. {0x01, 41000},
  167. {0x02, 21000},
  168. {0x03, 11000},
  169. {0x04, 6000},
  170. {0x05, 4000},
  171. {0x06, 3000},
  172. {0x07, 2000},
  173. },
  174. };
  175. static const struct {
  176. u16 scale;
  177. u8 gsel_0;
  178. u8 gsel_1;
  179. } KXCJK1013_scale_table[] = { {9582, 0, 0},
  180. {19163, 1, 0},
  181. {38326, 0, 1} };
  182. static const struct {
  183. int val;
  184. int val2;
  185. int odr_bits;
  186. } wake_odr_data_rate_table[] = { {0, 781000, 0x00},
  187. {1, 563000, 0x01},
  188. {3, 125000, 0x02},
  189. {6, 250000, 0x03},
  190. {12, 500000, 0x04},
  191. {25, 0, 0x05},
  192. {50, 0, 0x06},
  193. {100, 0, 0x06},
  194. {200, 0, 0x06},
  195. {400, 0, 0x06},
  196. {800, 0, 0x06},
  197. {1600, 0, 0x06} };
  198. static int kxcjk1013_set_mode(struct kxcjk1013_data *data,
  199. enum kxcjk1013_mode mode)
  200. {
  201. int ret;
  202. ret = i2c_smbus_read_byte_data(data->client, KXCJK1013_REG_CTRL1);
  203. if (ret < 0) {
  204. dev_err(&data->client->dev, "Error reading reg_ctrl1\n");
  205. return ret;
  206. }
  207. if (mode == STANDBY)
  208. ret &= ~KXCJK1013_REG_CTRL1_BIT_PC1;
  209. else
  210. ret |= KXCJK1013_REG_CTRL1_BIT_PC1;
  211. ret = i2c_smbus_write_byte_data(data->client,
  212. KXCJK1013_REG_CTRL1, ret);
  213. if (ret < 0) {
  214. dev_err(&data->client->dev, "Error writing reg_ctrl1\n");
  215. return ret;
  216. }
  217. return 0;
  218. }
  219. static int kxcjk1013_get_mode(struct kxcjk1013_data *data,
  220. enum kxcjk1013_mode *mode)
  221. {
  222. int ret;
  223. ret = i2c_smbus_read_byte_data(data->client, KXCJK1013_REG_CTRL1);
  224. if (ret < 0) {
  225. dev_err(&data->client->dev, "Error reading reg_ctrl1\n");
  226. return ret;
  227. }
  228. if (ret & KXCJK1013_REG_CTRL1_BIT_PC1)
  229. *mode = OPERATION;
  230. else
  231. *mode = STANDBY;
  232. return 0;
  233. }
  234. static int kxcjk1013_set_range(struct kxcjk1013_data *data, int range_index)
  235. {
  236. int ret;
  237. ret = i2c_smbus_read_byte_data(data->client, KXCJK1013_REG_CTRL1);
  238. if (ret < 0) {
  239. dev_err(&data->client->dev, "Error reading reg_ctrl1\n");
  240. return ret;
  241. }
  242. ret |= (KXCJK1013_scale_table[range_index].gsel_0 << 3);
  243. ret |= (KXCJK1013_scale_table[range_index].gsel_1 << 4);
  244. ret = i2c_smbus_write_byte_data(data->client,
  245. KXCJK1013_REG_CTRL1,
  246. ret);
  247. if (ret < 0) {
  248. dev_err(&data->client->dev, "Error writing reg_ctrl1\n");
  249. return ret;
  250. }
  251. data->range = range_index;
  252. return 0;
  253. }
  254. static int kxcjk1013_chip_init(struct kxcjk1013_data *data)
  255. {
  256. int ret;
  257. ret = i2c_smbus_read_byte_data(data->client, KXCJK1013_REG_WHO_AM_I);
  258. if (ret < 0) {
  259. dev_err(&data->client->dev, "Error reading who_am_i\n");
  260. return ret;
  261. }
  262. dev_dbg(&data->client->dev, "KXCJK1013 Chip Id %x\n", ret);
  263. ret = kxcjk1013_set_mode(data, STANDBY);
  264. if (ret < 0)
  265. return ret;
  266. ret = i2c_smbus_read_byte_data(data->client, KXCJK1013_REG_CTRL1);
  267. if (ret < 0) {
  268. dev_err(&data->client->dev, "Error reading reg_ctrl1\n");
  269. return ret;
  270. }
  271. /* Set 12 bit mode */
  272. ret |= KXCJK1013_REG_CTRL1_BIT_RES;
  273. ret = i2c_smbus_write_byte_data(data->client, KXCJK1013_REG_CTRL1,
  274. ret);
  275. if (ret < 0) {
  276. dev_err(&data->client->dev, "Error reading reg_ctrl\n");
  277. return ret;
  278. }
  279. /* Setting range to 4G */
  280. ret = kxcjk1013_set_range(data, KXCJK1013_RANGE_4G);
  281. if (ret < 0)
  282. return ret;
  283. ret = i2c_smbus_read_byte_data(data->client, KXCJK1013_REG_DATA_CTRL);
  284. if (ret < 0) {
  285. dev_err(&data->client->dev, "Error reading reg_data_ctrl\n");
  286. return ret;
  287. }
  288. data->odr_bits = ret;
  289. /* Set up INT polarity */
  290. ret = i2c_smbus_read_byte_data(data->client, KXCJK1013_REG_INT_CTRL1);
  291. if (ret < 0) {
  292. dev_err(&data->client->dev, "Error reading reg_int_ctrl1\n");
  293. return ret;
  294. }
  295. if (data->active_high_intr)
  296. ret |= KXCJK1013_REG_INT_REG1_BIT_IEA;
  297. else
  298. ret &= ~KXCJK1013_REG_INT_REG1_BIT_IEA;
  299. ret = i2c_smbus_write_byte_data(data->client, KXCJK1013_REG_INT_CTRL1,
  300. ret);
  301. if (ret < 0) {
  302. dev_err(&data->client->dev, "Error writing reg_int_ctrl1\n");
  303. return ret;
  304. }
  305. ret = kxcjk1013_set_mode(data, OPERATION);
  306. if (ret < 0)
  307. return ret;
  308. data->wake_thres = KXCJK1013_DEFAULT_WAKE_THRES;
  309. return 0;
  310. }
  311. #ifdef CONFIG_PM_RUNTIME
  312. static int kxcjk1013_get_startup_times(struct kxcjk1013_data *data)
  313. {
  314. int i;
  315. int idx = data->chipset;
  316. for (i = 0; i < ARRAY_SIZE(odr_start_up_times[idx]); ++i) {
  317. if (odr_start_up_times[idx][i].odr_bits == data->odr_bits)
  318. return odr_start_up_times[idx][i].usec;
  319. }
  320. return KXCJK1013_MAX_STARTUP_TIME_US;
  321. }
  322. #endif
  323. static int kxcjk1013_set_power_state(struct kxcjk1013_data *data, bool on)
  324. {
  325. int ret;
  326. if (on)
  327. ret = pm_runtime_get_sync(&data->client->dev);
  328. else {
  329. pm_runtime_mark_last_busy(&data->client->dev);
  330. ret = pm_runtime_put_autosuspend(&data->client->dev);
  331. }
  332. if (ret < 0) {
  333. dev_err(&data->client->dev,
  334. "Failed: kxcjk1013_set_power_state for %d\n", on);
  335. return ret;
  336. }
  337. return 0;
  338. }
  339. static int kxcjk1013_chip_update_thresholds(struct kxcjk1013_data *data)
  340. {
  341. int ret;
  342. ret = i2c_smbus_write_byte_data(data->client,
  343. KXCJK1013_REG_WAKE_TIMER,
  344. data->wake_dur);
  345. if (ret < 0) {
  346. dev_err(&data->client->dev,
  347. "Error writing reg_wake_timer\n");
  348. return ret;
  349. }
  350. ret = i2c_smbus_write_byte_data(data->client,
  351. KXCJK1013_REG_WAKE_THRES,
  352. data->wake_thres);
  353. if (ret < 0) {
  354. dev_err(&data->client->dev, "Error writing reg_wake_thres\n");
  355. return ret;
  356. }
  357. return 0;
  358. }
  359. static int kxcjk1013_setup_any_motion_interrupt(struct kxcjk1013_data *data,
  360. bool status)
  361. {
  362. int ret;
  363. enum kxcjk1013_mode store_mode;
  364. ret = kxcjk1013_get_mode(data, &store_mode);
  365. if (ret < 0)
  366. return ret;
  367. /* This is requirement by spec to change state to STANDBY */
  368. ret = kxcjk1013_set_mode(data, STANDBY);
  369. if (ret < 0)
  370. return ret;
  371. ret = kxcjk1013_chip_update_thresholds(data);
  372. if (ret < 0)
  373. return ret;
  374. ret = i2c_smbus_read_byte_data(data->client, KXCJK1013_REG_INT_CTRL1);
  375. if (ret < 0) {
  376. dev_err(&data->client->dev, "Error reading reg_int_ctrl1\n");
  377. return ret;
  378. }
  379. if (status)
  380. ret |= KXCJK1013_REG_INT_REG1_BIT_IEN;
  381. else
  382. ret &= ~KXCJK1013_REG_INT_REG1_BIT_IEN;
  383. ret = i2c_smbus_write_byte_data(data->client, KXCJK1013_REG_INT_CTRL1,
  384. ret);
  385. if (ret < 0) {
  386. dev_err(&data->client->dev, "Error writing reg_int_ctrl1\n");
  387. return ret;
  388. }
  389. ret = i2c_smbus_read_byte_data(data->client, KXCJK1013_REG_CTRL1);
  390. if (ret < 0) {
  391. dev_err(&data->client->dev, "Error reading reg_ctrl1\n");
  392. return ret;
  393. }
  394. if (status)
  395. ret |= KXCJK1013_REG_CTRL1_BIT_WUFE;
  396. else
  397. ret &= ~KXCJK1013_REG_CTRL1_BIT_WUFE;
  398. ret = i2c_smbus_write_byte_data(data->client,
  399. KXCJK1013_REG_CTRL1, ret);
  400. if (ret < 0) {
  401. dev_err(&data->client->dev, "Error writing reg_ctrl1\n");
  402. return ret;
  403. }
  404. if (store_mode == OPERATION) {
  405. ret = kxcjk1013_set_mode(data, OPERATION);
  406. if (ret < 0)
  407. return ret;
  408. }
  409. return 0;
  410. }
  411. static int kxcjk1013_setup_new_data_interrupt(struct kxcjk1013_data *data,
  412. bool status)
  413. {
  414. int ret;
  415. enum kxcjk1013_mode store_mode;
  416. ret = kxcjk1013_get_mode(data, &store_mode);
  417. if (ret < 0)
  418. return ret;
  419. /* This is requirement by spec to change state to STANDBY */
  420. ret = kxcjk1013_set_mode(data, STANDBY);
  421. if (ret < 0)
  422. return ret;
  423. ret = i2c_smbus_read_byte_data(data->client, KXCJK1013_REG_INT_CTRL1);
  424. if (ret < 0) {
  425. dev_err(&data->client->dev, "Error reading reg_int_ctrl1\n");
  426. return ret;
  427. }
  428. if (status)
  429. ret |= KXCJK1013_REG_INT_REG1_BIT_IEN;
  430. else
  431. ret &= ~KXCJK1013_REG_INT_REG1_BIT_IEN;
  432. ret = i2c_smbus_write_byte_data(data->client, KXCJK1013_REG_INT_CTRL1,
  433. ret);
  434. if (ret < 0) {
  435. dev_err(&data->client->dev, "Error writing reg_int_ctrl1\n");
  436. return ret;
  437. }
  438. ret = i2c_smbus_read_byte_data(data->client, KXCJK1013_REG_CTRL1);
  439. if (ret < 0) {
  440. dev_err(&data->client->dev, "Error reading reg_ctrl1\n");
  441. return ret;
  442. }
  443. if (status)
  444. ret |= KXCJK1013_REG_CTRL1_BIT_DRDY;
  445. else
  446. ret &= ~KXCJK1013_REG_CTRL1_BIT_DRDY;
  447. ret = i2c_smbus_write_byte_data(data->client,
  448. KXCJK1013_REG_CTRL1, ret);
  449. if (ret < 0) {
  450. dev_err(&data->client->dev, "Error writing reg_ctrl1\n");
  451. return ret;
  452. }
  453. if (store_mode == OPERATION) {
  454. ret = kxcjk1013_set_mode(data, OPERATION);
  455. if (ret < 0)
  456. return ret;
  457. }
  458. return 0;
  459. }
  460. static int kxcjk1013_convert_freq_to_bit(int val, int val2)
  461. {
  462. int i;
  463. for (i = 0; i < ARRAY_SIZE(samp_freq_table); ++i) {
  464. if (samp_freq_table[i].val == val &&
  465. samp_freq_table[i].val2 == val2) {
  466. return samp_freq_table[i].odr_bits;
  467. }
  468. }
  469. return -EINVAL;
  470. }
  471. static int kxcjk1013_convert_wake_odr_to_bit(int val, int val2)
  472. {
  473. int i;
  474. for (i = 0; i < ARRAY_SIZE(wake_odr_data_rate_table); ++i) {
  475. if (wake_odr_data_rate_table[i].val == val &&
  476. wake_odr_data_rate_table[i].val2 == val2) {
  477. return wake_odr_data_rate_table[i].odr_bits;
  478. }
  479. }
  480. return -EINVAL;
  481. }
  482. static int kxcjk1013_set_odr(struct kxcjk1013_data *data, int val, int val2)
  483. {
  484. int ret;
  485. int odr_bits;
  486. enum kxcjk1013_mode store_mode;
  487. ret = kxcjk1013_get_mode(data, &store_mode);
  488. if (ret < 0)
  489. return ret;
  490. odr_bits = kxcjk1013_convert_freq_to_bit(val, val2);
  491. if (odr_bits < 0)
  492. return odr_bits;
  493. /* To change ODR, the chip must be set to STANDBY as per spec */
  494. ret = kxcjk1013_set_mode(data, STANDBY);
  495. if (ret < 0)
  496. return ret;
  497. ret = i2c_smbus_write_byte_data(data->client, KXCJK1013_REG_DATA_CTRL,
  498. odr_bits);
  499. if (ret < 0) {
  500. dev_err(&data->client->dev, "Error writing data_ctrl\n");
  501. return ret;
  502. }
  503. data->odr_bits = odr_bits;
  504. odr_bits = kxcjk1013_convert_wake_odr_to_bit(val, val2);
  505. if (odr_bits < 0)
  506. return odr_bits;
  507. ret = i2c_smbus_write_byte_data(data->client, KXCJK1013_REG_CTRL2,
  508. odr_bits);
  509. if (ret < 0) {
  510. dev_err(&data->client->dev, "Error writing reg_ctrl2\n");
  511. return ret;
  512. }
  513. if (store_mode == OPERATION) {
  514. ret = kxcjk1013_set_mode(data, OPERATION);
  515. if (ret < 0)
  516. return ret;
  517. }
  518. return 0;
  519. }
  520. static int kxcjk1013_get_odr(struct kxcjk1013_data *data, int *val, int *val2)
  521. {
  522. int i;
  523. for (i = 0; i < ARRAY_SIZE(samp_freq_table); ++i) {
  524. if (samp_freq_table[i].odr_bits == data->odr_bits) {
  525. *val = samp_freq_table[i].val;
  526. *val2 = samp_freq_table[i].val2;
  527. return IIO_VAL_INT_PLUS_MICRO;
  528. }
  529. }
  530. return -EINVAL;
  531. }
  532. static int kxcjk1013_get_acc_reg(struct kxcjk1013_data *data, int axis)
  533. {
  534. u8 reg = KXCJK1013_REG_XOUT_L + axis * 2;
  535. int ret;
  536. ret = i2c_smbus_read_word_data(data->client, reg);
  537. if (ret < 0) {
  538. dev_err(&data->client->dev,
  539. "failed to read accel_%c registers\n", 'x' + axis);
  540. return ret;
  541. }
  542. return ret;
  543. }
  544. static int kxcjk1013_set_scale(struct kxcjk1013_data *data, int val)
  545. {
  546. int ret, i;
  547. enum kxcjk1013_mode store_mode;
  548. for (i = 0; i < ARRAY_SIZE(KXCJK1013_scale_table); ++i) {
  549. if (KXCJK1013_scale_table[i].scale == val) {
  550. ret = kxcjk1013_get_mode(data, &store_mode);
  551. if (ret < 0)
  552. return ret;
  553. ret = kxcjk1013_set_mode(data, STANDBY);
  554. if (ret < 0)
  555. return ret;
  556. ret = kxcjk1013_set_range(data, i);
  557. if (ret < 0)
  558. return ret;
  559. if (store_mode == OPERATION) {
  560. ret = kxcjk1013_set_mode(data, OPERATION);
  561. if (ret)
  562. return ret;
  563. }
  564. return 0;
  565. }
  566. }
  567. return -EINVAL;
  568. }
  569. static int kxcjk1013_read_raw(struct iio_dev *indio_dev,
  570. struct iio_chan_spec const *chan, int *val,
  571. int *val2, long mask)
  572. {
  573. struct kxcjk1013_data *data = iio_priv(indio_dev);
  574. int ret;
  575. switch (mask) {
  576. case IIO_CHAN_INFO_RAW:
  577. mutex_lock(&data->mutex);
  578. if (iio_buffer_enabled(indio_dev))
  579. ret = -EBUSY;
  580. else {
  581. ret = kxcjk1013_set_power_state(data, true);
  582. if (ret < 0) {
  583. mutex_unlock(&data->mutex);
  584. return ret;
  585. }
  586. ret = kxcjk1013_get_acc_reg(data, chan->scan_index);
  587. if (ret < 0) {
  588. kxcjk1013_set_power_state(data, false);
  589. mutex_unlock(&data->mutex);
  590. return ret;
  591. }
  592. *val = sign_extend32(ret >> 4, 11);
  593. ret = kxcjk1013_set_power_state(data, false);
  594. }
  595. mutex_unlock(&data->mutex);
  596. if (ret < 0)
  597. return ret;
  598. return IIO_VAL_INT;
  599. case IIO_CHAN_INFO_SCALE:
  600. *val = 0;
  601. *val2 = KXCJK1013_scale_table[data->range].scale;
  602. return IIO_VAL_INT_PLUS_MICRO;
  603. case IIO_CHAN_INFO_SAMP_FREQ:
  604. mutex_lock(&data->mutex);
  605. ret = kxcjk1013_get_odr(data, val, val2);
  606. mutex_unlock(&data->mutex);
  607. return ret;
  608. default:
  609. return -EINVAL;
  610. }
  611. }
  612. static int kxcjk1013_write_raw(struct iio_dev *indio_dev,
  613. struct iio_chan_spec const *chan, int val,
  614. int val2, long mask)
  615. {
  616. struct kxcjk1013_data *data = iio_priv(indio_dev);
  617. int ret;
  618. switch (mask) {
  619. case IIO_CHAN_INFO_SAMP_FREQ:
  620. mutex_lock(&data->mutex);
  621. ret = kxcjk1013_set_odr(data, val, val2);
  622. mutex_unlock(&data->mutex);
  623. break;
  624. case IIO_CHAN_INFO_SCALE:
  625. if (val)
  626. return -EINVAL;
  627. mutex_lock(&data->mutex);
  628. ret = kxcjk1013_set_scale(data, val2);
  629. mutex_unlock(&data->mutex);
  630. break;
  631. default:
  632. ret = -EINVAL;
  633. }
  634. return ret;
  635. }
  636. static int kxcjk1013_read_event(struct iio_dev *indio_dev,
  637. const struct iio_chan_spec *chan,
  638. enum iio_event_type type,
  639. enum iio_event_direction dir,
  640. enum iio_event_info info,
  641. int *val, int *val2)
  642. {
  643. struct kxcjk1013_data *data = iio_priv(indio_dev);
  644. *val2 = 0;
  645. switch (info) {
  646. case IIO_EV_INFO_VALUE:
  647. *val = data->wake_thres;
  648. break;
  649. case IIO_EV_INFO_PERIOD:
  650. *val = data->wake_dur;
  651. break;
  652. default:
  653. return -EINVAL;
  654. }
  655. return IIO_VAL_INT;
  656. }
  657. static int kxcjk1013_write_event(struct iio_dev *indio_dev,
  658. const struct iio_chan_spec *chan,
  659. enum iio_event_type type,
  660. enum iio_event_direction dir,
  661. enum iio_event_info info,
  662. int val, int val2)
  663. {
  664. struct kxcjk1013_data *data = iio_priv(indio_dev);
  665. if (data->ev_enable_state)
  666. return -EBUSY;
  667. switch (info) {
  668. case IIO_EV_INFO_VALUE:
  669. data->wake_thres = val;
  670. break;
  671. case IIO_EV_INFO_PERIOD:
  672. data->wake_dur = val;
  673. break;
  674. default:
  675. return -EINVAL;
  676. }
  677. return 0;
  678. }
  679. static int kxcjk1013_read_event_config(struct iio_dev *indio_dev,
  680. const struct iio_chan_spec *chan,
  681. enum iio_event_type type,
  682. enum iio_event_direction dir)
  683. {
  684. struct kxcjk1013_data *data = iio_priv(indio_dev);
  685. return data->ev_enable_state;
  686. }
  687. static int kxcjk1013_write_event_config(struct iio_dev *indio_dev,
  688. const struct iio_chan_spec *chan,
  689. enum iio_event_type type,
  690. enum iio_event_direction dir,
  691. int state)
  692. {
  693. struct kxcjk1013_data *data = iio_priv(indio_dev);
  694. int ret;
  695. if (state && data->ev_enable_state)
  696. return 0;
  697. mutex_lock(&data->mutex);
  698. if (!state && data->motion_trigger_on) {
  699. data->ev_enable_state = 0;
  700. mutex_unlock(&data->mutex);
  701. return 0;
  702. }
  703. /*
  704. * We will expect the enable and disable to do operation in
  705. * in reverse order. This will happen here anyway as our
  706. * resume operation uses sync mode runtime pm calls, the
  707. * suspend operation will be delayed by autosuspend delay
  708. * So the disable operation will still happen in reverse of
  709. * enable operation. When runtime pm is disabled the mode
  710. * is always on so sequence doesn't matter
  711. */
  712. ret = kxcjk1013_set_power_state(data, state);
  713. if (ret < 0) {
  714. mutex_unlock(&data->mutex);
  715. return ret;
  716. }
  717. ret = kxcjk1013_setup_any_motion_interrupt(data, state);
  718. if (ret < 0) {
  719. mutex_unlock(&data->mutex);
  720. return ret;
  721. }
  722. data->ev_enable_state = state;
  723. mutex_unlock(&data->mutex);
  724. return 0;
  725. }
  726. static int kxcjk1013_validate_trigger(struct iio_dev *indio_dev,
  727. struct iio_trigger *trig)
  728. {
  729. struct kxcjk1013_data *data = iio_priv(indio_dev);
  730. if (data->dready_trig != trig && data->motion_trig != trig)
  731. return -EINVAL;
  732. return 0;
  733. }
  734. static IIO_CONST_ATTR_SAMP_FREQ_AVAIL(
  735. "0.781000 1.563000 3.125000 6.250000 12.500000 25 50 100 200 400 800 1600");
  736. static IIO_CONST_ATTR(in_accel_scale_available, "0.009582 0.019163 0.038326");
  737. static struct attribute *kxcjk1013_attributes[] = {
  738. &iio_const_attr_sampling_frequency_available.dev_attr.attr,
  739. &iio_const_attr_in_accel_scale_available.dev_attr.attr,
  740. NULL,
  741. };
  742. static const struct attribute_group kxcjk1013_attrs_group = {
  743. .attrs = kxcjk1013_attributes,
  744. };
  745. static const struct iio_event_spec kxcjk1013_event = {
  746. .type = IIO_EV_TYPE_THRESH,
  747. .dir = IIO_EV_DIR_RISING | IIO_EV_DIR_FALLING,
  748. .mask_separate = BIT(IIO_EV_INFO_VALUE) |
  749. BIT(IIO_EV_INFO_ENABLE) |
  750. BIT(IIO_EV_INFO_PERIOD)
  751. };
  752. #define KXCJK1013_CHANNEL(_axis) { \
  753. .type = IIO_ACCEL, \
  754. .modified = 1, \
  755. .channel2 = IIO_MOD_##_axis, \
  756. .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
  757. .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \
  758. BIT(IIO_CHAN_INFO_SAMP_FREQ), \
  759. .scan_index = AXIS_##_axis, \
  760. .scan_type = { \
  761. .sign = 's', \
  762. .realbits = 12, \
  763. .storagebits = 16, \
  764. .shift = 4, \
  765. .endianness = IIO_CPU, \
  766. }, \
  767. .event_spec = &kxcjk1013_event, \
  768. .num_event_specs = 1 \
  769. }
  770. static const struct iio_chan_spec kxcjk1013_channels[] = {
  771. KXCJK1013_CHANNEL(X),
  772. KXCJK1013_CHANNEL(Y),
  773. KXCJK1013_CHANNEL(Z),
  774. IIO_CHAN_SOFT_TIMESTAMP(3),
  775. };
  776. static const struct iio_info kxcjk1013_info = {
  777. .attrs = &kxcjk1013_attrs_group,
  778. .read_raw = kxcjk1013_read_raw,
  779. .write_raw = kxcjk1013_write_raw,
  780. .read_event_value = kxcjk1013_read_event,
  781. .write_event_value = kxcjk1013_write_event,
  782. .write_event_config = kxcjk1013_write_event_config,
  783. .read_event_config = kxcjk1013_read_event_config,
  784. .validate_trigger = kxcjk1013_validate_trigger,
  785. .driver_module = THIS_MODULE,
  786. };
  787. static irqreturn_t kxcjk1013_trigger_handler(int irq, void *p)
  788. {
  789. struct iio_poll_func *pf = p;
  790. struct iio_dev *indio_dev = pf->indio_dev;
  791. struct kxcjk1013_data *data = iio_priv(indio_dev);
  792. int bit, ret, i = 0;
  793. mutex_lock(&data->mutex);
  794. for_each_set_bit(bit, indio_dev->buffer->scan_mask,
  795. indio_dev->masklength) {
  796. ret = kxcjk1013_get_acc_reg(data, bit);
  797. if (ret < 0) {
  798. mutex_unlock(&data->mutex);
  799. goto err;
  800. }
  801. data->buffer[i++] = ret;
  802. }
  803. mutex_unlock(&data->mutex);
  804. iio_push_to_buffers_with_timestamp(indio_dev, data->buffer,
  805. data->timestamp);
  806. err:
  807. iio_trigger_notify_done(indio_dev->trig);
  808. return IRQ_HANDLED;
  809. }
  810. static int kxcjk1013_trig_try_reen(struct iio_trigger *trig)
  811. {
  812. struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig);
  813. struct kxcjk1013_data *data = iio_priv(indio_dev);
  814. int ret;
  815. ret = i2c_smbus_read_byte_data(data->client, KXCJK1013_REG_INT_REL);
  816. if (ret < 0) {
  817. dev_err(&data->client->dev, "Error reading reg_int_rel\n");
  818. return ret;
  819. }
  820. return 0;
  821. }
  822. static int kxcjk1013_data_rdy_trigger_set_state(struct iio_trigger *trig,
  823. bool state)
  824. {
  825. struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig);
  826. struct kxcjk1013_data *data = iio_priv(indio_dev);
  827. int ret;
  828. mutex_lock(&data->mutex);
  829. if (!state && data->ev_enable_state && data->motion_trigger_on) {
  830. data->motion_trigger_on = false;
  831. mutex_unlock(&data->mutex);
  832. return 0;
  833. }
  834. ret = kxcjk1013_set_power_state(data, state);
  835. if (ret < 0) {
  836. mutex_unlock(&data->mutex);
  837. return ret;
  838. }
  839. if (data->motion_trig == trig)
  840. ret = kxcjk1013_setup_any_motion_interrupt(data, state);
  841. else
  842. ret = kxcjk1013_setup_new_data_interrupt(data, state);
  843. if (ret < 0) {
  844. mutex_unlock(&data->mutex);
  845. return ret;
  846. }
  847. if (data->motion_trig == trig)
  848. data->motion_trigger_on = state;
  849. else
  850. data->dready_trigger_on = state;
  851. mutex_unlock(&data->mutex);
  852. return 0;
  853. }
  854. static const struct iio_trigger_ops kxcjk1013_trigger_ops = {
  855. .set_trigger_state = kxcjk1013_data_rdy_trigger_set_state,
  856. .try_reenable = kxcjk1013_trig_try_reen,
  857. .owner = THIS_MODULE,
  858. };
  859. static irqreturn_t kxcjk1013_event_handler(int irq, void *private)
  860. {
  861. struct iio_dev *indio_dev = private;
  862. struct kxcjk1013_data *data = iio_priv(indio_dev);
  863. int ret;
  864. ret = i2c_smbus_read_byte_data(data->client, KXCJK1013_REG_INT_SRC1);
  865. if (ret < 0) {
  866. dev_err(&data->client->dev, "Error reading reg_int_src1\n");
  867. goto ack_intr;
  868. }
  869. if (ret & 0x02) {
  870. ret = i2c_smbus_read_byte_data(data->client,
  871. KXCJK1013_REG_INT_SRC2);
  872. if (ret < 0) {
  873. dev_err(&data->client->dev,
  874. "Error reading reg_int_src2\n");
  875. goto ack_intr;
  876. }
  877. if (ret & KXCJK1013_REG_INT_SRC2_BIT_XN)
  878. iio_push_event(indio_dev,
  879. IIO_MOD_EVENT_CODE(IIO_ACCEL,
  880. 0,
  881. IIO_MOD_X,
  882. IIO_EV_TYPE_THRESH,
  883. IIO_EV_DIR_FALLING),
  884. data->timestamp);
  885. if (ret & KXCJK1013_REG_INT_SRC2_BIT_XP)
  886. iio_push_event(indio_dev,
  887. IIO_MOD_EVENT_CODE(IIO_ACCEL,
  888. 0,
  889. IIO_MOD_X,
  890. IIO_EV_TYPE_THRESH,
  891. IIO_EV_DIR_RISING),
  892. data->timestamp);
  893. if (ret & KXCJK1013_REG_INT_SRC2_BIT_YN)
  894. iio_push_event(indio_dev,
  895. IIO_MOD_EVENT_CODE(IIO_ACCEL,
  896. 0,
  897. IIO_MOD_Y,
  898. IIO_EV_TYPE_THRESH,
  899. IIO_EV_DIR_FALLING),
  900. data->timestamp);
  901. if (ret & KXCJK1013_REG_INT_SRC2_BIT_YP)
  902. iio_push_event(indio_dev,
  903. IIO_MOD_EVENT_CODE(IIO_ACCEL,
  904. 0,
  905. IIO_MOD_Y,
  906. IIO_EV_TYPE_THRESH,
  907. IIO_EV_DIR_RISING),
  908. data->timestamp);
  909. if (ret & KXCJK1013_REG_INT_SRC2_BIT_ZN)
  910. iio_push_event(indio_dev,
  911. IIO_MOD_EVENT_CODE(IIO_ACCEL,
  912. 0,
  913. IIO_MOD_Z,
  914. IIO_EV_TYPE_THRESH,
  915. IIO_EV_DIR_FALLING),
  916. data->timestamp);
  917. if (ret & KXCJK1013_REG_INT_SRC2_BIT_ZP)
  918. iio_push_event(indio_dev,
  919. IIO_MOD_EVENT_CODE(IIO_ACCEL,
  920. 0,
  921. IIO_MOD_Z,
  922. IIO_EV_TYPE_THRESH,
  923. IIO_EV_DIR_RISING),
  924. data->timestamp);
  925. }
  926. ack_intr:
  927. if (data->dready_trigger_on)
  928. return IRQ_HANDLED;
  929. ret = i2c_smbus_read_byte_data(data->client, KXCJK1013_REG_INT_REL);
  930. if (ret < 0)
  931. dev_err(&data->client->dev, "Error reading reg_int_rel\n");
  932. return IRQ_HANDLED;
  933. }
  934. static irqreturn_t kxcjk1013_data_rdy_trig_poll(int irq, void *private)
  935. {
  936. struct iio_dev *indio_dev = private;
  937. struct kxcjk1013_data *data = iio_priv(indio_dev);
  938. data->timestamp = iio_get_time_ns();
  939. if (data->dready_trigger_on)
  940. iio_trigger_poll(data->dready_trig);
  941. else if (data->motion_trigger_on)
  942. iio_trigger_poll(data->motion_trig);
  943. if (data->ev_enable_state)
  944. return IRQ_WAKE_THREAD;
  945. else
  946. return IRQ_HANDLED;
  947. }
  948. static const char *kxcjk1013_match_acpi_device(struct device *dev,
  949. enum kx_chipset *chipset)
  950. {
  951. const struct acpi_device_id *id;
  952. id = acpi_match_device(dev->driver->acpi_match_table, dev);
  953. if (!id)
  954. return NULL;
  955. *chipset = (enum kx_chipset)id->driver_data;
  956. return dev_name(dev);
  957. }
  958. static int kxcjk1013_gpio_probe(struct i2c_client *client,
  959. struct kxcjk1013_data *data)
  960. {
  961. struct device *dev;
  962. struct gpio_desc *gpio;
  963. int ret;
  964. if (!client)
  965. return -EINVAL;
  966. dev = &client->dev;
  967. /* data ready gpio interrupt pin */
  968. gpio = devm_gpiod_get_index(dev, "kxcjk1013_int", 0);
  969. if (IS_ERR(gpio)) {
  970. dev_err(dev, "acpi gpio get index failed\n");
  971. return PTR_ERR(gpio);
  972. }
  973. ret = gpiod_direction_input(gpio);
  974. if (ret)
  975. return ret;
  976. ret = gpiod_to_irq(gpio);
  977. dev_dbg(dev, "GPIO resource, no:%d irq:%d\n", desc_to_gpio(gpio), ret);
  978. return ret;
  979. }
  980. static int kxcjk1013_probe(struct i2c_client *client,
  981. const struct i2c_device_id *id)
  982. {
  983. struct kxcjk1013_data *data;
  984. struct iio_dev *indio_dev;
  985. struct kxcjk_1013_platform_data *pdata;
  986. const char *name;
  987. int ret;
  988. indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data));
  989. if (!indio_dev)
  990. return -ENOMEM;
  991. data = iio_priv(indio_dev);
  992. i2c_set_clientdata(client, indio_dev);
  993. data->client = client;
  994. pdata = dev_get_platdata(&client->dev);
  995. if (pdata)
  996. data->active_high_intr = pdata->active_high_intr;
  997. else
  998. data->active_high_intr = true; /* default polarity */
  999. if (id) {
  1000. data->chipset = (enum kx_chipset)(id->driver_data);
  1001. name = id->name;
  1002. } else if (ACPI_HANDLE(&client->dev)) {
  1003. name = kxcjk1013_match_acpi_device(&client->dev,
  1004. &data->chipset);
  1005. } else
  1006. return -ENODEV;
  1007. ret = kxcjk1013_chip_init(data);
  1008. if (ret < 0)
  1009. return ret;
  1010. mutex_init(&data->mutex);
  1011. indio_dev->dev.parent = &client->dev;
  1012. indio_dev->channels = kxcjk1013_channels;
  1013. indio_dev->num_channels = ARRAY_SIZE(kxcjk1013_channels);
  1014. indio_dev->name = name;
  1015. indio_dev->modes = INDIO_DIRECT_MODE;
  1016. indio_dev->info = &kxcjk1013_info;
  1017. if (client->irq < 0)
  1018. client->irq = kxcjk1013_gpio_probe(client, data);
  1019. if (client->irq >= 0) {
  1020. ret = devm_request_threaded_irq(&client->dev, client->irq,
  1021. kxcjk1013_data_rdy_trig_poll,
  1022. kxcjk1013_event_handler,
  1023. IRQF_TRIGGER_RISING,
  1024. KXCJK1013_IRQ_NAME,
  1025. indio_dev);
  1026. if (ret)
  1027. return ret;
  1028. data->dready_trig = devm_iio_trigger_alloc(&client->dev,
  1029. "%s-dev%d",
  1030. indio_dev->name,
  1031. indio_dev->id);
  1032. if (!data->dready_trig)
  1033. return -ENOMEM;
  1034. data->motion_trig = devm_iio_trigger_alloc(&client->dev,
  1035. "%s-any-motion-dev%d",
  1036. indio_dev->name,
  1037. indio_dev->id);
  1038. if (!data->motion_trig)
  1039. return -ENOMEM;
  1040. data->dready_trig->dev.parent = &client->dev;
  1041. data->dready_trig->ops = &kxcjk1013_trigger_ops;
  1042. iio_trigger_set_drvdata(data->dready_trig, indio_dev);
  1043. indio_dev->trig = data->dready_trig;
  1044. iio_trigger_get(indio_dev->trig);
  1045. ret = iio_trigger_register(data->dready_trig);
  1046. if (ret)
  1047. return ret;
  1048. data->motion_trig->dev.parent = &client->dev;
  1049. data->motion_trig->ops = &kxcjk1013_trigger_ops;
  1050. iio_trigger_set_drvdata(data->motion_trig, indio_dev);
  1051. ret = iio_trigger_register(data->motion_trig);
  1052. if (ret) {
  1053. data->motion_trig = NULL;
  1054. goto err_trigger_unregister;
  1055. }
  1056. ret = iio_triggered_buffer_setup(indio_dev,
  1057. &iio_pollfunc_store_time,
  1058. kxcjk1013_trigger_handler,
  1059. NULL);
  1060. if (ret < 0) {
  1061. dev_err(&client->dev,
  1062. "iio triggered buffer setup failed\n");
  1063. goto err_trigger_unregister;
  1064. }
  1065. }
  1066. ret = iio_device_register(indio_dev);
  1067. if (ret < 0) {
  1068. dev_err(&client->dev, "unable to register iio device\n");
  1069. goto err_buffer_cleanup;
  1070. }
  1071. ret = pm_runtime_set_active(&client->dev);
  1072. if (ret)
  1073. goto err_iio_unregister;
  1074. pm_runtime_enable(&client->dev);
  1075. pm_runtime_set_autosuspend_delay(&client->dev,
  1076. KXCJK1013_SLEEP_DELAY_MS);
  1077. pm_runtime_use_autosuspend(&client->dev);
  1078. return 0;
  1079. err_iio_unregister:
  1080. iio_device_unregister(indio_dev);
  1081. err_buffer_cleanup:
  1082. if (data->dready_trig)
  1083. iio_triggered_buffer_cleanup(indio_dev);
  1084. err_trigger_unregister:
  1085. if (data->dready_trig)
  1086. iio_trigger_unregister(data->dready_trig);
  1087. if (data->motion_trig)
  1088. iio_trigger_unregister(data->motion_trig);
  1089. return ret;
  1090. }
  1091. static int kxcjk1013_remove(struct i2c_client *client)
  1092. {
  1093. struct iio_dev *indio_dev = i2c_get_clientdata(client);
  1094. struct kxcjk1013_data *data = iio_priv(indio_dev);
  1095. pm_runtime_disable(&client->dev);
  1096. pm_runtime_set_suspended(&client->dev);
  1097. pm_runtime_put_noidle(&client->dev);
  1098. iio_device_unregister(indio_dev);
  1099. if (data->dready_trig) {
  1100. iio_triggered_buffer_cleanup(indio_dev);
  1101. iio_trigger_unregister(data->dready_trig);
  1102. iio_trigger_unregister(data->motion_trig);
  1103. }
  1104. mutex_lock(&data->mutex);
  1105. kxcjk1013_set_mode(data, STANDBY);
  1106. mutex_unlock(&data->mutex);
  1107. return 0;
  1108. }
  1109. #ifdef CONFIG_PM_SLEEP
  1110. static int kxcjk1013_suspend(struct device *dev)
  1111. {
  1112. struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev));
  1113. struct kxcjk1013_data *data = iio_priv(indio_dev);
  1114. int ret;
  1115. mutex_lock(&data->mutex);
  1116. ret = kxcjk1013_set_mode(data, STANDBY);
  1117. mutex_unlock(&data->mutex);
  1118. return ret;
  1119. }
  1120. static int kxcjk1013_resume(struct device *dev)
  1121. {
  1122. struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev));
  1123. struct kxcjk1013_data *data = iio_priv(indio_dev);
  1124. int ret = 0;
  1125. mutex_lock(&data->mutex);
  1126. /* Check, if the suspend occured while active */
  1127. if (data->dready_trigger_on || data->motion_trigger_on ||
  1128. data->ev_enable_state)
  1129. ret = kxcjk1013_set_mode(data, OPERATION);
  1130. mutex_unlock(&data->mutex);
  1131. return ret;
  1132. }
  1133. #endif
  1134. #ifdef CONFIG_PM_RUNTIME
  1135. static int kxcjk1013_runtime_suspend(struct device *dev)
  1136. {
  1137. struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev));
  1138. struct kxcjk1013_data *data = iio_priv(indio_dev);
  1139. return kxcjk1013_set_mode(data, STANDBY);
  1140. }
  1141. static int kxcjk1013_runtime_resume(struct device *dev)
  1142. {
  1143. struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev));
  1144. struct kxcjk1013_data *data = iio_priv(indio_dev);
  1145. int ret;
  1146. int sleep_val;
  1147. ret = kxcjk1013_set_mode(data, OPERATION);
  1148. if (ret < 0)
  1149. return ret;
  1150. sleep_val = kxcjk1013_get_startup_times(data);
  1151. if (sleep_val < 20000)
  1152. usleep_range(sleep_val, 20000);
  1153. else
  1154. msleep_interruptible(sleep_val/1000);
  1155. return 0;
  1156. }
  1157. #endif
  1158. static const struct dev_pm_ops kxcjk1013_pm_ops = {
  1159. SET_SYSTEM_SLEEP_PM_OPS(kxcjk1013_suspend, kxcjk1013_resume)
  1160. SET_RUNTIME_PM_OPS(kxcjk1013_runtime_suspend,
  1161. kxcjk1013_runtime_resume, NULL)
  1162. };
  1163. static const struct acpi_device_id kx_acpi_match[] = {
  1164. {"KXCJ1013", KXCJK1013},
  1165. {"KXCJ1008", KXCJ91008},
  1166. {"KXTJ1009", KXTJ21009},
  1167. { },
  1168. };
  1169. MODULE_DEVICE_TABLE(acpi, kx_acpi_match);
  1170. static const struct i2c_device_id kxcjk1013_id[] = {
  1171. {"kxcjk1013", KXCJK1013},
  1172. {"kxcj91008", KXCJ91008},
  1173. {"kxtj21009", KXTJ21009},
  1174. {}
  1175. };
  1176. MODULE_DEVICE_TABLE(i2c, kxcjk1013_id);
  1177. static struct i2c_driver kxcjk1013_driver = {
  1178. .driver = {
  1179. .name = KXCJK1013_DRV_NAME,
  1180. .acpi_match_table = ACPI_PTR(kx_acpi_match),
  1181. .pm = &kxcjk1013_pm_ops,
  1182. },
  1183. .probe = kxcjk1013_probe,
  1184. .remove = kxcjk1013_remove,
  1185. .id_table = kxcjk1013_id,
  1186. };
  1187. module_i2c_driver(kxcjk1013_driver);
  1188. MODULE_AUTHOR("Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>");
  1189. MODULE_LICENSE("GPL v2");
  1190. MODULE_DESCRIPTION("KXCJK1013 accelerometer driver");