tlb_uv.c 56 KB

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  1. /*
  2. * SGI UltraViolet TLB flush routines.
  3. *
  4. * (c) 2008-2014 Cliff Wickman <cpw@sgi.com>, SGI.
  5. *
  6. * This code is released under the GNU General Public License version 2 or
  7. * later.
  8. */
  9. #include <linux/seq_file.h>
  10. #include <linux/proc_fs.h>
  11. #include <linux/debugfs.h>
  12. #include <linux/kernel.h>
  13. #include <linux/slab.h>
  14. #include <linux/delay.h>
  15. #include <asm/mmu_context.h>
  16. #include <asm/uv/uv.h>
  17. #include <asm/uv/uv_mmrs.h>
  18. #include <asm/uv/uv_hub.h>
  19. #include <asm/uv/uv_bau.h>
  20. #include <asm/apic.h>
  21. #include <asm/idle.h>
  22. #include <asm/tsc.h>
  23. #include <asm/irq_vectors.h>
  24. #include <asm/timer.h>
  25. /* timeouts in nanoseconds (indexed by UVH_AGING_PRESCALE_SEL urgency7 30:28) */
  26. static int timeout_base_ns[] = {
  27. 20,
  28. 160,
  29. 1280,
  30. 10240,
  31. 81920,
  32. 655360,
  33. 5242880,
  34. 167772160
  35. };
  36. static int timeout_us;
  37. static int nobau;
  38. static int nobau_perm;
  39. static cycles_t congested_cycles;
  40. /* tunables: */
  41. static int max_concurr = MAX_BAU_CONCURRENT;
  42. static int max_concurr_const = MAX_BAU_CONCURRENT;
  43. static int plugged_delay = PLUGGED_DELAY;
  44. static int plugsb4reset = PLUGSB4RESET;
  45. static int giveup_limit = GIVEUP_LIMIT;
  46. static int timeoutsb4reset = TIMEOUTSB4RESET;
  47. static int ipi_reset_limit = IPI_RESET_LIMIT;
  48. static int complete_threshold = COMPLETE_THRESHOLD;
  49. static int congested_respns_us = CONGESTED_RESPONSE_US;
  50. static int congested_reps = CONGESTED_REPS;
  51. static int disabled_period = DISABLED_PERIOD;
  52. static struct tunables tunables[] = {
  53. {&max_concurr, MAX_BAU_CONCURRENT}, /* must be [0] */
  54. {&plugged_delay, PLUGGED_DELAY},
  55. {&plugsb4reset, PLUGSB4RESET},
  56. {&timeoutsb4reset, TIMEOUTSB4RESET},
  57. {&ipi_reset_limit, IPI_RESET_LIMIT},
  58. {&complete_threshold, COMPLETE_THRESHOLD},
  59. {&congested_respns_us, CONGESTED_RESPONSE_US},
  60. {&congested_reps, CONGESTED_REPS},
  61. {&disabled_period, DISABLED_PERIOD},
  62. {&giveup_limit, GIVEUP_LIMIT}
  63. };
  64. static struct dentry *tunables_dir;
  65. static struct dentry *tunables_file;
  66. /* these correspond to the statistics printed by ptc_seq_show() */
  67. static char *stat_description[] = {
  68. "sent: number of shootdown messages sent",
  69. "stime: time spent sending messages",
  70. "numuvhubs: number of hubs targeted with shootdown",
  71. "numuvhubs16: number times 16 or more hubs targeted",
  72. "numuvhubs8: number times 8 or more hubs targeted",
  73. "numuvhubs4: number times 4 or more hubs targeted",
  74. "numuvhubs2: number times 2 or more hubs targeted",
  75. "numuvhubs1: number times 1 hub targeted",
  76. "numcpus: number of cpus targeted with shootdown",
  77. "dto: number of destination timeouts",
  78. "retries: destination timeout retries sent",
  79. "rok: : destination timeouts successfully retried",
  80. "resetp: ipi-style resource resets for plugs",
  81. "resett: ipi-style resource resets for timeouts",
  82. "giveup: fall-backs to ipi-style shootdowns",
  83. "sto: number of source timeouts",
  84. "bz: number of stay-busy's",
  85. "throt: number times spun in throttle",
  86. "swack: image of UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE",
  87. "recv: shootdown messages received",
  88. "rtime: time spent processing messages",
  89. "all: shootdown all-tlb messages",
  90. "one: shootdown one-tlb messages",
  91. "mult: interrupts that found multiple messages",
  92. "none: interrupts that found no messages",
  93. "retry: number of retry messages processed",
  94. "canc: number messages canceled by retries",
  95. "nocan: number retries that found nothing to cancel",
  96. "reset: number of ipi-style reset requests processed",
  97. "rcan: number messages canceled by reset requests",
  98. "disable: number times use of the BAU was disabled",
  99. "enable: number times use of the BAU was re-enabled"
  100. };
  101. static int __init
  102. setup_nobau(char *arg)
  103. {
  104. nobau = 1;
  105. return 0;
  106. }
  107. early_param("nobau", setup_nobau);
  108. /* base pnode in this partition */
  109. static int uv_base_pnode __read_mostly;
  110. static DEFINE_PER_CPU(struct ptc_stats, ptcstats);
  111. static DEFINE_PER_CPU(struct bau_control, bau_control);
  112. static DEFINE_PER_CPU(cpumask_var_t, uv_flush_tlb_mask);
  113. static void
  114. set_bau_on(void)
  115. {
  116. int cpu;
  117. struct bau_control *bcp;
  118. if (nobau_perm) {
  119. pr_info("BAU not initialized; cannot be turned on\n");
  120. return;
  121. }
  122. nobau = 0;
  123. for_each_present_cpu(cpu) {
  124. bcp = &per_cpu(bau_control, cpu);
  125. bcp->nobau = 0;
  126. }
  127. pr_info("BAU turned on\n");
  128. return;
  129. }
  130. static void
  131. set_bau_off(void)
  132. {
  133. int cpu;
  134. struct bau_control *bcp;
  135. nobau = 1;
  136. for_each_present_cpu(cpu) {
  137. bcp = &per_cpu(bau_control, cpu);
  138. bcp->nobau = 1;
  139. }
  140. pr_info("BAU turned off\n");
  141. return;
  142. }
  143. /*
  144. * Determine the first node on a uvhub. 'Nodes' are used for kernel
  145. * memory allocation.
  146. */
  147. static int __init uvhub_to_first_node(int uvhub)
  148. {
  149. int node, b;
  150. for_each_online_node(node) {
  151. b = uv_node_to_blade_id(node);
  152. if (uvhub == b)
  153. return node;
  154. }
  155. return -1;
  156. }
  157. /*
  158. * Determine the apicid of the first cpu on a uvhub.
  159. */
  160. static int __init uvhub_to_first_apicid(int uvhub)
  161. {
  162. int cpu;
  163. for_each_present_cpu(cpu)
  164. if (uvhub == uv_cpu_to_blade_id(cpu))
  165. return per_cpu(x86_cpu_to_apicid, cpu);
  166. return -1;
  167. }
  168. /*
  169. * Free a software acknowledge hardware resource by clearing its Pending
  170. * bit. This will return a reply to the sender.
  171. * If the message has timed out, a reply has already been sent by the
  172. * hardware but the resource has not been released. In that case our
  173. * clear of the Timeout bit (as well) will free the resource. No reply will
  174. * be sent (the hardware will only do one reply per message).
  175. */
  176. static void reply_to_message(struct msg_desc *mdp, struct bau_control *bcp,
  177. int do_acknowledge)
  178. {
  179. unsigned long dw;
  180. struct bau_pq_entry *msg;
  181. msg = mdp->msg;
  182. if (!msg->canceled && do_acknowledge) {
  183. dw = (msg->swack_vec << UV_SW_ACK_NPENDING) | msg->swack_vec;
  184. write_mmr_sw_ack(dw);
  185. }
  186. msg->replied_to = 1;
  187. msg->swack_vec = 0;
  188. }
  189. /*
  190. * Process the receipt of a RETRY message
  191. */
  192. static void bau_process_retry_msg(struct msg_desc *mdp,
  193. struct bau_control *bcp)
  194. {
  195. int i;
  196. int cancel_count = 0;
  197. unsigned long msg_res;
  198. unsigned long mmr = 0;
  199. struct bau_pq_entry *msg = mdp->msg;
  200. struct bau_pq_entry *msg2;
  201. struct ptc_stats *stat = bcp->statp;
  202. stat->d_retries++;
  203. /*
  204. * cancel any message from msg+1 to the retry itself
  205. */
  206. for (msg2 = msg+1, i = 0; i < DEST_Q_SIZE; msg2++, i++) {
  207. if (msg2 > mdp->queue_last)
  208. msg2 = mdp->queue_first;
  209. if (msg2 == msg)
  210. break;
  211. /* same conditions for cancellation as do_reset */
  212. if ((msg2->replied_to == 0) && (msg2->canceled == 0) &&
  213. (msg2->swack_vec) && ((msg2->swack_vec &
  214. msg->swack_vec) == 0) &&
  215. (msg2->sending_cpu == msg->sending_cpu) &&
  216. (msg2->msg_type != MSG_NOOP)) {
  217. mmr = read_mmr_sw_ack();
  218. msg_res = msg2->swack_vec;
  219. /*
  220. * This is a message retry; clear the resources held
  221. * by the previous message only if they timed out.
  222. * If it has not timed out we have an unexpected
  223. * situation to report.
  224. */
  225. if (mmr & (msg_res << UV_SW_ACK_NPENDING)) {
  226. unsigned long mr;
  227. /*
  228. * Is the resource timed out?
  229. * Make everyone ignore the cancelled message.
  230. */
  231. msg2->canceled = 1;
  232. stat->d_canceled++;
  233. cancel_count++;
  234. mr = (msg_res << UV_SW_ACK_NPENDING) | msg_res;
  235. write_mmr_sw_ack(mr);
  236. }
  237. }
  238. }
  239. if (!cancel_count)
  240. stat->d_nocanceled++;
  241. }
  242. /*
  243. * Do all the things a cpu should do for a TLB shootdown message.
  244. * Other cpu's may come here at the same time for this message.
  245. */
  246. static void bau_process_message(struct msg_desc *mdp, struct bau_control *bcp,
  247. int do_acknowledge)
  248. {
  249. short socket_ack_count = 0;
  250. short *sp;
  251. struct atomic_short *asp;
  252. struct ptc_stats *stat = bcp->statp;
  253. struct bau_pq_entry *msg = mdp->msg;
  254. struct bau_control *smaster = bcp->socket_master;
  255. /*
  256. * This must be a normal message, or retry of a normal message
  257. */
  258. if (msg->address == TLB_FLUSH_ALL) {
  259. local_flush_tlb();
  260. stat->d_alltlb++;
  261. } else {
  262. __flush_tlb_one(msg->address);
  263. stat->d_onetlb++;
  264. }
  265. stat->d_requestee++;
  266. /*
  267. * One cpu on each uvhub has the additional job on a RETRY
  268. * of releasing the resource held by the message that is
  269. * being retried. That message is identified by sending
  270. * cpu number.
  271. */
  272. if (msg->msg_type == MSG_RETRY && bcp == bcp->uvhub_master)
  273. bau_process_retry_msg(mdp, bcp);
  274. /*
  275. * This is a swack message, so we have to reply to it.
  276. * Count each responding cpu on the socket. This avoids
  277. * pinging the count's cache line back and forth between
  278. * the sockets.
  279. */
  280. sp = &smaster->socket_acknowledge_count[mdp->msg_slot];
  281. asp = (struct atomic_short *)sp;
  282. socket_ack_count = atom_asr(1, asp);
  283. if (socket_ack_count == bcp->cpus_in_socket) {
  284. int msg_ack_count;
  285. /*
  286. * Both sockets dump their completed count total into
  287. * the message's count.
  288. */
  289. *sp = 0;
  290. asp = (struct atomic_short *)&msg->acknowledge_count;
  291. msg_ack_count = atom_asr(socket_ack_count, asp);
  292. if (msg_ack_count == bcp->cpus_in_uvhub) {
  293. /*
  294. * All cpus in uvhub saw it; reply
  295. * (unless we are in the UV2 workaround)
  296. */
  297. reply_to_message(mdp, bcp, do_acknowledge);
  298. }
  299. }
  300. return;
  301. }
  302. /*
  303. * Determine the first cpu on a pnode.
  304. */
  305. static int pnode_to_first_cpu(int pnode, struct bau_control *smaster)
  306. {
  307. int cpu;
  308. struct hub_and_pnode *hpp;
  309. for_each_present_cpu(cpu) {
  310. hpp = &smaster->thp[cpu];
  311. if (pnode == hpp->pnode)
  312. return cpu;
  313. }
  314. return -1;
  315. }
  316. /*
  317. * Last resort when we get a large number of destination timeouts is
  318. * to clear resources held by a given cpu.
  319. * Do this with IPI so that all messages in the BAU message queue
  320. * can be identified by their nonzero swack_vec field.
  321. *
  322. * This is entered for a single cpu on the uvhub.
  323. * The sender want's this uvhub to free a specific message's
  324. * swack resources.
  325. */
  326. static void do_reset(void *ptr)
  327. {
  328. int i;
  329. struct bau_control *bcp = &per_cpu(bau_control, smp_processor_id());
  330. struct reset_args *rap = (struct reset_args *)ptr;
  331. struct bau_pq_entry *msg;
  332. struct ptc_stats *stat = bcp->statp;
  333. stat->d_resets++;
  334. /*
  335. * We're looking for the given sender, and
  336. * will free its swack resource.
  337. * If all cpu's finally responded after the timeout, its
  338. * message 'replied_to' was set.
  339. */
  340. for (msg = bcp->queue_first, i = 0; i < DEST_Q_SIZE; msg++, i++) {
  341. unsigned long msg_res;
  342. /* do_reset: same conditions for cancellation as
  343. bau_process_retry_msg() */
  344. if ((msg->replied_to == 0) &&
  345. (msg->canceled == 0) &&
  346. (msg->sending_cpu == rap->sender) &&
  347. (msg->swack_vec) &&
  348. (msg->msg_type != MSG_NOOP)) {
  349. unsigned long mmr;
  350. unsigned long mr;
  351. /*
  352. * make everyone else ignore this message
  353. */
  354. msg->canceled = 1;
  355. /*
  356. * only reset the resource if it is still pending
  357. */
  358. mmr = read_mmr_sw_ack();
  359. msg_res = msg->swack_vec;
  360. mr = (msg_res << UV_SW_ACK_NPENDING) | msg_res;
  361. if (mmr & msg_res) {
  362. stat->d_rcanceled++;
  363. write_mmr_sw_ack(mr);
  364. }
  365. }
  366. }
  367. return;
  368. }
  369. /*
  370. * Use IPI to get all target uvhubs to release resources held by
  371. * a given sending cpu number.
  372. */
  373. static void reset_with_ipi(struct pnmask *distribution, struct bau_control *bcp)
  374. {
  375. int pnode;
  376. int apnode;
  377. int maskbits;
  378. int sender = bcp->cpu;
  379. cpumask_t *mask = bcp->uvhub_master->cpumask;
  380. struct bau_control *smaster = bcp->socket_master;
  381. struct reset_args reset_args;
  382. reset_args.sender = sender;
  383. cpus_clear(*mask);
  384. /* find a single cpu for each uvhub in this distribution mask */
  385. maskbits = sizeof(struct pnmask) * BITSPERBYTE;
  386. /* each bit is a pnode relative to the partition base pnode */
  387. for (pnode = 0; pnode < maskbits; pnode++) {
  388. int cpu;
  389. if (!bau_uvhub_isset(pnode, distribution))
  390. continue;
  391. apnode = pnode + bcp->partition_base_pnode;
  392. cpu = pnode_to_first_cpu(apnode, smaster);
  393. cpu_set(cpu, *mask);
  394. }
  395. /* IPI all cpus; preemption is already disabled */
  396. smp_call_function_many(mask, do_reset, (void *)&reset_args, 1);
  397. return;
  398. }
  399. /*
  400. * Not to be confused with cycles_2_ns() from tsc.c; this gives a relative
  401. * number, not an absolute. It converts a duration in cycles to a duration in
  402. * ns.
  403. */
  404. static inline unsigned long long cycles_2_ns(unsigned long long cyc)
  405. {
  406. struct cyc2ns_data *data = cyc2ns_read_begin();
  407. unsigned long long ns;
  408. ns = mul_u64_u32_shr(cyc, data->cyc2ns_mul, data->cyc2ns_shift);
  409. cyc2ns_read_end(data);
  410. return ns;
  411. }
  412. /*
  413. * The reverse of the above; converts a duration in ns to a duration in cycles.
  414. */
  415. static inline unsigned long long ns_2_cycles(unsigned long long ns)
  416. {
  417. struct cyc2ns_data *data = cyc2ns_read_begin();
  418. unsigned long long cyc;
  419. cyc = (ns << data->cyc2ns_shift) / data->cyc2ns_mul;
  420. cyc2ns_read_end(data);
  421. return cyc;
  422. }
  423. static inline unsigned long cycles_2_us(unsigned long long cyc)
  424. {
  425. return cycles_2_ns(cyc) / NSEC_PER_USEC;
  426. }
  427. static inline cycles_t sec_2_cycles(unsigned long sec)
  428. {
  429. return ns_2_cycles(sec * NSEC_PER_SEC);
  430. }
  431. static inline unsigned long long usec_2_cycles(unsigned long usec)
  432. {
  433. return ns_2_cycles(usec * NSEC_PER_USEC);
  434. }
  435. /*
  436. * wait for all cpus on this hub to finish their sends and go quiet
  437. * leaves uvhub_quiesce set so that no new broadcasts are started by
  438. * bau_flush_send_and_wait()
  439. */
  440. static inline void quiesce_local_uvhub(struct bau_control *hmaster)
  441. {
  442. atom_asr(1, (struct atomic_short *)&hmaster->uvhub_quiesce);
  443. }
  444. /*
  445. * mark this quiet-requestor as done
  446. */
  447. static inline void end_uvhub_quiesce(struct bau_control *hmaster)
  448. {
  449. atom_asr(-1, (struct atomic_short *)&hmaster->uvhub_quiesce);
  450. }
  451. static unsigned long uv1_read_status(unsigned long mmr_offset, int right_shift)
  452. {
  453. unsigned long descriptor_status;
  454. descriptor_status = uv_read_local_mmr(mmr_offset);
  455. descriptor_status >>= right_shift;
  456. descriptor_status &= UV_ACT_STATUS_MASK;
  457. return descriptor_status;
  458. }
  459. /*
  460. * Wait for completion of a broadcast software ack message
  461. * return COMPLETE, RETRY(PLUGGED or TIMEOUT) or GIVEUP
  462. */
  463. static int uv1_wait_completion(struct bau_desc *bau_desc,
  464. unsigned long mmr_offset, int right_shift,
  465. struct bau_control *bcp, long try)
  466. {
  467. unsigned long descriptor_status;
  468. cycles_t ttm;
  469. struct ptc_stats *stat = bcp->statp;
  470. descriptor_status = uv1_read_status(mmr_offset, right_shift);
  471. /* spin on the status MMR, waiting for it to go idle */
  472. while ((descriptor_status != DS_IDLE)) {
  473. /*
  474. * Our software ack messages may be blocked because
  475. * there are no swack resources available. As long
  476. * as none of them has timed out hardware will NACK
  477. * our message and its state will stay IDLE.
  478. */
  479. if (descriptor_status == DS_SOURCE_TIMEOUT) {
  480. stat->s_stimeout++;
  481. return FLUSH_GIVEUP;
  482. } else if (descriptor_status == DS_DESTINATION_TIMEOUT) {
  483. stat->s_dtimeout++;
  484. ttm = get_cycles();
  485. /*
  486. * Our retries may be blocked by all destination
  487. * swack resources being consumed, and a timeout
  488. * pending. In that case hardware returns the
  489. * ERROR that looks like a destination timeout.
  490. */
  491. if (cycles_2_us(ttm - bcp->send_message) < timeout_us) {
  492. bcp->conseccompletes = 0;
  493. return FLUSH_RETRY_PLUGGED;
  494. }
  495. bcp->conseccompletes = 0;
  496. return FLUSH_RETRY_TIMEOUT;
  497. } else {
  498. /*
  499. * descriptor_status is still BUSY
  500. */
  501. cpu_relax();
  502. }
  503. descriptor_status = uv1_read_status(mmr_offset, right_shift);
  504. }
  505. bcp->conseccompletes++;
  506. return FLUSH_COMPLETE;
  507. }
  508. /*
  509. * UV2 could have an extra bit of status in the ACTIVATION_STATUS_2 register.
  510. * But not currently used.
  511. */
  512. static unsigned long uv2_3_read_status(unsigned long offset, int rshft, int desc)
  513. {
  514. unsigned long descriptor_status;
  515. descriptor_status =
  516. ((read_lmmr(offset) >> rshft) & UV_ACT_STATUS_MASK) << 1;
  517. return descriptor_status;
  518. }
  519. /*
  520. * Return whether the status of the descriptor that is normally used for this
  521. * cpu (the one indexed by its hub-relative cpu number) is busy.
  522. * The status of the original 32 descriptors is always reflected in the 64
  523. * bits of UVH_LB_BAU_SB_ACTIVATION_STATUS_0.
  524. * The bit provided by the activation_status_2 register is irrelevant to
  525. * the status if it is only being tested for busy or not busy.
  526. */
  527. int normal_busy(struct bau_control *bcp)
  528. {
  529. int cpu = bcp->uvhub_cpu;
  530. int mmr_offset;
  531. int right_shift;
  532. mmr_offset = UVH_LB_BAU_SB_ACTIVATION_STATUS_0;
  533. right_shift = cpu * UV_ACT_STATUS_SIZE;
  534. return (((((read_lmmr(mmr_offset) >> right_shift) &
  535. UV_ACT_STATUS_MASK)) << 1) == UV2H_DESC_BUSY);
  536. }
  537. /*
  538. * Entered when a bau descriptor has gone into a permanent busy wait because
  539. * of a hardware bug.
  540. * Workaround the bug.
  541. */
  542. int handle_uv2_busy(struct bau_control *bcp)
  543. {
  544. struct ptc_stats *stat = bcp->statp;
  545. stat->s_uv2_wars++;
  546. bcp->busy = 1;
  547. return FLUSH_GIVEUP;
  548. }
  549. static int uv2_3_wait_completion(struct bau_desc *bau_desc,
  550. unsigned long mmr_offset, int right_shift,
  551. struct bau_control *bcp, long try)
  552. {
  553. unsigned long descriptor_stat;
  554. cycles_t ttm;
  555. int desc = bcp->uvhub_cpu;
  556. long busy_reps = 0;
  557. struct ptc_stats *stat = bcp->statp;
  558. descriptor_stat = uv2_3_read_status(mmr_offset, right_shift, desc);
  559. /* spin on the status MMR, waiting for it to go idle */
  560. while (descriptor_stat != UV2H_DESC_IDLE) {
  561. if ((descriptor_stat == UV2H_DESC_SOURCE_TIMEOUT)) {
  562. /*
  563. * A h/w bug on the destination side may
  564. * have prevented the message being marked
  565. * pending, thus it doesn't get replied to
  566. * and gets continually nacked until it times
  567. * out with a SOURCE_TIMEOUT.
  568. */
  569. stat->s_stimeout++;
  570. return FLUSH_GIVEUP;
  571. } else if (descriptor_stat == UV2H_DESC_DEST_TIMEOUT) {
  572. ttm = get_cycles();
  573. /*
  574. * Our retries may be blocked by all destination
  575. * swack resources being consumed, and a timeout
  576. * pending. In that case hardware returns the
  577. * ERROR that looks like a destination timeout.
  578. * Without using the extended status we have to
  579. * deduce from the short time that this was a
  580. * strong nack.
  581. */
  582. if (cycles_2_us(ttm - bcp->send_message) < timeout_us) {
  583. bcp->conseccompletes = 0;
  584. stat->s_plugged++;
  585. /* FLUSH_RETRY_PLUGGED causes hang on boot */
  586. return FLUSH_GIVEUP;
  587. }
  588. stat->s_dtimeout++;
  589. bcp->conseccompletes = 0;
  590. /* FLUSH_RETRY_TIMEOUT causes hang on boot */
  591. return FLUSH_GIVEUP;
  592. } else {
  593. busy_reps++;
  594. if (busy_reps > 1000000) {
  595. /* not to hammer on the clock */
  596. busy_reps = 0;
  597. ttm = get_cycles();
  598. if ((ttm - bcp->send_message) > bcp->timeout_interval)
  599. return handle_uv2_busy(bcp);
  600. }
  601. /*
  602. * descriptor_stat is still BUSY
  603. */
  604. cpu_relax();
  605. }
  606. descriptor_stat = uv2_3_read_status(mmr_offset, right_shift, desc);
  607. }
  608. bcp->conseccompletes++;
  609. return FLUSH_COMPLETE;
  610. }
  611. /*
  612. * There are 2 status registers; each and array[32] of 2 bits. Set up for
  613. * which register to read and position in that register based on cpu in
  614. * current hub.
  615. */
  616. static int wait_completion(struct bau_desc *bau_desc, struct bau_control *bcp, long try)
  617. {
  618. int right_shift;
  619. unsigned long mmr_offset;
  620. int desc = bcp->uvhub_cpu;
  621. if (desc < UV_CPUS_PER_AS) {
  622. mmr_offset = UVH_LB_BAU_SB_ACTIVATION_STATUS_0;
  623. right_shift = desc * UV_ACT_STATUS_SIZE;
  624. } else {
  625. mmr_offset = UVH_LB_BAU_SB_ACTIVATION_STATUS_1;
  626. right_shift = ((desc - UV_CPUS_PER_AS) * UV_ACT_STATUS_SIZE);
  627. }
  628. if (bcp->uvhub_version == 1)
  629. return uv1_wait_completion(bau_desc, mmr_offset, right_shift, bcp, try);
  630. else
  631. return uv2_3_wait_completion(bau_desc, mmr_offset, right_shift, bcp, try);
  632. }
  633. /*
  634. * Our retries are blocked by all destination sw ack resources being
  635. * in use, and a timeout is pending. In that case hardware immediately
  636. * returns the ERROR that looks like a destination timeout.
  637. */
  638. static void destination_plugged(struct bau_desc *bau_desc,
  639. struct bau_control *bcp,
  640. struct bau_control *hmaster, struct ptc_stats *stat)
  641. {
  642. udelay(bcp->plugged_delay);
  643. bcp->plugged_tries++;
  644. if (bcp->plugged_tries >= bcp->plugsb4reset) {
  645. bcp->plugged_tries = 0;
  646. quiesce_local_uvhub(hmaster);
  647. spin_lock(&hmaster->queue_lock);
  648. reset_with_ipi(&bau_desc->distribution, bcp);
  649. spin_unlock(&hmaster->queue_lock);
  650. end_uvhub_quiesce(hmaster);
  651. bcp->ipi_attempts++;
  652. stat->s_resets_plug++;
  653. }
  654. }
  655. static void destination_timeout(struct bau_desc *bau_desc,
  656. struct bau_control *bcp, struct bau_control *hmaster,
  657. struct ptc_stats *stat)
  658. {
  659. hmaster->max_concurr = 1;
  660. bcp->timeout_tries++;
  661. if (bcp->timeout_tries >= bcp->timeoutsb4reset) {
  662. bcp->timeout_tries = 0;
  663. quiesce_local_uvhub(hmaster);
  664. spin_lock(&hmaster->queue_lock);
  665. reset_with_ipi(&bau_desc->distribution, bcp);
  666. spin_unlock(&hmaster->queue_lock);
  667. end_uvhub_quiesce(hmaster);
  668. bcp->ipi_attempts++;
  669. stat->s_resets_timeout++;
  670. }
  671. }
  672. /*
  673. * Stop all cpus on a uvhub from using the BAU for a period of time.
  674. * This is reversed by check_enable.
  675. */
  676. static void disable_for_period(struct bau_control *bcp, struct ptc_stats *stat)
  677. {
  678. int tcpu;
  679. struct bau_control *tbcp;
  680. struct bau_control *hmaster;
  681. cycles_t tm1;
  682. hmaster = bcp->uvhub_master;
  683. spin_lock(&hmaster->disable_lock);
  684. if (!bcp->baudisabled) {
  685. stat->s_bau_disabled++;
  686. tm1 = get_cycles();
  687. for_each_present_cpu(tcpu) {
  688. tbcp = &per_cpu(bau_control, tcpu);
  689. if (tbcp->uvhub_master == hmaster) {
  690. tbcp->baudisabled = 1;
  691. tbcp->set_bau_on_time =
  692. tm1 + bcp->disabled_period;
  693. }
  694. }
  695. }
  696. spin_unlock(&hmaster->disable_lock);
  697. }
  698. static void count_max_concurr(int stat, struct bau_control *bcp,
  699. struct bau_control *hmaster)
  700. {
  701. bcp->plugged_tries = 0;
  702. bcp->timeout_tries = 0;
  703. if (stat != FLUSH_COMPLETE)
  704. return;
  705. if (bcp->conseccompletes <= bcp->complete_threshold)
  706. return;
  707. if (hmaster->max_concurr >= hmaster->max_concurr_const)
  708. return;
  709. hmaster->max_concurr++;
  710. }
  711. static void record_send_stats(cycles_t time1, cycles_t time2,
  712. struct bau_control *bcp, struct ptc_stats *stat,
  713. int completion_status, int try)
  714. {
  715. cycles_t elapsed;
  716. if (time2 > time1) {
  717. elapsed = time2 - time1;
  718. stat->s_time += elapsed;
  719. if ((completion_status == FLUSH_COMPLETE) && (try == 1)) {
  720. bcp->period_requests++;
  721. bcp->period_time += elapsed;
  722. if ((elapsed > congested_cycles) &&
  723. (bcp->period_requests > bcp->cong_reps) &&
  724. ((bcp->period_time / bcp->period_requests) >
  725. congested_cycles)) {
  726. stat->s_congested++;
  727. disable_for_period(bcp, stat);
  728. }
  729. }
  730. } else
  731. stat->s_requestor--;
  732. if (completion_status == FLUSH_COMPLETE && try > 1)
  733. stat->s_retriesok++;
  734. else if (completion_status == FLUSH_GIVEUP) {
  735. stat->s_giveup++;
  736. if (get_cycles() > bcp->period_end)
  737. bcp->period_giveups = 0;
  738. bcp->period_giveups++;
  739. if (bcp->period_giveups == 1)
  740. bcp->period_end = get_cycles() + bcp->disabled_period;
  741. if (bcp->period_giveups > bcp->giveup_limit) {
  742. disable_for_period(bcp, stat);
  743. stat->s_giveuplimit++;
  744. }
  745. }
  746. }
  747. /*
  748. * Because of a uv1 hardware bug only a limited number of concurrent
  749. * requests can be made.
  750. */
  751. static void uv1_throttle(struct bau_control *hmaster, struct ptc_stats *stat)
  752. {
  753. spinlock_t *lock = &hmaster->uvhub_lock;
  754. atomic_t *v;
  755. v = &hmaster->active_descriptor_count;
  756. if (!atomic_inc_unless_ge(lock, v, hmaster->max_concurr)) {
  757. stat->s_throttles++;
  758. do {
  759. cpu_relax();
  760. } while (!atomic_inc_unless_ge(lock, v, hmaster->max_concurr));
  761. }
  762. }
  763. /*
  764. * Handle the completion status of a message send.
  765. */
  766. static void handle_cmplt(int completion_status, struct bau_desc *bau_desc,
  767. struct bau_control *bcp, struct bau_control *hmaster,
  768. struct ptc_stats *stat)
  769. {
  770. if (completion_status == FLUSH_RETRY_PLUGGED)
  771. destination_plugged(bau_desc, bcp, hmaster, stat);
  772. else if (completion_status == FLUSH_RETRY_TIMEOUT)
  773. destination_timeout(bau_desc, bcp, hmaster, stat);
  774. }
  775. /*
  776. * Send a broadcast and wait for it to complete.
  777. *
  778. * The flush_mask contains the cpus the broadcast is to be sent to including
  779. * cpus that are on the local uvhub.
  780. *
  781. * Returns 0 if all flushing represented in the mask was done.
  782. * Returns 1 if it gives up entirely and the original cpu mask is to be
  783. * returned to the kernel.
  784. */
  785. int uv_flush_send_and_wait(struct cpumask *flush_mask, struct bau_control *bcp,
  786. struct bau_desc *bau_desc)
  787. {
  788. int seq_number = 0;
  789. int completion_stat = 0;
  790. int uv1 = 0;
  791. long try = 0;
  792. unsigned long index;
  793. cycles_t time1;
  794. cycles_t time2;
  795. struct ptc_stats *stat = bcp->statp;
  796. struct bau_control *hmaster = bcp->uvhub_master;
  797. struct uv1_bau_msg_header *uv1_hdr = NULL;
  798. struct uv2_3_bau_msg_header *uv2_3_hdr = NULL;
  799. if (bcp->uvhub_version == 1) {
  800. uv1 = 1;
  801. uv1_throttle(hmaster, stat);
  802. }
  803. while (hmaster->uvhub_quiesce)
  804. cpu_relax();
  805. time1 = get_cycles();
  806. if (uv1)
  807. uv1_hdr = &bau_desc->header.uv1_hdr;
  808. else
  809. /* uv2 and uv3 */
  810. uv2_3_hdr = &bau_desc->header.uv2_3_hdr;
  811. do {
  812. if (try == 0) {
  813. if (uv1)
  814. uv1_hdr->msg_type = MSG_REGULAR;
  815. else
  816. uv2_3_hdr->msg_type = MSG_REGULAR;
  817. seq_number = bcp->message_number++;
  818. } else {
  819. if (uv1)
  820. uv1_hdr->msg_type = MSG_RETRY;
  821. else
  822. uv2_3_hdr->msg_type = MSG_RETRY;
  823. stat->s_retry_messages++;
  824. }
  825. if (uv1)
  826. uv1_hdr->sequence = seq_number;
  827. else
  828. uv2_3_hdr->sequence = seq_number;
  829. index = (1UL << AS_PUSH_SHIFT) | bcp->uvhub_cpu;
  830. bcp->send_message = get_cycles();
  831. write_mmr_activation(index);
  832. try++;
  833. completion_stat = wait_completion(bau_desc, bcp, try);
  834. handle_cmplt(completion_stat, bau_desc, bcp, hmaster, stat);
  835. if (bcp->ipi_attempts >= bcp->ipi_reset_limit) {
  836. bcp->ipi_attempts = 0;
  837. stat->s_overipilimit++;
  838. completion_stat = FLUSH_GIVEUP;
  839. break;
  840. }
  841. cpu_relax();
  842. } while ((completion_stat == FLUSH_RETRY_PLUGGED) ||
  843. (completion_stat == FLUSH_RETRY_TIMEOUT));
  844. time2 = get_cycles();
  845. count_max_concurr(completion_stat, bcp, hmaster);
  846. while (hmaster->uvhub_quiesce)
  847. cpu_relax();
  848. atomic_dec(&hmaster->active_descriptor_count);
  849. record_send_stats(time1, time2, bcp, stat, completion_stat, try);
  850. if (completion_stat == FLUSH_GIVEUP)
  851. /* FLUSH_GIVEUP will fall back to using IPI's for tlb flush */
  852. return 1;
  853. return 0;
  854. }
  855. /*
  856. * The BAU is disabled for this uvhub. When the disabled time period has
  857. * expired re-enable it.
  858. * Return 0 if it is re-enabled for all cpus on this uvhub.
  859. */
  860. static int check_enable(struct bau_control *bcp, struct ptc_stats *stat)
  861. {
  862. int tcpu;
  863. struct bau_control *tbcp;
  864. struct bau_control *hmaster;
  865. hmaster = bcp->uvhub_master;
  866. spin_lock(&hmaster->disable_lock);
  867. if (bcp->baudisabled && (get_cycles() >= bcp->set_bau_on_time)) {
  868. stat->s_bau_reenabled++;
  869. for_each_present_cpu(tcpu) {
  870. tbcp = &per_cpu(bau_control, tcpu);
  871. if (tbcp->uvhub_master == hmaster) {
  872. tbcp->baudisabled = 0;
  873. tbcp->period_requests = 0;
  874. tbcp->period_time = 0;
  875. tbcp->period_giveups = 0;
  876. }
  877. }
  878. spin_unlock(&hmaster->disable_lock);
  879. return 0;
  880. }
  881. spin_unlock(&hmaster->disable_lock);
  882. return -1;
  883. }
  884. static void record_send_statistics(struct ptc_stats *stat, int locals, int hubs,
  885. int remotes, struct bau_desc *bau_desc)
  886. {
  887. stat->s_requestor++;
  888. stat->s_ntargcpu += remotes + locals;
  889. stat->s_ntargremotes += remotes;
  890. stat->s_ntarglocals += locals;
  891. /* uvhub statistics */
  892. hubs = bau_uvhub_weight(&bau_desc->distribution);
  893. if (locals) {
  894. stat->s_ntarglocaluvhub++;
  895. stat->s_ntargremoteuvhub += (hubs - 1);
  896. } else
  897. stat->s_ntargremoteuvhub += hubs;
  898. stat->s_ntarguvhub += hubs;
  899. if (hubs >= 16)
  900. stat->s_ntarguvhub16++;
  901. else if (hubs >= 8)
  902. stat->s_ntarguvhub8++;
  903. else if (hubs >= 4)
  904. stat->s_ntarguvhub4++;
  905. else if (hubs >= 2)
  906. stat->s_ntarguvhub2++;
  907. else
  908. stat->s_ntarguvhub1++;
  909. }
  910. /*
  911. * Translate a cpu mask to the uvhub distribution mask in the BAU
  912. * activation descriptor.
  913. */
  914. static int set_distrib_bits(struct cpumask *flush_mask, struct bau_control *bcp,
  915. struct bau_desc *bau_desc, int *localsp, int *remotesp)
  916. {
  917. int cpu;
  918. int pnode;
  919. int cnt = 0;
  920. struct hub_and_pnode *hpp;
  921. for_each_cpu(cpu, flush_mask) {
  922. /*
  923. * The distribution vector is a bit map of pnodes, relative
  924. * to the partition base pnode (and the partition base nasid
  925. * in the header).
  926. * Translate cpu to pnode and hub using a local memory array.
  927. */
  928. hpp = &bcp->socket_master->thp[cpu];
  929. pnode = hpp->pnode - bcp->partition_base_pnode;
  930. bau_uvhub_set(pnode, &bau_desc->distribution);
  931. cnt++;
  932. if (hpp->uvhub == bcp->uvhub)
  933. (*localsp)++;
  934. else
  935. (*remotesp)++;
  936. }
  937. if (!cnt)
  938. return 1;
  939. return 0;
  940. }
  941. /*
  942. * globally purge translation cache of a virtual address or all TLB's
  943. * @cpumask: mask of all cpu's in which the address is to be removed
  944. * @mm: mm_struct containing virtual address range
  945. * @start: start virtual address to be removed from TLB
  946. * @end: end virtual address to be remove from TLB
  947. * @cpu: the current cpu
  948. *
  949. * This is the entry point for initiating any UV global TLB shootdown.
  950. *
  951. * Purges the translation caches of all specified processors of the given
  952. * virtual address, or purges all TLB's on specified processors.
  953. *
  954. * The caller has derived the cpumask from the mm_struct. This function
  955. * is called only if there are bits set in the mask. (e.g. flush_tlb_page())
  956. *
  957. * The cpumask is converted into a uvhubmask of the uvhubs containing
  958. * those cpus.
  959. *
  960. * Note that this function should be called with preemption disabled.
  961. *
  962. * Returns NULL if all remote flushing was done.
  963. * Returns pointer to cpumask if some remote flushing remains to be
  964. * done. The returned pointer is valid till preemption is re-enabled.
  965. */
  966. const struct cpumask *uv_flush_tlb_others(const struct cpumask *cpumask,
  967. struct mm_struct *mm,
  968. unsigned long start,
  969. unsigned long end,
  970. unsigned int cpu)
  971. {
  972. int locals = 0;
  973. int remotes = 0;
  974. int hubs = 0;
  975. struct bau_desc *bau_desc;
  976. struct cpumask *flush_mask;
  977. struct ptc_stats *stat;
  978. struct bau_control *bcp;
  979. unsigned long descriptor_status;
  980. unsigned long status;
  981. bcp = &per_cpu(bau_control, cpu);
  982. if (bcp->nobau)
  983. return cpumask;
  984. stat = bcp->statp;
  985. stat->s_enters++;
  986. if (bcp->busy) {
  987. descriptor_status =
  988. read_lmmr(UVH_LB_BAU_SB_ACTIVATION_STATUS_0);
  989. status = ((descriptor_status >> (bcp->uvhub_cpu *
  990. UV_ACT_STATUS_SIZE)) & UV_ACT_STATUS_MASK) << 1;
  991. if (status == UV2H_DESC_BUSY)
  992. return cpumask;
  993. bcp->busy = 0;
  994. }
  995. /* bau was disabled due to slow response */
  996. if (bcp->baudisabled) {
  997. if (check_enable(bcp, stat)) {
  998. stat->s_ipifordisabled++;
  999. return cpumask;
  1000. }
  1001. }
  1002. /*
  1003. * Each sending cpu has a per-cpu mask which it fills from the caller's
  1004. * cpu mask. All cpus are converted to uvhubs and copied to the
  1005. * activation descriptor.
  1006. */
  1007. flush_mask = (struct cpumask *)per_cpu(uv_flush_tlb_mask, cpu);
  1008. /* don't actually do a shootdown of the local cpu */
  1009. cpumask_andnot(flush_mask, cpumask, cpumask_of(cpu));
  1010. if (cpu_isset(cpu, *cpumask))
  1011. stat->s_ntargself++;
  1012. bau_desc = bcp->descriptor_base;
  1013. bau_desc += (ITEMS_PER_DESC * bcp->uvhub_cpu);
  1014. bau_uvhubs_clear(&bau_desc->distribution, UV_DISTRIBUTION_SIZE);
  1015. if (set_distrib_bits(flush_mask, bcp, bau_desc, &locals, &remotes))
  1016. return NULL;
  1017. record_send_statistics(stat, locals, hubs, remotes, bau_desc);
  1018. if (!end || (end - start) <= PAGE_SIZE)
  1019. bau_desc->payload.address = start;
  1020. else
  1021. bau_desc->payload.address = TLB_FLUSH_ALL;
  1022. bau_desc->payload.sending_cpu = cpu;
  1023. /*
  1024. * uv_flush_send_and_wait returns 0 if all cpu's were messaged,
  1025. * or 1 if it gave up and the original cpumask should be returned.
  1026. */
  1027. if (!uv_flush_send_and_wait(flush_mask, bcp, bau_desc))
  1028. return NULL;
  1029. else
  1030. return cpumask;
  1031. }
  1032. /*
  1033. * Search the message queue for any 'other' unprocessed message with the
  1034. * same software acknowledge resource bit vector as the 'msg' message.
  1035. */
  1036. struct bau_pq_entry *find_another_by_swack(struct bau_pq_entry *msg,
  1037. struct bau_control *bcp)
  1038. {
  1039. struct bau_pq_entry *msg_next = msg + 1;
  1040. unsigned char swack_vec = msg->swack_vec;
  1041. if (msg_next > bcp->queue_last)
  1042. msg_next = bcp->queue_first;
  1043. while (msg_next != msg) {
  1044. if ((msg_next->canceled == 0) && (msg_next->replied_to == 0) &&
  1045. (msg_next->swack_vec == swack_vec))
  1046. return msg_next;
  1047. msg_next++;
  1048. if (msg_next > bcp->queue_last)
  1049. msg_next = bcp->queue_first;
  1050. }
  1051. return NULL;
  1052. }
  1053. /*
  1054. * UV2 needs to work around a bug in which an arriving message has not
  1055. * set a bit in the UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE register.
  1056. * Such a message must be ignored.
  1057. */
  1058. void process_uv2_message(struct msg_desc *mdp, struct bau_control *bcp)
  1059. {
  1060. unsigned long mmr_image;
  1061. unsigned char swack_vec;
  1062. struct bau_pq_entry *msg = mdp->msg;
  1063. struct bau_pq_entry *other_msg;
  1064. mmr_image = read_mmr_sw_ack();
  1065. swack_vec = msg->swack_vec;
  1066. if ((swack_vec & mmr_image) == 0) {
  1067. /*
  1068. * This message was assigned a swack resource, but no
  1069. * reserved acknowlegment is pending.
  1070. * The bug has prevented this message from setting the MMR.
  1071. */
  1072. /*
  1073. * Some message has set the MMR 'pending' bit; it might have
  1074. * been another message. Look for that message.
  1075. */
  1076. other_msg = find_another_by_swack(msg, bcp);
  1077. if (other_msg) {
  1078. /*
  1079. * There is another. Process this one but do not
  1080. * ack it.
  1081. */
  1082. bau_process_message(mdp, bcp, 0);
  1083. /*
  1084. * Let the natural processing of that other message
  1085. * acknowledge it. Don't get the processing of sw_ack's
  1086. * out of order.
  1087. */
  1088. return;
  1089. }
  1090. }
  1091. /*
  1092. * Either the MMR shows this one pending a reply or there is no
  1093. * other message using this sw_ack, so it is safe to acknowledge it.
  1094. */
  1095. bau_process_message(mdp, bcp, 1);
  1096. return;
  1097. }
  1098. /*
  1099. * The BAU message interrupt comes here. (registered by set_intr_gate)
  1100. * See entry_64.S
  1101. *
  1102. * We received a broadcast assist message.
  1103. *
  1104. * Interrupts are disabled; this interrupt could represent
  1105. * the receipt of several messages.
  1106. *
  1107. * All cores/threads on this hub get this interrupt.
  1108. * The last one to see it does the software ack.
  1109. * (the resource will not be freed until noninterruptable cpus see this
  1110. * interrupt; hardware may timeout the s/w ack and reply ERROR)
  1111. */
  1112. void uv_bau_message_interrupt(struct pt_regs *regs)
  1113. {
  1114. int count = 0;
  1115. cycles_t time_start;
  1116. struct bau_pq_entry *msg;
  1117. struct bau_control *bcp;
  1118. struct ptc_stats *stat;
  1119. struct msg_desc msgdesc;
  1120. ack_APIC_irq();
  1121. time_start = get_cycles();
  1122. bcp = &per_cpu(bau_control, smp_processor_id());
  1123. stat = bcp->statp;
  1124. msgdesc.queue_first = bcp->queue_first;
  1125. msgdesc.queue_last = bcp->queue_last;
  1126. msg = bcp->bau_msg_head;
  1127. while (msg->swack_vec) {
  1128. count++;
  1129. msgdesc.msg_slot = msg - msgdesc.queue_first;
  1130. msgdesc.msg = msg;
  1131. if (bcp->uvhub_version == 2)
  1132. process_uv2_message(&msgdesc, bcp);
  1133. else
  1134. /* no error workaround for uv1 or uv3 */
  1135. bau_process_message(&msgdesc, bcp, 1);
  1136. msg++;
  1137. if (msg > msgdesc.queue_last)
  1138. msg = msgdesc.queue_first;
  1139. bcp->bau_msg_head = msg;
  1140. }
  1141. stat->d_time += (get_cycles() - time_start);
  1142. if (!count)
  1143. stat->d_nomsg++;
  1144. else if (count > 1)
  1145. stat->d_multmsg++;
  1146. }
  1147. /*
  1148. * Each target uvhub (i.e. a uvhub that has cpu's) needs to have
  1149. * shootdown message timeouts enabled. The timeout does not cause
  1150. * an interrupt, but causes an error message to be returned to
  1151. * the sender.
  1152. */
  1153. static void __init enable_timeouts(void)
  1154. {
  1155. int uvhub;
  1156. int nuvhubs;
  1157. int pnode;
  1158. unsigned long mmr_image;
  1159. nuvhubs = uv_num_possible_blades();
  1160. for (uvhub = 0; uvhub < nuvhubs; uvhub++) {
  1161. if (!uv_blade_nr_possible_cpus(uvhub))
  1162. continue;
  1163. pnode = uv_blade_to_pnode(uvhub);
  1164. mmr_image = read_mmr_misc_control(pnode);
  1165. /*
  1166. * Set the timeout period and then lock it in, in three
  1167. * steps; captures and locks in the period.
  1168. *
  1169. * To program the period, the SOFT_ACK_MODE must be off.
  1170. */
  1171. mmr_image &= ~(1L << SOFTACK_MSHIFT);
  1172. write_mmr_misc_control(pnode, mmr_image);
  1173. /*
  1174. * Set the 4-bit period.
  1175. */
  1176. mmr_image &= ~((unsigned long)0xf << SOFTACK_PSHIFT);
  1177. mmr_image |= (SOFTACK_TIMEOUT_PERIOD << SOFTACK_PSHIFT);
  1178. write_mmr_misc_control(pnode, mmr_image);
  1179. /*
  1180. * UV1:
  1181. * Subsequent reversals of the timebase bit (3) cause an
  1182. * immediate timeout of one or all INTD resources as
  1183. * indicated in bits 2:0 (7 causes all of them to timeout).
  1184. */
  1185. mmr_image |= (1L << SOFTACK_MSHIFT);
  1186. if (is_uv2_hub()) {
  1187. /* do not touch the legacy mode bit */
  1188. /* hw bug workaround; do not use extended status */
  1189. mmr_image &= ~(1L << UV2_EXT_SHFT);
  1190. } else if (is_uv3_hub()) {
  1191. mmr_image &= ~(1L << PREFETCH_HINT_SHFT);
  1192. mmr_image |= (1L << SB_STATUS_SHFT);
  1193. }
  1194. write_mmr_misc_control(pnode, mmr_image);
  1195. }
  1196. }
  1197. static void *ptc_seq_start(struct seq_file *file, loff_t *offset)
  1198. {
  1199. if (*offset < num_possible_cpus())
  1200. return offset;
  1201. return NULL;
  1202. }
  1203. static void *ptc_seq_next(struct seq_file *file, void *data, loff_t *offset)
  1204. {
  1205. (*offset)++;
  1206. if (*offset < num_possible_cpus())
  1207. return offset;
  1208. return NULL;
  1209. }
  1210. static void ptc_seq_stop(struct seq_file *file, void *data)
  1211. {
  1212. }
  1213. /*
  1214. * Display the statistics thru /proc/sgi_uv/ptc_statistics
  1215. * 'data' points to the cpu number
  1216. * Note: see the descriptions in stat_description[].
  1217. */
  1218. static int ptc_seq_show(struct seq_file *file, void *data)
  1219. {
  1220. struct ptc_stats *stat;
  1221. struct bau_control *bcp;
  1222. int cpu;
  1223. cpu = *(loff_t *)data;
  1224. if (!cpu) {
  1225. seq_printf(file,
  1226. "# cpu bauoff sent stime self locals remotes ncpus localhub ");
  1227. seq_printf(file,
  1228. "remotehub numuvhubs numuvhubs16 numuvhubs8 ");
  1229. seq_printf(file,
  1230. "numuvhubs4 numuvhubs2 numuvhubs1 dto snacks retries ");
  1231. seq_printf(file,
  1232. "rok resetp resett giveup sto bz throt disable ");
  1233. seq_printf(file,
  1234. "enable wars warshw warwaits enters ipidis plugged ");
  1235. seq_printf(file,
  1236. "ipiover glim cong swack recv rtime all one mult ");
  1237. seq_printf(file,
  1238. "none retry canc nocan reset rcan\n");
  1239. }
  1240. if (cpu < num_possible_cpus() && cpu_online(cpu)) {
  1241. bcp = &per_cpu(bau_control, cpu);
  1242. stat = bcp->statp;
  1243. /* source side statistics */
  1244. seq_printf(file,
  1245. "cpu %d %d %ld %ld %ld %ld %ld %ld %ld %ld %ld %ld ",
  1246. cpu, bcp->nobau, stat->s_requestor,
  1247. cycles_2_us(stat->s_time),
  1248. stat->s_ntargself, stat->s_ntarglocals,
  1249. stat->s_ntargremotes, stat->s_ntargcpu,
  1250. stat->s_ntarglocaluvhub, stat->s_ntargremoteuvhub,
  1251. stat->s_ntarguvhub, stat->s_ntarguvhub16);
  1252. seq_printf(file, "%ld %ld %ld %ld %ld %ld ",
  1253. stat->s_ntarguvhub8, stat->s_ntarguvhub4,
  1254. stat->s_ntarguvhub2, stat->s_ntarguvhub1,
  1255. stat->s_dtimeout, stat->s_strongnacks);
  1256. seq_printf(file, "%ld %ld %ld %ld %ld %ld %ld %ld ",
  1257. stat->s_retry_messages, stat->s_retriesok,
  1258. stat->s_resets_plug, stat->s_resets_timeout,
  1259. stat->s_giveup, stat->s_stimeout,
  1260. stat->s_busy, stat->s_throttles);
  1261. seq_printf(file, "%ld %ld %ld %ld %ld %ld %ld %ld %ld %ld %ld ",
  1262. stat->s_bau_disabled, stat->s_bau_reenabled,
  1263. stat->s_uv2_wars, stat->s_uv2_wars_hw,
  1264. stat->s_uv2_war_waits, stat->s_enters,
  1265. stat->s_ipifordisabled, stat->s_plugged,
  1266. stat->s_overipilimit, stat->s_giveuplimit,
  1267. stat->s_congested);
  1268. /* destination side statistics */
  1269. seq_printf(file,
  1270. "%lx %ld %ld %ld %ld %ld %ld %ld %ld %ld %ld %ld\n",
  1271. read_gmmr_sw_ack(uv_cpu_to_pnode(cpu)),
  1272. stat->d_requestee, cycles_2_us(stat->d_time),
  1273. stat->d_alltlb, stat->d_onetlb, stat->d_multmsg,
  1274. stat->d_nomsg, stat->d_retries, stat->d_canceled,
  1275. stat->d_nocanceled, stat->d_resets,
  1276. stat->d_rcanceled);
  1277. }
  1278. return 0;
  1279. }
  1280. /*
  1281. * Display the tunables thru debugfs
  1282. */
  1283. static ssize_t tunables_read(struct file *file, char __user *userbuf,
  1284. size_t count, loff_t *ppos)
  1285. {
  1286. char *buf;
  1287. int ret;
  1288. buf = kasprintf(GFP_KERNEL, "%s %s %s\n%d %d %d %d %d %d %d %d %d %d\n",
  1289. "max_concur plugged_delay plugsb4reset timeoutsb4reset",
  1290. "ipi_reset_limit complete_threshold congested_response_us",
  1291. "congested_reps disabled_period giveup_limit",
  1292. max_concurr, plugged_delay, plugsb4reset,
  1293. timeoutsb4reset, ipi_reset_limit, complete_threshold,
  1294. congested_respns_us, congested_reps, disabled_period,
  1295. giveup_limit);
  1296. if (!buf)
  1297. return -ENOMEM;
  1298. ret = simple_read_from_buffer(userbuf, count, ppos, buf, strlen(buf));
  1299. kfree(buf);
  1300. return ret;
  1301. }
  1302. /*
  1303. * handle a write to /proc/sgi_uv/ptc_statistics
  1304. * -1: reset the statistics
  1305. * 0: display meaning of the statistics
  1306. */
  1307. static ssize_t ptc_proc_write(struct file *file, const char __user *user,
  1308. size_t count, loff_t *data)
  1309. {
  1310. int cpu;
  1311. int i;
  1312. int elements;
  1313. long input_arg;
  1314. char optstr[64];
  1315. struct ptc_stats *stat;
  1316. if (count == 0 || count > sizeof(optstr))
  1317. return -EINVAL;
  1318. if (copy_from_user(optstr, user, count))
  1319. return -EFAULT;
  1320. optstr[count - 1] = '\0';
  1321. if (!strcmp(optstr, "on")) {
  1322. set_bau_on();
  1323. return count;
  1324. } else if (!strcmp(optstr, "off")) {
  1325. set_bau_off();
  1326. return count;
  1327. }
  1328. if (kstrtol(optstr, 10, &input_arg) < 0) {
  1329. printk(KERN_DEBUG "%s is invalid\n", optstr);
  1330. return -EINVAL;
  1331. }
  1332. if (input_arg == 0) {
  1333. elements = ARRAY_SIZE(stat_description);
  1334. printk(KERN_DEBUG "# cpu: cpu number\n");
  1335. printk(KERN_DEBUG "Sender statistics:\n");
  1336. for (i = 0; i < elements; i++)
  1337. printk(KERN_DEBUG "%s\n", stat_description[i]);
  1338. } else if (input_arg == -1) {
  1339. for_each_present_cpu(cpu) {
  1340. stat = &per_cpu(ptcstats, cpu);
  1341. memset(stat, 0, sizeof(struct ptc_stats));
  1342. }
  1343. }
  1344. return count;
  1345. }
  1346. static int local_atoi(const char *name)
  1347. {
  1348. int val = 0;
  1349. for (;; name++) {
  1350. switch (*name) {
  1351. case '0' ... '9':
  1352. val = 10*val+(*name-'0');
  1353. break;
  1354. default:
  1355. return val;
  1356. }
  1357. }
  1358. }
  1359. /*
  1360. * Parse the values written to /sys/kernel/debug/sgi_uv/bau_tunables.
  1361. * Zero values reset them to defaults.
  1362. */
  1363. static int parse_tunables_write(struct bau_control *bcp, char *instr,
  1364. int count)
  1365. {
  1366. char *p;
  1367. char *q;
  1368. int cnt = 0;
  1369. int val;
  1370. int e = ARRAY_SIZE(tunables);
  1371. p = instr + strspn(instr, WHITESPACE);
  1372. q = p;
  1373. for (; *p; p = q + strspn(q, WHITESPACE)) {
  1374. q = p + strcspn(p, WHITESPACE);
  1375. cnt++;
  1376. if (q == p)
  1377. break;
  1378. }
  1379. if (cnt != e) {
  1380. printk(KERN_INFO "bau tunable error: should be %d values\n", e);
  1381. return -EINVAL;
  1382. }
  1383. p = instr + strspn(instr, WHITESPACE);
  1384. q = p;
  1385. for (cnt = 0; *p; p = q + strspn(q, WHITESPACE), cnt++) {
  1386. q = p + strcspn(p, WHITESPACE);
  1387. val = local_atoi(p);
  1388. switch (cnt) {
  1389. case 0:
  1390. if (val == 0) {
  1391. max_concurr = MAX_BAU_CONCURRENT;
  1392. max_concurr_const = MAX_BAU_CONCURRENT;
  1393. continue;
  1394. }
  1395. if (val < 1 || val > bcp->cpus_in_uvhub) {
  1396. printk(KERN_DEBUG
  1397. "Error: BAU max concurrent %d is invalid\n",
  1398. val);
  1399. return -EINVAL;
  1400. }
  1401. max_concurr = val;
  1402. max_concurr_const = val;
  1403. continue;
  1404. default:
  1405. if (val == 0)
  1406. *tunables[cnt].tunp = tunables[cnt].deflt;
  1407. else
  1408. *tunables[cnt].tunp = val;
  1409. continue;
  1410. }
  1411. if (q == p)
  1412. break;
  1413. }
  1414. return 0;
  1415. }
  1416. /*
  1417. * Handle a write to debugfs. (/sys/kernel/debug/sgi_uv/bau_tunables)
  1418. */
  1419. static ssize_t tunables_write(struct file *file, const char __user *user,
  1420. size_t count, loff_t *data)
  1421. {
  1422. int cpu;
  1423. int ret;
  1424. char instr[100];
  1425. struct bau_control *bcp;
  1426. if (count == 0 || count > sizeof(instr)-1)
  1427. return -EINVAL;
  1428. if (copy_from_user(instr, user, count))
  1429. return -EFAULT;
  1430. instr[count] = '\0';
  1431. cpu = get_cpu();
  1432. bcp = &per_cpu(bau_control, cpu);
  1433. ret = parse_tunables_write(bcp, instr, count);
  1434. put_cpu();
  1435. if (ret)
  1436. return ret;
  1437. for_each_present_cpu(cpu) {
  1438. bcp = &per_cpu(bau_control, cpu);
  1439. bcp->max_concurr = max_concurr;
  1440. bcp->max_concurr_const = max_concurr;
  1441. bcp->plugged_delay = plugged_delay;
  1442. bcp->plugsb4reset = plugsb4reset;
  1443. bcp->timeoutsb4reset = timeoutsb4reset;
  1444. bcp->ipi_reset_limit = ipi_reset_limit;
  1445. bcp->complete_threshold = complete_threshold;
  1446. bcp->cong_response_us = congested_respns_us;
  1447. bcp->cong_reps = congested_reps;
  1448. bcp->disabled_period = sec_2_cycles(disabled_period);
  1449. bcp->giveup_limit = giveup_limit;
  1450. }
  1451. return count;
  1452. }
  1453. static const struct seq_operations uv_ptc_seq_ops = {
  1454. .start = ptc_seq_start,
  1455. .next = ptc_seq_next,
  1456. .stop = ptc_seq_stop,
  1457. .show = ptc_seq_show
  1458. };
  1459. static int ptc_proc_open(struct inode *inode, struct file *file)
  1460. {
  1461. return seq_open(file, &uv_ptc_seq_ops);
  1462. }
  1463. static int tunables_open(struct inode *inode, struct file *file)
  1464. {
  1465. return 0;
  1466. }
  1467. static const struct file_operations proc_uv_ptc_operations = {
  1468. .open = ptc_proc_open,
  1469. .read = seq_read,
  1470. .write = ptc_proc_write,
  1471. .llseek = seq_lseek,
  1472. .release = seq_release,
  1473. };
  1474. static const struct file_operations tunables_fops = {
  1475. .open = tunables_open,
  1476. .read = tunables_read,
  1477. .write = tunables_write,
  1478. .llseek = default_llseek,
  1479. };
  1480. static int __init uv_ptc_init(void)
  1481. {
  1482. struct proc_dir_entry *proc_uv_ptc;
  1483. if (!is_uv_system())
  1484. return 0;
  1485. proc_uv_ptc = proc_create(UV_PTC_BASENAME, 0444, NULL,
  1486. &proc_uv_ptc_operations);
  1487. if (!proc_uv_ptc) {
  1488. printk(KERN_ERR "unable to create %s proc entry\n",
  1489. UV_PTC_BASENAME);
  1490. return -EINVAL;
  1491. }
  1492. tunables_dir = debugfs_create_dir(UV_BAU_TUNABLES_DIR, NULL);
  1493. if (!tunables_dir) {
  1494. printk(KERN_ERR "unable to create debugfs directory %s\n",
  1495. UV_BAU_TUNABLES_DIR);
  1496. return -EINVAL;
  1497. }
  1498. tunables_file = debugfs_create_file(UV_BAU_TUNABLES_FILE, 0600,
  1499. tunables_dir, NULL, &tunables_fops);
  1500. if (!tunables_file) {
  1501. printk(KERN_ERR "unable to create debugfs file %s\n",
  1502. UV_BAU_TUNABLES_FILE);
  1503. return -EINVAL;
  1504. }
  1505. return 0;
  1506. }
  1507. /*
  1508. * Initialize the sending side's sending buffers.
  1509. */
  1510. static void activation_descriptor_init(int node, int pnode, int base_pnode)
  1511. {
  1512. int i;
  1513. int cpu;
  1514. int uv1 = 0;
  1515. unsigned long gpa;
  1516. unsigned long m;
  1517. unsigned long n;
  1518. size_t dsize;
  1519. struct bau_desc *bau_desc;
  1520. struct bau_desc *bd2;
  1521. struct uv1_bau_msg_header *uv1_hdr;
  1522. struct uv2_3_bau_msg_header *uv2_3_hdr;
  1523. struct bau_control *bcp;
  1524. /*
  1525. * each bau_desc is 64 bytes; there are 8 (ITEMS_PER_DESC)
  1526. * per cpu; and one per cpu on the uvhub (ADP_SZ)
  1527. */
  1528. dsize = sizeof(struct bau_desc) * ADP_SZ * ITEMS_PER_DESC;
  1529. bau_desc = kmalloc_node(dsize, GFP_KERNEL, node);
  1530. BUG_ON(!bau_desc);
  1531. gpa = uv_gpa(bau_desc);
  1532. n = uv_gpa_to_gnode(gpa);
  1533. m = uv_gpa_to_offset(gpa);
  1534. if (is_uv1_hub())
  1535. uv1 = 1;
  1536. /* the 14-bit pnode */
  1537. write_mmr_descriptor_base(pnode, (n << UV_DESC_PSHIFT | m));
  1538. /*
  1539. * Initializing all 8 (ITEMS_PER_DESC) descriptors for each
  1540. * cpu even though we only use the first one; one descriptor can
  1541. * describe a broadcast to 256 uv hubs.
  1542. */
  1543. for (i = 0, bd2 = bau_desc; i < (ADP_SZ * ITEMS_PER_DESC); i++, bd2++) {
  1544. memset(bd2, 0, sizeof(struct bau_desc));
  1545. if (uv1) {
  1546. uv1_hdr = &bd2->header.uv1_hdr;
  1547. uv1_hdr->swack_flag = 1;
  1548. /*
  1549. * The base_dest_nasid set in the message header
  1550. * is the nasid of the first uvhub in the partition.
  1551. * The bit map will indicate destination pnode numbers
  1552. * relative to that base. They may not be consecutive
  1553. * if nasid striding is being used.
  1554. */
  1555. uv1_hdr->base_dest_nasid =
  1556. UV_PNODE_TO_NASID(base_pnode);
  1557. uv1_hdr->dest_subnodeid = UV_LB_SUBNODEID;
  1558. uv1_hdr->command = UV_NET_ENDPOINT_INTD;
  1559. uv1_hdr->int_both = 1;
  1560. /*
  1561. * all others need to be set to zero:
  1562. * fairness chaining multilevel count replied_to
  1563. */
  1564. } else {
  1565. /*
  1566. * BIOS uses legacy mode, but uv2 and uv3 hardware always
  1567. * uses native mode for selective broadcasts.
  1568. */
  1569. uv2_3_hdr = &bd2->header.uv2_3_hdr;
  1570. uv2_3_hdr->swack_flag = 1;
  1571. uv2_3_hdr->base_dest_nasid =
  1572. UV_PNODE_TO_NASID(base_pnode);
  1573. uv2_3_hdr->dest_subnodeid = UV_LB_SUBNODEID;
  1574. uv2_3_hdr->command = UV_NET_ENDPOINT_INTD;
  1575. }
  1576. }
  1577. for_each_present_cpu(cpu) {
  1578. if (pnode != uv_blade_to_pnode(uv_cpu_to_blade_id(cpu)))
  1579. continue;
  1580. bcp = &per_cpu(bau_control, cpu);
  1581. bcp->descriptor_base = bau_desc;
  1582. }
  1583. }
  1584. /*
  1585. * initialize the destination side's receiving buffers
  1586. * entered for each uvhub in the partition
  1587. * - node is first node (kernel memory notion) on the uvhub
  1588. * - pnode is the uvhub's physical identifier
  1589. */
  1590. static void pq_init(int node, int pnode)
  1591. {
  1592. int cpu;
  1593. size_t plsize;
  1594. char *cp;
  1595. void *vp;
  1596. unsigned long pn;
  1597. unsigned long first;
  1598. unsigned long pn_first;
  1599. unsigned long last;
  1600. struct bau_pq_entry *pqp;
  1601. struct bau_control *bcp;
  1602. plsize = (DEST_Q_SIZE + 1) * sizeof(struct bau_pq_entry);
  1603. vp = kmalloc_node(plsize, GFP_KERNEL, node);
  1604. pqp = (struct bau_pq_entry *)vp;
  1605. BUG_ON(!pqp);
  1606. cp = (char *)pqp + 31;
  1607. pqp = (struct bau_pq_entry *)(((unsigned long)cp >> 5) << 5);
  1608. for_each_present_cpu(cpu) {
  1609. if (pnode != uv_cpu_to_pnode(cpu))
  1610. continue;
  1611. /* for every cpu on this pnode: */
  1612. bcp = &per_cpu(bau_control, cpu);
  1613. bcp->queue_first = pqp;
  1614. bcp->bau_msg_head = pqp;
  1615. bcp->queue_last = pqp + (DEST_Q_SIZE - 1);
  1616. }
  1617. /*
  1618. * need the gnode of where the memory was really allocated
  1619. */
  1620. pn = uv_gpa_to_gnode(uv_gpa(pqp));
  1621. first = uv_physnodeaddr(pqp);
  1622. pn_first = ((unsigned long)pn << UV_PAYLOADQ_PNODE_SHIFT) | first;
  1623. last = uv_physnodeaddr(pqp + (DEST_Q_SIZE - 1));
  1624. write_mmr_payload_first(pnode, pn_first);
  1625. write_mmr_payload_tail(pnode, first);
  1626. write_mmr_payload_last(pnode, last);
  1627. write_gmmr_sw_ack(pnode, 0xffffUL);
  1628. /* in effect, all msg_type's are set to MSG_NOOP */
  1629. memset(pqp, 0, sizeof(struct bau_pq_entry) * DEST_Q_SIZE);
  1630. }
  1631. /*
  1632. * Initialization of each UV hub's structures
  1633. */
  1634. static void __init init_uvhub(int uvhub, int vector, int base_pnode)
  1635. {
  1636. int node;
  1637. int pnode;
  1638. unsigned long apicid;
  1639. node = uvhub_to_first_node(uvhub);
  1640. pnode = uv_blade_to_pnode(uvhub);
  1641. activation_descriptor_init(node, pnode, base_pnode);
  1642. pq_init(node, pnode);
  1643. /*
  1644. * The below initialization can't be in firmware because the
  1645. * messaging IRQ will be determined by the OS.
  1646. */
  1647. apicid = uvhub_to_first_apicid(uvhub) | uv_apicid_hibits;
  1648. write_mmr_data_config(pnode, ((apicid << 32) | vector));
  1649. }
  1650. /*
  1651. * We will set BAU_MISC_CONTROL with a timeout period.
  1652. * But the BIOS has set UVH_AGING_PRESCALE_SEL and UVH_TRANSACTION_TIMEOUT.
  1653. * So the destination timeout period has to be calculated from them.
  1654. */
  1655. static int calculate_destination_timeout(void)
  1656. {
  1657. unsigned long mmr_image;
  1658. int mult1;
  1659. int mult2;
  1660. int index;
  1661. int base;
  1662. int ret;
  1663. unsigned long ts_ns;
  1664. if (is_uv1_hub()) {
  1665. mult1 = SOFTACK_TIMEOUT_PERIOD & BAU_MISC_CONTROL_MULT_MASK;
  1666. mmr_image = uv_read_local_mmr(UVH_AGING_PRESCALE_SEL);
  1667. index = (mmr_image >> BAU_URGENCY_7_SHIFT) & BAU_URGENCY_7_MASK;
  1668. mmr_image = uv_read_local_mmr(UVH_TRANSACTION_TIMEOUT);
  1669. mult2 = (mmr_image >> BAU_TRANS_SHIFT) & BAU_TRANS_MASK;
  1670. ts_ns = timeout_base_ns[index];
  1671. ts_ns *= (mult1 * mult2);
  1672. ret = ts_ns / 1000;
  1673. } else {
  1674. /* same destination timeout for uv2 and uv3 */
  1675. /* 4 bits 0/1 for 10/80us base, 3 bits of multiplier */
  1676. mmr_image = uv_read_local_mmr(UVH_LB_BAU_MISC_CONTROL);
  1677. mmr_image = (mmr_image & UV_SA_MASK) >> UV_SA_SHFT;
  1678. if (mmr_image & (1L << UV2_ACK_UNITS_SHFT))
  1679. base = 80;
  1680. else
  1681. base = 10;
  1682. mult1 = mmr_image & UV2_ACK_MASK;
  1683. ret = mult1 * base;
  1684. }
  1685. return ret;
  1686. }
  1687. static void __init init_per_cpu_tunables(void)
  1688. {
  1689. int cpu;
  1690. struct bau_control *bcp;
  1691. for_each_present_cpu(cpu) {
  1692. bcp = &per_cpu(bau_control, cpu);
  1693. bcp->baudisabled = 0;
  1694. if (nobau)
  1695. bcp->nobau = 1;
  1696. bcp->statp = &per_cpu(ptcstats, cpu);
  1697. /* time interval to catch a hardware stay-busy bug */
  1698. bcp->timeout_interval = usec_2_cycles(2*timeout_us);
  1699. bcp->max_concurr = max_concurr;
  1700. bcp->max_concurr_const = max_concurr;
  1701. bcp->plugged_delay = plugged_delay;
  1702. bcp->plugsb4reset = plugsb4reset;
  1703. bcp->timeoutsb4reset = timeoutsb4reset;
  1704. bcp->ipi_reset_limit = ipi_reset_limit;
  1705. bcp->complete_threshold = complete_threshold;
  1706. bcp->cong_response_us = congested_respns_us;
  1707. bcp->cong_reps = congested_reps;
  1708. bcp->disabled_period = sec_2_cycles(disabled_period);
  1709. bcp->giveup_limit = giveup_limit;
  1710. spin_lock_init(&bcp->queue_lock);
  1711. spin_lock_init(&bcp->uvhub_lock);
  1712. spin_lock_init(&bcp->disable_lock);
  1713. }
  1714. }
  1715. /*
  1716. * Scan all cpus to collect blade and socket summaries.
  1717. */
  1718. static int __init get_cpu_topology(int base_pnode,
  1719. struct uvhub_desc *uvhub_descs,
  1720. unsigned char *uvhub_mask)
  1721. {
  1722. int cpu;
  1723. int pnode;
  1724. int uvhub;
  1725. int socket;
  1726. struct bau_control *bcp;
  1727. struct uvhub_desc *bdp;
  1728. struct socket_desc *sdp;
  1729. for_each_present_cpu(cpu) {
  1730. bcp = &per_cpu(bau_control, cpu);
  1731. memset(bcp, 0, sizeof(struct bau_control));
  1732. pnode = uv_cpu_hub_info(cpu)->pnode;
  1733. if ((pnode - base_pnode) >= UV_DISTRIBUTION_SIZE) {
  1734. printk(KERN_EMERG
  1735. "cpu %d pnode %d-%d beyond %d; BAU disabled\n",
  1736. cpu, pnode, base_pnode, UV_DISTRIBUTION_SIZE);
  1737. return 1;
  1738. }
  1739. bcp->osnode = cpu_to_node(cpu);
  1740. bcp->partition_base_pnode = base_pnode;
  1741. uvhub = uv_cpu_hub_info(cpu)->numa_blade_id;
  1742. *(uvhub_mask + (uvhub/8)) |= (1 << (uvhub%8));
  1743. bdp = &uvhub_descs[uvhub];
  1744. bdp->num_cpus++;
  1745. bdp->uvhub = uvhub;
  1746. bdp->pnode = pnode;
  1747. /* kludge: 'assuming' one node per socket, and assuming that
  1748. disabling a socket just leaves a gap in node numbers */
  1749. socket = bcp->osnode & 1;
  1750. bdp->socket_mask |= (1 << socket);
  1751. sdp = &bdp->socket[socket];
  1752. sdp->cpu_number[sdp->num_cpus] = cpu;
  1753. sdp->num_cpus++;
  1754. if (sdp->num_cpus > MAX_CPUS_PER_SOCKET) {
  1755. printk(KERN_EMERG "%d cpus per socket invalid\n",
  1756. sdp->num_cpus);
  1757. return 1;
  1758. }
  1759. }
  1760. return 0;
  1761. }
  1762. /*
  1763. * Each socket is to get a local array of pnodes/hubs.
  1764. */
  1765. static void make_per_cpu_thp(struct bau_control *smaster)
  1766. {
  1767. int cpu;
  1768. size_t hpsz = sizeof(struct hub_and_pnode) * num_possible_cpus();
  1769. smaster->thp = kmalloc_node(hpsz, GFP_KERNEL, smaster->osnode);
  1770. memset(smaster->thp, 0, hpsz);
  1771. for_each_present_cpu(cpu) {
  1772. smaster->thp[cpu].pnode = uv_cpu_hub_info(cpu)->pnode;
  1773. smaster->thp[cpu].uvhub = uv_cpu_hub_info(cpu)->numa_blade_id;
  1774. }
  1775. }
  1776. /*
  1777. * Each uvhub is to get a local cpumask.
  1778. */
  1779. static void make_per_hub_cpumask(struct bau_control *hmaster)
  1780. {
  1781. int sz = sizeof(cpumask_t);
  1782. hmaster->cpumask = kzalloc_node(sz, GFP_KERNEL, hmaster->osnode);
  1783. }
  1784. /*
  1785. * Initialize all the per_cpu information for the cpu's on a given socket,
  1786. * given what has been gathered into the socket_desc struct.
  1787. * And reports the chosen hub and socket masters back to the caller.
  1788. */
  1789. static int scan_sock(struct socket_desc *sdp, struct uvhub_desc *bdp,
  1790. struct bau_control **smasterp,
  1791. struct bau_control **hmasterp)
  1792. {
  1793. int i;
  1794. int cpu;
  1795. struct bau_control *bcp;
  1796. for (i = 0; i < sdp->num_cpus; i++) {
  1797. cpu = sdp->cpu_number[i];
  1798. bcp = &per_cpu(bau_control, cpu);
  1799. bcp->cpu = cpu;
  1800. if (i == 0) {
  1801. *smasterp = bcp;
  1802. if (!(*hmasterp))
  1803. *hmasterp = bcp;
  1804. }
  1805. bcp->cpus_in_uvhub = bdp->num_cpus;
  1806. bcp->cpus_in_socket = sdp->num_cpus;
  1807. bcp->socket_master = *smasterp;
  1808. bcp->uvhub = bdp->uvhub;
  1809. if (is_uv1_hub())
  1810. bcp->uvhub_version = 1;
  1811. else if (is_uv2_hub())
  1812. bcp->uvhub_version = 2;
  1813. else if (is_uv3_hub())
  1814. bcp->uvhub_version = 3;
  1815. else {
  1816. printk(KERN_EMERG "uvhub version not 1, 2 or 3\n");
  1817. return 1;
  1818. }
  1819. bcp->uvhub_master = *hmasterp;
  1820. bcp->uvhub_cpu = uv_cpu_hub_info(cpu)->blade_processor_id;
  1821. if (bcp->uvhub_cpu >= MAX_CPUS_PER_UVHUB) {
  1822. printk(KERN_EMERG "%d cpus per uvhub invalid\n",
  1823. bcp->uvhub_cpu);
  1824. return 1;
  1825. }
  1826. }
  1827. return 0;
  1828. }
  1829. /*
  1830. * Summarize the blade and socket topology into the per_cpu structures.
  1831. */
  1832. static int __init summarize_uvhub_sockets(int nuvhubs,
  1833. struct uvhub_desc *uvhub_descs,
  1834. unsigned char *uvhub_mask)
  1835. {
  1836. int socket;
  1837. int uvhub;
  1838. unsigned short socket_mask;
  1839. for (uvhub = 0; uvhub < nuvhubs; uvhub++) {
  1840. struct uvhub_desc *bdp;
  1841. struct bau_control *smaster = NULL;
  1842. struct bau_control *hmaster = NULL;
  1843. if (!(*(uvhub_mask + (uvhub/8)) & (1 << (uvhub%8))))
  1844. continue;
  1845. bdp = &uvhub_descs[uvhub];
  1846. socket_mask = bdp->socket_mask;
  1847. socket = 0;
  1848. while (socket_mask) {
  1849. struct socket_desc *sdp;
  1850. if ((socket_mask & 1)) {
  1851. sdp = &bdp->socket[socket];
  1852. if (scan_sock(sdp, bdp, &smaster, &hmaster))
  1853. return 1;
  1854. make_per_cpu_thp(smaster);
  1855. }
  1856. socket++;
  1857. socket_mask = (socket_mask >> 1);
  1858. }
  1859. make_per_hub_cpumask(hmaster);
  1860. }
  1861. return 0;
  1862. }
  1863. /*
  1864. * initialize the bau_control structure for each cpu
  1865. */
  1866. static int __init init_per_cpu(int nuvhubs, int base_part_pnode)
  1867. {
  1868. unsigned char *uvhub_mask;
  1869. void *vp;
  1870. struct uvhub_desc *uvhub_descs;
  1871. timeout_us = calculate_destination_timeout();
  1872. vp = kmalloc(nuvhubs * sizeof(struct uvhub_desc), GFP_KERNEL);
  1873. uvhub_descs = (struct uvhub_desc *)vp;
  1874. memset(uvhub_descs, 0, nuvhubs * sizeof(struct uvhub_desc));
  1875. uvhub_mask = kzalloc((nuvhubs+7)/8, GFP_KERNEL);
  1876. if (get_cpu_topology(base_part_pnode, uvhub_descs, uvhub_mask))
  1877. goto fail;
  1878. if (summarize_uvhub_sockets(nuvhubs, uvhub_descs, uvhub_mask))
  1879. goto fail;
  1880. kfree(uvhub_descs);
  1881. kfree(uvhub_mask);
  1882. init_per_cpu_tunables();
  1883. return 0;
  1884. fail:
  1885. kfree(uvhub_descs);
  1886. kfree(uvhub_mask);
  1887. return 1;
  1888. }
  1889. /*
  1890. * Initialization of BAU-related structures
  1891. */
  1892. static int __init uv_bau_init(void)
  1893. {
  1894. int uvhub;
  1895. int pnode;
  1896. int nuvhubs;
  1897. int cur_cpu;
  1898. int cpus;
  1899. int vector;
  1900. cpumask_var_t *mask;
  1901. if (!is_uv_system())
  1902. return 0;
  1903. for_each_possible_cpu(cur_cpu) {
  1904. mask = &per_cpu(uv_flush_tlb_mask, cur_cpu);
  1905. zalloc_cpumask_var_node(mask, GFP_KERNEL, cpu_to_node(cur_cpu));
  1906. }
  1907. nuvhubs = uv_num_possible_blades();
  1908. congested_cycles = usec_2_cycles(congested_respns_us);
  1909. uv_base_pnode = 0x7fffffff;
  1910. for (uvhub = 0; uvhub < nuvhubs; uvhub++) {
  1911. cpus = uv_blade_nr_possible_cpus(uvhub);
  1912. if (cpus && (uv_blade_to_pnode(uvhub) < uv_base_pnode))
  1913. uv_base_pnode = uv_blade_to_pnode(uvhub);
  1914. }
  1915. enable_timeouts();
  1916. if (init_per_cpu(nuvhubs, uv_base_pnode)) {
  1917. set_bau_off();
  1918. nobau_perm = 1;
  1919. return 0;
  1920. }
  1921. vector = UV_BAU_MESSAGE;
  1922. for_each_possible_blade(uvhub) {
  1923. if (uv_blade_nr_possible_cpus(uvhub))
  1924. init_uvhub(uvhub, vector, uv_base_pnode);
  1925. }
  1926. alloc_intr_gate(vector, uv_bau_message_intr1);
  1927. for_each_possible_blade(uvhub) {
  1928. if (uv_blade_nr_possible_cpus(uvhub)) {
  1929. unsigned long val;
  1930. unsigned long mmr;
  1931. pnode = uv_blade_to_pnode(uvhub);
  1932. /* INIT the bau */
  1933. val = 1L << 63;
  1934. write_gmmr_activation(pnode, val);
  1935. mmr = 1; /* should be 1 to broadcast to both sockets */
  1936. if (!is_uv1_hub())
  1937. write_mmr_data_broadcast(pnode, mmr);
  1938. }
  1939. }
  1940. return 0;
  1941. }
  1942. core_initcall(uv_bau_init);
  1943. fs_initcall(uv_ptc_init);