mpic_pasemi_msi.c 4.3 KB

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  1. /*
  2. * Copyright 2007, Olof Johansson, PA Semi
  3. *
  4. * Based on arch/powerpc/sysdev/mpic_u3msi.c:
  5. *
  6. * Copyright 2006, Segher Boessenkool, IBM Corporation.
  7. * Copyright 2006-2007, Michael Ellerman, IBM Corporation.
  8. *
  9. * This program is free software; you can redistribute it and/or
  10. * modify it under the terms of the GNU General Public License
  11. * as published by the Free Software Foundation; version 2 of the
  12. * License.
  13. *
  14. */
  15. #undef DEBUG
  16. #include <linux/irq.h>
  17. #include <linux/bootmem.h>
  18. #include <linux/msi.h>
  19. #include <asm/mpic.h>
  20. #include <asm/prom.h>
  21. #include <asm/hw_irq.h>
  22. #include <asm/ppc-pci.h>
  23. #include <asm/msi_bitmap.h>
  24. #include "mpic.h"
  25. /* Allocate 16 interrupts per device, to give an alignment of 16,
  26. * since that's the size of the grouping w.r.t. affinity. If someone
  27. * needs more than 32 MSI's down the road we'll have to rethink this,
  28. * but it should be OK for now.
  29. */
  30. #define ALLOC_CHUNK 16
  31. #define PASEMI_MSI_ADDR 0xfc080000
  32. /* A bit ugly, can we get this from the pci_dev somehow? */
  33. static struct mpic *msi_mpic;
  34. static void mpic_pasemi_msi_mask_irq(struct irq_data *data)
  35. {
  36. pr_debug("mpic_pasemi_msi_mask_irq %d\n", data->irq);
  37. mask_msi_irq(data);
  38. mpic_mask_irq(data);
  39. }
  40. static void mpic_pasemi_msi_unmask_irq(struct irq_data *data)
  41. {
  42. pr_debug("mpic_pasemi_msi_unmask_irq %d\n", data->irq);
  43. mpic_unmask_irq(data);
  44. unmask_msi_irq(data);
  45. }
  46. static struct irq_chip mpic_pasemi_msi_chip = {
  47. .irq_shutdown = mpic_pasemi_msi_mask_irq,
  48. .irq_mask = mpic_pasemi_msi_mask_irq,
  49. .irq_unmask = mpic_pasemi_msi_unmask_irq,
  50. .irq_eoi = mpic_end_irq,
  51. .irq_set_type = mpic_set_irq_type,
  52. .irq_set_affinity = mpic_set_affinity,
  53. .name = "PASEMI-MSI",
  54. };
  55. static void pasemi_msi_teardown_msi_irqs(struct pci_dev *pdev)
  56. {
  57. struct msi_desc *entry;
  58. pr_debug("pasemi_msi_teardown_msi_irqs, pdev %p\n", pdev);
  59. list_for_each_entry(entry, &pdev->msi_list, list) {
  60. if (entry->irq == NO_IRQ)
  61. continue;
  62. irq_set_msi_desc(entry->irq, NULL);
  63. msi_bitmap_free_hwirqs(&msi_mpic->msi_bitmap,
  64. virq_to_hw(entry->irq), ALLOC_CHUNK);
  65. irq_dispose_mapping(entry->irq);
  66. }
  67. return;
  68. }
  69. static int pasemi_msi_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type)
  70. {
  71. unsigned int virq;
  72. struct msi_desc *entry;
  73. struct msi_msg msg;
  74. int hwirq;
  75. if (type == PCI_CAP_ID_MSIX)
  76. pr_debug("pasemi_msi: MSI-X untested, trying anyway\n");
  77. pr_debug("pasemi_msi_setup_msi_irqs, pdev %p nvec %d type %d\n",
  78. pdev, nvec, type);
  79. msg.address_hi = 0;
  80. msg.address_lo = PASEMI_MSI_ADDR;
  81. list_for_each_entry(entry, &pdev->msi_list, list) {
  82. /* Allocate 16 interrupts for now, since that's the grouping for
  83. * affinity. This can be changed later if it turns out 32 is too
  84. * few MSIs for someone, but restrictions will apply to how the
  85. * sources can be changed independently.
  86. */
  87. hwirq = msi_bitmap_alloc_hwirqs(&msi_mpic->msi_bitmap,
  88. ALLOC_CHUNK);
  89. if (hwirq < 0) {
  90. pr_debug("pasemi_msi: failed allocating hwirq\n");
  91. return hwirq;
  92. }
  93. virq = irq_create_mapping(msi_mpic->irqhost, hwirq);
  94. if (virq == NO_IRQ) {
  95. pr_debug("pasemi_msi: failed mapping hwirq 0x%x\n",
  96. hwirq);
  97. msi_bitmap_free_hwirqs(&msi_mpic->msi_bitmap, hwirq,
  98. ALLOC_CHUNK);
  99. return -ENOSPC;
  100. }
  101. /* Vector on MSI is really an offset, the hardware adds
  102. * it to the value written at the magic address. So set
  103. * it to 0 to remain sane.
  104. */
  105. mpic_set_vector(virq, 0);
  106. irq_set_msi_desc(virq, entry);
  107. irq_set_chip(virq, &mpic_pasemi_msi_chip);
  108. irq_set_irq_type(virq, IRQ_TYPE_EDGE_RISING);
  109. pr_debug("pasemi_msi: allocated virq 0x%x (hw 0x%x) " \
  110. "addr 0x%x\n", virq, hwirq, msg.address_lo);
  111. /* Likewise, the device writes [0...511] into the target
  112. * register to generate MSI [512...1023]
  113. */
  114. msg.data = hwirq-0x200;
  115. write_msi_msg(virq, &msg);
  116. }
  117. return 0;
  118. }
  119. int mpic_pasemi_msi_init(struct mpic *mpic)
  120. {
  121. int rc;
  122. if (!mpic->irqhost->of_node ||
  123. !of_device_is_compatible(mpic->irqhost->of_node,
  124. "pasemi,pwrficient-openpic"))
  125. return -ENODEV;
  126. rc = mpic_msi_init_allocator(mpic);
  127. if (rc) {
  128. pr_debug("pasemi_msi: Error allocating bitmap!\n");
  129. return rc;
  130. }
  131. pr_debug("pasemi_msi: Registering PA Semi MPIC MSI callbacks\n");
  132. msi_mpic = mpic;
  133. WARN_ON(ppc_md.setup_msi_irqs);
  134. ppc_md.setup_msi_irqs = pasemi_msi_setup_msi_irqs;
  135. ppc_md.teardown_msi_irqs = pasemi_msi_teardown_msi_irqs;
  136. return 0;
  137. }