uncompress.h 4.6 KB

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  1. /*
  2. * arch/arm/mach-at91/include/mach/uncompress.h
  3. *
  4. * Copyright (C) 2003 SAN People
  5. * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License as published by
  9. * the Free Software Foundation; either version 2 of the License, or
  10. * (at your option) any later version.
  11. *
  12. * This program is distributed in the hope that it will be useful,
  13. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15. * GNU General Public License for more details.
  16. *
  17. * You should have received a copy of the GNU General Public License
  18. * along with this program; if not, write to the Free Software
  19. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  20. */
  21. #ifndef __ASM_ARCH_UNCOMPRESS_H
  22. #define __ASM_ARCH_UNCOMPRESS_H
  23. #include <linux/io.h>
  24. #include <linux/atmel_serial.h>
  25. #include <mach/hardware.h>
  26. #include <mach/at91_dbgu.h>
  27. #include <mach/cpu.h>
  28. void __iomem *at91_uart;
  29. #if !defined(CONFIG_ARCH_AT91X40)
  30. static const u32 uarts_rm9200[] = {
  31. AT91_BASE_DBGU0,
  32. AT91RM9200_BASE_US0,
  33. AT91RM9200_BASE_US1,
  34. AT91RM9200_BASE_US2,
  35. AT91RM9200_BASE_US3,
  36. 0,
  37. };
  38. static const u32 uarts_sam9260[] = {
  39. AT91_BASE_DBGU0,
  40. AT91SAM9260_BASE_US0,
  41. AT91SAM9260_BASE_US1,
  42. AT91SAM9260_BASE_US2,
  43. AT91SAM9260_BASE_US3,
  44. AT91SAM9260_BASE_US4,
  45. AT91SAM9260_BASE_US5,
  46. 0,
  47. };
  48. static const u32 uarts_sam9261[] = {
  49. AT91_BASE_DBGU0,
  50. AT91SAM9261_BASE_US0,
  51. AT91SAM9261_BASE_US1,
  52. AT91SAM9261_BASE_US2,
  53. 0,
  54. };
  55. static const u32 uarts_sam9263[] = {
  56. AT91_BASE_DBGU1,
  57. AT91SAM9263_BASE_US0,
  58. AT91SAM9263_BASE_US1,
  59. AT91SAM9263_BASE_US2,
  60. 0,
  61. };
  62. static const u32 uarts_sam9g45[] = {
  63. AT91_BASE_DBGU1,
  64. AT91SAM9G45_BASE_US0,
  65. AT91SAM9G45_BASE_US1,
  66. AT91SAM9G45_BASE_US2,
  67. AT91SAM9G45_BASE_US3,
  68. 0,
  69. };
  70. static const u32 uarts_sam9rl[] = {
  71. AT91_BASE_DBGU0,
  72. AT91SAM9RL_BASE_US0,
  73. AT91SAM9RL_BASE_US1,
  74. AT91SAM9RL_BASE_US2,
  75. AT91SAM9RL_BASE_US3,
  76. 0,
  77. };
  78. static const u32 uarts_sam9x5[] = {
  79. AT91_BASE_DBGU0,
  80. AT91SAM9X5_BASE_USART0,
  81. AT91SAM9X5_BASE_USART1,
  82. AT91SAM9X5_BASE_USART2,
  83. 0,
  84. };
  85. static const u32 uarts_sama5d3[] = {
  86. AT91_BASE_DBGU1,
  87. SAMA5D3_BASE_USART0,
  88. SAMA5D3_BASE_USART1,
  89. SAMA5D3_BASE_USART2,
  90. SAMA5D3_BASE_USART3,
  91. 0,
  92. };
  93. static const u32 uarts_sama5d4[] = {
  94. AT91_BASE_DBGU2,
  95. SAMA5D4_BASE_USART3,
  96. 0,
  97. };
  98. static inline const u32* decomp_soc_detect(void __iomem *dbgu_base)
  99. {
  100. u32 cidr, socid;
  101. cidr = __raw_readl(dbgu_base + AT91_DBGU_CIDR);
  102. socid = cidr & ~AT91_CIDR_VERSION;
  103. switch (socid) {
  104. case ARCH_ID_AT91RM9200:
  105. return uarts_rm9200;
  106. case ARCH_ID_AT91SAM9G20:
  107. case ARCH_ID_AT91SAM9260:
  108. return uarts_sam9260;
  109. case ARCH_ID_AT91SAM9261:
  110. return uarts_sam9261;
  111. case ARCH_ID_AT91SAM9263:
  112. return uarts_sam9263;
  113. case ARCH_ID_AT91SAM9G45:
  114. return uarts_sam9g45;
  115. case ARCH_ID_AT91SAM9RL64:
  116. return uarts_sam9rl;
  117. case ARCH_ID_AT91SAM9N12:
  118. case ARCH_ID_AT91SAM9X5:
  119. return uarts_sam9x5;
  120. case ARCH_ID_SAMA5:
  121. cidr = __raw_readl(dbgu_base + AT91_DBGU_EXID);
  122. if (cidr & ARCH_EXID_SAMA5D3)
  123. return uarts_sama5d3;
  124. else if (cidr & ARCH_EXID_SAMA5D4)
  125. return uarts_sama5d4;
  126. break;
  127. }
  128. /* at91sam9g10 */
  129. if ((cidr & ~AT91_CIDR_EXT) == ARCH_ID_AT91SAM9G10) {
  130. return uarts_sam9261;
  131. }
  132. /* at91sam9xe */
  133. else if ((cidr & AT91_CIDR_ARCH) == ARCH_FAMILY_AT91SAM9XE) {
  134. return uarts_sam9260;
  135. }
  136. return NULL;
  137. }
  138. static inline void arch_decomp_setup(void)
  139. {
  140. int i = 0;
  141. const u32* usarts;
  142. usarts = decomp_soc_detect((void __iomem *)AT91_BASE_DBGU0);
  143. if (!usarts)
  144. usarts = decomp_soc_detect((void __iomem *)AT91_BASE_DBGU1);
  145. if (!usarts)
  146. usarts = decomp_soc_detect((void __iomem *)AT91_BASE_DBGU2);
  147. if (!usarts) {
  148. at91_uart = NULL;
  149. return;
  150. }
  151. do {
  152. /* physical address */
  153. at91_uart = (void __iomem *)usarts[i];
  154. if (__raw_readl(at91_uart + ATMEL_US_BRGR))
  155. return;
  156. i++;
  157. } while (usarts[i]);
  158. at91_uart = NULL;
  159. }
  160. #else
  161. static inline void arch_decomp_setup(void)
  162. {
  163. at91_uart = NULL;
  164. }
  165. #endif
  166. /*
  167. * The following code assumes the serial port has already been
  168. * initialized by the bootloader. If you didn't setup a port in
  169. * your bootloader then nothing will appear (which might be desired).
  170. *
  171. * This does not append a newline
  172. */
  173. static void putc(int c)
  174. {
  175. if (!at91_uart)
  176. return;
  177. while (!(__raw_readl(at91_uart + ATMEL_US_CSR) & ATMEL_US_TXRDY))
  178. barrier();
  179. __raw_writel(c, at91_uart + ATMEL_US_THR);
  180. }
  181. static inline void flush(void)
  182. {
  183. if (!at91_uart)
  184. return;
  185. /* wait for transmission to complete */
  186. while (!(__raw_readl(at91_uart + ATMEL_US_CSR) & ATMEL_US_TXEMPTY))
  187. barrier();
  188. }
  189. #endif