perf_event.c 8.3 KB

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  1. /*
  2. * Linux performance counter support for ARC700 series
  3. *
  4. * Copyright (C) 2013 Synopsys, Inc. (www.synopsys.com)
  5. *
  6. * This code is inspired by the perf support of various other architectures.
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License version 2 as
  10. * published by the Free Software Foundation.
  11. *
  12. */
  13. #include <linux/errno.h>
  14. #include <linux/module.h>
  15. #include <linux/of.h>
  16. #include <linux/perf_event.h>
  17. #include <linux/platform_device.h>
  18. #include <asm/arcregs.h>
  19. struct arc_pmu {
  20. struct pmu pmu;
  21. int counter_size; /* in bits */
  22. int n_counters;
  23. unsigned long used_mask[BITS_TO_LONGS(ARC_PMU_MAX_HWEVENTS)];
  24. int ev_hw_idx[PERF_COUNT_ARC_HW_MAX];
  25. };
  26. /* read counter #idx; note that counter# != event# on ARC! */
  27. static uint64_t arc_pmu_read_counter(int idx)
  28. {
  29. uint32_t tmp;
  30. uint64_t result;
  31. /*
  32. * ARC supports making 'snapshots' of the counters, so we don't
  33. * need to care about counters wrapping to 0 underneath our feet
  34. */
  35. write_aux_reg(ARC_REG_PCT_INDEX, idx);
  36. tmp = read_aux_reg(ARC_REG_PCT_CONTROL);
  37. write_aux_reg(ARC_REG_PCT_CONTROL, tmp | ARC_REG_PCT_CONTROL_SN);
  38. result = (uint64_t) (read_aux_reg(ARC_REG_PCT_SNAPH)) << 32;
  39. result |= read_aux_reg(ARC_REG_PCT_SNAPL);
  40. return result;
  41. }
  42. static void arc_perf_event_update(struct perf_event *event,
  43. struct hw_perf_event *hwc, int idx)
  44. {
  45. struct arc_pmu *arc_pmu = container_of(event->pmu, struct arc_pmu, pmu);
  46. uint64_t prev_raw_count, new_raw_count;
  47. int64_t delta;
  48. do {
  49. prev_raw_count = local64_read(&hwc->prev_count);
  50. new_raw_count = arc_pmu_read_counter(idx);
  51. } while (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
  52. new_raw_count) != prev_raw_count);
  53. delta = (new_raw_count - prev_raw_count) &
  54. ((1ULL << arc_pmu->counter_size) - 1ULL);
  55. local64_add(delta, &event->count);
  56. local64_sub(delta, &hwc->period_left);
  57. }
  58. static void arc_pmu_read(struct perf_event *event)
  59. {
  60. arc_perf_event_update(event, &event->hw, event->hw.idx);
  61. }
  62. static int arc_pmu_cache_event(u64 config)
  63. {
  64. unsigned int cache_type, cache_op, cache_result;
  65. int ret;
  66. cache_type = (config >> 0) & 0xff;
  67. cache_op = (config >> 8) & 0xff;
  68. cache_result = (config >> 16) & 0xff;
  69. if (cache_type >= PERF_COUNT_HW_CACHE_MAX)
  70. return -EINVAL;
  71. if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX)
  72. return -EINVAL;
  73. if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
  74. return -EINVAL;
  75. ret = arc_pmu_cache_map[cache_type][cache_op][cache_result];
  76. if (ret == CACHE_OP_UNSUPPORTED)
  77. return -ENOENT;
  78. return ret;
  79. }
  80. /* initializes hw_perf_event structure if event is supported */
  81. static int arc_pmu_event_init(struct perf_event *event)
  82. {
  83. struct arc_pmu *arc_pmu = container_of(event->pmu, struct arc_pmu, pmu);
  84. struct hw_perf_event *hwc = &event->hw;
  85. int ret;
  86. switch (event->attr.type) {
  87. case PERF_TYPE_HARDWARE:
  88. if (event->attr.config >= PERF_COUNT_HW_MAX)
  89. return -ENOENT;
  90. if (arc_pmu->ev_hw_idx[event->attr.config] < 0)
  91. return -ENOENT;
  92. hwc->config = arc_pmu->ev_hw_idx[event->attr.config];
  93. pr_debug("initializing event %d with cfg %d\n",
  94. (int) event->attr.config, (int) hwc->config);
  95. return 0;
  96. case PERF_TYPE_HW_CACHE:
  97. ret = arc_pmu_cache_event(event->attr.config);
  98. if (ret < 0)
  99. return ret;
  100. hwc->config = arc_pmu->ev_hw_idx[ret];
  101. return 0;
  102. default:
  103. return -ENOENT;
  104. }
  105. }
  106. /* starts all counters */
  107. static void arc_pmu_enable(struct pmu *pmu)
  108. {
  109. uint32_t tmp;
  110. tmp = read_aux_reg(ARC_REG_PCT_CONTROL);
  111. write_aux_reg(ARC_REG_PCT_CONTROL, (tmp & 0xffff0000) | 0x1);
  112. }
  113. /* stops all counters */
  114. static void arc_pmu_disable(struct pmu *pmu)
  115. {
  116. uint32_t tmp;
  117. tmp = read_aux_reg(ARC_REG_PCT_CONTROL);
  118. write_aux_reg(ARC_REG_PCT_CONTROL, (tmp & 0xffff0000) | 0x0);
  119. }
  120. /*
  121. * Assigns hardware counter to hardware condition.
  122. * Note that there is no separate start/stop mechanism;
  123. * stopping is achieved by assigning the 'never' condition
  124. */
  125. static void arc_pmu_start(struct perf_event *event, int flags)
  126. {
  127. struct hw_perf_event *hwc = &event->hw;
  128. int idx = hwc->idx;
  129. if (WARN_ON_ONCE(idx == -1))
  130. return;
  131. if (flags & PERF_EF_RELOAD)
  132. WARN_ON_ONCE(!(event->hw.state & PERF_HES_UPTODATE));
  133. event->hw.state = 0;
  134. /* enable ARC pmu here */
  135. write_aux_reg(ARC_REG_PCT_INDEX, idx);
  136. write_aux_reg(ARC_REG_PCT_CONFIG, hwc->config);
  137. }
  138. static void arc_pmu_stop(struct perf_event *event, int flags)
  139. {
  140. struct hw_perf_event *hwc = &event->hw;
  141. int idx = hwc->idx;
  142. if (!(event->hw.state & PERF_HES_STOPPED)) {
  143. /* stop ARC pmu here */
  144. write_aux_reg(ARC_REG_PCT_INDEX, idx);
  145. /* condition code #0 is always "never" */
  146. write_aux_reg(ARC_REG_PCT_CONFIG, 0);
  147. event->hw.state |= PERF_HES_STOPPED;
  148. }
  149. if ((flags & PERF_EF_UPDATE) &&
  150. !(event->hw.state & PERF_HES_UPTODATE)) {
  151. arc_perf_event_update(event, &event->hw, idx);
  152. event->hw.state |= PERF_HES_UPTODATE;
  153. }
  154. }
  155. static void arc_pmu_del(struct perf_event *event, int flags)
  156. {
  157. struct arc_pmu *arc_pmu = container_of(event->pmu, struct arc_pmu, pmu);
  158. arc_pmu_stop(event, PERF_EF_UPDATE);
  159. __clear_bit(event->hw.idx, arc_pmu->used_mask);
  160. perf_event_update_userpage(event);
  161. }
  162. /* allocate hardware counter and optionally start counting */
  163. static int arc_pmu_add(struct perf_event *event, int flags)
  164. {
  165. struct arc_pmu *arc_pmu = container_of(event->pmu, struct arc_pmu, pmu);
  166. struct hw_perf_event *hwc = &event->hw;
  167. int idx = hwc->idx;
  168. if (__test_and_set_bit(idx, arc_pmu->used_mask)) {
  169. idx = find_first_zero_bit(arc_pmu->used_mask,
  170. arc_pmu->n_counters);
  171. if (idx == arc_pmu->n_counters)
  172. return -EAGAIN;
  173. __set_bit(idx, arc_pmu->used_mask);
  174. hwc->idx = idx;
  175. }
  176. write_aux_reg(ARC_REG_PCT_INDEX, idx);
  177. write_aux_reg(ARC_REG_PCT_CONFIG, 0);
  178. write_aux_reg(ARC_REG_PCT_COUNTL, 0);
  179. write_aux_reg(ARC_REG_PCT_COUNTH, 0);
  180. local64_set(&hwc->prev_count, 0);
  181. hwc->state = PERF_HES_UPTODATE | PERF_HES_STOPPED;
  182. if (flags & PERF_EF_START)
  183. arc_pmu_start(event, PERF_EF_RELOAD);
  184. perf_event_update_userpage(event);
  185. return 0;
  186. }
  187. static int arc_pmu_device_probe(struct platform_device *pdev)
  188. {
  189. struct arc_pmu *arc_pmu;
  190. struct arc_reg_pct_build pct_bcr;
  191. struct arc_reg_cc_build cc_bcr;
  192. int i, j, ret;
  193. union cc_name {
  194. struct {
  195. uint32_t word0, word1;
  196. char sentinel;
  197. } indiv;
  198. char str[9];
  199. } cc_name;
  200. READ_BCR(ARC_REG_PCT_BUILD, pct_bcr);
  201. if (!pct_bcr.v) {
  202. pr_err("This core does not have performance counters!\n");
  203. return -ENODEV;
  204. }
  205. arc_pmu = devm_kzalloc(&pdev->dev, sizeof(struct arc_pmu),
  206. GFP_KERNEL);
  207. if (!arc_pmu)
  208. return -ENOMEM;
  209. arc_pmu->n_counters = pct_bcr.c;
  210. BUG_ON(arc_pmu->n_counters > ARC_PMU_MAX_HWEVENTS);
  211. arc_pmu->counter_size = 32 + (pct_bcr.s << 4);
  212. pr_info("ARC PMU found with %d counters of size %d bits\n",
  213. arc_pmu->n_counters, arc_pmu->counter_size);
  214. READ_BCR(ARC_REG_CC_BUILD, cc_bcr);
  215. if (!cc_bcr.v)
  216. pr_err("Strange! Performance counters exist, but no countable conditions?\n");
  217. pr_info("ARC PMU has %d countable conditions\n", cc_bcr.c);
  218. cc_name.str[8] = 0;
  219. for (i = 0; i < PERF_COUNT_HW_MAX; i++)
  220. arc_pmu->ev_hw_idx[i] = -1;
  221. for (j = 0; j < cc_bcr.c; j++) {
  222. write_aux_reg(ARC_REG_CC_INDEX, j);
  223. cc_name.indiv.word0 = read_aux_reg(ARC_REG_CC_NAME0);
  224. cc_name.indiv.word1 = read_aux_reg(ARC_REG_CC_NAME1);
  225. for (i = 0; i < ARRAY_SIZE(arc_pmu_ev_hw_map); i++) {
  226. if (arc_pmu_ev_hw_map[i] &&
  227. !strcmp(arc_pmu_ev_hw_map[i], cc_name.str) &&
  228. strlen(arc_pmu_ev_hw_map[i])) {
  229. pr_debug("mapping %d to idx %d with name %s\n",
  230. i, j, cc_name.str);
  231. arc_pmu->ev_hw_idx[i] = j;
  232. }
  233. }
  234. }
  235. arc_pmu->pmu = (struct pmu) {
  236. .pmu_enable = arc_pmu_enable,
  237. .pmu_disable = arc_pmu_disable,
  238. .event_init = arc_pmu_event_init,
  239. .add = arc_pmu_add,
  240. .del = arc_pmu_del,
  241. .start = arc_pmu_start,
  242. .stop = arc_pmu_stop,
  243. .read = arc_pmu_read,
  244. };
  245. /* ARC 700 PMU does not support sampling events */
  246. arc_pmu->pmu.capabilities |= PERF_PMU_CAP_NO_INTERRUPT;
  247. ret = perf_pmu_register(&arc_pmu->pmu, pdev->name, PERF_TYPE_RAW);
  248. return ret;
  249. }
  250. #ifdef CONFIG_OF
  251. static const struct of_device_id arc_pmu_match[] = {
  252. { .compatible = "snps,arc700-pmu" },
  253. {},
  254. };
  255. MODULE_DEVICE_TABLE(of, arc_pmu_match);
  256. #endif
  257. static struct platform_driver arc_pmu_driver = {
  258. .driver = {
  259. .name = "arc700-pmu",
  260. .of_match_table = of_match_ptr(arc_pmu_match),
  261. },
  262. .probe = arc_pmu_device_probe,
  263. };
  264. module_platform_driver(arc_pmu_driver);
  265. MODULE_LICENSE("GPL");
  266. MODULE_AUTHOR("Mischa Jonker <mjonker@synopsys.com>");
  267. MODULE_DESCRIPTION("ARC PMU driver");