Kconfig 10 KB

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  1. #
  2. # EDAC Kconfig
  3. # Copyright (c) 2008 Doug Thompson www.softwarebitmaker.com
  4. # Licensed and distributed under the GPL
  5. #
  6. menuconfig EDAC
  7. bool "EDAC (Error Detection And Correction) reporting"
  8. depends on HAS_IOMEM
  9. depends on X86 || PPC || TILE || ARM || EDAC_SUPPORT
  10. help
  11. EDAC is designed to report errors in the core system.
  12. These are low-level errors that are reported in the CPU or
  13. supporting chipset or other subsystems:
  14. memory errors, cache errors, PCI errors, thermal throttling, etc..
  15. If unsure, select 'Y'.
  16. If this code is reporting problems on your system, please
  17. see the EDAC project web pages for more information at:
  18. <http://bluesmoke.sourceforge.net/>
  19. and:
  20. <http://buttersideup.com/edacwiki>
  21. There is also a mailing list for the EDAC project, which can
  22. be found via the sourceforge page.
  23. config EDAC_SUPPORT
  24. bool
  25. if EDAC
  26. comment "Reporting subsystems"
  27. config EDAC_LEGACY_SYSFS
  28. bool "EDAC legacy sysfs"
  29. default y
  30. help
  31. Enable the compatibility sysfs nodes.
  32. Use 'Y' if your edac utilities aren't ported to work with the newer
  33. structures.
  34. config EDAC_DEBUG
  35. bool "Debugging"
  36. help
  37. This turns on debugging information for the entire EDAC subsystem.
  38. You do so by inserting edac_module with "edac_debug_level=x." Valid
  39. levels are 0-4 (from low to high) and by default it is set to 2.
  40. Usually you should select 'N' here.
  41. config EDAC_DECODE_MCE
  42. tristate "Decode MCEs in human-readable form (only on AMD for now)"
  43. depends on CPU_SUP_AMD && X86_MCE_AMD
  44. default y
  45. ---help---
  46. Enable this option if you want to decode Machine Check Exceptions
  47. occurring on your machine in human-readable form.
  48. You should definitely say Y here in case you want to decode MCEs
  49. which occur really early upon boot, before the module infrastructure
  50. has been initialized.
  51. config EDAC_MCE_INJ
  52. tristate "Simple MCE injection interface over /sysfs"
  53. depends on EDAC_DECODE_MCE
  54. default n
  55. help
  56. This is a simple interface to inject MCEs over /sysfs and test
  57. the MCE decoding code in EDAC.
  58. This is currently AMD-only.
  59. config EDAC_MM_EDAC
  60. tristate "Main Memory EDAC (Error Detection And Correction) reporting"
  61. help
  62. Some systems are able to detect and correct errors in main
  63. memory. EDAC can report statistics on memory error
  64. detection and correction (EDAC - or commonly referred to ECC
  65. errors). EDAC will also try to decode where these errors
  66. occurred so that a particular failing memory module can be
  67. replaced. If unsure, select 'Y'.
  68. config EDAC_AMD64
  69. tristate "AMD64 (Opteron, Athlon64) K8, F10h"
  70. depends on EDAC_MM_EDAC && AMD_NB && X86_64 && EDAC_DECODE_MCE
  71. help
  72. Support for error detection and correction of DRAM ECC errors on
  73. the AMD64 families of memory controllers (K8 and F10h)
  74. config EDAC_AMD64_ERROR_INJECTION
  75. bool "Sysfs HW Error injection facilities"
  76. depends on EDAC_AMD64
  77. help
  78. Recent Opterons (Family 10h and later) provide for Memory Error
  79. Injection into the ECC detection circuits. The amd64_edac module
  80. allows the operator/user to inject Uncorrectable and Correctable
  81. errors into DRAM.
  82. When enabled, in each of the respective memory controller directories
  83. (/sys/devices/system/edac/mc/mcX), there are 3 input files:
  84. - inject_section (0..3, 16-byte section of 64-byte cacheline),
  85. - inject_word (0..8, 16-bit word of 16-byte section),
  86. - inject_ecc_vector (hex ecc vector: select bits of inject word)
  87. In addition, there are two control files, inject_read and inject_write,
  88. which trigger the DRAM ECC Read and Write respectively.
  89. config EDAC_AMD76X
  90. tristate "AMD 76x (760, 762, 768)"
  91. depends on EDAC_MM_EDAC && PCI && X86_32
  92. help
  93. Support for error detection and correction on the AMD 76x
  94. series of chipsets used with the Athlon processor.
  95. config EDAC_E7XXX
  96. tristate "Intel e7xxx (e7205, e7500, e7501, e7505)"
  97. depends on EDAC_MM_EDAC && PCI && X86_32
  98. help
  99. Support for error detection and correction on the Intel
  100. E7205, E7500, E7501 and E7505 server chipsets.
  101. config EDAC_E752X
  102. tristate "Intel e752x (e7520, e7525, e7320) and 3100"
  103. depends on EDAC_MM_EDAC && PCI && X86 && HOTPLUG
  104. help
  105. Support for error detection and correction on the Intel
  106. E7520, E7525, E7320 server chipsets.
  107. config EDAC_I82443BXGX
  108. tristate "Intel 82443BX/GX (440BX/GX)"
  109. depends on EDAC_MM_EDAC && PCI && X86_32
  110. depends on BROKEN
  111. help
  112. Support for error detection and correction on the Intel
  113. 82443BX/GX memory controllers (440BX/GX chipsets).
  114. config EDAC_I82875P
  115. tristate "Intel 82875p (D82875P, E7210)"
  116. depends on EDAC_MM_EDAC && PCI && X86_32
  117. help
  118. Support for error detection and correction on the Intel
  119. DP82785P and E7210 server chipsets.
  120. config EDAC_I82975X
  121. tristate "Intel 82975x (D82975x)"
  122. depends on EDAC_MM_EDAC && PCI && X86
  123. help
  124. Support for error detection and correction on the Intel
  125. DP82975x server chipsets.
  126. config EDAC_I3000
  127. tristate "Intel 3000/3010"
  128. depends on EDAC_MM_EDAC && PCI && X86
  129. help
  130. Support for error detection and correction on the Intel
  131. 3000 and 3010 server chipsets.
  132. config EDAC_I3200
  133. tristate "Intel 3200"
  134. depends on EDAC_MM_EDAC && PCI && X86 && EXPERIMENTAL
  135. help
  136. Support for error detection and correction on the Intel
  137. 3200 and 3210 server chipsets.
  138. config EDAC_X38
  139. tristate "Intel X38"
  140. depends on EDAC_MM_EDAC && PCI && X86
  141. help
  142. Support for error detection and correction on the Intel
  143. X38 server chipsets.
  144. config EDAC_I5400
  145. tristate "Intel 5400 (Seaburg) chipsets"
  146. depends on EDAC_MM_EDAC && PCI && X86
  147. help
  148. Support for error detection and correction the Intel
  149. i5400 MCH chipset (Seaburg).
  150. config EDAC_I7CORE
  151. tristate "Intel i7 Core (Nehalem) processors"
  152. depends on EDAC_MM_EDAC && PCI && X86 && X86_MCE_INTEL
  153. help
  154. Support for error detection and correction the Intel
  155. i7 Core (Nehalem) Integrated Memory Controller that exists on
  156. newer processors like i7 Core, i7 Core Extreme, Xeon 35xx
  157. and Xeon 55xx processors.
  158. config EDAC_I82860
  159. tristate "Intel 82860"
  160. depends on EDAC_MM_EDAC && PCI && X86_32
  161. help
  162. Support for error detection and correction on the Intel
  163. 82860 chipset.
  164. config EDAC_R82600
  165. tristate "Radisys 82600 embedded chipset"
  166. depends on EDAC_MM_EDAC && PCI && X86_32
  167. help
  168. Support for error detection and correction on the Radisys
  169. 82600 embedded chipset.
  170. config EDAC_I5000
  171. tristate "Intel Greencreek/Blackford chipset"
  172. depends on EDAC_MM_EDAC && X86 && PCI
  173. help
  174. Support for error detection and correction the Intel
  175. Greekcreek/Blackford chipsets.
  176. config EDAC_I5100
  177. tristate "Intel San Clemente MCH"
  178. depends on EDAC_MM_EDAC && X86 && PCI
  179. help
  180. Support for error detection and correction the Intel
  181. San Clemente MCH.
  182. config EDAC_I7300
  183. tristate "Intel Clarksboro MCH"
  184. depends on EDAC_MM_EDAC && X86 && PCI
  185. help
  186. Support for error detection and correction the Intel
  187. Clarksboro MCH (Intel 7300 chipset).
  188. config EDAC_SBRIDGE
  189. tristate "Intel Sandy-Bridge Integrated MC"
  190. depends on EDAC_MM_EDAC && PCI && X86_64 && X86_MCE_INTEL
  191. depends on PCI_MMCONFIG && EXPERIMENTAL
  192. help
  193. Support for error detection and correction the Intel
  194. Sandy Bridge Integrated Memory Controller.
  195. config EDAC_MPC85XX
  196. tristate "Freescale MPC83xx / MPC85xx"
  197. depends on EDAC_MM_EDAC && FSL_SOC && (PPC_83xx || PPC_85xx)
  198. help
  199. Support for error detection and correction on the Freescale
  200. MPC8349, MPC8560, MPC8540, MPC8548
  201. config EDAC_MV64X60
  202. tristate "Marvell MV64x60"
  203. depends on EDAC_MM_EDAC && MV64X60
  204. help
  205. Support for error detection and correction on the Marvell
  206. MV64360 and MV64460 chipsets.
  207. config EDAC_PASEMI
  208. tristate "PA Semi PWRficient"
  209. depends on EDAC_MM_EDAC && PCI
  210. depends on PPC_PASEMI
  211. help
  212. Support for error detection and correction on PA Semi
  213. PWRficient.
  214. config EDAC_CELL
  215. tristate "Cell Broadband Engine memory controller"
  216. depends on EDAC_MM_EDAC && PPC_CELL_COMMON
  217. help
  218. Support for error detection and correction on the
  219. Cell Broadband Engine internal memory controller
  220. on platform without a hypervisor
  221. config EDAC_PPC4XX
  222. tristate "PPC4xx IBM DDR2 Memory Controller"
  223. depends on EDAC_MM_EDAC && 4xx
  224. help
  225. This enables support for EDAC on the ECC memory used
  226. with the IBM DDR2 memory controller found in various
  227. PowerPC 4xx embedded processors such as the 405EX[r],
  228. 440SP, 440SPe, 460EX, 460GT and 460SX.
  229. config EDAC_AMD8131
  230. tristate "AMD8131 HyperTransport PCI-X Tunnel"
  231. depends on EDAC_MM_EDAC && PCI && PPC_MAPLE
  232. help
  233. Support for error detection and correction on the
  234. AMD8131 HyperTransport PCI-X Tunnel chip.
  235. Note, add more Kconfig dependency if it's adopted
  236. on some machine other than Maple.
  237. config EDAC_AMD8111
  238. tristate "AMD8111 HyperTransport I/O Hub"
  239. depends on EDAC_MM_EDAC && PCI && PPC_MAPLE
  240. help
  241. Support for error detection and correction on the
  242. AMD8111 HyperTransport I/O Hub chip.
  243. Note, add more Kconfig dependency if it's adopted
  244. on some machine other than Maple.
  245. config EDAC_CPC925
  246. tristate "IBM CPC925 Memory Controller (PPC970FX)"
  247. depends on EDAC_MM_EDAC && PPC64
  248. help
  249. Support for error detection and correction on the
  250. IBM CPC925 Bridge and Memory Controller, which is
  251. a companion chip to the PowerPC 970 family of
  252. processors.
  253. config EDAC_TILE
  254. tristate "Tilera Memory Controller"
  255. depends on EDAC_MM_EDAC && TILE
  256. default y
  257. help
  258. Support for error detection and correction on the
  259. Tilera memory controller.
  260. config EDAC_HIGHBANK_MC
  261. tristate "Highbank Memory Controller"
  262. depends on EDAC_MM_EDAC && ARCH_HIGHBANK
  263. help
  264. Support for error detection and correction on the
  265. Calxeda Highbank memory controller.
  266. config EDAC_HIGHBANK_L2
  267. tristate "Highbank L2 Cache"
  268. depends on EDAC_MM_EDAC && ARCH_HIGHBANK
  269. help
  270. Support for error detection and correction on the
  271. Calxeda Highbank memory controller.
  272. config EDAC_OCTEON_PC
  273. tristate "Cavium Octeon Primary Caches"
  274. depends on EDAC_MM_EDAC && CPU_CAVIUM_OCTEON
  275. help
  276. Support for error detection and correction on the primary caches of
  277. the cnMIPS cores of Cavium Octeon family SOCs.
  278. config EDAC_OCTEON_L2C
  279. tristate "Cavium Octeon Secondary Caches (L2C)"
  280. depends on EDAC_MM_EDAC && CPU_CAVIUM_OCTEON
  281. help
  282. Support for error detection and correction on the
  283. Cavium Octeon family of SOCs.
  284. config EDAC_OCTEON_LMC
  285. tristate "Cavium Octeon DRAM Memory Controller (LMC)"
  286. depends on EDAC_MM_EDAC && CPU_CAVIUM_OCTEON
  287. help
  288. Support for error detection and correction on the
  289. Cavium Octeon family of SOCs.
  290. config EDAC_OCTEON_PCI
  291. tristate "Cavium Octeon PCI Controller"
  292. depends on EDAC_MM_EDAC && PCI && CPU_CAVIUM_OCTEON
  293. help
  294. Support for error detection and correction on the
  295. Cavium Octeon family of SOCs.
  296. endif # EDAC