phy-ralink-usb.c 6.7 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249
  1. /*
  2. * Copyright (C) 2017 John Crispin <john@phrozen.org>
  3. *
  4. * Based on code from
  5. * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License as published by
  9. * the Free Software Foundation; either version 2 of the License, or
  10. * (at your option) any later version.
  11. *
  12. * This program is distributed in the hope that it will be useful,
  13. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15. * GNU General Public License for more details.
  16. */
  17. #include <linux/delay.h>
  18. #include <linux/err.h>
  19. #include <linux/io.h>
  20. #include <linux/kernel.h>
  21. #include <linux/mfd/syscon.h>
  22. #include <linux/module.h>
  23. #include <linux/mutex.h>
  24. #include <linux/of_platform.h>
  25. #include <linux/phy/phy.h>
  26. #include <linux/platform_device.h>
  27. #include <linux/regmap.h>
  28. #include <linux/reset.h>
  29. #define RT_SYSC_REG_SYSCFG1 0x014
  30. #define RT_SYSC_REG_CLKCFG1 0x030
  31. #define RT_SYSC_REG_USB_PHY_CFG 0x05c
  32. #define OFS_U2_PHY_AC0 0x800
  33. #define OFS_U2_PHY_AC1 0x804
  34. #define OFS_U2_PHY_AC2 0x808
  35. #define OFS_U2_PHY_ACR0 0x810
  36. #define OFS_U2_PHY_ACR1 0x814
  37. #define OFS_U2_PHY_ACR2 0x818
  38. #define OFS_U2_PHY_ACR3 0x81C
  39. #define OFS_U2_PHY_ACR4 0x820
  40. #define OFS_U2_PHY_AMON0 0x824
  41. #define OFS_U2_PHY_DCR0 0x860
  42. #define OFS_U2_PHY_DCR1 0x864
  43. #define OFS_U2_PHY_DTM0 0x868
  44. #define OFS_U2_PHY_DTM1 0x86C
  45. #define RT_RSTCTRL_UDEV BIT(25)
  46. #define RT_RSTCTRL_UHST BIT(22)
  47. #define RT_SYSCFG1_USB0_HOST_MODE BIT(10)
  48. #define MT7620_CLKCFG1_UPHY0_CLK_EN BIT(25)
  49. #define MT7620_CLKCFG1_UPHY1_CLK_EN BIT(22)
  50. #define RT_CLKCFG1_UPHY1_CLK_EN BIT(20)
  51. #define RT_CLKCFG1_UPHY0_CLK_EN BIT(18)
  52. #define USB_PHY_UTMI_8B60M BIT(1)
  53. #define UDEV_WAKEUP BIT(0)
  54. struct ralink_usb_phy {
  55. struct reset_control *rstdev;
  56. struct reset_control *rsthost;
  57. u32 clk;
  58. struct phy *phy;
  59. void __iomem *base;
  60. struct regmap *sysctl;
  61. };
  62. static void u2_phy_w32(struct ralink_usb_phy *phy, u32 val, u32 reg)
  63. {
  64. writel(val, phy->base + reg);
  65. }
  66. static u32 u2_phy_r32(struct ralink_usb_phy *phy, u32 reg)
  67. {
  68. return readl(phy->base + reg);
  69. }
  70. static void ralink_usb_phy_init(struct ralink_usb_phy *phy)
  71. {
  72. u2_phy_r32(phy, OFS_U2_PHY_AC2);
  73. u2_phy_r32(phy, OFS_U2_PHY_ACR0);
  74. u2_phy_r32(phy, OFS_U2_PHY_DCR0);
  75. u2_phy_w32(phy, 0x00ffff02, OFS_U2_PHY_DCR0);
  76. u2_phy_r32(phy, OFS_U2_PHY_DCR0);
  77. u2_phy_w32(phy, 0x00555502, OFS_U2_PHY_DCR0);
  78. u2_phy_r32(phy, OFS_U2_PHY_DCR0);
  79. u2_phy_w32(phy, 0x00aaaa02, OFS_U2_PHY_DCR0);
  80. u2_phy_r32(phy, OFS_U2_PHY_DCR0);
  81. u2_phy_w32(phy, 0x00000402, OFS_U2_PHY_DCR0);
  82. u2_phy_r32(phy, OFS_U2_PHY_DCR0);
  83. u2_phy_w32(phy, 0x0048086a, OFS_U2_PHY_AC0);
  84. u2_phy_w32(phy, 0x4400001c, OFS_U2_PHY_AC1);
  85. u2_phy_w32(phy, 0xc0200000, OFS_U2_PHY_ACR3);
  86. u2_phy_w32(phy, 0x02000000, OFS_U2_PHY_DTM0);
  87. }
  88. static int ralink_usb_phy_power_on(struct phy *_phy)
  89. {
  90. struct ralink_usb_phy *phy = phy_get_drvdata(_phy);
  91. u32 t;
  92. /* enable the phy */
  93. regmap_update_bits(phy->sysctl, RT_SYSC_REG_CLKCFG1,
  94. phy->clk, phy->clk);
  95. /* setup host mode */
  96. regmap_update_bits(phy->sysctl, RT_SYSC_REG_SYSCFG1,
  97. RT_SYSCFG1_USB0_HOST_MODE,
  98. RT_SYSCFG1_USB0_HOST_MODE);
  99. /* deassert the reset lines */
  100. reset_control_deassert(phy->rsthost);
  101. reset_control_deassert(phy->rstdev);
  102. /*
  103. * The SDK kernel had a delay of 100ms. however on device
  104. * testing showed that 10ms is enough
  105. */
  106. mdelay(10);
  107. if (phy->base)
  108. ralink_usb_phy_init(phy);
  109. /* print some status info */
  110. regmap_read(phy->sysctl, RT_SYSC_REG_USB_PHY_CFG, &t);
  111. dev_info(&phy->phy->dev, "remote usb device wakeup %s\n",
  112. (t & UDEV_WAKEUP) ? ("enabled") : ("disabled"));
  113. if (t & USB_PHY_UTMI_8B60M)
  114. dev_info(&phy->phy->dev, "UTMI 8bit 60MHz\n");
  115. else
  116. dev_info(&phy->phy->dev, "UTMI 16bit 30MHz\n");
  117. return 0;
  118. }
  119. static int ralink_usb_phy_power_off(struct phy *_phy)
  120. {
  121. struct ralink_usb_phy *phy = phy_get_drvdata(_phy);
  122. /* disable the phy */
  123. regmap_update_bits(phy->sysctl, RT_SYSC_REG_CLKCFG1,
  124. phy->clk, 0);
  125. /* assert the reset lines */
  126. reset_control_assert(phy->rstdev);
  127. reset_control_assert(phy->rsthost);
  128. return 0;
  129. }
  130. static struct phy_ops ralink_usb_phy_ops = {
  131. .power_on = ralink_usb_phy_power_on,
  132. .power_off = ralink_usb_phy_power_off,
  133. .owner = THIS_MODULE,
  134. };
  135. static const struct of_device_id ralink_usb_phy_of_match[] = {
  136. {
  137. .compatible = "ralink,rt3352-usbphy",
  138. .data = (void *) (RT_CLKCFG1_UPHY1_CLK_EN |
  139. RT_CLKCFG1_UPHY0_CLK_EN)
  140. },
  141. {
  142. .compatible = "mediatek,mt7620-usbphy",
  143. .data = (void *) (MT7620_CLKCFG1_UPHY1_CLK_EN |
  144. MT7620_CLKCFG1_UPHY0_CLK_EN)
  145. },
  146. {
  147. .compatible = "mediatek,mt7628-usbphy",
  148. .data = (void *) (MT7620_CLKCFG1_UPHY1_CLK_EN |
  149. MT7620_CLKCFG1_UPHY0_CLK_EN) },
  150. { },
  151. };
  152. MODULE_DEVICE_TABLE(of, ralink_usb_phy_of_match);
  153. static int ralink_usb_phy_probe(struct platform_device *pdev)
  154. {
  155. struct device *dev = &pdev->dev;
  156. struct resource *res;
  157. struct phy_provider *phy_provider;
  158. const struct of_device_id *match;
  159. struct ralink_usb_phy *phy;
  160. match = of_match_device(ralink_usb_phy_of_match, &pdev->dev);
  161. if (!match)
  162. return -ENODEV;
  163. phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL);
  164. if (!phy)
  165. return -ENOMEM;
  166. phy->clk = (u32) match->data;
  167. phy->base = NULL;
  168. phy->sysctl = syscon_regmap_lookup_by_phandle(dev->of_node, "ralink,sysctl");
  169. if (IS_ERR(phy->sysctl)) {
  170. dev_err(dev, "failed to get sysctl registers\n");
  171. return PTR_ERR(phy->sysctl);
  172. }
  173. /* The MT7628 and MT7688 require extra setup of PHY registers. */
  174. if (of_device_is_compatible(dev->of_node, "mediatek,mt7628-usbphy")) {
  175. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  176. phy->base = devm_ioremap_resource(&pdev->dev, res);
  177. if (IS_ERR(phy->base)) {
  178. dev_err(dev, "failed to remap register memory\n");
  179. return PTR_ERR(phy->base);
  180. }
  181. }
  182. phy->rsthost = devm_reset_control_get(&pdev->dev, "host");
  183. if (IS_ERR(phy->rsthost)) {
  184. dev_err(dev, "host reset is missing\n");
  185. return PTR_ERR(phy->rsthost);
  186. }
  187. phy->rstdev = devm_reset_control_get(&pdev->dev, "device");
  188. if (IS_ERR(phy->rstdev)) {
  189. dev_err(dev, "device reset is missing\n");
  190. return PTR_ERR(phy->rstdev);
  191. }
  192. phy->phy = devm_phy_create(dev, NULL, &ralink_usb_phy_ops);
  193. if (IS_ERR(phy->phy)) {
  194. dev_err(dev, "failed to create PHY\n");
  195. return PTR_ERR(phy->phy);
  196. }
  197. phy_set_drvdata(phy->phy, phy);
  198. phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
  199. return PTR_ERR_OR_ZERO(phy_provider);
  200. }
  201. static struct platform_driver ralink_usb_phy_driver = {
  202. .probe = ralink_usb_phy_probe,
  203. .driver = {
  204. .of_match_table = ralink_usb_phy_of_match,
  205. .name = "ralink-usb-phy",
  206. }
  207. };
  208. module_platform_driver(ralink_usb_phy_driver);
  209. MODULE_DESCRIPTION("Ralink USB phy driver");
  210. MODULE_AUTHOR("John Crispin <john@phrozen.org>");
  211. MODULE_LICENSE("GPL v2");