amdgpu_ctx.c 5.9 KB

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  1. /*
  2. * Copyright 2015 Advanced Micro Devices, Inc.
  3. *
  4. * Permission is hereby granted, free of charge, to any person obtaining a
  5. * copy of this software and associated documentation files (the "Software"),
  6. * to deal in the Software without restriction, including without limitation
  7. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8. * and/or sell copies of the Software, and to permit persons to whom the
  9. * Software is furnished to do so, subject to the following conditions:
  10. *
  11. * The above copyright notice and this permission notice shall be included in
  12. * all copies or substantial portions of the Software.
  13. *
  14. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  17. * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18. * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19. * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20. * OTHER DEALINGS IN THE SOFTWARE.
  21. *
  22. * Authors: monk liu <monk.liu@amd.com>
  23. */
  24. #include <drm/drmP.h>
  25. #include "amdgpu.h"
  26. static void amdgpu_ctx_do_release(struct kref *ref)
  27. {
  28. struct amdgpu_ctx *ctx;
  29. unsigned i, j;
  30. ctx = container_of(ref, struct amdgpu_ctx, refcount);
  31. for (i = 0; i < AMDGPU_MAX_RINGS; ++i)
  32. for (j = 0; j < AMDGPU_CTX_MAX_CS_PENDING; ++j)
  33. fence_put(ctx->rings[i].fences[j]);
  34. kfree(ctx);
  35. }
  36. int amdgpu_ctx_alloc(struct amdgpu_device *adev, struct amdgpu_fpriv *fpriv,
  37. uint32_t *id)
  38. {
  39. struct amdgpu_ctx *ctx;
  40. struct amdgpu_ctx_mgr *mgr = &fpriv->ctx_mgr;
  41. int i, r;
  42. ctx = kmalloc(sizeof(*ctx), GFP_KERNEL);
  43. if (!ctx)
  44. return -ENOMEM;
  45. mutex_lock(&mgr->lock);
  46. r = idr_alloc(&mgr->ctx_handles, ctx, 0, 0, GFP_KERNEL);
  47. if (r < 0) {
  48. mutex_unlock(&mgr->lock);
  49. kfree(ctx);
  50. return r;
  51. }
  52. *id = (uint32_t)r;
  53. memset(ctx, 0, sizeof(*ctx));
  54. kref_init(&ctx->refcount);
  55. spin_lock_init(&ctx->ring_lock);
  56. for (i = 0; i < AMDGPU_MAX_RINGS; ++i)
  57. ctx->rings[i].sequence = 1;
  58. mutex_unlock(&mgr->lock);
  59. return 0;
  60. }
  61. int amdgpu_ctx_free(struct amdgpu_device *adev, struct amdgpu_fpriv *fpriv, uint32_t id)
  62. {
  63. struct amdgpu_ctx *ctx;
  64. struct amdgpu_ctx_mgr *mgr = &fpriv->ctx_mgr;
  65. mutex_lock(&mgr->lock);
  66. ctx = idr_find(&mgr->ctx_handles, id);
  67. if (ctx) {
  68. idr_remove(&mgr->ctx_handles, id);
  69. kref_put(&ctx->refcount, amdgpu_ctx_do_release);
  70. mutex_unlock(&mgr->lock);
  71. return 0;
  72. }
  73. mutex_unlock(&mgr->lock);
  74. return -EINVAL;
  75. }
  76. static int amdgpu_ctx_query(struct amdgpu_device *adev,
  77. struct amdgpu_fpriv *fpriv, uint32_t id,
  78. union drm_amdgpu_ctx_out *out)
  79. {
  80. struct amdgpu_ctx *ctx;
  81. struct amdgpu_ctx_mgr *mgr = &fpriv->ctx_mgr;
  82. unsigned reset_counter;
  83. mutex_lock(&mgr->lock);
  84. ctx = idr_find(&mgr->ctx_handles, id);
  85. if (!ctx) {
  86. mutex_unlock(&mgr->lock);
  87. return -EINVAL;
  88. }
  89. /* TODO: these two are always zero */
  90. out->state.flags = 0x0;
  91. out->state.hangs = 0x0;
  92. /* determine if a GPU reset has occured since the last call */
  93. reset_counter = atomic_read(&adev->gpu_reset_counter);
  94. /* TODO: this should ideally return NO, GUILTY, or INNOCENT. */
  95. if (ctx->reset_counter == reset_counter)
  96. out->state.reset_status = AMDGPU_CTX_NO_RESET;
  97. else
  98. out->state.reset_status = AMDGPU_CTX_UNKNOWN_RESET;
  99. ctx->reset_counter = reset_counter;
  100. mutex_unlock(&mgr->lock);
  101. return 0;
  102. }
  103. void amdgpu_ctx_fini(struct amdgpu_fpriv *fpriv)
  104. {
  105. struct idr *idp;
  106. struct amdgpu_ctx *ctx;
  107. uint32_t id;
  108. struct amdgpu_ctx_mgr *mgr = &fpriv->ctx_mgr;
  109. idp = &mgr->ctx_handles;
  110. idr_for_each_entry(idp,ctx,id) {
  111. if (kref_put(&ctx->refcount, amdgpu_ctx_do_release) != 1)
  112. DRM_ERROR("ctx %p is still alive\n", ctx);
  113. }
  114. mutex_destroy(&mgr->lock);
  115. }
  116. int amdgpu_ctx_ioctl(struct drm_device *dev, void *data,
  117. struct drm_file *filp)
  118. {
  119. int r;
  120. uint32_t id;
  121. union drm_amdgpu_ctx *args = data;
  122. struct amdgpu_device *adev = dev->dev_private;
  123. struct amdgpu_fpriv *fpriv = filp->driver_priv;
  124. r = 0;
  125. id = args->in.ctx_id;
  126. switch (args->in.op) {
  127. case AMDGPU_CTX_OP_ALLOC_CTX:
  128. r = amdgpu_ctx_alloc(adev, fpriv, &id);
  129. args->out.alloc.ctx_id = id;
  130. break;
  131. case AMDGPU_CTX_OP_FREE_CTX:
  132. r = amdgpu_ctx_free(adev, fpriv, id);
  133. break;
  134. case AMDGPU_CTX_OP_QUERY_STATE:
  135. r = amdgpu_ctx_query(adev, fpriv, id, &args->out);
  136. break;
  137. default:
  138. return -EINVAL;
  139. }
  140. return r;
  141. }
  142. struct amdgpu_ctx *amdgpu_ctx_get(struct amdgpu_fpriv *fpriv, uint32_t id)
  143. {
  144. struct amdgpu_ctx *ctx;
  145. struct amdgpu_ctx_mgr *mgr = &fpriv->ctx_mgr;
  146. mutex_lock(&mgr->lock);
  147. ctx = idr_find(&mgr->ctx_handles, id);
  148. if (ctx)
  149. kref_get(&ctx->refcount);
  150. mutex_unlock(&mgr->lock);
  151. return ctx;
  152. }
  153. int amdgpu_ctx_put(struct amdgpu_ctx *ctx)
  154. {
  155. if (ctx == NULL)
  156. return -EINVAL;
  157. kref_put(&ctx->refcount, amdgpu_ctx_do_release);
  158. return 0;
  159. }
  160. uint64_t amdgpu_ctx_add_fence(struct amdgpu_ctx *ctx, struct amdgpu_ring *ring,
  161. struct fence *fence)
  162. {
  163. struct amdgpu_ctx_ring *cring = & ctx->rings[ring->idx];
  164. uint64_t seq = cring->sequence;
  165. unsigned idx = seq % AMDGPU_CTX_MAX_CS_PENDING;
  166. struct fence *other = cring->fences[idx];
  167. if (other) {
  168. signed long r;
  169. r = fence_wait_timeout(other, false, MAX_SCHEDULE_TIMEOUT);
  170. if (r < 0)
  171. DRM_ERROR("Error (%ld) waiting for fence!\n", r);
  172. }
  173. fence_get(fence);
  174. spin_lock(&ctx->ring_lock);
  175. cring->fences[idx] = fence;
  176. cring->sequence++;
  177. spin_unlock(&ctx->ring_lock);
  178. fence_put(other);
  179. return seq;
  180. }
  181. struct fence *amdgpu_ctx_get_fence(struct amdgpu_ctx *ctx,
  182. struct amdgpu_ring *ring, uint64_t seq)
  183. {
  184. struct amdgpu_ctx_ring *cring = & ctx->rings[ring->idx];
  185. struct fence *fence;
  186. spin_lock(&ctx->ring_lock);
  187. if (seq >= cring->sequence) {
  188. spin_unlock(&ctx->ring_lock);
  189. return ERR_PTR(-EINVAL);
  190. }
  191. if (seq < cring->sequence - AMDGPU_CTX_MAX_CS_PENDING) {
  192. spin_unlock(&ctx->ring_lock);
  193. return NULL;
  194. }
  195. fence = fence_get(cring->fences[seq % AMDGPU_CTX_MAX_CS_PENDING]);
  196. spin_unlock(&ctx->ring_lock);
  197. return fence;
  198. }